CS4352-CZZR - Cirrus Logic, Inc. - Datasheet.Directory

http://www.cirrus.com

192 kHz Stereo DAC with 2 Vrms Line Out

Features

Multi-bit Delta-Sigma Modulator

24-Bit Resolution

Supports Sample Rates up to 192 kHz

106 dB A-wt Dynamic Range

-93 dB THD+N

Integrated Line Driver

2 Vrms Output into 5 kΩ AC Load

Analog Low-Pass Filter

Stereo Mutes with Auto-Mute Function

Low Clock-Jitter Sensitivity

Low-Latency Digital Filtering

Popguard® Technology for Control of Clicks

and Pops

Single-Ended Outputs

+3.3 V Core, +9 to 12 V Analog, and +1.5 to

3.3 V Interface Power Supplies

Low Power Consumption

20-pin TSSOP, Lead-Free Assembly

Description

The CS4352 is a complete stereo digital-to- ana log sys-

tem including digital interpolation, fifth-order multi-bit

delta-sigma digital-to-analog conversion, digital de-em-

phasis, analog filtering, and on-chip 2 Vrms line-level

driver. The advantage s of this architecture include ideal

differential linearity, no distortion mechanisms due to re-

sistor matching errors, no linearity drift over time and

temperature, high tolerance to clock jitter, and a minimal

set of external components.

The CS4352 is available in a 20-pin TSSOP package in

both Commercial grade (-40°C to +85°C) and Automo-

tive grade (-40°C to +105°C). The CDB4352 Customer

Demonstration Board is al so available for de vice evalu-

ation and implementation suggestions. Please see

“Ordering Informatio n” on p age 20 for complete details.

These features are ideal for cost-sensitive, 2-channel

audio systems including video game consoles, DVD

players, A/V receivers, set-top boxes, digital TVs and

DVD Recorders, mini-component systems, and mixing

consoles.

PCM

Serial

Interface Interpolation

Filter

Serial Audio Input

Left and Right

Mute Controls

2 Vrms Line Level

Right Channel

Output

2 Vrms Line Level

Left Channel

Output

Reset

1.5 V to 3.3 V

Hardware

Configuration

Level Translator

Hardware Control

Multibit

∆Σ Modulator

3.3 V 9 V to 12 V

Interpolation

Filter

Amp

Filter

Amp

Filter

Multibit

∆Σ Modulator

Auto Speed Mode

Detect

DAC

External

Mute

Control

Internal Voltage

Reference

JUN '07

DS684F2

CS4352

Confidential Draft

6/18/07

2DS684F2
CS4352
TABLE OF CONTENTS
1. PIN DESCRIPTIONS  ............................................................................................................................. 3
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4
RECOMMENDED OPERATING CONDITIONS  .................................................................................... 4
ABSOLUTE MAXIMUM RATINGS  ........................................................................................................ 4
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) ............................................................. 5
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ) .............................................................. 6
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 7
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE        ................................................... 8
DIGITAL CHARACTERISTI CS ............... ... ... .... ... ................ ... .... ... ... ... ... ................. ... ... ... ... .... .............. 9
POWER AND THERMAL CHARACTERISTICS  ................................................................................... 9
3. TYPICAL CONNECTION DIAGRAM  ................................................................................................... 10
4. APPLICATIONS  ................................................................................................................................... 11
4.6.1 Capacitor Placement ... .......................................................................................................... 13
4.7.1 Power-Up  ....... ... .... ... ................ ... ................ .... ................ ... ................ ... ................ ................ 14
4.7.2 Power-Down ................ ... ................ .... ... ................ ... .... ................ ... ... ................ ... ................ 14
4.7.3 Discharge Time .................. ... ... ... ... .... ... ... ... .... ................ ... ... ... ................. ... ... ... ... ................ 14
5. DIGITAL FILTER RESPONSE PLOTS         ......................................................................................... 16
6. PARAMETER DEFINITIONS ................................................................................................................ 18
7. PACKAGE DIMENSIONS   ................................................................................................................... 19
8. ORDERING INFORMATION   ............................................................................................................... 20
9. REVISION HISTORY ............................................................................................................................ 20
LIST OF FIGURES
Figure 1.Serial Input Timing ......... ... ... .... ... ... ... ... .... ... ................ ... .... ... ... ... ... ................. ... ... ........................ 8
Figure 2.Typical Connection Diagram ....................................................................................................... 10
Figure 3.I²S, up to 24-Bit Data  .................................................................................................................. 12
Figure 4.Right-Justified Data ..... ... ... ... ................ .... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ...................... 12
Figure 5.Left-Justified up to 24-Bit Data .................................................................................................... 12
Figure 6.De-Emphasis Curve ................. ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... .... ............................ 13
Figure 7.Single-Speed Stopband Rejection .............................................................................................. 16
Figure 8.Single-Speed Transition Band .................................................................................................... 16
Figure 9.Single-Speed Transition Band (detail) ........................................................................................ 16
Figure 10.Single-Speed Passband Ripple ................... ... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... .... ... ......... 16
Figure 11.Double-Speed Stopband Rejection .... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 16
Figure 12.Double-Speed Transition Band ................................................................................................. 16
Figure 13.Double-Speed Transition Band (detail) ..................................................................................... 17
Figure 14.Double-Speed Passband Ripple ............................................................................................... 17
Figure 15.Quad-Speed Stopband Rejection ............................................................................................. 17
Figure 16.Quad-Speed Transition Band  ................ ... ................ ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 17
Figure 17.Quad-Speed Transition Band (detail)  ................. ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 17
Figure 18.Quad-Speed Passband Ripple  ................................................................................................. 17
LIST OF TABLES
Table 1. CS4352 Auto-Detect ................................................................................................................... 11
Table 2. Single-Speed Mode Standard Frequencies  ................................................................................11
Table 3. Double-Speed Mode Standard Frequencies ............................................................................... 11
Table 4. Quad-Speed Mode Standard Frequencies  ................................................................................. 11
Table 5. Digital Interface Format ............................................................................................................... 12

DS684F2 3

CS4352

1. PIN DESCRIPTIONS

Pin Name Pin # Pin Description

SDIN 1 Serial Audio Da ta Input (Input) - Input for two’s complement serial audio data.

SCLK 2 Serial Clock (Input) - Serial clock for the serial audio interface.

LRCK 3 Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line.

MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

VD 5 Digital Power (Input) - Positive power supply for the digital section.

GND 6

16 Ground (Input) - Ground reference.

DIF0

DIF1 8

7Digital Interface Format (Input) - Defines the required relationship between the Left/Right Clock, Serial

Clock, and Serial Audio Data.

DEM 9 De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1 kHz

sample rates

RST 10 Reset (Input) - Powers down the device and resets all internal registers to their defa ult settings when

enabled.

VA 11 Low Voltage Analog Power (Input) - Positive power supply for the analog section.

VBIAS 12 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.

VQ 13 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

VA_H 17 High Voltage Analog Power (Input) - Positive power supply for the analog section.

VL 20 Serial Audio Interface Power (Input) - Positive power for the serial audio interface

BMUTEC

AMUTEC 14

19 Mute Control (Output) - Control signal for optional mute circu it.

AOUTB

AOUTA 15

18 Analog Outputs (Output) - The full-scale analog line output leve l is spec ified in the Analog Characteris-

tics table.

SDIN VL

SCLK AMUTEC

LRCK AOUTA

MCLK VA_H

VD GND

GND AOUTB

DIF1 BMUTEC

DIF0 VQ

DEM VBIAS

RST VA

10 11

4DS684F2

CS4352

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

(GND = 0 V; all voltages with respect to ground.)

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to ground.)

Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guar-

anteed at these extremes.

Parameters Symbol Min Typ Max Units

DC Power Supply High Voltage Analog power

Low Voltage Analog power

Digital power

Interface power

VA_H

8.40

3.13

1.43

3.3

1.5

12.6

3.47

Ambient Operating Temperature (power applied) -CZZ

-DZZ TA-40

-40 -

-+85

+105 °C

°C

Parameters Symbol Min Max Units

DC Power Supply High Voltage Analog power

Low Voltage Analog power

Digital power

Interface power

VA_H

-0.3

14.0

3.63

Input Current, Any Pin Except Supplies Iin -±10mA

Digital Input Voltage Digital Interface VIN-L -0.3 VL+ 0.4 V

Ambient Operating Temperature (power applied) TA-55 +125 °C

Storage Temperature Tstg -65 +150 °C

DS684F2 5

CS4352

DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ)

Test conditions (unless otherwise specified): TA = 25 °C, VA_H = 9 V, VA = 3.3 V, VD = 3.3 V GND = 0 V; VBIAS+

and VQ capacitors as shown in Figure 2 on page 10; input test signal is a 997 Hz sine wave at 0 dBFS; measure-

ment bandwidth 10 Hz to 20 kHz.

Notes: 1. One-half LSB of triangular PDF dither is added to data.

Parameter Symbol Min Typ Max Unit

All Speed Modes Fs = 48, 96, and 192 kHz

Dynamic Range (Note 1) 24-bit A-Weighted

unweighted

16-bit A-Weighted

unweighted

100

106

103

Total Harmonic Distortion + Noise (Note 1)

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

-20 dB

-60 dB

THD+N

-93

-83

-43

-93

-75

-35

-89

-77

-37

Idle Channel Noise / Signal-to-noise ratio (A-wt) - 106 - dB

Interchannel Isolation (1 kHz) - 99 - dB

Analog Output - All Modes

Full Scale Output Voltage 1.84 2.00 2.11 Vrms

Common Mode Voltage VQ-4-Vdc

Max Current draw from an AOUT pin IOUTmax - 575 - µA

Max Current draw from VQ IQmax -1-µA

Interchannel Gain Mismatch - 0.1 - dB

Gain Drift - 100 - ppm/°C

Output Impedance ZOUT -50-Ω

AC-Load Resistance RL5--kΩ

Load Capacitance CL--100pF

6DS684F2

CS4352

DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ)

Test conditions (unless otherwise specified): TA = -40°C to 85°C, VA_H = 9 V, VA = 3.3 V, VD = 3.3 V GND = 0 V;

VBIAS+ and VQ capacitors as shown in Figure 2 on page 10; input test signal is a 997 Hz sine wave at 0 dBFS;

measurement bandwidth 10 Hz to 20 kHz.

Notes: 2. One-half LSB of triangular PDF dither is added to data.

Parameter Symbol Min Typ Max Unit

All Speed Modes Fs = 48, 96, and 192 kHz

Dynamic Range (Note 2) 24-bit A-Weighted

unweighted

16-bit A-Weight ed

unweighted

106

103

Tot al Harmonic Distortion + Noise (Note 2)

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

-20 dB

-60 dB

THD+N

-93

-83

-43

-93

-75

-35

-89

-73

-33

Idle Channel Noise / Signal-to-noise ratio (A-wt) - 106 - dB

Interchannel Isolation (1 kHz) - 99 - dB

Analog Output - All Modes

Full Scale Output Voltage 1.81 2.00 2.17 Vrms

Common Mode Voltage VQ-4-Vdc

Max Current draw from an AOUT pin IOUTmax -575-µA

Max Current draw from VQ IQmax -1-µA

Interchannel Gain Misma tch - 0.1 - dB

Gain Drift - 100 - ppm/°C

Output Impedance ZOUT -50-Ω

AC-Load Resistance RL5--kΩ

Load Capacitance CL- - 100 pF

DS684F2 7
CS4352
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-
ple rate by multiplying the given characteristic by Fs. Amplitude vs. frequency plots of the data in the table below 
are available in “Digital Filter Response Plots” on page 16.) 
Notes: 3. Response is clock-dependent and will scale with Fs.
4. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. 
For Double-Speed Mod e, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
5. De-emphasis is available only in Single-Speed Mode.
Parameter Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 3) to -0.01 dB corner
to -3 dB corner 0
0-
-.454
.499 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand 0.547 - - Fs
StopBand Attenuation (Note 4) 102 - - dB
Total Group Delay (Fs = Output Sample Rate) - 9.4/Fs - s
Intra-channel Phase Deviation - - ±0.56/Fs s
Inter-channel Phase Deviation - - 0 s
De-emphasis Error (Note 5) (Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 3) to -0.01 dB corner
to -3 dB corner 0
0-
-.430
.499 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB
StopBand .583 - - Fs
StopBand Attenuation (Note 4) 80 - - dB
Total Group Delay (Fs = Output Sample Rate) - 4.6/Fs - s
Intra-channel Phase Deviation - - ±0.03/Fs s
Inter-channel Phase Deviation - - 0 s
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 3)  to -0.01 dB corner
to -3 dB corner 0
0-
-.105
.490 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB
StopBand .635 - - Fs
StopBand Attenuation (Note 4) 90 - - dB
Total Group Delay (Fs = Output Sample Rate) - 4.7/Fs - s
Intra-channel Phase Deviation - - ±0.01/Fs s
Inter-channel Phase Deviation - - 0 s

8DS684F2

CS4352

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Parameters Symbol Min Max Units

MCLK Frequency 1.024 48.0 MHz

MCLK Duty Cycle 45 55 %

Input Sample Rate (Auto selection) Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

170

108

216

kHz

LRCK Duty Cycle 40 60 %

SCLK Pulse Width Low tsclkl 20 - ns

SCLK Pulse Width High tsclkh 20 - ns

SCLK Period Single-Speed Mode tsclkw --

Double-Speed Mode tsclkw --

Quad-Speed Mode tsclkw --

SCLK rising to LRCK edge delay tslrd 20 - ns

SCLK rising to LRCK edge setup time tslrs 20 - ns

SDIN valid to SCLK rising setup time tsdlrs 20 - ns

SCLK rising to SDIN hold time tsdh 20 - ns

sclkh

slrs

slrd

sdlrs

sdh

sclkl

SDATA

SCLK

LRCK

Figure 1. Serial Inp ut Timing

128()Fs

----------------------

64()Fs

------------------

MCLK

-----------------

DS684F2 9
CS4352
DIGITAL CHARACTERISTICS
POWER AND THERMAL CHARACTERISTICS  
Notes: 6. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Variance between speed modes is small.  
7. Power down mode is defined as RST pin = Low with all clock and data lines held static low. All digital
inputs have a weak p ull-down which is only present during reset. Opposing this pull-down will slightly
increase the power-down current (pull-down is equivalent to a 50 kΩ resistor per pin).
8. Valid  with the recommende d capacitor values on VQ and VBIAS as shown in the typical connection dia-
gram in Section 3.
Parameters Symbol Min  Typ Max Units
High-Level Input Voltage VL = 3.3 V
VL = 2.5 V
VL = 1.5 V
VIH
VIH
VIH
2.0
1.7
1.05
-
-
-
-
-
-
V
V
V
Low-Level Input Voltage VL = 3.3 V
VL = 2.5 V
VL = 1.5 V
VIL
VIL
VIL
-
-
-
-
-
-
0.8
0.7
0.38
V
V
V
Input Leakage Current Iin --±10µA
Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 2 - mA
MUTEC High-Level Output Voltage VOH -VA_H- V
MUTEC Low-Level Output Voltage VOL -0- V
Parameters Symbol Min Typ Max Units
Power Supplies 
Power Supply Current normal operation, VA_H = 12 V
(Note 6) VA_H = 9 V
  VA= 3.3 V
VD= 3.3 V
Interface current VL= 3.3 V
power-down state, all supplies (Note 7)
IA_H
IA_H
IA
ID
IL
Ipd
-
-
-
-
-
-
12
10
3
12
0.02
380
21
16
4
16
0.09
-
mA
mA
mA
mA
mA
µA
Power Dissipation (all supplies) (Note 6)
VA_H = 12 V  normal operation
power-down (Note 7)
VA_H = 9 V normal operation
power-down (Note 7)
-
-
-
-
121
1
91
1
158
-
122
-
mW
mW
mW
mW
Power Supply Rejection Ratio (Note 8) (1 kHz)
(60 Hz) PSRR -
-60
60 -
-dB
dB

10 DS684F2

CS4352

3. TYPICAL CONNECTION DIAGRAM

Digital

Audio

Source

GND

MCLK

AOUTA

0.1 µF 10 µF

+3.3 V *

Mode

Configuration

SDIN

DIF1

DIF0

DEM

Optional

Mute

Circuit

RST

BMUTEC

3.3 µF

Left Out

VBIAS+

LRCK

SCLK

3.3 µF 10 kΩ

560 Ω

AOUTB

3.3 µF

VA_H

0.1 µF

10 µF

GND

0.1 µF

+1.5 V to VD

+9 V to +12 V

AMUTEC

0.1 µF 10 µF

+3.3 V

5.1Ω∗

2.2 nF*

*Optional

*Shown value is

for Fc=130 kHz

*Remove this supply if

optional resistor is present.

The decoupling caps should

remain.

615

511

Optional

Mute

Circuit Right Out

3.3 µF 10 kΩ

560 Ω

2.2 nF*

Figure 2. Typical Connection Diagram

CS4352

DS684F2 11

CS4352

4. APPLICATIONS

4.1 Sample Rate Range/Operational Mode Detect

The device operates in one of three operational modes. The allowed sample rate range in each mode is

auto-detected.

The CS4352 will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK fre-

quency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for

each mode ar e no t su pp orted.

Table 1. CS4352 Auto-Detect

4.2 System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.

The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the

MCLK according to specified ratios. The specified ra tios of MCLK to LRCK, along with several standard au-

dio sample rates and the required MCLK frequency, are illustrated in Tables 2-4.

Refer to Section 4.3 for th e required SCLK timing associa ted with th e selected Digital Interface For mat and

to “Switching Specifications - Serial Audio Interface” on page 8 for the maximum allo wed clock frequencies.

Table 2. Single-Speed Mode St andard Frequencies

Table 3. Double-Spee d Mod e Standard Frequencies

Table 4. Quad-Speed Mode Standard Frequencies

Input Sample Rate (FS) Mode

4 kHz - 54 kHz Single-Speed Mode

84 kHz - 108 kHz Double-Speed Mode

170 kHz - 216 kHz Quad-Speed Mode

Sample Rate

(kHz) MCLK (MHz)

256x 384x 512x 768x 1024x

32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 33.8688 45.1584

48 12.2880 18.4320 24.5760 36.8640 49.1520

Sample Rate

(kHz) MCLK (MHz)

128x 192x 256x 384x 512x

88.2 11.2896 16.9344 22.5792 33.8688 45.1584

96 12.2880 18.4320 24.5760 36.8640 49.1520

Sample Rate

(kHz) MCLK (MHz)

128x 192x 256x

176.4 22.5792 33.8688 45.1584

192 24.5760 36.8640 49.1520

12 DS684F2

CS4352

4.3 Digital Interface Format

The device will accept audio samples in 1 of 4 digital interface formats, as illustrated in Table 5.

The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship

between the LRCK, SCLK and SDIN, see Figures 3-5. For all formats, SDIN is valid on the rising edge of

SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2 and 48 cycles per LRCK period

in format 3.

For more information about se rial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-

nel Serial Audio Interface: A Tutorial, available at www.cirrus.com.

Table 5. Digital Interface Format

Figure 3. I²S, up to 24-Bit Data

Figure 4. Right-Justified Data

Figure 5. Left-Justified up to 24-Bit Data

DIF1 DIF0 DESCRIPTION FORMAT FIGURE

I²S, up to 24-bit Data 03

Right-Justified, 24-bit Data 14

Left-Justified, up to 24-bit Data 25

Right-Justified, 16-bit Data 34

LRCK

SCLK

Left Channel Right Channel

SDIN +3 +2 +1+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

MSB

LSB LSB

LRCK

SCLK

Left Channel

SDIN -6 -5 -4 -3 -2 -1-7

+1 +2 +3 +4 +5

MSB

Right Channel

LSBMSB +1 +2 +3 +4 +5 LSB

-6 -5 -4 -3 -2 -1-7

MSB

LRCK

SCLK

Left Channel Right Channel

SDIN +3 +2 +1+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

LSB MSB LSB

DS684F2 13

CS4352

4.4 De-Emphasis Control

The device includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve for Fs equal to

44.1 kHz. The frequency response of the de-emphasis curve scales with changes in sample rate, Fs. The

De-emphasis error will increase for sample rates other than 44.1 kHz

When pulled to VL, the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND , the DEM

pin turns off the de-emphasis filter.

Note: De-emphasis is only available in Single-Speed Mode.

4.5 Recommended Power-Up Sequence

1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right

clocks are lock ed to the a ppropria te frequencies, as discussed in Section 4.2. In this state, VQ will re-

main low and VBIAS will be connected to VA.

2. Bring RST high. The device will remain in a low power state with V Q low and will initiate th e power-up

sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-

Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

4.6 Grounding and Power Supply Arrangements

As with any high-resolution converter, the CS4352 requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 2 shows the recommended power ar-

rangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between

digital ground and analog ground, the GND pins of the CS4352 should be connected to the analog ground

plane.

All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted

coupling into the DAC.

4.6.1 Capacitor Placement

Decoupling capacitors should be placed a s close to the DAC as possible, with the low-value ceramic ca-

pacitor being the closest. To further minimize impedance, these capacitors should be located on the same

layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling ca-

pacitor should still be placed on each supply pin.

Note: All decoupling capacitors should be referenced to analog ground.

The CDB4352 evaluation board demonstrates the optimum layout and power supply arrangements.

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 k Hz 10.61 kHz

Figure 6. De-Emphasis Curve

14 DS684F2

CS4352

4.7 Popguard Transient Control

The CS4352 uses a novel technique to minimize the effects of output transients during power-up and power-

down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,

minimizes the audio transients com monly produ ced by single-ended, single-s upply conver ters. It is activat-

ed inside the DAC when the RST pin is toggled and requires no other exte rnal control, aside from choosing

the appropriat e DC- blo ckin g capa cit ors .

4.7.1 Power-Up

When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.

Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies-

cent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins.

This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies-

cent voltage, minimizing audible power-up transients.

4.7.2 Power-Down

To prevent audibl e tran sients at pow er-down, th e device must first enter its power-do wn state. Whe n this

occurs, audio ou tput ceases, and the internal outpu t buffers are disconn ected from AOUTA and AOUTB.

In their place, a soft-start current sink is substituted that allows the DC-blocking capacitors to slowly dis-

charge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready

for the next power-on.

4.7.3 Discharge Time

To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-

fore turning on the power or exiting the power- down sta te. If full discha rge does not occur, a transient will

occur when the audio outputs are initially clamped to GND. The time that the device must remain in the

power-down state is related to the value of the DC-blocking capacitance and the output load. For example,

with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.

4.8 Mute Control

The Mute Control pins go active during power-up initialization, reset, muting, or if the MCLK to LRCK ratio

is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks

and pops that can occur in any single-ended, single-supply syste m.

Use of the Mute Control function is not mandatory but r ecommended for designs requiring the ab solute min-

imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system d esigner

to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.

Please see the CDB4352 data sheet for a suggested mute circuit for dual-supply systems. Alternately, the

FET muting circuit from the CS4351 data sheet may be used as well. This FET circuit must be placed in

series after the RC filter; otherwise noise may occur during muting conditions. Further ESD protection will

need to be taken into consideration for the FET used.

DS684F2 15

CS4352

4.9 Initialization and Power-Down Sequence Diagram

USER: Apply Power

Wait State

USER: Apply MCLK, SCLK, and LRCK

MCLK/LRCK R atio Detect ion

USER: Remove

LRCK or MCLK

USER: change

MCLK/LRCK ratio

Analog Out put

is Generated

USER: Apply RST

USER: Apply MCLK, SCLK, LRCK,

and release RST

Power-Down State

VQ and outputs low VQ and outputs

ramp down

VQ and outputs ramp up

16 DS684F2

CS4352

5. DIGITAL FILTER RESPONSE PLOTS

0.4 0.5 0.6 0.7 0.8 0.9 1

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

Figure 7. Single-Speed Stopband Rejection Figure 8. Single-Speed Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−0.02

−0.015

−0.01

−0.005

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 9. Single-Speed Transition Band (detail) Figure 10. Single-Speed Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 11. Double-Speed Stopband Rejecti on Figure 12. Doub le-Speed Trans iti on Band

DS684F2 17

CS4352

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 13. Double-Speed Transition Ban d (detail) Figure 14. Double-Speed Passband Ripple

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.8

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 15. Quad-Speed Stopband Rejection Figure 16. Quad-Speed Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25

0.2

0.15

0.1

0.05

0.1

0.15

0.2

Frequency(normalized to Fs)

Amplitude (dB)

Figure 17. Quad-Speed Transition Ban d (detail) Figure 18. Quad-Speed Passban d Ripple

18 DS684F2

CS4352

6. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the

specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made

with a -60 dBFS signal. 60 dB is then added to the resulting measure ment to refer the measurement to full

scale. This technique ensu res that the distortion components are be low the noise level and do not effect the

measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-

1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with all zeros to the in put under test and a full-scale signal applied to the other channel. Units in deci-

bels.

Interchannel Gain Mismatc h

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Intra-channel Phase Deviation

The deviation from linear phase within a given channel.

Inter-channel Phase Deviation

The difference in phase between channels.

DS684F2 19

CS4352

7. PACKAGE DIMENSIONS

1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion sha ll not re-

duce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10

A1 0.002 0.004 0.006 0.05 -- 0.15

A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.252 0.256 0.259 6.40 6.50 6.60 1

E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- -- 0.026 -- -- 0.65

L 0.020 0.024 0.028 0.50 0.60 0.70

µ0° 4° 8° 0° 4° 8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

Parameters Symbol Min Typ Max Units

Package Thermal Resistance 20L TSSOP θJA -72-°C/Watt

20L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

20 DS684F2

CS4352

8. ORDERING INFORMATION

9. REVISION HISTORY

Release Changes

PP1

Lowered VA_H minimum specification.

Updated Idle channel noise specification to A-wt.

Updated AOUT current draw specification.

Updated VIL for VL=1.5V.

F1 Updated performance specifications and limits based on statistical data.

Added Automotive grade specifications and ordering information.

Updated Commercial grade idle ch annel noise specification.

Lowered VIL maximum specifcation.

Updated power supply current specification .

Updated MCLK maximum specification.

Product Description Package Pb-Free Grade Temp Range Contain e r Order #

CS4352 20-pin, 192 kHz Stereo

DAC with 2 Vrms Line

Out

20-pin

TSSOP YES Commercial -40° to +85° C Rail

Tape & Reel CS4352-CZZ

CS4352-CZZR

Automotive -40° to +105° C Rail

Tape & Reel CS4352-DZZ

CS4352-DZZR

CDB4352 CS4352 Evaluation Board - - - - CDB4352

Contacting Cirrus Logic Support

For all product questions and inq uiries, contact a Cirrus Logic Sales Representative.

To find the one nearest you, go to www.cirrus.com.

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