Integrated
Circuit
Systems, Inc.
ICS97U877
0792A—04/15/04
Block Diagram
1.8V Wide Range Frequency Clock Driver
Pin Configuration
40-Pin MLF
Recommended Application:
• DDR2 Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR DIMM logic solution with
ICSSSTU32864
Product Description/Features:
• Low sk ew, low jitter PLL clock driv er
• 1 to 10 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• A uto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps
• Half-period jitter: 60ps
• CYCLE - CYCLE jitter 40ps
• OUTPUT - OUTPUT skew: 40ps
A
B
123456
C
D
E
F
G
H
J
K
VDDQ
CLKC2
CLKT2
CLK_INT
CLK_INC
VDDQ
AGND
AVDD
VDDQ
GND
CLKC7
CLKT7
VDDQ
FB_INT
FB_INC
FB_OUTC
FB_OUTT
VDDQ
OE
OS
CLKT3
CLKC3
CLKC4
CLKT4
VDDQ
CLKT9
CLKC9
CLKC8
CLKT8
VDDQ
CLKC1
CLKT1
CLKT0
CLKC0
VDDQ
CLKC5
CLKT5
CLKT6
CLKC6
VDDQ
1
10
11 20
21
31
30
40
ICS97U877
52-Ball BGA
T op View
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
AV
DD
FB_INT
CLK_INT
CLK_INC
FB_INC
PLL
Powerdown
Control and
Test Logic
OE LD* or OE
PLL bypass
LD*
LD*, OS or OE
OS
GND
10K-100
k
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
12345 6
ACLKT1 CLKT0 CLKC0 CLKC5 CLKT5 CLKT6
BCLKC1 GND GND GND GND CLKC6
C CLKC2 GND NB NB GND CLKC7
DCLKT2 VDDQ VDDQ VDDQ OS CLKT7
ECLK_INT VDDQ NB NB VDDQ FB_INT
FCLK_INC VDDQ NB NB OE FB_INC
GAGND VDDQ VDDQ VDDQ VDDQ FB_OUTC
HAVDD GND NB NB GND FB_OUTT
JCLKT3 GND GND GND GND CLKT8
KCLKC3 CLKC4 CLKT4 CLKT9 CLKC9 CLKC8
2
ICS97U877
0792A—04/15/04
Pin Descriptions
lanimreT emaN noitpircseD lacirtcelE scitsiretcarahC
DNGAdnuorGgolanA dnuorG
VA
DD
rewopgolanA lanimonV8.1
TNI_KLCrotsisernwodllup)mhOK001-K01(ahtiwtupnikcolC tupnilaitnereffiD
CNI_KLC rotsisernwodllup)mhOK001-K01(ahtiwtupnikcolcyratnelpmoC tupnilaitnereffiD
TNI_BFtupnikcolckcabdeeF tupnilaitnereffiD
CNI_BFtupnikcolckcabdeefyratnemelpmoC tupnilaitnereffiD
TTUO_BFtuptuokcolckcabdeeF tuptuolaitnereffiD
CTUO_BFtuptuokcolckcabdeefyratnemelpmoC tuptuolaitnereffiD
EO)suonorhcnysA(elbanEtuptuO tupniSOMCVL
SOVroDNGotdeit(tceleStuptuO
QDD
)tupniSOMCVL
DNGdnuorG dnuorG
V
QDD
rewoptuptuodnacigoL lanimonV8.1
]9:0[TKLCstuptuokcolC stuptuolaitnereffiD
]9:0[CKLCstuptuokcolcyratnemelpmoC stuptuolaitnereffiD
BNllaboN
The PLL clock buffer, ICS97U877, is designed for a VDDQ of 1.8 V , a AVDD of 1.8 V and differential data input and output
le vels . P ackage options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one diff erential pair feedback clock outputs (FB_OUTT, FBOUTC).
The clock outputs are controlled by the input clocks (CLK_INT , CLK_INC), the feedback clocks (FB_INT , FB_INC), the
L VCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/
FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency . OS (Output Select) is a
program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low,
OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded,
the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the de vice will enter a low po w er mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT , FB_INC) and the input clock pair (CLK_INT , CLK_INC)
within the specified stabilization time tSTAB.
The PLL in ICS97U877 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS97U877
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97U877 is characterized for operation from 0°C to 70°C.
3
ICS97U877
0792A—04/15/04
Function Table
stupnIstuptuO LLP
DDVAEOSOTNI_KLCTNI_KLCTKLCCKLCTTUO_BFCTUO_BF
DNGHXL H L H L H ffO/dessapyB
DNGHXH L H L H L ffO/dessapyB
DNGLHL H )Z(L*)Z(L*LH ffO/dessapyB
DNGLLH L ,)Z(L* 7TKLC evitca
,)Z(L* 7CKLC evitca HLffO/dessapyB
)mon(V8.1LHLH )Z(L*)Z(L*LH nO
)mon(V8.1LLHL ,)Z(L* 7TKLC evitca
,)Z(L* 7CKLC evitca
HL nO
)mon(V8.1HXLHLHLH nO
)mon(V8.1HXHLHLHL nO
)mon(V8.1XXLL )Z(L*)Z(L*)Z(L*)Z(L*ffO
)mon(V8.1XXHH devreseR
*L(Z) means the outputs are disabled to a low stated meeting the IODL limit.
4
ICS97U877
0792A—04/15/04
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . . -0.5V to 2.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VDDQ + 0.5V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature. . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses abov e those listed under
Absolute Maximum Ratings
ma y cause permanent damage to the device . These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
f or e xtended periods may aff ect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Current
(
CLK_INT, CLK_INC
)
IIH VI = VDDQ or GND ±250 µA
Input Low Current (OE,
OS, FB_INT, FB_INC
)
IIL VI = VDDQ or GND ±10 µA
Output Disabled Low
Current IODL OE = L, VODL = 100mV 100 µA
IDD1.8 CL = 0pf @ 270MHz 300 mA
IDDLD CL = 0pf 500 µA
Input Clamp Voltage VIK VDDQ = 1.7V Iin = -18mA -1.2 V
IOH = -100
µ
AVDDQ - 0.2 V
IOH = -9 mA 1.1 1.45 V
IOL=100
µ
A0.25 0.10 V
IOL=9 mA 0.6 V
In
p
ut Ca
p
acitance1CIN VI = GND or VDDQ 23pF
Out
p
ut Ca
p
acitance1COUT VOUT = GND or VDDQ 23pF
1Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
Operating Supply
Current
High-level output voltage VOH
Low-level output voltage VOL
5
ICS97U877
0792A—04/15/04
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required f or s witching, where VTR is the true input lev el and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track v ariations of VDDQ and is the
voltage at which the differential signal must be crossing.
Recommended Operating Condition (see note1)
TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VDDQ, AVDD 1.7 1.8 1.9 V
CLK_INT, CLK_INC, FB_INC,
FB_INT 0.35 x VDDQ V
OE, OS 0.35 x VDDQ V
CLK_INT, CLK_INC, FB_INC,
FB_INT 0.65 x VDDQ V
OE, OS 0.65 x VDDQ V
DC input signal voltage (note
2
)
VIN -0.3 VDDQ + 0.3 V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT 0.3 VDDQ + 0.4 V
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT 0.6 VDDQ + 0.4 V
Output differential cross-
volta
e
note 4
VOX VDDQ/2 - 0.10 VDDQ/2 + 0.10 V
Input differential cross-
volta
e
note 4
VIX VDDQ/2 - 0.15 VDD/2 VDDQ2 + 0.15 V
High level output current IOH -9 mA
Low level output current IOL 9mA
Operating free-air
tem
p
erature TA070°C
Differential input signal
voltage (note 3) VID
Low level input voltage VIL
High level input voltage VIH
6
ICS97U877
0792A—04/15/04
Notes:
1 . Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
Timing Requirements
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
Max clock frequency freqop 1.8V+0.1V @ 25°C 95 370 MHz
Application Frequency Range freqApp 1.8V+0.1V @ 25°C 160 350 MHz
Input clock duty cycle dtin 40 60 %
CLK stabilization TSTAB 15 µs
Switching Characteristics1
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Output enable time ten OE to any output 4.73 8 ns
Output disable time tdis OE to any output 5.82 8 ns
Period jitter t
j
it
(p
er
)
-30 30 ps
Half-period jitter t
j
it
(
h
p
er
)
-60 60 ps
In
p
ut Clock 1 2.5 4 v/ns
Out
p
ut Enable
(
OE
)
,
(
OS
)
0.5 v/ns
Out
p
ut clock slew rate SLr1
(
o
)
1.5 2.5 3 v/ns
t
j
it
(
cc+
)
040ps
t
j
it
(
cc-
)
0 -40 ps
Dynamic Phase Offset t
(
)
d
y
n-20 20 ps
Static Phase Offset tSPO2-50 0 50 ps
Output to Output Skew tskew 40 ps
SSC modulation fre
q
uenc
y
30.00 33 kHz
SSC clock input frequency
deviation 0.00 -0.50 %
PLL Loop bandwidth (-3 dB
from unit
y
g
ain
)
2.0 MHz
Cycle-to-cycle period jitter
Input slew rate SLr1(i)
7
ICS97U877
0792A—04/15/04
GND
ICS97U877
V
DD
V(CLKC)
V(CLKC)
SCOPE
C=10pF
-VDD/2
GND
- GND
VDD/2
Z=6
Z = 2.97"
Z = 120Ω
Z = 2.97"
0Ω
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=10Ω
V(TT)
V(TT)
C=10pF
Note: V
TT
= GND
tc(n) tc(n+1)
tjit(cc) =t
c(n)±t
c(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS97U877
Figure 3. Cycle-to-Cycle Jitter
R = 1MΩ
C = 1 pF
R = 1MΩ
C = 1 pF
8
ICS97U877
0792A—04/15/04
(N is a large number of samples)
t
( ) n+1
t
()n
t
()
=1
n=N
t
()n
N
CLK_INC
CLK_INT
FB_INC
FB_INT
t(skew)
Y#
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
YX
Parameter Measurement Information
Figure 4. Static Phase Offset
Figure 5. Output Skew
1
fO
t=
t
-
(jit_per) tc(n)
C(n)
1
fO
Figure 6. Period Jitter
9
ICS97U877
0792A—04/15/04
Clock Inputs
and Outputs
80%
20%
80%
20%
tslr tslf
VID,V
OD
Figure 8. Input and Output Slew Rates
Parameter Measurement Information
tjit(hper_n) tjit(hper_n+1)
1
fo
Y , FB_OUTC
X
Y , FB_OUTT
X
Figure 7. Half-Period Jitter
tjit(hper) tjit(hper_n) 1
2xfO
=-
10
ICS97U877
0792A—04/15/04
Figure 9. Dynamic Phase Offset
Figure 10. Time de lay between OE and Clock Output (Y, Y)
t
( )
t
( )
FBIN
FBIN
CK
CK
t
( )dyn
t
( )dyn
t
( )dyn
t
( )dyn
SSC OFF
SSC ON SSC ON
SSC OFF
50% VDDQ
ten
tdis
OE
OE
Y/Y
Y
50% VDDQ
Y
Y
Y
50% VDDQ
50 % VDDQ
11
ICS97U877
0792A—04/15/04
Figure 11. AV
DD Filtering
- Place the 2200pF capacitor close to the PLL.
- Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one
GND via (farthest from PLL).
- Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
12
ICS97U877
0792A—04/15/04
Ordering Information
ICS97U877yHLF-T
- e -
TYP
b
REF
b
REF
Alpha Designations
forVertical Grid
(Letters I, O, Q & S
not used)
Alpha Designations
forVertical Grid
(Letters I, O, Q & S
not used)
Numeric Designations
for Horizontal Grid
Numeric Designations
for Horizontal Grid
h
TYP
h
TYP
c
REF
c
REF
A
B
C
D
TOP VIEW
A1 3 2 1
4
Seating
Plane
Seating
Plane
C
T
0.12 C
d TYP
E
D
D1D1D1D1D1
- e -- e -- e -
E1
TYP
TYP
D E T e HORIZ VE RT TOTAL d h D1 E1 b c
Min/Max Min/Max Min/Max
7. 00 Bsc 4. 50 B s c 0.86/1.00 0. 65 B s c 6 10 60 0.35/ 0. 45 0.15/ 0. 21 5.85 B sc 3. 25 B s c 0. 575 0.625 **
* Source Ref.: JEDEC Publication 95,
10-0055
A L L DIMENS IONS IN M IL LIM ET ERS
RE F . DI MEN SIONS ----- B A L L G RI D ----- M a x .
Note: Ball
g
rid total indicates maximum ball count for
p
acka
g
e. Les ser
q
uantit
y
ma
y
be used.
MO-205*, MO-225**
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Packag e Type
H = BGA
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y H LF- T
13
ICS97U877
0792A—04/15/04
Ordering Information
ICS97U877yKLF-T
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Packag e Type
K = MLF
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y K LF- T
Top View
Index Area
1
E
D
Sawn
Singulation
Anvil
Singulation
or
A
0.08 C C
A3
A1
Seating Plane
E2 E22
L
(N -1)x e
(Ref.)
D
(Ref.)
N&N
Even
DE
N
eD22
D2
DE
(Ref.)
N&N
Odd
1
2
e2(Typ.)
If N & N
are Even
(N -1)x e
(Ref.)
E
E
D
b
Thermal
Base
2
N
ALL DIMENSIO NS IN MILL IMET ERS
N SYMBOL MIN. MAX.
NDA 0.80 1.00
NEA1 0 0.05
D x E BASIC A3
D2 MIN. / MAX. b 0.18 0.30
E2 MIN. / MAX. e
L MIN. / MAX. SPECIAL
NON-JEDEC
ALL DIM.
SAME EXCEPT
AS BELOW:
4.35 / 4.65
5.05 / 5.35
10-0053
Source R eference: MLF2™ SE
R
THERMALL Y ENHANCED, VERY THIN, FI NE PIT CH
QUAD FLAT / NO LEAD P LASTIC PACKAGE
0.30 / 0.50
D2 MIN. / MAX.
E2 MIN. / MAX.
0.25 Reference
0.50 BASIC
6.00 x 6.00
2.75 / 3.05
2.75 / 3.05
40
10
10
Global Sites       Global Sites      Â
Email | Print
Search Entire Site
Search Entire Site
Contact IDT | Investors | Press
Document Search | Package Search | Parametric Search | Cross Ref erence Search | Green & RoHS | Calculators | Thermal Data | Reliability & Quality | Military
97U877A (DDR2 PLL)
Description
1.8V Wide Range Frequency Clock Driver
Market Group
DIMM
Additional Info
Not recommended for new designs
Add to m yIDT [?] Home > Products > Memory Interface Products > RDIMM > DDR2 > DDR2 PLL > 97U877A
You may also like...
2
1
Related Orderable Parts
Attributes
97U877AH
97U877AHLF
97U877AHLFT
97U877AHT
97U877AK
97U877AKI
Package
CVBGA 52 (BV52)
CVBGA 52 (BVG52)
CVBGA 52 (BVG52)
CVBGA 52 (BV52)
VFQFPN 40 (NL40)
VFQFPN 40 (NL40)
Speed
NA
NA
NA
NA
NA
NA
Temperature
C
C
C
C
C
I
Voltage
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
Status
Active
Active
Active
Active
Active
Active
Sample
No
No
No
No
No
No
Minimum Order
Quantity
325
325
2500
2500
490
490
Factory Order
Increment
325
325
2500
2500
490
490
2
1
Type
Title
Size
Revision Date
Product Change Notice
PCN#: TB-0510-14 New Carrier Tape for 52L/56L CABGA
102 KB
12/14/2005
PCN#: TB-0512-01 Reel Color Changed from Blue to Black
730 KB
12/16/2005
PCN# : TB-0605-05 New Shipping Tray for CVBGA 52L & 56L
1134 KB
06/29/2006
PCN# : A-0607-02 IDT Penang as Alternate Assembly Facility for ICS CVBGA and FPBGA
100 KB
07/27/2006
PCN# A-0607-05 Green Mold Compound KMC3580 for BGA
195 KB
08/30/2006
PCN# : A-0610-02 ASAT China as Alternate Facility for CABGA/CVBGA/FPBGA/TQFP/PQFP
253 KB
10/19/2006
Related Documents
Home | Site Map | About IDT | Press Room | Investor Relations | Trademark | Privacy Policy | Careers | Register | Contact Us
Use of this website signifies your agreement to the acceptable use and privacy policy. Copyright 1997-2007 Integrated Device Technology, Inc. All Rights Reserved.
Node: www.idt.com