The following document contains information on Cypress products. FUJITSU MICROELECTRONICS DATA SHEET DS07-13713-6E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90495G Series MB90497G/F497G/F498G/V495G DESCRIPTION The MB90495G Series is a general-purpose, high-performance 16-bit microcontroller. It was designed for devices like consumer electronics, which require high-speed, real-time process control. This series features an on-chip full-CAN interface. In addition to being backwards compatible with the F2MC* family architecture, the instruction set has been expanded to add support for high-level language instructions, expanded addressing mode, and enhanced multiply/ divide and bit processing instructions. A 32-bit accumulator is also provided, making it possible to process long word (32-bit) data. The MB90495G Series peripheral resources include on chip 8/10-bit A/D converter, UART (SCI) 0/1, 8/16-bit PPG timer, 16-bit I/O timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU) ) , and CAN controller. * : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. FEATURES * Models that support operating temperature (TA) +125 C * Clock *Built-in PLL clock multiplier circuit *Choose 1/2 oscillation clock or x1 to x4 multiplied oscillation clock (for a 4-MHz oscillation clock, 4 to 16 MHz) machine (PLL) clock (Continued) For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ Copyright(c)2001-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.3 MB90495G Series (Continued) *Select subclock behavior (8.192 kHz) *Minimum instruction execution time : 62.5 ns (operating with 4-MHz oscillation clock and x 4 PLL clock) * 16-Mbyte CPU memory space *24-bit internal addressing *External access possible through selection of 8/16-bit bus width (external bus mode) * Optimum instruction set for controller applications *Wealth of data types (Bit, Byte, Word, Long Word) *Wealth of addressing modes (23 different modes) *Enhanced signed multiply-divide instructions and RETI instruction functions *Enhanced high-precision arithmetic employing 32-bit accumulator * Instruction set supports high-level programming language (C) and multitasking *Employs system stack pointer *Enhanced indirect instructions with all pointer types *Barrel shift instructions * Improved execution speed *4-byte instruction queue * Powerful interrupt feature *Powerful 8-level, 34-condition interrupt feature * CPU-independent automated data forwarding *Extended intelligent I/O service feature (EI2OS) : maximum 16 channels * Low-power consumption (Standby) Mode *Sleep mode (CPU operation clock stopped) *Time-base timer mode (oscillation clock and subclock, time-base timer and watch timer only operational) *Watch mode (subclock and watch timer only operational) *Stop mode (oscillation clock and subclock stopped) *CPU intermittent operation mode * Process *CMOS technology * I/O Ports *Generic I/O ports (CMOS output) : 49 * Timer *Time-base timer, watch timer, watchdog timer : 1 channel *8/16-bit PPG timer : four 8-bit channels, or two 16-bit channels *16-bit reload timer : 2 channels *16-bit I/O timer *16-bit free-run timer : 1 channel *16-bit input capture (ICU) : 4 channels Generates interrupt requests by latching onto the count value of the 16-bit free-run timer with pin input edge detection (Continued) 2 DS07-13713-6E MB90495G Series (Continued) * CAN Controller : 1 channel *CAN specifications conform to versions 2.0A and 2.0B *8 on-chip message buffers *Forwarding rate 10 kbps to 1 Mbps (with 16-MHz machine clock) * UART0 (SCI) /UART1 (SCI) : 2 channels *All with full duplex double buffer *Use clock-asynchronous or clock-synchronous serial forwarding * DTP/external interrupt : 8 channels *A module for launching extended intelligent I/O service (EI2OS) and generating external interrupts through external output * Delayed interrupt generation module *Generates interrupt requests for switching tasks * 8/10-bit A/D converter : 8 channels *Switch between 8-bit and 10-bit resolution *Launch through external trigger input *Conversion time : 6.13 s (with 16-MHz machine clock, including sampling time) * Program batch function *2-address pointer ROM correction * Clock output function DS07-13713-6E 3 MB90495G Series PRODUCT LINEUP Part Number Parameter Feature Classification ROM Size MB90F497G MB90497G MB90F498G MB90V495G Flash ROM Mask ROM Flash ROM Product Evaluated 128 Kbytes 64 Kbytes RAM Size 2 Kbytes Process 6 Kbytes CMOS Package LQFP64 (pin pitch 0.65 mm) , QFP64 (pin pitch 1.00 mm) Operating Power 4.5 V to 5.5 V Emulator power supply* Number of instructions Instruction bit length Instruction length Data bit length CPU Functions PGA256 None : 351 : 8-bit, 16-bit : 1 to 7 bytes : 1 bit, 8-bit, 16-bit Minimum execution time : 62.5 ns (with 16-MHz machine clock) Interrupt processing time : minimum 1.5 s (with 16-MHz machine clock) Low-power consumption (Standby) Mode Sleep mode/watch mode/time-base timer mode/stop mode / CPU intermittent mode I/O Ports General-purpose I/O ports (CMOS output) : 49 Time-base timer 18-bit free-run counter Interrupt interval : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms (with 4-MHz oscillation clock) Watchdog timer Reset generation intervals : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (with 4-MHz oscillation clock) 16-bit I/O Timer 16-bit Number of channels : 1 free-run timer Interrupts from overflow generation Input capture Number of channels : 4 Maintenance of free-run timer value through pin input (rising, falling or both edges) 16-bit reload timer Number of channels : 2 16-bit reload timer operation Count clock interval : 0.25 s, 0.5 s, 2.0 s (with 16-MHz machine clock) External event count enabled Watch timer 15-bit free-run counter Interrupt intervals : 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with 8.192-kHz subclock) 8/16-bit PPG timer Number of channels : 2 (two 8-bit channels can be used) Two 8-bit or one 16-bit channel PPG operation possible Free interval, free duty pulse output possible Count clock : 62.5 ns to 1 s (with 16-MHz machine clock) * : The S2 dipswitch setting when using the MB2145-507 emulation baud. For details, see the MB2145-507 hardware manual (2.7 Emulator Power Pin) . (Continued) 4 DS07-13713-6E MB90495G Series (Continued) Part Number Parameter MB90F497G MB90497G MB90F498G MB90V495G Delayed interrupt generation module Module for delayed interrupt generation switching tasks Used in real-time OS DTP/external interrupt circuit Number of inputs : 8 Starting by rising edge, falling edge, "H" level input, or "L" level input, external interrupts or extended intelligent I/O service (EI2OS) can be used 8/10-bit A/D converter Number of channels : 8 Resolution : set 10-bit or 8-bit Conversion time : 6.13 s (with 16-MHz machine clock, including sampling time) Continuous conversion of multiple linked channels possible (up to 8 channels can be set) One-shot conversion mode : converts selected channel only once Continuous conversion mode : converts selected channel continuously Stop conversion mode : converts selected channel and suspends operation repeatedly UART0 (SCI) Number of channels : 1 Clock-synchronous forwarding : 62.5 kbps to 2 Mbps Clock-asynchronous forwarding : 1,202 bps to 62,500 bps Transmission can be performed by two-way serial transmission or by master/ slave connection UART1 (SCI) Number of channels : 1 Clock-synchronous forwarding : 62.5 kbps to 2 Mbps Clock-asynchronous forwarding : 9,615 bps to 500 kbps Transmission can be performed by two-way serial transmission or by master/ slave connection CAN Compliant with CAN specification versions 2.0A and 2.0B Send/receive message buffers : 8 Forwarding bit rate : 10 kbps to 1 Mbps (with 16-MHz machine clock) PACKAGES AND CORRESPONDING PRODUCTS Package MB90F497G MB90497G MB90F498G FPT-64P-M06 FPT-64P-M23 : available x : not available Note : See " PACKAGE DIMENSIONS" for details. PRODUCT COMPARISON Memory Size When evaluating with evaluation chips and other means, take careful note of the different between the evaluation chip and the chip actually used. Take particular note of the following. * While the MB90V495G does not feature an on-chip ROM, the dedicated development tool can be used to achieve operation equivalent to a product with built-in ROM. Therefore, the ROM size is configured by the development tool. * On the MB90V495G, the FF4000H to FFFFFFH image is only visible in the 00 bank, and the FE0000H to FF3FFFH is only visible in the FE and FF banks (configurable on development tool) . * On the MB90F497G/F498G/497G, the FF4000H to FFFFFFH image is visible in the 00 bank, and the FF0000H to FF3FFFH is visible only in the FF bank. DS07-13713-6E 5 P44/RX P61/INT1 P62/INT2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 X0A X1A P63/INT3 MD0 6 58 19 P31/SCK0/RD P32/SIN0/WRL P33/WRH P34/HRQ P35/HAK VCC C P36/FRCK/RDY P37/ADTG/CLK P40/SIN1 P41/SCK1 P42/SOT1 P43/TX 10 1 33 42 51 P30/SOT0/ALE VSS P27/INT7/A23 P26/INT6/A22 P25/INT5/A21 P24/INT4/A20 P23/TOT1/A19 P22/TIN1/A18 P21/TOT0/A17 P20/TIN0/A16 P17/PPG3/AD15 P16/PPG2/AD14 P15/PPG1/AD13 P14/PPG0/AD12 P13/IN3/AD11 P12/IN2/AD10 P11/IN1/AD09 P10/IN0/AD08 P07/AD07 MB90495G Series PIN ASSIGNMENTS (TOP VIEW) 52 32 QFP-64P 26 64 20 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VSS X1 X0 MD2 MD1 RST (FPT-64P-M06) DS07-13713-6E P61/INT1 P62/INT2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 X0A X1A DS07-13713-6E 57 16 VSS P30/SOT0/ALE P31/SCK0/RD P32/SIN0/WRL P33/WRH P34/HRQ P35/HAK VCC C P36/FRCK/RDY P37/ADTG/CLK P40/SIN1 P41/SCK1 P42/SOT1 P43/TX P44/RX 8 1 33 40 48 P27/INT7/A23 P26/INT6/A22 P25/INT5/A21 P24/INT4/A20 P23/TOT1/A19 P22/TIN1/A18 P21/TOT0/A17 P20/TIN0/A16 P17/PPG3/AD15 P16/PPG2/AD14 P15/PPG1/AD13 P14/PPG0/AD12 P13/IN3/AD11 P12/IN2/AD10 P11/IN1/AD09 P10/IN0/AD08 MB90495G Series (TOP VIEW) 49 32 LQFP-64P 24 64 17 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VSS X1 X0 MD2 MD1 RST MD0 P63/INT3 (FPT-64P-M23) 7 MB90495G Series PIN DESCRIPTION Pin No. QFP- LQFP- Pin Name 64P *1 64P *2 2 1 3 2 P61 INT1 P62 INT2 Circuit Type D D P50 to P57 4 to 11 3 to 10 Description General-purpose I/O port Functions as external interrupt input pin. Set this to input port. General-purpose I/O port Functions as external interrupt input pin. Set this to input port. General-purpose I/O port AN0 to AN7 E Functions as analog input port of A/D converter. This is enabled if analog input configuration is permitted. 12 11 AVCC VCC power input pin of A/D converter. 13 12 AVR Reference voltage (+) input pin for the A/D converter.This voltage must not exceed VCC and AVCC. Reference voltage (-) is fixed to AVSS. 14 13 AVSS VSS power input pin of A/D converter. 15 14 16 15 X0A A Low-speed oscillation pin. Perform pull-down processing if not connected to an oscillator. 17 16 X1A A Low-speed oscillation pin. Set to open if not connected to an oscillator. 18 17 19 18 MD0 C Input pin for specifying operation mode. 20 19 RST B External reset input pin. 21 20 MD1 C Input pin for specifying operation mode. 22 21 MD2 F Input pin for specifying operation mode. 23 22 X0 A High-speed oscillation pin. 24 23 X1 A High-speed oscillation pin. 25 24 VSS Power supply (0 V) input pin. 26 to 33 25 to 32 P60 INT0 P63 INT3 D D P00 to P07 AD00 to AD07 D P10 to P13 34 to 37 33 to 36 IN0 to IN3 AD08 to AD11 General-purpose I/O port Functions as external interrupt input pin. Set this to input port. General-purpose I/O port Functions as external interrupt input pin. Set this to input port. General-purpose I/O port Only enabled in single-chip mode. I/O pin for the lower 8-bit of the external address data bus. Only enabled during external bus mode. General-purpose I/O port. Only enabled in single-chip mode. D Functions as trigger input pin for input capture channels ch.0 to ch.3. Set this to input port. I/O pin for upper 4-bit of external address data bus. Only enabled during external bus mode. (Continued) 8 DS07-13713-6E MB90495G Series (Continued) Pin No. QFP- LQFP- Pin Name 64P *1 64P *2 Circuit Type General-purpose I/O port. Only enabled in single-chip mode. P14 to P17 38 to 41 37 to 40 PPG0 to PPG3 D AD12 to AD15 43 44 45 41 42 43 44 TIN0 General-purpose I/O port. When the bits of high address control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. D Functions as event input pin of TIN0 reload timer 0. Set this to input port. A16 Output pin of external address bus (A16) . Only valid when the bits of high address control register (HACR) are set to "0" in external bus mode. P21 General-purpose I/O port. When the bits of high address control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. TOT0 D Functions as event output pin of TOT0 reload timer 0. Only valid if output configuration enabled. A17 Output pin of external address bus (A17) . Only valid when the bits of high address control register (HACR) are set to "0" in external bus mode. P22 General-purpose I/O port. When the bits of high address control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. TIN1 D Functions as event input pin of TIN1 reload timer 1. Set this to input port. A18 Output pin of external address bus (A18) . Only valid when the bits of high address control register (HACR) are set to "0" in external bus mode. P23 General-purpose I/O port. When the bits of high address control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. TOT1 A19 DS07-13713-6E Functions as output pin of PPG timer 0/1, 2/3. Only valid if output configuration is enabled. I/O pin for upper 4-bit of external address data bus. Only enabled during external bus mode. P20 42 Description D Functions as event output pin for TOT1 reload timer 1. Only valid if output configuration enabled. Output pin for external address bus (A19) . Only valid when the bits of high address control register (HACR) are set to "0" in external bus mode. (Continued) 9 MB90495G Series (Continued) Pin No. QFP- LQFP- Pin Name 64P *1 64P *2 Circuit Type General-purpose I/O port. When the bits of high address control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. P24 to P27 46 to 49 45 to 48 INT4 to INT7 D 49 VSS 52 53 50 51 52 SOT0 D Address latch authorization output pin. Only enabled during external bus mode. P31 General-purpose I/O port. Only enabled in single-chip mode. SCK0 D Lead strobe output pin. Only enabled during external bus mode. P32 General-purpose I/O port. SIN0 D WRH 54 56 55 57 56 58 57 HRQ General-purpose I/O port. D Write strobe output pin for upper 8-bit of data bus. Only valid if external bus mode/16-bit bus mode/WRH pin output enabled. General-purpose I/O port. D P35 10 UART0 serial data input pin. Set this to input port. Write strobe output pin for lower 8-bit of data bus. Only valid if WRL pin output is enabled, in external bus mode. P34 55 UART0 serial clock I/O pin. Only valid if UART0 serial clock I/O configuration is enabled. RD P33 53 UART0 serial data output pin. Only valid if UART0 serial data output configuration is enabled. ALE WRL 54 Power supply (0 V) input pin. General-purpose I/O port. Only enabled in single-chip mode. P30 51 Functions as external interrupt input pin. Set this to input port. Output pin for external address bus (A20 to A23) . Only valid when the bits of high address control register (HACR) are set to "0" in external bus mode. A20 to A23 50 Description Hold request input pin. Only valid if hold input is enabled, in external bus mode. General-purpose I/O port. D Hold addressing output pin. Only valid if hold input is enabled, in external bus mode. VCC Power supply (5 V) input pin. C Capacity pin for power stabilization. Please connect to an approximately 0.1 F ceramic capacitor. (Continued) HAK DS07-13713-6E MB90495G Series (Continued) Pin No. QFP- LQFP- Pin Name 64P *1 64P *2 Circuit Type P36 59 60 61 58 59 60 FRCK General-purpose I/O port. D 61 External ready input pin. Only valid if external ready input is enabled, in external bus mode. P37 General-purpose I/O port. ADTG D 62 External clock output pin. Only valid if external clock output is enabled, in external bus mode. P40 General-purpose I/O port. SIN1 D SCK1 SOT1 63 TX D 64 RX UART1 serial clock I/O pin. Only valid if UART1 clock I/O configuration is enabled. General-purpose I/O port. D UART1 serial data output pin. Only valid if UART1 serial data output configuration is enabled. General-purpose I/O port. D P44 1 UART1 serial data input pin. Set this to input port. General-purpose I/O port. P43 64 Functions as A/D converter external trigger input pin. Set this to input port. CLK P42 63 Functions as an external clock input pin for a FRCK 16-bit free-run timer. Set this to input port. RDY P41 62 Description CAN transmission output pin. Only valid if output configuration enabled. General-purpose I/O port. D CAN reception input pin. Set this to input port. *1 : FPT-64P-M06 *2 : FPT-64P-M23 DS07-13713-6E 11 MB90495G Series I/O CIRCUIT TYPE Type Circuit Remarks A X1 Clock input X1A * High speed oscillation feedback resistor : 1 M approx. * Low speed oscillation feedback resistor : 10 M approx. X0 X0A Standby control signal B * Hysteresis input with pull-up * Pull-up Resistor : 50 k approx. VCC R R Hysteresis input C Hysteresis input R Hysteresis input D VCC P-ch N-ch R Digital output * CMOS hysteresis input * CMOS level output * Standby control available Digital output VSS Hysteresis input IOL = 4 mA Standby control E VCC P-ch N-ch R Digital output * * * * CMOS hysteresis input CMOS level output Doubles as analog input pin Standby control available Digital output VSS IOL = 4 mA Hysteresis input Standby control Analog input (Continued) 12 DS07-13713-6E MB90495G Series (Continued) Type Circuit Remarks F R Hysteresis input * Hysteresis input with pull-down * Pull-down Resistor : 50 k approx. (except Flash device) R VSS DS07-13713-6E 13 MB90495G Series HANDLING DEVICES * Make sure you do not exceed the maximum rated values (in order to prevent latch-up) . * CMOS IC chips may suffer latch-up if a voltage higher than VCC or lower than VSS is applied to an input or output pin with other than mid or high current resistance; or voltage exceeding the rating is applied across VCC and VSS pins. * Latch-ups can dramatically increase the power supply current, causing thermal breakdown of the device. Make sure that you do not exceed the maximum rated value of your device, in order to prevent a latch-up. * When turning the analog power supply on or off, make sure that the analog power voltage (AVCC, AVR) and analog input voltages do not exceed the digital voltage (VCC) . * Handling Unused Pins Leaving unused input/output pins open may cause malfunctions and latch-ups, permanently damaging the device. Prevent this by connecting it to a pull-up or pull-down resistor of no less than 2 k. Leave unused input/ output pins open in output mode, or if in input mode, handle them in the same as input pins. * Notes on Using External Clock When using the external clock, drive pin X0 only, and leave pin X1 unconnected. See below for an example of external clock use. Example External Clock Use X0 Open X1 MB90495G Series * Notes on Not Using Subclock If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open. * Power Supply Pins * If your product has multiple VCC or VSS pins, pins of the same potential are internally connected in the device in order to avoid abnormal operation, including latch-up. However, you should make sure to connect the pins' external power and ground lines, in order to lower unneeded emissions, prevent abnormal operation of strobe signals due to a rise in ground levels, and maintain total output current within rated levels. * Take care to connect the VCC and VSS pins of MB90495G Series devices to power lines via the lowest possible impedance. * It is recommended that you connect a bypass capacitor of approximately 0.1 F between VCC and VSS pins near MB90495G Series device pins. * Crystal Oscillator Circuit * Noise in the vicinity of X0 and X1 pins could cause abnormal operations in MB90495G Series devices. Make sure to provide bypass capacitors via the shortest possible distance from X0 and X1 pins, crystal oscillators (or ceramic resonators) , and ground lines. In addition, design your printed circuit boards so as to keep X0 and X1 wiring from crossing other wiring, if at all possible. * It is strongly recommended that you provide printed circuit board artwork surrounding X0 and X1 pins within a grand area, as this should stabilize operation. 14 DS07-13713-6E MB90495G Series * A/D Converter Power-up and Analog Input Initiation Sequence * Make sure to power up the A/D converter and analog input (pins AN0 to AN7) after turning on digital power (VCC) . * Turn off digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage of AVR does not exceed AVCC (it is permissible to turn off analog and digital power simultaneously) . * Connecting Unused A/D Converter Pins If you are not using the A/D converter, set unused pins to AVCC = AVR = VCC, AVSS = VSS. * Notes for Powering Up Ensure that the voltage step-up time (between 0.2 V and 2.7 V) at power-up is no less than 50 s, in order to prevent malfunction in the built-in step-down circuit. * Initialization The device contains built-in registers which are only initialized by a power-on reset. Cycle the power supply to initialize these registers. * Stabilizing the Power Supply Make sure that the VCC power supply voltage is stable. Even at the rated operating VCC power supply voltage, large, sudden changes in the voltage could cause malfunctions. As a standard for stable power supply, keep VCC ripples (peak-to-peak value) at commercial power frequencies (50 Hz / 60 Hz) to no more than 10% of the power supply voltage, and momentary surges caused by switching the power supply and other events to more than 0.1 V/ms. * If Output from Ports 0/1 Becomes Undefined After power is turned on, if the RST pin is set to "H" during step-down circuit stabilization standby (during poweron reset) , ports 0 and 1 output will be undefined. If the RST pin is set to "L", ports 0 and 1 will go into a high impedance state. Take careful note of the timing of events outlined in figures 1 and 2. DS07-13713-6E 15 MB90495G Series * Figure 1 - Timing Chart of Undefined Output from Ports 0/1 (with RST pin set to "H") Time in standby for oscillation to stabilize*2 Time in standby for stepdown circuit to stabilize*1 VCC (power supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operating clock A) signal KB (internal operating clock B) signal PORT (port output) signal Time of undefined output *1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency (with 16-MHz oscillation clock frequency, about 8.19 ms) *2 : Oscillation stabilization standby time : 218/oscillation clock frequency (with 16-MHz oscillation clock frequency, about 16.38 ms) * Figure 2 - Timing Chart of High Impedance State for Ports 0/1 (when RST pin is "L") Time in standby for oscillation to stabilize*2 Step-down circuit stabilization standby time*1 VCC (power supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operating clock B) signal PORT (port output) signal High impedance *1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency (with 16-MHz oscillation clock frequency, about 8.19 ms) *2 : Oscillation stabilization standby time : 218/oscillation clock frequency (with 16-MHz oscillation clock frequency, about 16.38 ms) 16 DS07-13713-6E MB90495G Series * Caution on Operations during PLL Clock Mode If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or the clock input is stopped. Performance of this operation, however, cannot be guaranteed. * Support for TA = + 125 C If used exceeding TA = +105 C, be sure to contact us for reliability limitations. DS07-13713-6E 17 MB90495G Series BLOCK DIAGRAM X0, X1 RST X0A, X1A Clock control circuit CPU F2MC-16LX Core Watch timer 16-bit free-run timer RAM Input capture (4 ch) ROM/Flash Prescaler SOT1 SCK1 SIN1 Internal data bus Time-base timer 16-bit PPG timer (2 ch) CAN FRCK IN0 to IN3 PPG0 to PPG3 RX TX UART1 DTP/external interrupt circuit INT0 to INT7 16-bits reload timer (2 ch) TIN0, TIN1 TOT0, TOT1 External bus AD00 to AD15 A16 to A23 ALE RD WRL WRH HRQ HAK RDY CLK Prescaler SOT0 SCK0 SIN0 UART0 AVCC AVSS AN0 to AN7 AVR ADTG 18 8/10-bit A/D converter (8 ch) DS07-13713-6E MB90495G Series MEMORY MAP The memory access modes of the MB90495G Series can be set to single chip mode, internal ROM - external bus mode, and external ROM - external bus mode. 1. Memory Allocation of the MB90495G The MB90495G Series has 24-bit internal address bus and 24-bit external address bus output, enabling it to access up to 16 Mbytes of external access memory. The enable/disable time of the ROM mirror function is shown graphically in the memory map. 2. Memory Map Single chip mode (ROM mirror function available) Internal ROM External bus mode External ROM External bus mode Periphery Periphery Periphery RAM space Register RAM space Register RAM space Register Extention IO space ROM space (image of bank FF) Extention IO space ROM space (image of bank FF) Extention IO space ROM space ROM space 000000H 0000C0H 000100H Address #1 002000H 003800H 003900H Address #2 010000H Address #3 FFFFFFH Internal access memory External access memory Access prohibited Product Address #1* Address #2 Address #3* MB90V495G 001900H 004000H (FC0000H) MB90F497G 000900H 004000H FF0000H MB90497G 000900H 004000H FF0000H MB90F498G 000900H 004000H FE0000H * : Addresses #1 and #3 are product-specific. Note : When the internal ROM is operational, the ROM data in the upper address of bank 00 of the F2MC-16LX is visible in an image. This is called the ROM mirror function, and takes advantage of the small C compiler model. With the F2MC-16LX, the lower 16-bit address of bank FF and the lower 16-bit address of bank 00 are set identical to one another. This allows the ROM-internal table to be referenced without specifying a far pointer. For example, say the address "00C000H" is accessed. In actuality, the "FFC000H " address inside ROM will be accessed. However, as the ROM space in bank FF exceeds 48 Kbytes, the entire space cannot be viewed on bank 00's image. And so, since "FF4000H" to "FFFFFFH" ROM data will be visible on the "004000H" to "00FFFFH" image, save the ROM data table in the "FF4000H" to "FFFFFFH" space. DS07-13713-6E 19 MB90495G Series I/O MAP Address Register Abbreviation 000000H PDR0 000001H Register Name Access Resource Name Initial Value Port 0 data register R/W Port 0 XXXXXXXXB PDR1 Port 1 data register R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 data register R/W Port 2 XXXXXXXXB 000003H PDR3 Port 3 data register R/W Port 3 XXXXXXXXB 000004H PDR4 Port 4 data register R/W Port 4 XXXXXXXXB 000005H PDR5 Port 5 data register R/W Port 5 XXXXXXXXB 000006H PDR6 Port 6 data register R/W Port 6 XXXXXXXXB 000007H to 00000FH (system-reserved area) * 000010H DDR0 Port 0 direction register R/W Port 0 0 0 0 0 0 0 0 0B 000011H DDR1 Port 1 direction register R/W Port 1 0 0 0 0 0 0 0 0B 000012H DDR2 Port 2 direction register R/W Port 2 0 0 0 0 0 0 0 0B 000013H DDR3 Port 3 direction register R/W Port 3 0 0 0 0 0 0 0 0B 000014H DDR4 Port 4 direction register R/W Port 4 XXX 0 0 0 0 0B 000015H DDR5 Port 5 direction register R/W Port 5 0 0 0 0 0 0 0 0B 000016H DDR6 Port 6 direction register R/W Port 6 XXXX 0 0 0 0B 8/10-bit A/D converter 1 1 1 1 1 1 1 1B 000017H to 00001AH 00001BH (system-reserved area) * ADER Analog input enable register 00001CH to 00001FH R/W (system-reserved area) * 000020H SMR0 Serial mode register 0 R/W 0 0 0 0 0 0 0 0B 000021H SCR0 Serial control register 0 R/W 0 0 0 0 0 1 0 0B 000022H SIDR0/ SODR0 Serial input data register 0/ Serial output data register 0 R/W Serial status register 0 R/W Communication prescaler control register 0 R/W 0 XXX 1 1 1 1B XXXXXXXXB UART0 000023H SSR0 000024H CDCR0 000025H SES0 Serial edge selection register 0 R/W XXXXXXX 0B 000026H SMR1 Serial mode register 1 R/W 0 0 0 0 0 0 0 0B 000027H SCR1 Serial control register 1 R/W 000028H SIDR1/ SODR1 Serial input data register 1/ Serial output data register 1 R/W UART1 0 0 0 0 1 X 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB (Continued) 20 DS07-13713-6E MB90495G Series Address Register Abbreviation 000029H SSR1 Register Name Serial status register 1 00002AH 00002BH Access Resource Name Initial Value R/W UART1 0 0 0 0 1 0 0 0B UART1 0 XXX 0 0 0 0B (system-reserved area) * CDCR1 Communication prescaler control register 1 00002CH to 00002FH R/W (system-reserved area) * 000030H ENIR DTP/external interrupt enable register R/W 000031H EIRR DTP/external interrupt condition register R/W ELVR Detection level configuration register ADCS A/D control status register 000032H 000033H 000034H 000035H 000036H 000037H ADCR 000038H to 00003FH 000040H R/W 0 0 0 0 0 0 0 0B R/W PPGC0 PPG0 operation mode control register PPG01 PPG0/1 count clock selection register R/W 000043H PPGC2 PPG2 operation mode control register 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 XXB R/W PPGC3 PPG3 operation mode control register R/W 000046H PPG23 PPG2/3 count clock selection register R/W 000047H to 00004FH 0 X 0 0 0 XX 1B 8/16-bit PPG timer 2/3 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 XXB (system-reserved area) * IPCP0 Input capture data register 0 R IPCP1 Input capture data register 1 R 000054H ICS01 000055H ICS23 000057H 0 X 0 0 0 XX 1B 8/16-bit PPG timer 0/1 (system-reserved area) * 000045H 000056H XXXXXXXXB 0 0 1 0 1 XXXB R/W 000042H 000053H 0 0 0 0 0 0 0 0B (system-reserved area) * R/W 000052H 8/10-bit A/D converter R/W PPG1 operation mode control register 000051H 0 0 0 0 0 0 0 0B R/W PPGC1 000050H XXXXXXXXB 0 0 0 0 0 0 0 0B 000041H 000044H DTP/external interrupt R/W R A/D data register 0 0 0 0 0 0 0 0B TCDT XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit I/O timer Input capture control status register R/W Timer counter data register R/W XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Continued) DS07-13713-6E 21 MB90495G Series Address 000058H 000059H 00005AH 00005BH 00005CH 00005DH Register Abbreviation Register Name Access TCCS Timer counter control status register R/W IPCP2 Input capture data register 2 R IPCP3 Input capture data register 3 R 00005EH to 000065H 000066H 000067H 000068H 000069H R/W TMCSR0 Timer control status register TMCSR1 ROMM ROM mirror function selection register BVALR TREQR TCANR TCR RCR XXXXXXXXB R/W 16-bit reload timer 0 16-bit reload timer 1 0 0 0 0 0 0 0 0B XXXX0 0 0 0B 0 0 0 0 0 0 0 0B XXXX0 0 0 0B W ROM mirror function selection module XXXXXXX 1B Message buffer valid register R/W CAN controller 0 0 0 0 0 0 0 0B Send request register R/W CAN controller 0 0 0 0 0 0 0 0B Send cancel register W CAN controller 0 0 0 0 0 0 0 0B Send complete register R/W CAN controller 0 0 0 0 0 0 0 0B Reception complete register R/W CAN controller 0 0 0 0 0 0 0 0B CAN controller 0 0 0 0 0 0 0 0B CAN controller 0 0 0 0 0 0 0 0B CAN controller 0 0 0 0 0 0 0 0B (system-reserved area) * RRTRR Reception RTR register R/W (system-reserved area) * ROVRR 00008DH 00008EH XXXXXXXXB (system-reserved area) * 00008BH 00008CH XXXXXXXXB (system-reserved area) * 000089H 00008AH XXXXXXXXB (system-reserved area) * 000087H 000088H 16-bit I/O timer (system-reserved area) * 000085H 000086H 0 XXXXXXXB (system-reserved area) * 000083H 000084H 0 0 0 0 0 0 0 0B (system-reserved area) * 000081H 000082H R/W R/W 000070H to 00007FH 000080H Initial Value (system-reserved area) * 00006AH to 00006EH 00006FH Resource Name Reception overrun register R/W (system-reserved area) * RIER Reception complete interrupt enable register R/W (Continued) 22 DS07-13713-6E MB90495G Series Address Register Abbreviation 00008FH to 00009DH Register Name Access Resource Name Initial Value (system-reserved area) * Address detection control register R/W ROM correction function 0 0 0 0 0 0 0 0B Delayed interrupt request generate/ cancel register R/W Delayed interrupt generation module XXXXXXX 0B LPMCR Low power consumption mode control register R/W CKSCR Clock selection register R/W 00009EH PACSR 00009FH DIRR 0000A0H 0000A1H 0000A2H to 0000A4H Low-power 0 0 0 1 1 0 0 0B consumption modes Clock 1 1 1 1 1 1 0 0B (system-reserved area) * 0000A5H ARSR Auto ready function selection register W 0000A6H HACR High address control register W 0 0 1 1 XX 0 0B 0 0 0 0 0 0 0 0B External access ECSR Bus control signal selection register 0000A8H WDTC Watchdog timer control register R/W Watchdog timer XXXXX 1 1 1B 0000A9H TBTC Time-base timer control register R/W Time-base timer 1 XX 0 0 1 0 0B 0000AAH WTC Watch timer control register R/W Watch timer 1 X 0 0 1 0 0 0B 512-Kbit flash memory 0 0 0 X 0 0 0 0B 0000ABH to 0000ADH 0000AEH W 0 0 0 0 0 0 0 XB or 0 0 0 0 1 0 0 XB 0000A7H (system-reserved area) * FMCS 0000AFH Flash memory control status register R/W (system-reserved area) * 0000B0H ICR00 Interrupt control register 00 R/W 0 0 0 0 0 1 1 1B 0000B1H ICR01 Interrupt control register 01 R/W 0 0 0 0 0 1 1 1B 0000B2H ICR02 Interrupt control register 02 R/W 0 0 0 0 0 1 1 1B 0000B3H ICR03 Interrupt control register 03 R/W 0 0 0 0 0 1 1 1B 0000B4H ICR04 Interrupt control register 04 R/W 0 0 0 0 0 1 1 1B 0000B5H ICR05 Interrupt control register 05 R/W 0000B6H ICR06 Interrupt control register 06 R/W 0 0 0 0 0 1 1 1B 0000B7H ICR07 Interrupt control register 07 R/W 0 0 0 0 0 1 1 1B 0000B8H ICR08 Interrupt control register 08 R/W 0 0 0 0 0 1 1 1B 0000B9H ICR09 Interrupt control register 09 R/W 0 0 0 0 0 1 1 1B 0000BAH ICR10 Interrupt control register 10 R/W 0 0 0 0 0 1 1 1B Interrupt controller 0 0 0 0 0 1 1 1B (Continued) DS07-13713-6E 23 MB90495G Series Address Register Abbreviation 0000BBH ICR11 Interrupt control register 11 R/W 0 0 0 0 0 1 1 1B 0000BCH ICR12 Interrupt control register 12 R/W 0 0 0 0 0 1 1 1B 0000BDH ICR13 Interrupt control register 13 R/W 0000BEH ICR14 Interrupt control register 14 R/W 0 0 0 0 0 1 1 1B 0000BFH ICR15 Interrupt control register 15 R/W 0 0 0 0 0 1 1 1B Register Name 0000C0H to 0000FFH Access Resource Name Interrupt controller Initial Value 0 0 0 0 0 1 1 1B (system-reserved area) * Detection address configuration register 0 (lower) R/W XXXXXXXXB Detection address configuration register 0 (mid) R/W XXXXXXXXB 001FF2H Detection address configuration register 0 (upper) R/W 001FF3H Detection address configuration register 1 (lower) R/W Detection address configuration register 1 (mid) R/W XXXXXXXXB Detection address configuration register 1 (upper) R/W XXXXXXXXB TMR0/ TMRLR0 16-bit timer register 0/ 16-bit reload register 0 R/W 16-bit reload timer 0 TMR1/ TMRLR1 16-bit timer register 1/ 16-bit reload register 1 R/W 16-bit reload timer 1 001FF0H 001FF1H 001FF4H PADR0 PADR1 001FF5H 003900H 003901H 003902H 003903H 003904H to 00390FH ROM correction function XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (system-reserved area) * 003910H PRLL0 PPG0 reload register L R/W XXXXXXXXB 003911H PRLH0 PPG0 reload register H R/W XXXXXXXXB 003912H PRLL1 PPG1 reload register L R/W XXXXXXXXB 003913H PRLH1 PPG1 reload register H R/W 003914H PRLL2 PPG2 reload register L R/W 003915H PRLH2 PPG2 reload register H R/W XXXXXXXXB 003916H PRLL3 PPG3 reload register L R/W XXXXXXXXB 003917H PRLH3 PPG3 reload register H R/W XXXXXXXXB 003918H to 003BFFH 003C00H to 003C0FH 8/16-bit PPG timer XXXXXXXXB XXXXXXXXB (system-reserved area) * RAM (general-purpose RAM) (Continued) 24 DS07-13713-6E MB90495G Series Address Register Abbreviation 003C10H to 003C13H IDR0 ID register 0 R/W XXXXXXXXB to XXXXXXXXB 003C14H to 003C17H IDR1 ID register 1 R/W XXXXXXXXB to XXXXXXXXB 003C18H to 003C1BH IDR2 ID register 2 R/W XXXXXXXXB to XXXXXXXXB 003C1CH to 003C1FH IDR3 ID register 3 R/W XXXXXXXXB to XXXXXXXXB 003C20H to 003C23H IDR4 ID register 4 R/W XXXXXXXXB to XXXXXXXXB 003C24H to 003C27H IDR5 ID register 5 R/W XXXXXXXXB to XXXXXXXXB 003C28H to 003C2BH IDR6 ID register 6 R/W XXXXXXXXB to XXXXXXXXB 003C2CH to 003C2FH IDR7 ID register 7 R/W 003C30H, 003C31H DLCR0 DLC register 0 R/W XXXXXXXXB XXXXXXXXB 003C32H, 003C33H DLCR1 DLC register 1 R/W XXXXXXXXB XXXXXXXXB 003C34H, 003C35H DLCR2 DLC register 2 R/W XXXXXXXXB XXXXXXXXB 003C36H, 003C37H DLCR3 DLC register 3 R/W XXXXXXXXB XXXXXXXXB 003C38H, 003C39H DLCR4 DLC register 4 R/W XXXXXXXXB XXXXXXXXB 003C3AH, 003C3BH DLCR5 DLC register 5 R/W XXXXXXXXB XXXXXXXXB 003C3CH, 003C3DH DLCR6 DLC register 6 R/W XXXXXXXXB XXXXXXXXB 003C3EH, 003C3FH DLCR7 DLC register 7 R/W XXXXXXXXB XXXXXXXXB 003C40H to 003C47H DTR0 Data register 0 R/W XXXXXXXXB to XXXXXXXXB Register Name Access Resource Name CAN controller Initial Value XXXXXXXXB to XXXXXXXXB (Continued) DS07-13713-6E 25 MB90495G Series Address Register Abbreviation 003C48H to 003C4FH DTR1 Data register 1 R/W XXXXXXXXB to XXXXXXXXB 003C50H to 003C57H DTR2 Data register 2 R/W XXXXXXXXB to XXXXXXXXB 003C58H to 003C5FH DTR3 Data register 3 R/W XXXXXXXXB to XXXXXXXXB 003C60H to 003C67H DTR4 Data register 4 R/W 003C68H to 003C6FH DTR5 Data register 5 R/W XXXXXXXXB to XXXXXXXXB 003C70H to 003C77H DTR6 Data register 6 R/W XXXXXXXXB to XXXXXXXXB 003C78H to 003C7FH DTR7 Data register 7 R/W XXXXXXXXB to XXXXXXXXB Register Name 003C80H to 003CFFH Access CSR Control status register R/W 003D02H LEIR Display last event register R/W 003D03H RTEC 003D06H, 003D07H BTR Bit timing register R/W 003D08H IDER IDE register R/W Receive/transmit error counter 003D09H CAN controller 0 XXXX 0 0 1B 0 0 XXX 0 0 0B 0 0 0 XX 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R CAN controller 1 1 1 1 1 1 1 1B X 1 1 1 1 1 1 1B XXXXXXXXB (system-reserved area) * TRTRR 003D0BH Transmit RTR register R/W CAN controller 0 0 0 0 0 0 0 0B CAN controller XXXXXXXXB CAN controller 0 0 0 0 0 0 0 0B (system-reserved area) * RFWTR 003D0DH 003D0EH XXXXXXXXB to XXXXXXXXB (system-reserved area) * 003D04H, 003D05H 003D0CH CAN controller Initial Value (system-reserved area) * 003D00H, 003D01H 003D0AH Resource Name Remote frame reception standby register R/W (system-reserved area) * TIER Transmit complete interrupt enable register R/W (Continued) 26 DS07-13713-6E MB90495G Series (Continued) Address Register Abbreviation Register Name 003D0FH 003D10H, 003D11H Access Resource Name Initial Value CAN controller XXXXXXXXB XXXXXXXXB (system-reserved area) * AMSR Acceptance mask selection register 003D12H, 003D13H R/W (system-reserved area) * 003D14H to 003D17H AMR0 003D18H to 003D1BH AMR1 Acceptance mask register 0 R/W CAN controller Acceptance mask register 1 003D1CH to 003FFFH R/W XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB (system-reserved area) * Explanation of reset values 0 : The reset value of this bit is 0. 1 : The reset value of this bit is 1. X : The reset value of this bit is undefined. * : System-reserved area contains system-internal addresses, and cannot be used. DS07-13713-6E 27 MB90495G Series INTERRUPT CONDITIONS AND INTERRUPT VECTOR/REGISTER Interrupt Condition EI2OS Compatible Interrupt Vector Number Interrupt Register Address ICR Address Priority *3 Reset x #08 08H FFFFDCH Highest INT 9 instruction x #09 09H FFFFD8H Exception processing x #10 0AH FFFFD4H Can controller reception complete (RX) x #11 0BH FFFFD0H Can controller reception complete (TX) / Node status transition (NS) x #12 0CH FFFFCCH Reserved x #13 0DH FFFFC8H Reserved x #14 0EH FFFFC4H #15 0FH FFFFC0H #16 10H FFFFBCH 16-bit reload timer 0 #17 11H FFFFB8H 8/10-bit A/D converter #18 12H FFFFB4H 16-bit free-run timer overflow #19 13H FFFFB0H External interrupt (INT2/INT3) #20 14H FFFFACH External interrupt (INT0/INT1) Time-base timer x Reserved x #21 15H FFFFA8H PPG timer ch.0, ch.1 underflow x #22 16H FFFFA4H Input capture 0 load #23 17H FFFFA0H External interrupt (INT4/INT5) #24 18H FFFF9CH Input capture 1 load #25 19H FFFF98H #26 1AH FFFF94H External interrupt (INT6/INT7) #27 1BH FFFF90H Watch timer #28 1CH FFFF8CH PPG timer ch.2, ch.3 underflow x Reserved x #29 1DH FFFF88H Input capture 2 load Input capture 3 load x #30 1EH FFFF84H Reserved x #31 1FH FFFF80H Reserved x #32 20H FFFF7CH Reserved x #33 21H FFFF78H Reserved x #34 22H FFFF74H Reserved x #35 23H FFFF70H 16-bit reload timer 1 #36 24H FFFF6CH UART1 reception complete #37 25H FFFF68H UART1 transmission complete #38 26H FFFF64H ICR00 0000B0H (*1) ICR01 0000B1H ICR02 0000B2H (*1) ICR03 0000B3H (*1) ICR04 0000B4H (*1) ICR05 0000B5H (*2) ICR06 0000B6H (*1) ICR07 0000B7H (*1) ICR08 0000B8H (*1) ICR09 0000B9H (*1) ICR10 0000BAH (*1) ICR11 0000BBH (*1) ICR12 0000BCH (*1) ICR13 0000BDH (*1) (Continued) 28 DS07-13713-6E MB90495G Series (Continued) Interrupt Condition EI2OS Compatible Interrupt Vector Number Address UART0 reception complete #39 27H FFFF60H UART0 transmission complete #40 28H FFFF5CH Flash memory x #41 29H FFFF58H Delayed interrupt generation module x #42 2AH FFFF54H Interrupt Register ICR Address Priority *3 ICR14 0000BEH (*1) ICR15 0000BFH (*1) Lowest : Available x : Not available : Available, EI2OS halt function supplied : Available for interrupt conditions not shared by ICR *1 : * The interrupt level is the same for peripheral devices sharing the ICR register. * Peripheral devices that share the ICR register and use the extended intelligent I/O service only utilize one set. * If one side of a peripheral device sharing the ICR register is set to extended intelligent I/O service, the other side cannot use interrupts. *2 : Only the 16-bit reload timer is compatible with EI2OS. Since PPG does not support EI2OS, if you use EI2OS with the 16-bit reload timer, prohibit interrupts by PPG. *3 : Priority if two or more interrupts with the same level are generated simultaneously. DS07-13713-6E 29 MB90495G Series PERIPHERAL RESOURCES 1. I/O Port (1) Overview General-purpose (parallel) I/O ports can be used as the I/O ports. The MB90495G Series has 7 ports (49) . Each port doubles as a peripheral device I/O pin. * I/O Port Features I/O ports output data to I/O pins and load signals input to them, by means of the port data register (PDR) . Additionally, the port direction register (DDR) sets the I/O direction of the I/O pins at the bit level. Below is a description of each pin's function, and the peripheral device that shares it. * Port 0 : general-purpose I/O port/doubles as external address data bus pin * Port 1 : general-purpose I/O port/doubles as PPG timer output, input capture input, and external address data bus pin * Port 2 : general-purpose I/O port/doubles as reload timer I/O, external interrupt input pin, and external address bus pin * Port 3 : general-purpose I/O port/doubles as UART0 I/O, free-run timer, and A/D converter startup trigger pin * Port 4 : general-purpose I/O port/doubles as UART1 I/O, and CAN controller transmit/receive pin * Port 5 : general-purpose I/O port/doubles as analog input pin * Port 6 : general-purpose I/O port/doubles as external interrupt input pin 30 DS07-13713-6E MB90495G Series * Pin Block Diagram for Port 0 (single chip mode) PDR (port data register) Internal data bus PDR read Output latch P-ch PDR write Pin DDR (port direction register) Direction latch N-ch DDR write Standby control (SPL = 1) DDR read Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) and watch mode (SPL = 1) * Port 0 register (single chip mode) * The port 0 register contains the port 0 data register (PDR0) and the port 0 direction register (DDR0) . * The bits making up the register are in a one-to-one relation to the port 0 pin. Compatibility between port 0 register and pin Port Name Related register bit and corresponding pin Port 0 DS07-13713-6E PDR0, DDR0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin P07 P06 P05 P04 P03 P02 P01 P00 31 MB90495G Series * Block Diagram for Pins of Ports 1, 2, 3 and 4 (single-chip mode) Peripheral device input Peripheral device output Port data register (PDR) Peripheral device output enabled Internal data bus PDR read Output latch P-ch PDR write Pin Port direction register (DDR) Direction latch N-ch DDR write Standby control (SPL = 1) DDR read Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) and watch mode (SPL = 1) * Port 1 register (single-chip mode) * The port1 register contains the port 1 data register (PDR1) and the port 1 direction register (DDR1) . * The bits making up the register are in a one-to-one relationship with the port 1 pins. Port 1 Register and Corresponding Pins Port Name Related register bit and corresponding pin Port 1 32 PDR1, DDR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10 DS07-13713-6E MB90495G Series * Port 2 register * The port2 register contains the port 2 data register (PDR2) , the port 2 direction register (DDR2) and the high address control register (HACR). * The high address control register (HACR) enables or disables the output of external addresses (A16 to A23). When the register enables the output of the external addresses, the port can not be used as a peripheral device and a general-purpose I/O port. * The bits making up the register are in a one-to-one relationship with the port 2 pins. Port 2 Register and Corresponding Pins Port Name Related register bit and corresponding pin Port 2 PDR2, DDR2, HACR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin P27 P26 P25 P24 P23 P22 P21 P20 * Port 3 register * The port3 register contains the port 3 data register (PDR3) and the port 3 direction register (DDR3) . * The bus control signal selection register (ECSR) enables or disables the input and output of external bus control signals (WRL / WRH, HRQ / HAK, RDY, CLK). When the register enables the input and output of the external bus control signals, the port can not be used as a peripheral device and a general-purpose I/O port. * The bits making up the register are in a one-to-one relationship with the port 3 pins. Port 3 Register and Corresponding Pins Port Name Related register bit and corresponding pin Port 3 PDR3, DDR3 bit7 bit6 ECSR CKE RYE Corresponding pin P37 P36 bit5 bit4 bit3 HDE P35 bit2 bit1 WRE P34 P33 bit0 P32 P31 P30 * Port 4 register * The port4 register contains the port 4 data register (PDR4) and the port 4 direction register (DDR4) . * The bits making up the register are in a one-to-one relationship with the port 4 pins. Port 4 Register and Corresponding Pins Port Name Related register bit and corresponding pin Port 4 DS07-13713-6E PDR4, DDR4 bit4 bit3 bit2 bit1 bit0 Corresponding pin P44 P43 P42 P41 P40 33 MB90495G Series * Block Diagram of Port 5 Pins Analog input ADER Internal data bus Port data register (PDR) PDR read Output latch P-ch PDR write Pin Port direction register (DDR) Direction latch N-ch DDR write Standby control (SPL = 1) DDR read Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) , and watch mode (SPL = 1) * Port 5 register * The port 5 register contains the port 5 data register (PDR5) , the port 5 direction register (DDR5) and the analog input enable register (ADER) . * The analog data enable register (ADER) enables or disables the input of analog signals by the analog input pin. * The bits making up the register are in a one-to-one correspondence with the pins of port 5. Port 5 Register and Corresponding Pins Port Name Related register bit and corresponding pin PDR5, DDR5 Port 5 ADER Corresponding pin 34 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 P57 P56 P55 P54 P53 P52 P51 P50 DS07-13713-6E MB90495G Series * Block Diagram of Port 6 Pins Peripheral device input Port data register (PDR) Internal data bus PDR read Output latch P-ch PDR write Pin Port direction register (DDR) Direction latch N-ch DDR write Standby control (SPL = 1) DDR read Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) , and watch mode (SPL = 1) * Port 6 register * The port 6 register contains the port 6 data register (PDR6) and the port 6 direction register (DDR6) . * The bits making up the register are in a one-to-one relationship with the port 6 pins. Port 6 Register and Corresponding Pins Port Name Related register bit and corresponding pin Port 6 DS07-13713-6E PDR6, DDR6 Corresponding pin bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P63 P62 P61 P60 35 MB90495G Series 2. Time-base Timer The time-base timer is an 18-bit free-run counter (time-base counter) for counting up in synchronization with the main clock (1/2 main oscillation clock) . * Four interval times are available, and interrupt requests can be generated for each interval time. * The time-base timer also has a function for supplying timers for oscillation stabilize standby time and operating clocks for peripheral devices. * Interval timer feature * When the time-base timer counter reaches the interval set by the interval time selection bits (TBTC : TBC1, TBC0) , it generates an overflow (TBTC : TBOF = 1) and interrupt request. * If the interrupts due to overflow generation are enabled (TBTC : TBIE = 1) , when an overflow is generated (TBTC : TBOF = 1) , an interrupt is generated. * Select from the following 4 time-base timer intervals : Time-base timer interval times Count Clock Interval Time 212/HCLK (approx. 1.0 ms) 214/HCLK (approx. 4.1 ms) 2/HCLK (0.5 s) 216/HCLK (approx. 16.4 ms) 219/HCLK (approx. 131.1 ms) HCLK : oscillation clock The number in parentheses ( ) for 4-MHz oscillation clock operation * Time-base Timer Block Diagram To PPG timer To watchdog timer Time-base timer counter 21/HCLK x 21 x 22 x 23 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF Power-on Reset Stop Mode CKSCR : MCS = 1 0*1 CKSCR : SCS = 0 1*2 To clock controller oscillation stabilize standby time selector Clear counter circuit Time-base timer control register (TBTC) Interval Timer selector Clear TBOF Reserved Set TBOF TBIE TBOF TBR TBC1 TBC0 Time-base timer interrupt signal OF HCLK *1 *2 : overflow : oscillation clock : Switch machine clock from main clock to PLL clock : Switch machine clock from subclock to main clock See below for the actual interrupt request number of the time-base timer : Interrupt request number : #16 (10H) 36 DS07-13713-6E MB90495G Series 3. Watchdog Timer The watchdog timer is a 2-bit timer used as a count clock for the timer-based or watch timer. If the counter is not cleared within the interval time, it resets the CPU. * Watchdog Timer Function * The watchdog timer is a timer counter used to deal with runaway programs. Once the watchdog timer is launched, it is necessary to keep clearing its counter within the specified interval. If the specified interval passes without the watchdog timer counter being cleared, the CPU will be reset. This feature is called the watchdog timer. * The watchdog timer interval traces back to the clock interval input as the count clock. A watchdog reset is generated for the smallest to largest times. * The clock source output destination is set by the watchdog clock selection bit of the watch timer control register (WTC : WDCS) . * The watchdog timer interval is set time-base timer output selection bit/watch timer output selection bit of the watchdog timer control register (WDTC : WT1, WT0) . Watchdog Timer Intervals Minimum Maximum Clock Interval Minimum Maximum Clock Interval Approx. 3.58 ms Approx. 4.61 ms 214 211/ HCLK Approx. 0.457 s Approx. 0.576 s 212 29/ SCLK Approx. 14.33 ms Approx. 18.3 ms 216 213/ HCLK Approx. 3.584 s Approx. 4.608 s 215 212/ SCLK Approx. 57.23 ms Approx. 73.73 ms 218 215/ HCLK Approx. 7.168 s Approx. 9.216 s 216 213/ SCLK 221 218/ Approx. 14.336 s Approx. 18.432 s HCLK HCLK : oscillation clock (4 MHz) ; SCLK : Subclock (8.192 kHz) Approx. 458.75 ms Approx. 589.82 ms 217 214/ SCLK Notes: * If the count clock of the watchdog timer is set to time-base timer output (overflow signal) , then clearing the time-base timer could make it take longer to reset the watchdog. * If you are using a subclock as the machine clock, make sure to select watch timer output by setting the watchdog timer clock source selection bit (WDCS) of the watch timer control register (WTC) to 0. DS07-13713-6E 37 MB90495G Series * Watchdog Timer Block Diagram Watch timer control register (WTC) Watchdog timer control register (WDTC) PONR Watchdog timer WRST ERST SRST WTE WT1 WT0 WDCS 2 Launch Reset generation Go to sleep mode Go to time-base timer mode Counter clear control circuit Counter clock selector Go to watch mode Go to stop mode 2-bit counter Watchdog reset generation circuit To internal reset generation circuit Clear 4 4 (Time-base timer counter) Main clock (1/2 HCLK) x 2 1 x 22 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 (Clock counter) Subclock SCLK x 21 x 22 x 25 x 26 x 27 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 HCLK : Oscillation clock SCLK : Subclock 38 DS07-13713-6E MB90495G Series 4. 16-bit I/O Timer The 16-bit I/O timer is a complex module comprising one 16-bit free-run timer, and two input capture units (4 input pins) . Clock interval input signals and pulse widths can be measured based on the 16-bit free-run timer. * 16-bit I/O Timer Configuration The 16-bit I/O timer is made up of the following modules : * One 16-bit free-run timer * Two input capture units (each unit having 2 input pins) * 16-bit I/O Timer Function (1) 16-bit free-run timer function The 16-bit free-run timer consists of a 16-bit up counter, a time counter control status register, and prescaler. The 16-bit up counter counts up in synchronization with a fraction of the machine clock. * The count clock can be set to one of eight fractions of the machine clock. The external clock signals input to the 16-bit free-run timer clock input pin (FRCK) can be used as the count clock. * Interrupts can be generated in response to counter value overflows. * Interrupts launch the extended intelligent I/O service (EI2OS) . * The count value of the 16-bit free-run timer can be cleared to "0000H" by either a reset, or software clear via the timer count clear bit (TCCS : CLR) . * The count value of the 16-bit free-run timer is output to the input capture, and used as the base time for capture operation. (2) Input Capture Function When the input capture detects that an external signal edge has been input to an input pin, it stores the count value of the 16-bit free-run timer in the input capture data register, for the point at which the edge was detected. The input capture consists of an input capture register corresponding to four I/O pins, an input capture control status register, and an edge detection circuit. * When an edge is detected, either rising, falling, or both can be selected. * An interrupt request can be generated to the CPU when an input signal edge is detected. * Interrupts launch the extended intelligent I/O service (EI2OS) . * Since the input capture has four pairs of input pins and input capture data registers, it can measure up to 4 phenomena. * Block Diagram of 16-bit I/O Timer Internal data bus Input capture Dedicated bus 16-bit free-run timer 16-bit free-run timer: The counter value of the 16-bit free-run timer is used as the base time of the input capture. Input capture: Input capture detects rising, falling and both edges for external signals input to input pins, and stores the counter value of the 16-bit free-run timer. Interrupts can be generated in response to input signal edge detection. DS07-13713-6E 39 MB90495G Series * Block Diagram of 16-bit Free-run Timer Output count value to input capture Timer counter data register (TCDT) FRCK OF CLK STOP Internal data bus 16-bit free-run timer Pin CLR Prescaler 2 Timer counter control status register (TCCS) IVF IVFE STOP Re- CLR CLK2 CLK1 CLK0 served Free-run timer interrupt request OF : Machine clock : overflow Note: The 16-bit I/O timer contains one 16-bit free-run timer. The interrupt request number of the 16-bit free-run timer is as follows : Interrupt request number : 19 (13H) Prescaler: Takes a fraction of the machine clock, and supplies a count clock to the 16-bit up-counter. One of four machine clock fractions can be selected by setting the timer counter control status register (TCCS) . Timer Counter Register (TCDT) : This is a 16-bit up-counter. It is possible to read the current counter value of the 16-bit free-run timer by reading this counter. The counter can be set to an arbitrary value by writing to it while stopped. Timer Counter Control Status Register (TCCS) : TCCS selects the divide ratio of a machine clock, executes software clear of counter values. and enables or disables counter operation. Also TCCS confirms and clears an overflow generation flag, and enables or disables interruption. 40 DS07-13713-6E MB90495G Series * Input Capture Block Diagram 16-bit free-run timer Edge detection circuit IN3 Pin Input capture data register 3 (IPCP3) IN2 Pin Input capture data register 2 (IPCP2) 2 2 Input capture interrupt request Input capture control status register (ICS01) Internal data bus Input capture control status register ICP1 ICP0 ICE1 ICE0 EG11EG10EG01EG00 (ICS23) ICP1 ICP0 ICE1 ICE0 EG11EG10EG01EG00 2 2 IN1 Pin Input capture data register 1 (IPCP1) IN0 Pin Input capture data register 0 (IPCP0) Edge detection circuit DS07-13713-6E 41 MB90495G Series 5. 16-bit Reload Timer The functions of the 16-bit reload timer are as follows : * Choose one of three internal clocks or an external event clock as the count clock. * Choose a software or external launch trigger. * An interrupt can be sent to the CPU in response to an underflow generated by the 16-bit timer register. Interrupts can be used to utilize the timer as an interval timer. * When an underflow is generated by the 16-bit timer register (TMR) , select one-shot mode, where TMR counter operation is halted, or reload mode, where the 16-bit reload register value is reloaded, and TMR count operation continues. * Supports extended intelligent I/O service (EI2OS) . * The MB90495G Series features two on-chip 16-bit reload timer channels. * 16-bit Reload Timer Operation Mode Count Clock Launch Trigger Operation in Case of Underflow Internal clock mode Software trigger External trigger One-shot mode Reload mode Event count mode Software trigger One-shot mode Reload mode * Internal Clock Mode * Set the count clock selection bits of the timer control status register (TMCSR : CSL1, CSL0) to "00B", "01B" or "10B" to set the 16-bit reload timer to internal clock mode. * In internal clock mode, the timer counts down in synchronization with the internal clock. * Set the count clock selection bits of the timer control status register (TMCSR : CSL1, CSL0) to select one of three count clock intervals. * Select software-triggered or externally triggered (edge detection) launch. 42 DS07-13713-6E MB90495G Series * 16-bit Reload Timer Block Diagram Internal data bus TMRLR 16-bit reload register Reload signal Reload control circuit TMR UF 16-bit timer register CLK Count clock generation circuit Machine clock Prescaler Gate input 3 Valid clock determination circuit Wait signal Output to on-chip peripheral functions Clear Internal clock CLK Clock selector I/O control circuit Pin TIN External clock 3 2 Select function Output control circuit Output signal generation circuit Pin EN TOT Select signal Operation control circuit CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TMCSR) Output interrupt request DS07-13713-6E 43 MB90495G Series 6. Watch Timer The watch timer is a 15-bit free-run counter that counts up in synchronization with the subclock. * Eight different intervals can be selected, and interrupt requests generated for each interval time. * Supplies a timer for subclock oscillation stabilization standby, and an operational clock for the watchdog timer. * The subclock is always the count clock, regardless of the clock selection register (CKSCR) setting. * Interval timer feature * When the interval time set by the interval time selection bits (WTC : WTC2 to WTC0) is reached, the clock timer generates an overflow in the bits corresponding to the interval time of the watch timer counter, and sets the overflow flag bit (WTC : WTOF = 1) . * Interrupts arising from overflows are enabled (WTC : WTIE = 1) , an interrupt request is generated when the overflow flag bit is set (WTC : WTOF = 1) . * Select from one of the following 8 watch timer intervals : Clock Timer Interval Times Subclock Frequency Interval Time 8 2 /SCLK (31.25 ms) 29/SCLK (62.5 ms) 210/SCLK (125 ms) 1/SCLK (122 s) 211/SCLK (250 ms) 212/SCLK (500 ms) 213/SCLK (1.0 s) 214/SCLK (2.0 s) 215/SCLK (4.0 s) SCLK : Subclock frequency Figures in parentheses ( ) are a sample calculation with the subclock running at 8.192 kHz. 44 DS07-13713-6E MB90495G Series * Watch Timer Block Diagram To watchdog timer Watch timer counter x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 SCLK OF OF OF OF OF OF OF OF Power-on reset Go to hardware standby Counter clear circuit To subclock oscillation stabilization standby time Go to stop mode Interval timer selector Watch timer interrupt WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Watch timer control register (WTC) OF : Overflow SCLK : Subclock Notes: The actual interrupt request number generated by the watch timer is as follows : Interrupt request number : #28 (1CH) Watch timer counter: 15-bit up counter using the subclock (SCLK) as its count clock. Counter clear circuit: This circuit clears the watch timer counter. DS07-13713-6E 45 MB90495G Series 7. 8/16-Bit PPG The 8/16-bit PPG timer is a 2-channel reload timer module (PPG0, PPG1) capable of arbitrary synchronization and pulse output of duty ratio. Combining the 2 channel module can yield the following behavior : * 8-bit PPG output, 2-channel independent operation mode * 16-bit PPG output operation mode * 8 + 8-bit PPG output operation mode The MB90495G Series features two on-chip, 8/16-bit PPG timers. This section describes the functions of PPG0/ 1. PPG2/3 has the same functions as PPG0/1. * 8/16-bit PPG Timer Functions The 8/16-bit PPG timer is made up of four 8-bit reload registers (PRLH0/PRLL0, PRLH1/PRLL1) , and two PPG down counters (PCNT0, PCNT1) . * Since you can set each output pulse to "H" or "L" width independently, the interval and duty ratio of each pulse can be set to an arbitrary value. * Select one of 6 internal clocks as the count clock. * Interrupt requests can be generated for each interval time, allowing the timer to be used as an interval timer. * The use of an external circuit allows the timer to be used as a D/A converter. 46 DS07-13713-6E MB90495G Series * Block Diagram of 8/16-Bit PPG Timer 0 "H" level side data bus "L" level side data bus PPG0 reload register PRLH0 ("H" level side) PPG0 operation mode control register (PPGC0) PRLL0 ("L" level side) PEN0 PE0 PIE0 PUF0 Output interrupt request* R PPG0 temporary buffer 0 (PRLBH0) S Q 2 Operation mode control signal Select signal Reload register L/H selector Initial count value Reserved Reload PPG0 underflow PPG1 underflow (to PPG1) Clear Pulse selector PPG0 down counter (PCNT0) Underflow CLK Invert PPG0 output latch Pin PPG0 PPG output control circuit Time-base timer output (512/HCLK) Peripheral clock (1/) Peripheral clock (2/) Peripheral clock (4/) Peripheral clock (8/) Peripheral clock (16/) Count clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PPG0/1 count clock selection register (PPG01) Reserved HCLK * DS07-13713-6E : Undefined : Reserved bit : Oscillation clock frequency : Machine clock frequency : Interrupt output from 8/16-bit PPG timer 0 is merged with interrupt request output from PPG timer 1 into a single interrupt via an OR circuit. 47 MB90495G Series * Block Diagram of 8/16-Bit PPG Timer1 "H" level side data bus "L" level side data bus PPG1 operation mode control register (PPGC1) PPG1 reload register PRLL1 ("L" side) PRLH1 ("H" side) PEN1 PE1 PIE1 PUF1 MD1 MD0 Reserved 2 Operation mode control signal Output interrupt request* R PPG1 temporary buffer (PRLBH1) S Reload selector L/H selector Q Select signal Initial count value Reload PPG1 down counter (PCNT1) Clear Underflow Invert PPG1 output latch Pin PPG1 PPG1 underflow (to PPG0) CLK PPG output control circuit MD0 PPG0 underflow (from PPG0) Time-base timer output (512/HCLK) Peripheral clock (1/) Peripheral clock (2/) Peripheral clock (4/) Peripheral clock (8/) Peripheral clock (16/) Counter clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PPG0/1 count clock selection register (PPG01) Reserved HCLK * 48 : Undefined : Reserved bit : Oscillation clock frequency : Machine clock frequency : Interrupt output from 8/16-bit PPG timer 1 is merged with interrupt request output from PPG timer 0 into a single interrupt via an OR circuit. DS07-13713-6E MB90495G Series 8. Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks. This module can be used to generate hardware interrupts from the software. * Overview of the Delayed Interrupt Generation Module Use the delayed interrupt generation module to generate or cancel hardware interrupts from the software. Overview of the Delayed Interrupt Generation Module Functions and Control When the R0 bit of the delayed interrupt request generation/cancel register is set to 1 (DIRR : R0 = 1) : Generate interrupt request When the R0 bit of the delayed interrupt request generation/cancel register is set to 0 (DIRR : R0 = 0) : Cancel interrupt request Interrupt Condition Interrupt number #42 (2AH) Interrupt control There is no enable setting from the register Interrupt flag Stored in bit DIRR : R0 2 EI OS Does not support extended intelligent I/O service * Delayed Interrupt/Generation Module Block Diagram Internal data bus Delayed interrupt request generation/cancel register (DIRR) R0 S Interrupt R request latch Interrupt request signal : Undefined Interrupt request latch:This latch stores the delayed interrupt request generation/cancel register setting (generates/cancels delayed interrupt requests) . Delayed interrupt request generation/cancel register (DIRR) : Generates or cancels delayed interrupt requests. * Interrupt number Below is the interrupt number used by the delayed interrupt generation module. Interrupt number : #42 (2AH) DS07-13713-6E 49 MB90495G Series 9. DTP/External Interrupts The DTP/external interrupt transmits interrupt requests or data transfer requests generated by peripheral devices to the CPU, generates external interrupt request, and starts the extended intelligent I/O service (EI2OS) . * DTP/External Interrupt Functions Outputs interrupt requests from external peripheral devices to the CPU using the same procedure as for peripheral functions, and generates external interrupts, or starts the extended intelligent I/O service (EI2OS) . If the interrupt control register is configured to prohibit the extended intelligent I/O service (EI2OS) (ICR : ISE = 0) , then the external interrupt feature becomes valid, and the process branches into interrupt processing. If the EI2OS is enabled (ICR : ISE = 1) , then the DTP function becomes valid, and the EI2OS automatically transmits data, and after transmitting data a specified number of times, branches into interrupt processing. Overview of DTP/External Interrupts External interrupt Input pins Interrupt condition Interrupt numbers Interrupt control Interrupt flag Process selection Processing 50 DTP functions 8 (INT0 to INT7) Each pin sets individually in the detection level configuration register (ELVR) "H" / "L" level/rising edge/falling edge input "H" / "L" level input #15 (0FH) , #20 (14H) , #24 (18H) , #27 (1BH) The DTP/external interrupt enable register (ENIR) enables or prohibits interrupt request output Interrupt conditions stored by DTP/external interrupt condition register (EIRR) Set EI2OS to be prohibited (ICR : ISE = 0) Set EI2OS to be enabled (ICR : ISE = 1) Branch to external interrupt process After the EI2OS conducts automatic data forwarding the specified number of times, branches to interrupt processing. DS07-13713-6E MB90495G Series * DTP/External Interrupt Block Diagram Detection level configuration register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 Pin INT7 Pin Internal data bus INT6 Pin INT5 Pin INT4 Level/ edge selector Level/ edge selector Level/ edge selector Level/ edge selector LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Pin INT3 Pin INT2 Pin INT1 Pin INT0 Level/ edge selector Level/ edge selector Level/ edge selector Level/ edge selector DTP/external interrupt input detection circuit ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Interrupt request signal Interrupt request signal EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 DS07-13713-6E DTP/external interrupt condition register (EIRR) DTP/external interrupt enable register (ENIR) 51 MB90495G Series 10. 8/10-bit A/D Converter The 8/10-bit A/D converter converts analog voltage to 8 or 10-bit digital values, by means of RC successive approximation conversion. * The input signal can be selected from an 8-channel analog input pin set. * Select a software trigger, internal timer output, or external trigger as the start trigger. * Functions of the 8/10-bit A/D Converter Converts analog voltage (input voltage) input to the analog input pins to 8-bit or 10-bit digital values. (A/D conversion) The 8/10-bit A/D converter has the following features : * Single-channel A/D conversion time is a minimum of 6.12 s, including sampling time.* * Single-channel sampling time is a minimum of 2.0 s.* * RC-type successive approximation with sampling and hold circuits is used for conversion. * Select 8 or 10-bit resolution. * Analog input pins can use up to 8 channels. * A/D conversion results are stored in the A/D data register, allowing them to be used to generate interrupts. * Interrupt requests launch the EI2OS. Use the EI2OS to prevent dropped data even with continuous A/D conversion. * Select software, internal timer output, or external trigger (falling edge) as the start trigger. * : With machine clock operating at 16 MHz * Conversion Modes of the 8/10-bit A/D Converter Conversion Mode 52 Description Single conversion mode Conducts A/D conversion for each channel in turn, from the start channel to the end channel. When A/D conversion of the end channel is completed, the A/D conversion function halts. Continuous conversion mode Conducts A/D conversion for each channel in turn, from the start channel to the end channel. When A/D conversion of the end channel is completed, the function returns to the start channel and continues A/D conversion. Stop conversion mode Suspends each channel and conducts A/D conversion, one at a time. When A/D conversion of the end channel is completed, the function returns to the start channel and repeats the A/D conversion and channel stop. DS07-13713-6E MB90495G Series * 8/10-bit A/D Converter Block Diagram Output interrupt request A/D control status register ReBUSY INT INTE PAUS STS1 STS0 STAT served MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 (ADCS) 2 2 Launch Selector Decoder Internal data bus ADTG TO 6 Comparator AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Sample and hold circuit Control circuit Analog channel selector AVR AVCC AVSS D/A converter 2 2 A/D data register S10 ST1 ST0 CT1 CT0 (ADCR) TO Reserved DS07-13713-6E D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 : Internal timer output : Undefined : Make sure this is always set to "01" : Machine clock 53 MB90495G Series 11. UART0/1 The UART is a general-purpose serial data communications interface for synchronous or asynchronous communication with external devices. * The UART has a clock-synchronous/clock-asynchronous two-way communications feature . * Also supplies a master/slave communications feature (multi-processor mode) . (It can be used only master side.) * Interrupts can be generated upon send complete, receive complete, or reception error detection. * Supports extended intelligent I/O service (EI2OS) . * UART0/1 Functions Functions Data Buffer Transfer mode Full-duplex double buffer * Clock-synchronous (no start, stop, or parity bit) * Clock-asynchronous (start-stop synchronization) Baud Rate * Select from 8 dedicated baud rate generators * External clock input possible * Clock supplied from internal timer (16-bit reload timer) available Data length * 7-bit (asynchronous normal mode only) * 8-bit Signal method Non Return to Zero (NRZ) Reception Error Detection * Framing error * Overrun error * Parity error (not available in operation mode 1 (multi processor mode) ) Interrupt Requests * Receive interrupt (reception complete, reception error detected) * Send interrupt (send complete) * Both send and receive support extended intelligent I/O service (EI2OS) Master/Slave Communications Function (In multiprocessor mode) 1-to-n (master to slave) communication available (can only be used as master) Note : During clock-synchronous forwarding, just the data is forwarded, with no stop or start bit appended. 54 DS07-13713-6E MB90495G Series * UART0 Block Diagram Control bus Reception interrupt request output Dedicated baud rate generator 16-bit reload timer0 Send clock Clock selector Reception clock Pin SCK0 Send interrupt request output Send control circuit Reception control circuit Start bit detection circuit Send start circuit Reception bit counter Send bit counter Reception parity counter Send parity counter Pin SOT0 Reception shift register Pin Send shift register SIN0 Reception status determination circuit Serial input data register0 Reception end Send start Serial output data register0 EI2OS receive error generation signal (to CPU) Internal data bus Communications prescaler control register Serial edge selection register NEG DS07-13713-6E MD DIV3 DIV2 DIV1 DIV0 Serial mode register0 MD1 MD0 CS2 CS1 CS0 SCKE SOE Serial control register0 PEN P SBL CL A/D REC RXE TXE Serial status register0 PE ORE FRE RDRF TDRE RIE TIE 55 MB90495G Series * UART1 Block Diagram Control bus Reception interrupt request output Dedicated baud rate generator 16-bit reload timer1 Send clock Clock selector Reception clock Pin SCK1 Send interrupt request output Send control circuit Reception control circuit Start bit detection circuit Send start circuit Reception bit counter Send bit counter Reception parity counter Send parity counter Pin SOT1 Reception shift register Pin Send shift register SIN1 Reception status determination circuit Serial input data register1 Reception end Send start Serial output data register1 EI2OS receive error generation signal (to CPU) Internal data bus Communications prescaler control register 56 MD DIV2 DIV1 DIV0 Serial mode register1 MD1 MD0 CS2 CS1 CS0 RST SCKE SOE Serial control register1 PEN P SBL CL A/D REC RXE TXE Serial status register1 PE ORE FRE RDRF TDRE BDS RIE TIE DS07-13713-6E MB90495G Series 12. CAN Controller CAN (Controller Area Network) is a serial communications protocol conforming to CAN version 2.0 A and B. Sending and receiving is available in standard and extended frame format. * * * * * Can Controller Features The CAN controller format conforms to CAN versions 2.0 A and B. Sending and receiving is available in standard and extended frame format. Supports automatic data frame formatting through remote frame reception. Baud rate : 10 kbps to 1 Mbps. When using at 1 Mbps, the machine clock must be operated at 8 MHz or more. Data Transmission Baud Rates Machine clock Baud rate (Max) 16 MHz 1 Mbps 12 MHz 1 Mbps 8 MHz 1 Mbps 4 MHz 500 kbps 2 MHz 250 kbps Supplies 8 send/receive message buffers. Sending and receiving available in standard frame format (ID 11-bit) , and extended frame format (ID 29-bit) . Message data can be set to 0 to 8 bytes. Possible to configure a multi-level message buffer. The CAN controller has two built-in acceptance masks, each of which can be set to a different mask for reception message IDs. * The two acceptance masks can receive in standard or extended frame format. * Configure four types of partial masks with full-bit compare, full-bit mask, and acceptance mask register 0/1. * * * * * DS07-13713-6E 57 MB90495G Series * CAN Controller Block Diagram EI2OS -16LX Bus CPU operation clock PSC TS1 BTR TS2 RSJ TOE TS RS CSR HALT NIE NT NS1,0 Operation clock (TQ) Bit timing generation circuit Prescaler (1:1 to 1:64) Node status transition interrupt generation circuit Error control circuit TREQR Clear send buffer Send buffer determination circuit Idle/ interrupt/ suspend/ send/ receive/ error/ overload Bus status determination circuit Node status transition interrupt signal RTEC BVALR Sink segment Timer segment 1 Timer segment 2 Send buffer Send/receive sequence Error frame generation circuit Acceptance Data filter control counter circuit Send ReID DLC ception selection DLC Overload frame generation circuit Arbitration lost Bit error/ Staff error/ CRC error/ Frame error/ ACK error Send buffer TCANR Output driver Pin TX Input latch Pin RX TRTRR Send shift register RFWTR TCR TIER RCR Set/clear send buffer Send complete interrupt generation circuit Set reception buffer RRTRR Reception complete interrupt generation circuit Reception buffer Set/clear send buffer ROVRR Set reception Select ID buffer RIER Send complete interrupt signal Reception complete interrupt signal Send DLC Staffing ACK CRC generation generation circuit circuit CRC error Receive CRC generation DLC circuit/error check Reception shift register Staff error Destaffing/ staffing error check AMSR AMR0 AMR1 IDR0 to IDR7 DLCR0 to DLCR7 DTR0 to DTR7 RAM IDER 0 1 Acceptance filter Reception buffer determination circuit Arbitration lost Bit error Reception buffer RAM address generation circuit Reception buffer/ Send buffer/ Receive DLC/Send DLC/ Select ID Arbitration check Bit error check ACK error Acknowledgement error check Frame error Form error check LEIR 58 DS07-13713-6E MB90495G Series 13. ROM Correction Function In the case that the address of the instruction after the one that a program is currently processing matches the address configured in the detection address configuration register, the program forces the next instruction to be processed into an INT9 instruction, and branches to the interrupt process program. Since processing can be conducted using INT9 interrupts, programs can be repaired using batch processing. * Overview of the ROM Correction Function * The address of the instruction after the one that a program is currently processing is always stored in an address latch via the internal data bus. ROM correction constantly compares the address stored in the address latch with the one configured in the detection address configuration register. If the two compared addresses match, the CPU forcibly changes this instruction into an INT9 instruction, and executes an interrupt processing program. * There are two detection address configuration registers : PADR0 and PADR1. Each register provides an interrupt enable bit. This allows you to individually configure each register to enable/prohibit the generation of interrupts when the address stored in the address latch matches the one configured in the detection address configuration register. * ROM Correction Block Diagram Comparator Internal data bus Address latch PADR0 (24-bit) Detection address configuration register 0 PADR1 (24-bit) INT9 instruction (INT9 interrupt generation) Detection address configuration register 1 PACSR Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved Address detection control register (PACSR) Reserved : Make sure this is always set to "01" * Address latch Stores value of address output to internal data bus. * Address detection control register (PACSR) Set this register to enable/prohibit interrupt output when an address match is detected. * Detection address configuration register (PADR0, PADR1) Configure an address with which to compare the address latch value. DS07-13713-6E 59 MB90495G Series 14. ROM Mirror Function Selection Module The ROM mirror function selection module configures ROM-internal data arrayed inside bank FF to be readable by accessing bank 00. * ROM Mirror Function Selection Module Block Diagram ROM mirror function selection register (ROMM) Reserved Reserved Reserved Reserved Reserved Reserved Reserved MI Address Internal data bus Address area Bank FF Bank 00 Data ROM * Accessing Bank FF through ROM Mirror Function 004000H Bank 00 ROM mirror area 00FFFFH FC0000H FE0000H MB90V495G FEFFFFH FF0000H MB90F498G FF4000H Bank FF (Area corresponding to ROM mirror) MB90F497G MB90497G FFFFFFH 60 DS07-13713-6E MB90495G Series 15. 512-K/1-M bit Flash Memory * Overview There are three methods available for writing/deleting data to/from flash memory : 1. Parallel writer 2. Serial dedicated writer 3. Program runtime write/delete * Overview of 512-K/1-M bit flash memory 512-Kbit flash memory is arrayed in bank FFH on the CPU memory map, 1-Mbit flash memory is arrayed in bank FEH to FFH on the CPU memory map. The flash memory interface circuit provides read and program access from the CPU. Since instructions from the CPU are carried out via the flash memory interface circuit, flash memory can be overwritten at the implementation level. This allows you to efficiently improve programs and data. * Features of 512-K/1-M bit Flash Memory * 512-Kbit flash memory : 64 KWords x 8-bit/32 KWords x 16-bit (16-Kbyte + 8-Kbyte + 8-Kbyte + 32-Kbyte) sector architecture * 1-Mbit flash memory : 128 KWords x 8-bit/64 KWords x 16-bit (16-Kbyte + 8-Kbyte + 8-Kbyte + 32-Kbyte + 64-Kbyte) sector architecture * Auto program algorithm (Embedded Algorithm : same as MBM29LV200) * On-chip delete suspend/delete resume functions * Data polling, write/delete completion detection through toggle bit * Write/delete completion detection from CPU overwrite * Sector-specific deletion available (sectors can be combined as desired) * Write/delete iterations (minimum) : 10,000 Notes : There is no function to read the manufacture or device code. These codes also cannot be accessed through commands. * Flash memory write/delete * It is not possible to simultaneously write to and read from flash memory. * When writing to or deleting from flash memory, first copy the program residing in flash memory into RAM, then execute the program copied into RAM. This will allow you to write to flash memory. DS07-13713-6E 61 MB90495G Series * List of Flash Memory Registers and Reset Values Flash memory control status register (FMCS) bit 7 6 5 4 3 2 1 0 0 0 0 X 0 0 0 0 x : Undefined * Sector Architecture of 512-K/1-M bit Flash memory * Sector architecture 512-Kbit flash memory : When accessing from the CPU, SA0 to SA3 are arrayed in the Bank FF register. 1-Mbit flash memory : When accessing from the CPU, SA0 is arrayed in the Bank FE register, SA1 to SA4 are arrayed in the Bank FF register. Sector Architecture of 512-K/1-M bit Flash Memory 512-Kbit Flash Memory CPU Addresses Writer Address* FF0000H 70000H FF7FFFH 77FFFH FF8000H 78000H FF9FFFH 79FFFH FFA000H 7A000H FFBFFFH 7BFFFH FFC000H 7C000H FFFFFFH 7FFFFH CPU Addresses Writer Address* FE0000H 60000H FEFFFFH 6FFFFH FF0000H 70000H FF7FFFH 77FFFH FF8000H 78000H FF9FFFH 79FFFH FFA000H 7A000H FFBFFFH 7BFFFH FFC000H 7C000H FFFFFFH 7FFFFH SA0 (32 Kbytes) SA1 (8 Kbytes) SA2 (8 Kbytes) SA3 (16 Kbytes) 1-Mbit Flash Memory SA0 (64 Kbytes) SA1 (32 Kbytes) SA2 (8 Kbytes) SA3 (8 Kbytes) SA4 (16 Kbytes) * : If a parallel write is writing data to Flash memory, the write address corresponds to the CPU address. If a general-purpose writer is used to write/delete, this address is written to/over. 62 DS07-13713-6E MB90495G Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0 V) Parameter Symbol Rating Unit Remarks Min Max VCC VSS - 0.3 VSS + 6.0 V AVCC VSS - 0.3 VSS + 6.0 V VCC = AVCC *1 AVR VSS - 0.3 VSS + 6.0 V AVCC AVR *1 Input voltage VI VSS - 0.3 VSS + 6.0 V *2 Output voltage VO VSS - 0.3 VSS + 6.0 V *2 ICLAMP - 2.0 + 2.0 mA *6 | ICLAMP | 20 mA *6 IOL 15 mA *3 "L" level average output current IOLAV 4 mA *4 "L" level maximum total output current IOL 100 mA IOLAV 50 mA *5 IOH -15 mA *3 "H" level average output current IOHAV -4 mA *4 "H" level maximum total output current IOH -100 mA IOHAV -50 mA Power consumption PD 315 mW Operating temperature TA -40 +105 C -40 +125 C Storage temperature Tstg -55 +150 C Power supply voltage Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average total output current "H" level maximum output current "H" level average total output current *5 *7 *1 : AVCC and AVR shall never exceed VCC. Also, AVR shall never exceed AVCC. *2 : VI and VO shall never exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : The rating for the maximum output current is the peak value of one of the corresponding pins. *4 : The standard for computing average output current is the average current output from one of the corresponding pins over a period of 100 ms (the average value is taken by multiplying operating current by operational rate) . *5 : The standard for computing average total output current is the average current output from all of the corresponding pins over a period of 100 ms (the average value is taken by multiplying operating current by operational rate) . *6 : * Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P44, P50 to P57, P60 to P63 * Use within recommended operating conditions. * Use at DC voltage (current) * The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. (Continued) DS07-13713-6E 63 MB90495G Series (Continued) * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits: Protective diode VCC P-ch Limiting resistance +B input (0 V to 16 V) N-ch R *7 : If used exceeding TA = +105 C, be sure to contact us for reliability limitations. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 64 DS07-13713-6E MB90495G Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Power supply voltage Symbol VCC, AVCC Smoothing capacitor CS Operating temperature TA Value Unit Remarks Min Typ Max 4.5 5.0 5.5 V During normal operation, TA = -40 C to +105 C 4.75 5.0 5.25 V During normal operation, +105 C < TA +125 C 3.0 5.5 V Maintaining stop operation state 0.022 0.1 1.0 F *1 -40 +105 C -40 +125 C *2 *1 : Use a ceramic capacitor, or one with approximately the same frequency characteristics. The bypass capacitor of the VCC pin should have a greater capacity than CS. See the figure below for details about connecting a smooth capacitor to the CS. *2 : If used exceeding TA = +105 C, be sure to contact us for reliability limitations. * C Pin Connection Diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS07-13713-6E 65 MB90495G Series 3. DC Characteristics (VCC = 5.0 V 5%, VSS = AVSS = 0.0 V, TA = -40 C to +125 C) (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leakage current Symbol VIHS Pin Name CMOS hysteresis input pin VIHM MD input pin Condition Value Unit Min Typ Max 0.8 VCC VCC + 0.3 V VCC - 0.3 VCC + 0.3 V Remarks VILS CMOS hysteresis input pin VSS - 0.3 0.2 VCC V VILM MD input pin VSS - 0.3 VSS + 0.3 V VOH All output pins VCC = 4.5 V, IOH = -4.0 mA VCC - 0.5 V TA = -40 C to +105 C VCC = 4.75 V VCC - 0.5 V +105 C < TA +125 C VCC = 4.5 V, IOL = 4.0 mA 0.4 V TA = -40 C to +105 C VCC = 4.75 V 0.4 V +105 C < TA +125 C VCC = 5.5 V, VSS < VI < VCC -5 +5 A TA = -40 C to +105 C VCC = 5.25 V, VSS < VI < VCC -5 +5 A +105 C < TA +125 C VCC = 5.0 V Internal 16-MHz operation, Normal mode 30 40 MB90497G mA MB90F497G MB90F498G VCC = 5.0 V Internal 16-MHz operation, Flash memory write mode 45 50 mA MB90F497G MB90F498G VCC = 5.0 V Internal 16-MHz operation, Flash memory delete mode 45 50 mA MB90F497G MB90F498G VCC = 5.0 V Internal 16-MHz operation, Sleep mode 11 18 MB90497G mA MB90F497G MB90F498G VOL IIL All output pins All output pins ICC Power supply current* VCC ICCS (Continued) 66 DS07-13713-6E MB90495G Series (Continued) Parameter Power supply current* Power supply current* (VCC = 5.0 V 5%, VSS = AVSS = 0.0 V, TA = -40 C to +125 C) (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) SymPin Name bol Condition Value Unit Typ Max 0.6 1.2 MB90497G mA MB90F497G MB90F498G 30 50 A MB90497G 300 500 A ICCLS VCC = 5.0 V Internal 8-kHz operation, Subclock sleep mode TA = + 25 C 10 30 MB90497G A MB90F497G MB90F498G ICCT VCC = 5.0 V Internal 8-kHz operation, Clock mode TA = + 25 C 8 25 MB90497G A MB90F497G MB90F498G VCC = 5.0 V Stop mode, TA = + 25 C 5 20 MB90497G A MB90F497G MB90F498G ICTS VCC = 5.0 V Internal 2-MHz operation, Timer mode ICCL VCC = 5.0 V Internal 8-kHz operation, Subclock operation mode TA = + 25 C VCC ICCH VCC Input Capacity CIN Other than AVCC, AVSS, AVR, C, VCC, or VSS 5 15 pF Pull up Resistor RUP RST 25 50 100 k RDOWN MD2 25 50 100 k Pull down Resistor Remarks Min MB90F497G MB90F498G * : This is when using the external clock as the power supply current test condition. DS07-13713-6E 67 MB90495G Series 4. AC Characteristics (1) Clock Timing (VCC = 5.0 V 5%, VSS = AVSS = 0.0 V, TA = -40 C to +125 C) (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Clock frequency Clock Cycle Time Input clock pulse width Input clock rising/falling time Internal operation clock frequency Internal operation clock cycle time Symbol Pin Name fC Value Unit Remarks Min Typ Max X0, X1 3 16 MHz fCL X0A, X1A 32.768 kHz tHCYL X0, X1 62.5 333 ns tLCYL X0A, X1A 30.5 s PWH, PWL X0 10 ns PWLH, PWLL X0A 15.2 s tCR, tCF X0 5 ns fCP 1.5 16 MHz When oscillation circuit used fLCP 8.192 kHz When subclock used tCP 62.5 666 ns When using oscillation circuit tLCP 122.1 s When subclock used Duty ratio should be around 30 % to 70 % When external clock used * X0/X1 Clock Timing tHCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF tCR tLCYL 0.8 VCC X0A 0.2 VCC PWLH PWLL tCF 68 tCR DS07-13713-6E MB90495G Series * PLL guaranteed operation range Relationship between internal operating clock frequency and power supply voltage Power supply voltage VCC (V) MB90F497G/MB90F498G/MB90497G guaranteed operation range (TA = -40C to +105C) MB90F497G/MB90F498G/MB90497G guaranteed operation range ( = +105C < TA < +125C) 5.5 5.25 4.75 4.5 PLL guaranteed operation range 3.3 3.0 1.5 3 8 12 16 Internal clock fCP (MHz) Relationship between external clock frequency and internal operation clock frequency x4 Internal clock fCP (MHz) 16 x3 x2 x1 12 9 8 x1/2 (no multiplication) 4 3 4 8 16 External clock fC (MHz) AC characteristics are specified by the following reference voltage values. * Input Signal Waveform Hysteresis Input Pin * Output Signal Waveform Output Pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V DS07-13713-6E 69 MB90495G Series (2) Clock Output Timing (VCC = 5.0 V 5%, VSS = AVSS = 0.0 V, TA = -40 C to +125 C) (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Cycle time tCYC CLK CLK tCHCL Pin Name Condition CLK Value Unit Min Max 62.5 ns 20 ns Remarks tCYC tCHCL 2.4 V CLK 2.4 V 0.8 V (3) Reset Input Timing Parameter Reset input time Symbol tRSTL Value Pin Condition Name RST Min Max 16 tCP Oscillator oscillation time* + 16 tCP Unit Remarks ns Normal mode ms Stop mode, Watch mode, Subclock mode, Subsleep mode * : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several dozen ms; for a ceramic oscillator, this is several hundred s to a few ms, and for an external clock this is 0 ms. * Stop mode, Watch mode, Subclock mode, Subsleep mode tRSTL RST 0.2 VCC X0 Internal operation clock 0.2 VCC 90% of amplitude Oscillator oscillation time 16 tCP Oscillation stabilize standby time Instruction execution Internal reset 70 DS07-13713-6E MB90495G Series (4) Power-on Reset (VCC = 5.0 V 5%, VSS = AVSS = 0.0 V, TA = -40 C to +125 C) (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin Name Power supply rising time tR VCC Power supply cutoff time tOFF VCC Condition Value Unit Min Max 0.05 30 ms 1 ms Remarks Due to repeated operations tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended that you raise the voltage at a steady rate, in order to suppress fluctuations (see figure below). In this case, perform this operation when the PLL clock is not being used. If, however, the voltage falling speed is no more than 1 V/s, it is permissible to perform this operation while using the PLL clock. VCC 3V VSS DS07-13713-6E It is recommended that you keep the rising speed to no more than 50 mV/ms. RAM data hold period 71 MB90495G Series (5) Bus Read Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin Name ALE pulse width tLHLL Valid address ALE time Value Unit Min Max ALE tCP/2 - 20 ns tAVLL ALE, A23 to A16, AD15 to AD00 tCP/2 - 20 ns ALE address valid time tLLAX ALE, AD15 to AD00 tCP/2 - 15 ns Valid address RD time tAVRL A23 to A16, AD15 to AD00, RD tCP - 15 ns Valid address Valid data input tAVDV A23 to A16, AD15 to AD00 5 tCP/2 - 60 ns RD pulse width tRLRH RD 3 tCP/2 - 20 ns RD valid data input tRLDV RD, AD15 to AD00 3 tCP/2 - 60 ns RD data hold time tRHDX RD, AD15 to AD00 0 ns RD ALE time tRHLH RD, ALE tCP/2 - 15 ns RD address valid time tRHAX RD, A23 to A16 tCP/2 - 10 ns Valid address CLK time tAVCH A23 to A16, AD15 to AD00, CLK tCP/2 - 20 ns RD CLK time tRLCH RD, CLK tCP/2 - 20 ns ALE RD time tLLRL ALE, RD tCP/2 - 15 ns 72 Remarks DS07-13713-6E MB90495G Series * Bus read timing tAVCH tRLCH 2.4 V 2.4 V CLK tAVLL ALE tLLAX tRHLH 2.4 V 2.4 V 2.4 V tLHLL 0.8 V tAVRL tRLRH 2.4 V RD 0.8 V tLLRL tRHAX 2.4 V 2.4 V A23 to A16 0.8 V 0.8 V tRLDV tAVDV AD15 to AD00 2.4 V 2.4 V 0.8 VCC Address 0.8 V DS07-13713-6E tRHDX 0.8 VCC Read data 0.8 V 0.2 VCC 0.2 VCC 73 MB90495G Series (6) Bus Write Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin Name Valid Address WR time tAVWL WR pulse width tWLWH Valid data output WR time Value Unit Min Max A23 to A16, AD15 to AD00, WR tCP - 15 ns WR 3 tCP/2 - 20 ns tDVWH AD15 to AD00, WR 3 tCP/2 - 20 ns WR data hold time tWHDX AD15 to AD00, WR 20 ns WR address valid time tWHAX A23 to A16, WR tCP/2 - 10 ns WR ALE time tWHLH WR, ALE tCP/2 - 15 ns WR CLK time tWLCH WR, CLK tCP/2 - 20 ns Remarks tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL tWLWH 2.4 V WR (WRL, WRH) 0.8 V tWHAX 2.4 V 2.4 V 0.8 V 0.8 V A23 to A16 tDVWH AD15 to AD00 2.4 V Address 0.8 V 74 2.4 V tWHDX 2.4 V Write data 0.8 V 0.8 V DS07-13713-6E MB90495G Series (7) Ready Input Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin Name RDY setup time tRYHS RDY hold time tRYHH Value Unit Min Max RDY 45 ns RDY 0 ns Remarks Note : Use the automatic ready function if the setup time for the falling edge of the RDY signal is not sufficient. * Ready Input timing 2.4 V CLK ALE RD/WR tRYHS tRYHH 0.8 VCC RDY Unweighted RDY Weighted (1 cycle) 0.8 VCC 0.2 VCC (8) Hold Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin Name Value Min Max Unit Pin in floating status HAK time tXHAL HAK 30 tCP ns HAK pin valid time tHAHV HAK tCP 2 tCP ns Remarks Note : It will take at least 1 cycle from the time the HRQ pin is loaded until the HAK changes. * Hold Timing 2.4 V HAK 0.8 V tXHAL Each pin DS07-13713-6E tHAHV 2.4 V 0.8 V 2.4 V High-Z 0.8 V 75 MB90495G Series (9) UART Timing (VCC = 5.0 V5%, VSS = 0.0 V, TA = -40 C to +125 C) (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin Name Condition Serial clock cycle time tSCYC SCK1 SCK SOT delay time tSLOV Valid SIN SCK tIVSH SCK valid SIN hold time tSHIX Serial clock "H" pulse width tSHSL Serial clock "L" pulse width tSLSH SCK SOT delay time tSLOV Valid SIN SCK tIVSH External shift clock SCK1, SOT1 mode output pin : CL = 80 pF + 1 TTL SCK1, SIN1 SCK valid SIN hold time tSHIX SCK1, SIN1 Value Unit Min Max 8 tCP* ns -80 + 80 ns 100 ns 60 ns SCK1 4 tCP ns SCK1 4 tCP ns 150 ns 60 ns 60 ns SCK1, SOT1 Internal shift clock mode output pin : SCK1, SIN1 CL = 80 pF + 1 TTL SCK1, SIN1 Remarks * : See " (1) Clock Timing" for details about tCP (internal operating clock cycle time). Notes : * AC characteristics are for CLK synchronous mode. * CL is the load capacitor value connected to pins while testing. 76 DS07-13713-6E MB90495G Series * Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC * External shift clock mode tSLSH SCK 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN DS07-13713-6E tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 77 MB90495G Series (10) Timer Input Timing (VCC = 5.0 V5%, VSS = 0.0 V, TA = -40 C to +125 C) (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40 C to +105 C) Parameter Input pulse width Symbol Pin Name tTIWH TIN0, TIN1, FRCK tTIWL IN0 to IN3, FRCK Value Condition Min Max 4 tCP Unit Remarks ns * Timer Input Timing 0.8 VCC TIN0, TIN1, IN0 to IN3, FRCK 0.8 VCC 0.2 VCC tTIWH 0.2 VCC tTIWL (11) Timer Output Timing (VCC = 5.0 V5%, VSS = 0.0 V, TA = -40 C to +125 C) (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin Name Condition tTO TOT0, TOT1, PPG0 to PPG3 CLK TOUT change time Value Min Max 30 Unit Remarks ns * Timer Output Timing 2.4 V CLK 2.4 V TOT0, TOT1, PPG0 to PPG3 0.8 V tTO (12) Trigger Input Timing (VCC = 5.0 V5%, VSS = 0.0 V, TA = -40 C to +125 C) (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40 C to +105 C) Parameter Input pulse width Symbol Pin Name Condition tTRGH tTRGL INT0 to INT7, ADTG Value Unit Remarks ns Normal mode s Stop mode Min Max 5 tCP 1 * Trigger Input Timing INT0 to INT7, ADTG 0.8 VCC 0.8 VCC 0.2 VCC tTRGH 78 0.2 VCC tTRGL DS07-13713-6E MB90495G Series 5. A/D Converter (VCC = AVCC = 5.0 V5%, VSS = AVSS = 0.0 V, 3.0 V AVR - AVSS, TA = -40 C to +125 C) (VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, 3.0 V AVR - AVSS, TA = -40 C to +105 C) Parameter Value Symbol Pin Name Resolution Total error Nonlinearity error Differential linearity error Zero transition voltage Full-scale transition voltage Min Typ Max Unit 10 bit 5.0 LSB 2.5 LSB 1.9 LSB VOT AN0 to AN7 AVSS - 3.5 LSB AVSS + 0.5 LSB AVSS + 4.5 LSB V VFST AN0 to AN7 AVR - 6.5 LSB AVR - 1.5 LSB AVR + 1.5 LSB V Conversion time 66 tCP ns Sampling period 32 tCP ns Analog port input current IAIN AN0 to AN7 10 A Analog input voltage VAIN AN0 to AN7 AVSS AVR V AVR AVSS + 3.0 AVCC V IA AVCC 2 7 mA IAH AVCC 5 A Reference voltage Power supply current Reference voltage supply current IR AVR 0.9 1.3 mA IRH AVR 5 A Inter-channel variation AN0 to AN7 4 LSB Remarks 1 LSB = (AVR - AVSS) / 1024 Machine clock of 16 MHz * * * : Current (VCC = AVCC = AVR = 5.0 V) when A/D converter is not operating and CPU is halted. DS07-13713-6E 79 MB90495G Series 6. A/D Converter Glossary Resolution Linearity error : Analog changes that are identifiable with the A/D converter : The deviation of the straight line connecting the zero transition point ( "00 0000 0000" "00 0000 0001" ) with the full-scale transition point ( "11 1111 1110" "11 1111 1111" ) from actual conversion characteristics. Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the ideal value. Total error : The difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error, linearity error, and differential linearity error. Total error 3FFH 3FEH Actual conversion characteristics 1.5 LSB Digital output 3FDH {1 LSB x (N - 1) + 0.5 LSB} 004H VNT (actual measurement) 003H Actual conversion characteristics Ideal characteristics 002H 001H 0.5 LSB AVSS AVR Analog input VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVR - AVSS [V] 1024 Total error of digital output N = 1 LSB = (ideal value) [LSB] VOT (ideal value) = AVSS + 0.5 LSB [V] VFST (ideal value) = AVR - 1.5 LSB [V] VNT : The voltage to transition digital output from (N - 1) to N. (Continued) 80 DS07-13713-6E MB90495G Series (Continued) Differential linearity error Linearity error Ideal characteristics 3FF Actual conversion characteristics {1 LSB x (N - 1) + VOT } Digital output 3FD N+1 VFST (actual measurement) VNT (actual measurement) 004 Actual conversion characteristics 003 Digital output 3FE Actual conversion characteristics N V (N + 1) T (actual measurement) VNT (actual measurement) N-1 002 Ideal characteristics Actual conversion characteristics N-2 001 VOT (actual measurement) AVSS AVR AVSS AVR Analog input Analog input Linearity error of digital output N = Differential linearity error of digital output N = 1 LSB = VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N + 1) T - VNT 1 LSB VFST - VOT 1022 [LSB] - 1 LSB [LSB] [V] VOT : Voltage for transition from digital output 000H to 001H. VFST : Voltage for transition from digital output 3FEH to 3FFH. 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions : External circuit output impedance values of about 5 k or lower are recommended. If external capacitors are used, a capacitance of several thousand times the internal capacitor value is recommended in order to minimize the effect of voltage distribution between the external and internal capacitor. If the output impedance of the external circuit is too high, the sampling time for analog voltages may not be sufficient (sampling period = 2.00 s @ machine clock of 16 MHz) . * Model Analog Input Circuit Comparator Analog input R C MB90F497G, MB90F498G, MB90V495G R 3.2 k, C 30 pF MB90497G R 2.6 k, C 28 pF Note : The figures given here are the suggested values. * About Error The smaller the absolute value of | AVR - AVSS |, the greater the relative error. DS07-13713-6E 81 MB90495G Series 8. Flash Memory Program/Erase Characteristics Parameter Condition Sector erase time Chip erase time TA = + 25 C VCC = 5.0 V Word (16-bit width) programming time Erase/Program cycle 82 Value Unit Remarks 15 s Excludes 00H programming prior erasure 5 s Excludes 00H programming prior erasure 16 3,600 s Excludes system-level overhead 10,000 cycle Min Typ Max 1 DS07-13713-6E MB90495G Series EXAMPLE CHARACTERISTICS * MB90F497G/F498G ICC - VCC TA = + 25 C, external clock operation f = internal operation frequency 45 40 f = 16 MHz 35 ICC (mA) 30 f = 10 MHz 25 f = 8 MHz 20 15 f = 4 MHz 10 f = 2 MHz 5 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 ICCS - VCC TA = + 25 C, external clock operation f = internal operation frequency 16 14 12 f = 16 MHz ICCS (mA) 10 8 f = 10 MHz f = 8 MHz 6 4 f = 4 MHz 2 0 3.0 f = 2 MHz 4.0 5.0 VCC (V) 6.0 7.0 (Continued) DS07-13713-6E 83 MB90495G Series (Continued) ICCL - VCC TA = + 25 C, external clock operation f = internal operation frequency 180 160 140 ICCL (A) 120 f = 8 kHz 100 80 60 40 20 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 ICCLS - VCC TA = + 25 C, external clock operation f = internal operation frequency 10 9 8 ICCLS (A) 7 f = 8 kHz 6 5 4 3 2 1 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 (Continued) 84 DS07-13713-6E MB90495G Series (Continued) ICCT - VCC TA = + 25 C, external clock operation f = internal operation frequency 7 6 f = 8 kHz ICCT (A) 5 4 3 2 1 0 3.0 4.0 5.0 VCC (V) 6.0 VOL - IOL TA = + 25 C, VCC = 4.5 V 1000 1000 900 900 800 800 700 700 600 600 VOL (V) VCC - VOH (mV) (VCC - VOH) - IOH TA = + 25 C, VCC = 4.5 V 500 500 400 400 300 300 200 200 100 100 0 7.0 0 0 DS07-13713-6E 1 2 3 4 5 6 7 IOH (mA) 8 9 10 11 12 0 1 2 3 4 5 6 7 IOL (mA) 8 9 10 11 12 85 MB90495G Series * MB90497G ICC - VCC TA = + 25 C, external clock operation f = internal operation frequency 45 40 35 f = 16 MHz ICC (mA) 30 25 f = 10 MHz 20 f = 8 MHz 15 10 f = 4 MHz 5 f = 2 MHz 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 ICCS - VCC TA = + 25 C, external clock operation f = internal operation frequency 16 14 f = 16 MHz 12 ICCS (mA) 10 f = 10 MHz 8 f = 8 MHz 6 4 f = 4 MHz 2 0 3.0 f = 2 MHz 4.0 5.0 VCC (V) 6.0 7.0 (Continued) 86 DS07-13713-6E MB90495G Series (Continued) ICCL - VCC TA = + 25 C, external clock operation f = internal operation frequency 25 ICCL (A) 20 f = 8 kHz 15 10 5 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 ICCLS - VCC TA = + 25 C, external clock operation f = internal operation frequency 10 9 f = 8 kHz 8 ICCLS (A) 7 6 5 4 3 2 1 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 (Continued) DS07-13713-6E 87 MB90495G Series (Continued) ICCT - VCC TA = + 25 C, external clock operation f = internal operation frequency 7 f = 8 kHz 6 ICCT (A) 5 4 3 2 1 0 3.0 4.0 5.0 VCC (V) 6.0 1000 1000 900 900 800 800 700 700 600 600 500 500 400 400 300 300 200 200 100 100 0 0 0 88 VOL - IOL TA = + 25 C, VCC = 4.5 V VOL (V) VCC - VOH (mV) (VCC - VOH) - IOH TA = + 25 C, VCC = 4.5 V 7.0 1 2 3 4 5 6 7 IOH (mA) 8 9 10 11 12 0 1 2 3 4 5 6 7 IOL (mA) 8 9 10 11 12 DS07-13713-6E MB90495G Series ORDERING INFORMATION Part Number Package MB90F497GPF MB90497GPF MB90F498GPF 64-pin plastic QFP (FPT-64P-M06) MB90F497GPMC MB90497GPMC MB90F498GPMC 64-pin plastic LQFP (FPT-64P-M23) DS07-13713-6E Remarks 89 MB90495G Series PACKAGE DIMENSIONS 64-pin plastic QFP Lead pitch 1.00 mm Package width x package length 14 x 20 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP64-14x20-1.00 (FPT-64P-M06) 64-pin plastic QFP (FPT-64P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 24.700.40(.972.016) * 20.000.20(.787.008) 51 0.170.06 (.007.002) 33 32 52 18.700.40 (.736.016) *14.000.20 (.551.008) INDEX Details of "A" part +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 20 64 0~8 1 19 1.00(.039) 0.420.08 (.017.003) 0.20(.008) +0.15 M 0.25 -0.20 1.200.20 (.047.008) +.006 .010 -.008 (Stand off) "A" 0.10(.004) C 2003-2008 FUJITSU MICROELECTRONICS LIMITED F64013S-c-5-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 90 DS07-13713-6E MB90495G Series (Continued) 64-pin plastic LQFP Lead pitch 0.65 mm Package width x package length 12.0 x 12.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LFQFP64-12x12-0.65 (FPT-64P-M23) 64-pin plastic LQFP (FPT-64P-M23) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.000.20(.551.008)SQ *12.000.10(.472.004)SQ 48 0.1450.055 (.0057.0022) 33 49 32 0.10(.004) Details of "A" part +0.20 1.50 -0.10 +.008 (Mounting height) .059 -.004 0.25(.010) INDEX 0~8 64 17 1 "A" 16 0.65(.026) 0.320.05 (.013.002) 0.13(.005) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) (Stand off) M (c)2003-2008 FUJITSU LIMITED F64034S-c-1-2 C 2003 FUJITSU LIMITEDMICROELECTRONICS F64034S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ DS07-13713-6E 91 MB90495G Series MAIN CHANGES IN THIS EDITION Page 18 23 Section BLOCK DIAGRAM 16-bit reload timer I/O MAP Address : 0000AAH Change Results Corrected the direction of arrow for TIN0, TIN1 signal. " (output)" " (input)" Corrected the Initial Value of "Watch timer control register". 10001000B 1X001000B The vertical lines marked in the left side of the page show the changes. 92 DS07-13713-6E MB90495G Series MEMO DS07-13713-6E 93 MB90495G Series MEMO 94 DS07-13713-6E MB90495G Series MEMO DS07-13713-6E 95 MB90495G Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. 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