TM FQG4904 400V Dual N & P-Channel MOSFET General Description Features These dual N and P-channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic lamp ballast based on half bridge. * N-Channel 0.46A, 400V, RDS(on) = 3.0 @ VGS = 10 V P-Channel -0.46A, -400V, RDS(on) = 3.0 @ VGS = -10 V * Low gate charge ( typical N-Channel 7.6 nC) ( typical P-Channel 20.0 nC) * Fast switching * Improved dv/dt capability D2 D2 D1 D1 8-DIP G2 S2 G1 S1 Pin #1 Absolute Maximum Ratings Symbol VDSS ID 5 4 6 3 7 2 8 1 TA = 25C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TA = 25C) Drain Current N-Channel 400 P-Channel -400 Units V 0.46 -0.46 A 0.29 -0.29 A (Note 1) 3.68 -3.68 A (Note 2) 4.5 - Continuous (TA = 100C) IDM Drain Curent VGSS dv/dt PD Gate-Source Voltage Peak Diode Recovery dv/dt Power Dissipation (TA = 25C) TJ, TSTG - Derate above 25C Operating and Storage Temperature Range - Pulsed 30 -4.5 1.6 0.013 -55 to +150 V V/ns W W/C C Thermal Characteristics Symbol RJA Parameter Thermal Resistance, Junction-to-Ambient (c)2002 Fairchild Semiconductor Corporation (Note 5a) Typ -- Max 78 Units C/W Rev. A1, April 2002 FQG4904 QFET Symbol TA = 25C unless otherwise noted Parameter Test Conditions Type Min Typ Max Units Off Characteristics BVDSS BVDSS / TJ IDSS Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 A N-Ch 400 -- -- V VGS = 0 V, ID = -250 A P-Ch -400 -- -- V N-Ch -- 0.47 -- V/C P-Ch -- -0.3 -- V/C ID = 250 A, Referenced to 25C ID = -250 A, Referenced to 25C VDS = 400 V, VGS = 0 V VDS = 320 V, TA = 125C VDS = -400 V, VGS = 0 V VDS = -320 V, TA = 125C N-Ch P-Ch -- -- 10 A -- -- 100 A -- -- -10 A -- -- -100 A IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V All -- -- 100 nA IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V All -- -- -100 nA On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 A N-Ch 2.0 -- 4.0 V VDS = VGS, ID = -250 A P-Ch -2.0 -- -4.0 V VGS = 10 V, ID = 0.23 A N-Ch -- 2.0 3.0 VGS = -10 V, ID = -0.23 A P-Ch -- 2.2 3.0 VDS = 40 V, ID = 0.23 A N-Ch -- 0.8 -- S VDS = -40 V, ID = -0.23 A P-Ch -- 1.1 -- S N-Channel VDS = 25 V, VGS = 0 V, f = 1.0 MHz P-Channel VDS = -25 V, VGS = 0 V, f = 1.0 MHz N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch ------- 235 500 40 85 6.5 14 300 645 55 110 8.5 18.5 pF pF pF pF pF pF N-Channel VDD = 200 V, ID = 0.46 A, RG = 25 N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch --------------- 6.5 10 16 21 28 85 34 56 7.6 20 1.2 2.7 3.3 9.9 25 30 40 52 65 180 80 120 10 26 ----- ns ns ns ns ns ns ns ns nC nC nC nC nC nC Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge P-Channel VDD = -200 V, ID = -0.46 A, RG = 25 (Note 3,4) (c)2002 Fairchild Semiconductor Corporation N-Channel VDS = 320 V, ID = 0.46 A, VGS = 10 V P-Channel VDS = -320 V, ID = -0.46 A, (Note 3,4) VGS = -10 V Rev. A1, April 2002 FQG4904 Electrical Characteristics Symbol Parameter Test Conditions Type Min Typ Max Units ------ ------ 0.46 -0.46 3.68 -3.68 1.4 A A A A V -- -- -5.0 V -- 104 -- ns -- 248 -- nC -- 117 -- ns -- 497 -- nC Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current ISM Maximum Pulsed Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.46 A N-Ch P-Ch N-Ch P-Ch N-Ch VGS = 0 V, IS = -0.46 A P-Ch trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 0.46 A, (Note 3) dIF / dt = 100 A/s trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = -0.46 A, (Note 3) dIF / dt = 100 A/s N-Ch P-Ch Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. ISD 0.46A, di/dt 200A/s, VDD BVDSS, Starting TJ = 25C 3. Pulse Test : Pulse width 300s, Duty cycle 2% 4. Essentially independent of operating temperature 5. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance. RCA is determined by the user's board design Maximum RJA using the different board layouts on 3"x4.5" FR-4 PCB in a still air environment : a. 78C/W when mounted without any pad copper b. 60C/W when mounted on a 4.5 in2 pad of 2oz copper. In such an environment, the power dissipation can be enhanced up to 2.1W (c)2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Electrical Characteristics (Continued) FQG4904 Typical Characteristics : N-Channel VGS 15.0 V 10.0 V 8.0 V 6.0 V 5.5 V 5.0 V 4.5 V Bottom : 4.0 V 0 ID, Drain Current [A] 10 ID , Drain Current [A] Top : -1 10 0 10 150 25 -55 Notes : 1. 250 s Pulse Test 2. TA = 25 Notes : 1. VDS = 40V 2. 250 s Pulse Test -1 -1 0 10 10 1 10 10 0 2 4 6 8 10 VGS , Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 10 IDR, Reverse Drain Current [A] RDS(ON) [ ], Drain-Source On-Resistance 8 VGS = 10V 6 VGS = 20V 4 2 0 10 150 25 Notes : 1. VGS = 0V 2. 250 s Pulse Test Note : TJ = 25 -1 0 0 2 4 6 8 10 0.2 0.4 0.6 Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 500 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 1.0 1.2 1.4 Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 12 VDS = 80V Ciss 300 Coss 200 Note ; 1. VGS = 0 V 2. f = 1 MHz Crss 100 VGS, Gate-Source Voltage [V] 10 400 Capacitance [pF] 0.8 VSD, Source-Drain voltage [V] ID, Drain Current [A] VDS = 200V VDS = 320V 8 6 4 2 Note : ID = 0.46 A 0 -1 10 0 10 1 10 VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics (c)2002 Fairchild Semiconductor Corporation 0 0 2 4 6 8 10 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. A1, April 2002 FQG4904 Typical Characteristics : N-Channel (Continued) 2.5 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.0 1.1 1.0 Notes : 1. VGS = 0 V 2. ID = 250 A 0.9 0.8 -100 -50 0 50 100 150 1.5 1.0 Notes : 1. VGS = -10 V 2. ID = -0.23 A 0.5 0.0 -100 200 -50 0 o 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 0.5 Operation in This Area is Limited by R DS(on) 1 10 0 10 ID, Drain Current [A] ID, Drain Current [A] 0.4 100 s 1 ms 0.3 10 ms 100 ms 1s -1 10 0.2 DC Notes : o -2 1. TA = 25 C 10 0.1 o 2. TJ = 150 C 3. Single Pulse -3 10 0 10 1 2 10 0.0 25 3 10 10 50 J A Z (t) , T h e r m a l R e s p o n s e 100 125 150 Figure 10. Maximum Drain Current vs. Ambient Temperature Figure 9. Maximum Safe Operating Area 10 75 TA, Ambient Temperature [] VDS, Drain-Source Voltage [V] 2 D = 0 .5 0 .2 10 1 0 .1 PDM 0 .0 5 t1 0 .0 2 10 0 t2 0 .0 1 N o te s : 1 . Z J A ( t) = 7 8 / W M a x . 2 . D u t y F a c t o r , D = t 1 /t 2 3 . T J M - T A = P D M * Z J A ( t) s i n g le p u l s e 10 -1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t 1 , S q u a r e W a v e P u ls e D u ra tio n [s e c ] Figure 11. Transient Thermal Response Curve (c)2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Typical Characteristics : P-Channel VGS -15.0 V -10.0 V -8.0 V -6.0 V -5.5 V -5.0 V -4.5 V Bottom : -4.0 V 0 -ID, Drain Current [A] 10 -I D , Drain Current [A] Top : -1 0 10 150 25 -55 10 Notes : 1. VDS = -40V 2. 250 s Pulse Test Notes : 1. 250 s Pulse Test 2. TA = 25 -1 -1 0 10 10 1 10 10 0 2 4 6 8 10 -VGS , Gate-Source Voltage [V] -VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 10 -I DR, Reverse Drain Current [A] RDS(ON) [ ], Drain-Source On-Resistance 8 VGS = -10V 0 10 6 VGS = -20V 4 2 150 Notes : 1. VGS = 0V 2. 250 s Pulse Test 25 Note : TJ = 25 -1 0 10 0 2 4 6 8 10 12 0.0 0.5 Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 1400 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 1200 2.0 12 VDS = -80V Coss 600 Crss Note ; 1. VGS = 0 V 2. f = 1 MHz 400 200 -VGS, Gate-Source Voltage [V] Capacitance [pF] Ciss 800 1.5 Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature VDS = -200V 10 1000 1.0 -VSD, Source-Drain voltage [V] -ID, Drain Current [A] VDS = -320V 8 6 4 2 Note : ID = -0.46 A 0 -1 10 0 10 1 10 -VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics (c)2002 Fairchild Semiconductor Corporation 0 0 5 10 15 20 25 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. A1, April 2002 FQG4904 Typical Characteristics : P-Channel (Continued) 2.5 2.5 1.2 RDS(ON) , (Normalized) DS(ON) On-Resistance Drain-Source On-Resistance -BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.0 2.0 1.1 1.0 Notes : 1. VGS = 0 V 2. ID = -250 A 0.9 0.8 -100 -50 0 50 100 150 1.5 1.5 1.0 1.0 Notes Notes:: 1.1.VVGSGS==-10 -10VV 2.2.IDID==-0.23 -0.26AA 0.5 0.5 0.0 0.0 -100 -100 200 -50 0 o 50 100 100 150 150 200 200 oo TJ, Junction Temperature [ C] TJ, Junction Temperature Temperature[[ C] C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 0.5 Operation in This Area is Limited by R DS(on) 1 10 0 10 -ID, Drain Current [A] -ID, Drain Current [A] 0.4 100 s 1 ms 0.3 10 ms 100 ms 1s -1 10 0.2 DC Notes : o -2 1. TA = 25 C o 2. TJ = 150 C 3. Single Pulse 10 0.1 -3 10 0 10 1 2 10 0.0 25 3 10 10 50 J A Z (t) , T h e r m a l R e s p o n s e Figure 9. Maximum Safe Operating Area 10 75 100 125 150 TA, Ambient Temperature [] -VDS, Drain-Source Voltage [V] Figure 10. Maximum Drain Current vs. Ambient Temperature 2 D = 0 .5 0 .2 10 1 0 .1 PDM 0 .0 5 t1 0 .0 2 10 0 t2 0 .0 1 N o te s : 1 . Z J A ( t) = 7 8 / W M a x . 2 . D u t y F a c t o r , D = t 1 /t 2 3 . T J M - T A = P D M * Z J A ( t) s i n g le p u l s e 10 -1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t 1 , S q u a r e W a v e P u ls e D u ra tio n [s e c ] Figure 11. Transient Thermal Response Curve (c)2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Gate Charge Test Circuit & Waveform (N-Channel) 50K 12V VGS Same Type as DUT Qg 200nF 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms (N-Channel) VDS RL VDS 90% VDD VGS RG VGS DUT 10V 10% td(on) tr td(off) t on tf t off Gate Charge Test Circuit & Waveform (P-Channel) 50K 12V VGS Same Type as DUT Qg 200nF -10V 300nF VDS VGS Qgs Qgd DUT -3mA Charge Resistive Switching Test Circuit & Waveforms (P-Channel) VDS RL VDD VGS RG -10V t on td(on) VGS td(off) tf 10% DUT VDS (c)2002 Fairchild Semiconductor Corporation t off tr 90% Rev. A1, April 2002 FQG4904 Peak Diode Recovery dv/dt Test Circuit & Waveforms (N-Channel) DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD * dv/dt controlled by RG * ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop (c)2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Peak Diode Recovery dv/dt Test Circuit & Waveforms (P-Channel) + VDS DUT _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Compliment of DUT (N-Channel) VDD * dv/dt controlled by RG * ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop VDD Body Diode Recovery dv/dt (c)2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Package Dimensions #4 #5 1.524 0.10 0.060 0.004 0.46 0.10 #8 2.54 0.100 9.60 MAX 0.378 #1 9.20 0.20 0.362 0.008 ( 6.40 0.20 0.252 0.008 0.018 0.004 0.79 ) 0.031 8-DIP 5.08 MAX 0.200 7.62 0.300 3.40 0.20 0.134 0.008 3.30 0.30 0.130 0.012 0.33 MIN 0.013 +0.10 0.25 -0.05 +0.004 0~15 0.010 -0.002 Dimensions in Millimeters (c)2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM I2CTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench(R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SLIENT SWITCHER(R) SMART STARTTM SPMTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET(R) VCXTM STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. (c)2002 Fairchild Semiconductor Corporation Rev. H5 Product Folder - Fairchild P/N FQG4904 - 400V Dual N & P-Channel QFET SEARCH | Parametric | Cross Reference space Fairchild Semiconductor space GO space space space space space >> Find products >> Home find products space space space FQG4904 Products groups 400V Dual N & P-Channel QFET Analog and Mixed Signal Contents Discrete General description | Features | Product Interface status/pricing/packaging Logic space Microcontrollers Non-Volatile General description Memory spaceOptoelectronics Markets and These dual N and P-channel enhancement applications mode power field effect transistors are New products produced using Fairchild's proprietary, planar Product selection and stripe, DMOS technology. parametric search This advanced technology has been especially Cross-reference tailored to minimize on-state resistance, search provide superior switching performance, and withstand high energy pulse in the avalanche technical information and commutation mode. These devices are well buy products suited for electronic lamp ballast based on half bridge. technical support back to top company Features N-Channel 0.46A, 400V, RDS(on) = 3.0@ VGS = 10 V P-Channel -0.46A, -400V, RDS(on) = 3.0 @ VGS = -10 V Low gate charge (typical N-Channel 7.6 nC) (typical P-Channel 20.0 nC) Fast switching Improved dv/dt capability back to top Product status/pricing/packaging file:///D|/clubbed_SUN/SUN/FQG4904.html (1 of 2) [27-Jul-2002 12:05:53 PM] Application notes Related Links Datasheet Download this datasheet PDF e-mail this datasheet [Email] This pagePrint version space my Fairchild Product Folders and Datasheets Request samples Dotted line How to order products Dotted line Product Change Notices (PCNs) Dotted line Support Dotted line Distributor and field sales representatives Dotted line Quality and reliability Dotted line Design tools Product Folder - Fairchild P/N FQG4904 - 400V Dual N & P-Channel QFET Product FQG4904TU Product status Package type Leads Packing method Full Production DIP 8 RAIL back to top space Home | Find products | Technical information | Buy products | Support | Company | Contact us | Site index | Privacy policy space (c) Copyright 2002 Fairchild Semiconductor space file:///D|/clubbed_SUN/SUN/FQG4904.html (2 of 2) [27-Jul-2002 12:05:53 PM] space