©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002
FQG4904
QFETTM
FQG4904
400V Dual N & P-Cha nnel MOSFET
General Description
These dual N and P-channel enhancement mode power
field effect transistors are produced using Fairchild’s
proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for electronic lamp ballast based on half bridge.
Features
• N-Channel 0.46A, 400V, RDS(on) = 3.0 Ω @ VGS = 10 V
P-Channel -0.46A, -400V, RDS(on) = 3.0 Ω @ VGS = -10 V
• Low gate charge ( typical N-Channel 7.6 nC)
( typical P-Channel 20.0 nC)
• Fast switching
• Improved dv/dt capability
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Thermal Characteristics
Symbol Parameter N-Channel P-Channel Units
VDSS Drain-Source Voltage 400 -400 V
IDDrain Current - Continuous (TA = 25°C) 0.46 -0.46 A
- Continuous (TA = 100°C) 0.29 -0.29 A
IDM Drain Curent - Pulsed (Note 1) 3.68 -3.68 A
VGSS Gate-Source Voltage ± 30 V
dv/dt Peak Diode Recovery dv/dt (Note 2) 4.5 -4.5 V/ns
PDPower Dissipation (TA = 25°C) 1.6 W
- Derate above 25°C 0.013 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
Symbol Parameter Typ Max Units
RθJA Thermal Resistance, Junction-to-Ambient (Note 5a) -- 78 °C/W
4
3
2
1
5
6
7
8
S1G1S2G2
D1D1D2D2
Pin #1
8-DIP
Rev. A1, April 2002
FQG4904
©2002 Fairchild Semiconductor Corporation
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, ID = 250 µAN-Ch 400 -- -- V
VGS = 0 V, ID = -250 µAP-Ch -400 -- -- V
∆BVDSS
/ ∆TJ
Breakdown Vo ltage Temperature
Coefficient ID = 250 µA,
Referenced to 25°C N-Ch -- 0.47 -- V/°C
ID = -250 µA,
Referenced to 25°C P-Ch -- -0.3 -- V/°C
IDSS Zero Gate Voltage Drain Current VDS = 400 V, VGS = 0 V N-Ch -- -- 10 µA
VDS = 320 V, T A = 125°C -- -- 100 µA
VDS = -400 V, VGS = 0 V P-Ch -- -- -10 µA
VDS = -320 V, T A = 125°C -- -- -100 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V All -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V All -- -- -100 nA
On Characteri st ics
VGS(th) Gate Threshold Volt age VDS = VGS, ID = 250 µAN-Ch 2.0 -- 4.0 V
VDS = VGS, ID = -250 µAP-Ch -2.0 -- -4.0 V
RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 0.23 A N-Ch -- 2.0 3.0 Ω
VGS = -10 V, ID = -0.23 A P-Ch -- 2.2 3.0 Ω
gFS Forward Transconductance VDS = 40 V, ID = 0.23 A N-Ch -- 0.8 -- S
VDS = -40 V, ID = -0.23 A P-Ch -- 1.1 -- S
Dynamic Characteristics
Ciss Input Capacitance N-Channel
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
P-Channel
VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
N-Ch -- 235 300 pF
P-Ch -- 500 645 pF
Coss Output Capacitance N-Ch -- 40 55 pF
P-Ch -- 85 110 pF
Crss Reverse Transfer Capacit ance N-Ch -- 6.5 8.5 pF
P-Ch -- 14 18.5 pF
Switching Characteristics
td(on) Turn-On Delay Time N-Channel
VDD = 200 V, ID = 0.46 A,
RG = 25 Ω
P-Channel
VDD = -200 V, ID = -0.46 A,
RG = 25 Ω
(Note 3,4)
N-Ch -- 6.5 25 ns
P-Ch -- 10 30 ns
trTurn-On Rise Time N-Ch -- 16 40 ns
P-Ch -- 21 52 ns
td(off) Turn-Off Dela y Time N-Ch -- 28 65 n s
P-Ch -- 85 180 ns
tfTurn-Off Fall Time N - C h -- 34 8 0 n s
P-Ch -- 56 120 ns
QgTotal Gate Charge N-Channel
VDS = 320 V, ID = 0.46 A,
VGS = 10 V
P-Channel
VDS = -320 V, ID = -0.46 A,
VGS = -10 V (Note 3,4)
N-Ch -- 7.6 10 nC
P-Ch -- 20 26 nC
Qgs Gate-Source Charge N-Ch -- 1.2 -- nC
P-Ch -- 2.7 -- nC
Qgd Gate-Drain Charge N-Ch -- 3.3 -- nC
P-Ch -- 9.9 -- nC
Rev. A1, April 2002
FQG4904
©2002 Fairchild Semiconductor Corporation
Electrical Characteristics (Continued)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. ISD ≤ 0.46A, di/dt ≤ 200A/µs, VDD ≤ BVDSS , Starti ng TJ = 25°C
3. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤2%
4. Essentially independent of operating temperature
5. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance. RθCA is determined by the user’s board design
Maximum RθJA using the different board layouts on 3”x4.5” FR-4 PCB in a still air environment :
a. 78°C/W when moun ted without any pad copper
b. 60°C/W when mounted on a 4.5 in2 pad of 2oz copper. In such an environment, the power dissipation can be enhanced up to 2.1W
Symbol Parameter Test Condit ions Type Min Typ Max Units
Drain-Source Diode Characteristics and Maximum Ratings
ISMaximum Continuous Drain-Source Diode Forward Current N-Ch -- -- 0.46 A
P-Ch -- -- -0.46 A
ISM Maximum Pulsed Drain-Source Diode Forward Current N-Ch -- -- 3.68 A
P-Ch -- -- -3.68 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.46 A N-Ch -- -- 1.4 V
VGS = 0 V, IS = -0.46 A P-Ch -- -- -5.0 V
trr Reverse Recovery Time VGS = 0 V, IS = 0.46 A,
dIF / dt = 100 A/ µs (Note 3) N-Ch -- 104 -- ns
Qrr Reverse Recovery Charge -- 248 -- nC
trr Reverse Recovery Time VGS = 0 V, IS = -0.46 A,
dIF / dt = 100 A/ µs (Note 3) P-Ch -- 117 -- ns
Qrr Reverse Recovery Charge -- 497 -- nC
©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002
FQG4904
0246810
0
2
4
6
8
10
12
VDS = 200V
VDS = 80V
VDS = 320V
! No te : ID = 0.46 A
VGS, G ate-Source Voltage [V]
QG, T o tal G a te C h a rg e [n C ]
0.2 0.4 0.6 0.8 1.0 1.2 1.4
10-1
100
150"
! Note s :
1. V GS = 0V
2. 250#s Pulse Te st
25"
IDR, Reverse Drain Current [A]
VSD, Source-Drain voltage [V]
0246810
10-1
100
! No te s :
1. V DS = 40 V
2. 250#s P ulse Test
-55"
150"
25"
ID , Drain Current [A]
VGS , Gate-Source Voltage [V]
10-1 100101
10-1
100
VGS
T op : 1 5 .0 V
10.0 V
8.0 V
6.0 V
5.5 V
5.0 V
4.5 V
B otto m : 4 .0 V
! Note s :
1. 2 5 0 #s Pu lse T est
2. T A = 25"
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
10-1 100101
0
100
200
300
400
500 Ciss = C gs + C gd (Cds = shorted)
Coss = C ds + Cgd
Crss = C gd
! No te ;
1. V GS = 0 V
2. f = 1 MHz
Crss
Coss
Ciss
Capacitance [pF]
VDS, Drain-Source Voltage [V ]
02468
0
2
4
6
8
10
VGS = 20V
VGS = 10V
!
N o te : TJ = 25"
RDS(ON) [$],
Drain-Source On-Resistance
ID, D r ain Cur re n t [A ]
Typical Characteristics : N-Channel
Figure 5. C apacitance C haracteristi cs Figure 6. Gate Charge Chara ct eri stics
Figu re 3. On-R esistan ce Variat ion vs.
Drain Current and Gate Voltage
Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Characteri st ic s
Figure 4. Body Diode Fo rwa rd Voltage
Variation vs. Source Current
and Temperature
©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002
FQG4904
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
! No te s :
1. V GS = -10 V
2. ID = -0.23 A
RDS(ON) , (Norm alized)
Drain-Source On-Resistance
TJ, Junction Tem perature [oC]
10-5 10-4 10-3 10-2 10-1 100101102103
10-1
100
101
102
! No te s :
1 . Z%JA(t) = 7 8 "/W Ma x .
2. D u ty F ac to r, D= t1/t2
3 . TJM - T A = PDM * Z %JA(t)
sing le p ulse
D=0.5
0.02
0.2
0.05
0.1
0.01
ZθJA
(t), Thermal R esponse
t1, S quare Wave Pulse Duration [sec]
25 50 75 100 125 150
0.0
0.1
0.2
0.3
0.4
0.5
ID, Drain Current [A]
TA, Am bient Tem perature ["
]
100101102103
10-3
10-2
10-1
100
101
10 m s
100 ms
1 s
100 µs
DC
1 m s
Operation in This Area
is Lim ited by R DS(on)
! N o te s :
1. TA = 25 oC
2. TJ = 150 oC
3. Sing le P uls e
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
!
Notes :
1. VGS = 0 V
2. ID = 250 #A
BV DSS , (Norm alized)
D rain-Source Breakdown V oltage
TJ, Junction Tem perature [oC]
Typical Characteristics : N-Channel (Continued)
Figure 10. Maximum Drain Current
vs. Ambient Temperature
Figu re 7. Breakdo w n Vol ta g e Variat i on
vs. Temperature Figure 8. On-Resistance Variation
vs. Temperature
Figure 9. Maximum Safe Operating Area
Figure 11. Tr ansient Thermal Respons e Cur ve
t1
PDM
t2
©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002
FQG4904
0 5 10 15 20 25
0
2
4
6
8
10
12
VDS = -200V
VDS = -80V
VDS = -320V
! No te : I D = -0.46 A
-VGS, Gate-Source Voltage [V]
QG, T o tal G a te C ha rg e [nC ]
0.0 0.5 1.0 1.5 2.0
10-1
100
150"! N o te s :
1. V GS = 0V
2. 250#s Pulse Te st
25"
-IDR, Reverse Drain Current [A]
-VSD, Source-Drain voltage [V ]
0246810
10-1
100
! No tes :
1. VDS = -40V
2. 250#s Pulse Test
-55"
150"
25"
-ID , Drain Current [A]
-VGS , G ate-Source Voltage [V]
10-1 100101
10-1
100
VGS
To p : -15.0 V
-10.0 V
-8.0 V
-6.0 V
-5.5 V
-5.0 V
-4.5 V
Bo ttom : -4.0 V
! Notes :
1. 25 0 #s Pulse Test
2. TA = 25"
-ID, Drain Current [A]
-VDS, Drain-Source Voltage [V]
10-1 100101
0
200
400
600
800
1000
1200
1400 Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
! No te ;
1. VGS = 0 V
2. f = 1 MHz
Crss
Coss
Ciss
Ca pacitance [pF]
-VDS, Drain-Source Voltage [V]
024681012
0
2
4
6
8
10
VGS = -20V
VGS = -10V
! No te : TJ = 25"
RDS(ON) [$],
Drain-Source On-Resistance
-ID, Drain Current [A]
Typical Characteristics : P-Channel
Figure 5. C apacitance C haracteristi cs Figure 6. Gate Charge Chara ct eri stics
Figu re 3. On-R esistan ce Variat ion vs.
Drain Current and Gate Voltage
Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Characteri st ic s
Figure 4. Body Diode Fo rwa rd Voltage
Variation vs. Source Current
and Temperature
©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002
FQG4904
10-5 10-4 10-3 10-2 10-1 100101102103
10-1
100
101
102
! No te s :
1 . Z%JA(t) = 7 8 "/W Ma x .
2. D u ty F ac to r, D= t1/t2
3 . TJM - T A = PDM * Z %JA(t)
sing le p ulse
D=0.5
0.02
0.2
0.05
0.1
0.01
ZθJA
(t), Thermal R esponse
t1, S quare Wave Pulse Duration [sec]
25 50 75 100 125 150
0.0
0.1
0.2
0.3
0.4
0.5
-ID, Drain Current [A]
TA, Am bient Tem perature ["
]
100101102103
10-3
10-2
10-1
100
101
10 m s
100 m s
1 s
100 µs
DC
1 m s
Operation in This Area
is Limited by R DS(on)
! Notes :
1. TA = 25 oC
2. TJ = 150 oC
3. Sin gle P u lse
-ID, Drain Current [A]
-VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
!
N o te s :
1 . V GS = -10 V
2 . ID = -0.23 A
RDS(ON) , (Normalized)
D rain-Source O n-Resistance
TJ, Junction Tem perature [oC]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
!
N o te s :
1 . VGS = -10 V
2 . ID = -0 .2 6 A
RDS(ON) , (Normalized)
D rain-Source On-Resistance
TJ, Junction Tem perature [oC]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
!
Notes :
1. VGS = 0 V
2. ID = -250 #A
-BV DSS , (Norm alized)
D rain-Source Breakdow n Voltage
TJ, Junction Tem perature [oC]
Typical Characteristics : P-Channel (Continued)
Figure 10. Maximu m Drain Curr ent
vs. Ambient Temperature
Figu re 7. Breakdo w n Vol ta g e Variat i on
vs. Temperature Figure 8. On-Resistance Variation
vs. Temperature
Figure 9. Maximum Safe Operating Area
Figure 11. Tr ansient Thermal Respons e Cur ve
t1
PDM
t2
©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002
FQG4904
Charge
VGS
-10V Qg
Qgs Qgd
-3mA
VGS
DUT
VDS
300nF
50K&
200nF
12V
Same Type
as DUT
Charge
VGS
-10V Qg
Qgs Qgd
-3mA
VGS
DUT
VDS
300nF
50K&
200nF
12V
Same Type
as DUT
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50K&
200nF
12V
Same Type
as DUT
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50K&
200nF
12V
Same Type
as DUT
Gate Charge Test Circuit & Waveform (N-Channel)
Resistive Switching Test Circuit & Waveforms (N-Channel)
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
Gate Charge Test Circuit & Waveform (P-Channe l)
VDS
VGS 10%
90%
td(on) tr
ton toff
td(off) tf
VDD
-10V
VDS RL
DUT
RG
VGS
VDS
VGS 10%
90%
td(on) tr
ton toff
td(off) tf
VDD
-10V
VDS RL
DUT
RG
VGS
Resistive Switching Test Circuit & Waveforms (P-Channel)
©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002
FQG4904
Peak Diode Recovery dv/dt Test Circuit & Waveforms (N-Channel)
DUT
VDS
+
_
Driver
RGSame Typ e
as DUT
VGS • dv/dt controlled by RG
•I
SD con trolled by pulse per iod
VDD
L
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
DUT
VDS
+
_
Driver
RGSame Typ e
as DUT
VGS • dv/dt controlled by RG
•I
SD con trolled by pulse per iod
VDD
LL
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002
FQG4904
Peak Diode Recovery dv/dt Test Circuit & Waveforms (P-Channel)
DUT
VDS
+
_
Driver
RGCompliment of DUT
(N-Channel)
VGS • dv/dt controlled by RG
•I
SD con trolled by pulse per iod
VDD
L
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
DUT
VDS
+
_
Driver
RGCompliment of DUT
(N-Channel)
VGS • dv/dt controlled by RG
•I
SD con trolled by pulse per iod
VDD
LL
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
Rev. A1, April 2002©2002 Fairchild Semiconductor Corporation
FQG4904
Dimensions in Millimeters
Package Dimensions
8-DIP
6.40 ±0.20
3.30 ±0.30
0.130 ±0.012
3.40 ±0.20
0.134 ±0.008
#1
#4 #5
#8
0.252 ±0.008
9.20 ±0.20
0.79
2.54
0.100
0.031
()
0.46 ±0.10
0.018 ±0.004
0.060 ±0.004
1.524 ±0.10
0.362 ±0.008
9.60
0.378 MAX
5.08
0.200
0.33
0.013
7.62
0~15°
0.300
MAX
MIN
0.25 +0.10
–0.05
0.010+0.004
–0.002
©2002 Fairchild Semiconductor Corporation
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY A NY LICENSE UNDER ITS PATENT RIGHTS, N OR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devic es or syst em s
which, (a) ar e intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary First Production This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconduct or reserv es the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H5
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all su ch trademarks.
STAR*POWE R is used under license
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Contents
General description | Features | Product
status/pricing/packaging
General description
These dual N and P-channel enhancement
mode power field effect transistors are
produced using Fairchild’s proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially
tailored to minimize on-state resistance,
provide superior switching performance, and
withstand high energy pulse in the avalanche
and commutation mode. These devices are well
suited for electronic lamp ballast based on half
bridge.
back to top
Features
● N-Channel 0.46A, 400V, RDS(on) =
3.0Ω@ VGS = 10 V
P-Channel -0.46A, -400V, RDS(on) =
3.0Ω @ VGS = -10 V
● Low gate charge (typical N-Channel 7.6
nC)
(typical P-Channel 20.0 nC)
● Fast switching
● Improved dv/dt capability
back to top
space
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Product status/pricing/packaging
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Product Folder - Fairchild P/N FQG4904 - 400V Dual N & P-Channel QFET
Product Product status Package type Leads Packing method
FQG4904TU Full Production DIP 8 RAIL
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