L9524C Glow plug system control IC Features Quad gate driver for external N-channel Power MOSFETs in high-side configuration: - Gates driven by PWM output signal - Adjustable gate charge/discharge currents - Limited gate-to-source voltages - Negative clamping for inductive loads - Advanced run-off control - Regulation of the power through the glow plugs Control output for external relay driver Battery-voltage-compatible two-wire interface Supply voltage monitoring with shutdown Battery voltage monitoring with shutdown Junction temperature monitoring with shutdown Monitoring of currents through the glow plugs with shutdown at overcurrent (adjustable threshold) Monitoring of external switches Charge pump voltage monitoring with shutdown Active clamping during load dump Table 1. SO24 Description The L9524C is a control IC for up to six glow plugs of diesel engines. The glow plugs are switched by up to four external PWM-controlled N-channel Power MOSFETs or a single relay in high-side configuration. Supply voltage, battery voltage, junction temperature, switches, currents through the glow plugs, and charge pump voltage are monitored. A two-wire interface is used to communicate with the diesel engine management system. Device summary Order code Package Packing L9524C SO24 Tube L9524C-TR SO24 Tape and reel January 2008 Rev 3 1/27 www.st.com 1 Contents L9524C Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Control input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 Switch monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 Relay output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.10 Gate charge/discharge current variation . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11 Overcurrent threshold variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 Advanced run-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.13 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14 Power regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 L9524C List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Go / no-go protocol description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Failure register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sense input pin connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3/27 List of figures L9524C List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. 4/27 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Shunt sense versus transistor sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Control input signal in transistor mode (modes 3 to 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Permanent switch on of glow plugs at first falling edge in transistor mode (modes 3 to 6) 14 Control input signal in mode 2 for permanent switch on . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial diagnostic interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timing diagram of advanced run-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Mode 1: relay mode, go/no-go diagnostic interface protocol . . . . . . . . . . . . . . . . . . . . . . . 22 Mode 2: relay mode, serial diagnostic interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Mode 3: transistor mode, shunt sense, no power regulation . . . . . . . . . . . . . . . . . . . . . . . 23 Mode 4: transistor mode, shunt sense, power regulation . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Mode 5: transistor mode, transistor sense, no power regulation . . . . . . . . . . . . . . . . . . . . 24 Mode 6: transistor mode, transistor sense, power regulation . . . . . . . . . . . . . . . . . . . . . . . 24 SO24 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 L9524C Block diagram 1 Block diagram Figure 1. Block diagram VS CP Supply voltage monitor GND Charge pump G1 Gate driver Thermal shutdown SP1 SN1 Failure monitor DO Diagnostic output CI Control input Channel 1 Diagnostic logic G2 Gate driver SP2 SN2 Reference oscillator Control logic Failure monitor SN5 Channel 2 BAT Channel 3 Voltage controlled oscillator G3 SP3 (same as channel 1) SN3 G4 Channel 4 Charge/discharge current MS (same as channel 2) Program Overcurrent threshold SP4 SN4 SN6 CUR OCT Mode input / relay output IO 5/27 Pins description 2 L9524C Pins description Figure 2. Pin connection (top view) SP1 1 24 SP3 G1 2 23 G3 SN1 3 22 SN3 SP2 4 21 SP4 G2 5 20 G4 SN5 6 19 SN6 SN2 7 18 SN4 BAT 8 17 CI DO 9 16 GND VS 10 15 MS CP 11 14 CUR OCT 12 13 IO SO24 Table 2. 6/27 Pins description Pins # Name Function 1 SP1 Positive sense input, glow plug 1 2 G1 Driver output for external high-side power MOSFET, transistor 1 3 SN1 Negative sense input, glow plug 1 4 SP2 Positive sense input, glow plugs 2 and 5 5 G2 Driver output for external high-side power MOSFET, transistor 2 6 SN5 Negative sense input, glow plug 5 7 SN2 Negative sense input, glow plug 2 8 BAT Battery voltage input 9 DO Diagnostic output 10 VS Supply voltage input 11 CP Charge pump output 12 OCT 13 IO 14 CUR 15 MS 16 GND Overcurrent threshold setting Transistor mode: input for selection of power regulation feature Relay mode: output to control external relay driver Power MOSFET gate charge/discharge current setting Mode selection input: transistor modes (transistor sense / shunt sense) / relay mode Ground pin 17 CI 18 SN4 Negative sense input, glow plug 4 Control input 19 SN6 Negative sense input, glow plug 6 20 G4 Driver output for external high-side power MOSFET, transistor 4 21 SP4 Positive sense input, glow plugs 4 and 6 22 SN3 Negative sense input, glow plug 3 23 G3 Driver output for external high-side power MOSFET, transistor 3 24 SP3 Positive sense input, glow plug 3 L9524C Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VVS Supply voltage range -0.3 to 45 V |dVVS/dt| Supply voltage slope 10 V/s Charge pump voltage range -0.3 to 45 V Input pin voltage range (BAT, CI, SP1-4, SN1-6) -16 to 45 V -0.3 to 7 V -16 to 45 V VCP VBAT, VCI, VSP1-4, VSN1-6 VOCT, VCUR, Input pin voltage range (OCT, CUR, MS, IO) VMS, VIO VDO, VG1-4 Output pin voltage range (DO, G1-4) Warning: The device may become damaged if using externally applied voltages or currents exceeding these limits! All the pin of the IC are protected against ESD. the verification is performed according to: AEC Q100-002 (HBM) and AEC Q100-011 (CDM). 3.2 Thermal data Table 4. Symbol TJ TJSD Thermal data Parameter Value Unit Operating junction temperature -40 to 125 C Junction temperature thermal shutdown threshold 125 to 150 C 7/27 Electrical specifications 3.3 L9524C Electrical characteristics 5V VVS;VBAT 18V, -40C TJ 125C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when current flows into the pin. Table 5. Item Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit 1 5 20 mA 1 10 mA Supply (VS) 1.1 IVS Supply current VS = 12V 1.2 VVS uv Undervoltage threshold 4 5 V 1.3 VVS uvh Undervoltage threshold hysteresis (1) 100 400 mV 1.4 VVS ol Open-load detection threshold 5.5 7.2 V 1.5 VVS ov Overvoltage threshold 18 22 V 1.6 VVS ovh Overvoltage threshold hysteresis (1) 0.4 1.6 V 1.7 VVS ld Load dump threshold 28 35 V 1.8 tVS fil Filter time (2) 1 2 ms 1.9 tVS ld Load dump delay time (1) s 10 Supply (BAT) 2.1 2.2 IBAT leak RBAT 2.3 VBAT uv 2.4 tBAT fil VVS 3V 0V VBAT 12V 0 -40C 25 43 150 30C 25 65 150 125C 25 106 150 VMS > VMS tr (transistor mode) 1 2 V 300 760 s VVS +5V VVS +18V -1500 -100 VVS +3.5V VVS +5V (1) 0.6 7 MHz Filter time (2) 400 950 s Leakage current Internal pull-down resistance Battery undervoltage threshold Filter time (2) 5 A k Charge pump (CP) 3.1 VCP Charge pump voltage ICP = -100A 3.2 ICP Charging current VCP = VVS + 5V 3.3 VCP uv 3.4 fCP 3.5 tCP fil 8/27 Charge pump undervoltage threshold Charge pump frequency A L9524C Table 5. Item Electrical specifications Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Control input (CI) 4.1 VCI off Input "off" level 4.2 VCI on Input "on" level 4.3 VCI h Off-to-on hysteresis (1) 4.4 VCI to Input "timeout" threshold 4.5 4.6 4.7 RCI tCI fil tCI to 0.4 * VVS Internal pull-up resistance Filter time 0.6 * VVS 0.03 * VVS 1 0.05 * VVS 1.6 VCI VVS; -40C 20 35 120 VCI VVS; 30C 20 53 120 VCI VVS; 125C 20 87 120 (2) PWM time-out 0.04 * VVS V k 0.5 1 ms 50 100 ms VVS 4.5V; IDO 5mA 0.3 1.5 V VDO VVS; -40C 20 30 120 VDO VVS; 30C 20 45 120 VDO VVS; 125C 20 74 120 (2) Diagnostic output (DO) 5.1 5.2 5.3 VDOL Output low voltage RDO Internal pull-up resistance IDO max Current limitation 5 20 k mA Monitoring of currents through glow plugs (SP1-SN1, SP2-SN2, SP3-SN3, SP4-SN4, SP2-SN5, SP4-SN6) 6.1 6.2 6.3 6.4 VOL VOC 0 Open-load threshold Overcurrent threshold TCOC Overcurrent threshold temperature coefficient tOL fil Open-load filter time (2) 6V VSPX;VSNX VVS + 3V 6.7 14.7 mV 1.5V VSPX;VSNX VVS + 3V VMS < VMS tc (shunt sense) OCT pin open 150 185 mV 1.5V VSPX;VSNX VVS + 3V VMS < VMS tc (shunt sense) 0V VOCT VCUR VOCT * 0.385 VOCT * 0.445 1.5V VSPX;VSNX VVS + 3V VMS>VMS tc (transistor sense) = -40C; OCT pin open 150 290 1.5V VSPX;VSNX VVS + 3V VMS>VMS tc (transistor sense) = -40C; 0V VOCT VCUR VOCT * 0.345 VOCT * 0.485 VMS < VMS tc (shunt sense) 1) mV K-1 0 VMS>VMS tc (transistor sense) OCT pin open 0.008 0.012 K-1 VMS > VMS tr (transistor mode) 1 2 ms 9/27 Electrical specifications Table 5. Item 6.5 L9524C Electrical characteristics (continued) Symbol tOC fil Parameter Overcurrent filter time Test condition (2) Min. Typ. Max. Unit 400 950 s VVS * 0.4 VVS * 0.6 1 2 Monitoring of external switches (SN1, SN2, SN3, SN4) 7.1 VSD 7.2 tSD fil Switch defect threshold Switch defect filter time (2) ms Gate driver outputs (G1, G2, G3, G4) 8.1 VG off Gate off voltage IGX 100A VSNX VSNX +0.7V 8.2 VG on Gate on voltage VSNX = VVS VVS +5V VVS +10V 8.3 VG cl Gate clamping voltage VSNX = -20V -18 -16 V 8.4 IG off Gate discharge current ICUR = -125A 270 540 A 8.5 IG on Gate charge current ICUR = -125A 270 540 A 8.6 Slope Gate charge- dischargecurrent IG/ICUR -250A ICUR -70A 2.33 4.33 8.7 RG 8.8 tG on Output resistance (1) 1 Jitter of output on time k -300 300 s 3 6 V Mode input / relay output (IO) 9.1 VIO on Output on voltage IIO -100A 9.2 RIO Output resistance IIO -1mA 100 500 W 100 A IIO Input pull-down current VIO 1V 25 9.3 VVS = 0V 50 500 A 9.4 IIO max Current limitation -25 -5 mA 9.5 VIO pr Power regulation threshold 1 2 V 9.6 tIO sup Pulse suppress time (2) 2.5 5 ms Positive sense inputs (SP1, SP2, SP3, SP4) 10.1 ISP leak 10.2 ISP 10.3 RSP1-4 Leakage current VVS 3V 0 5 A Input pull-down current VSNX = VSPX 6V 15 780 A 6V VSNX = VSPX 20V -40C 40 100 270 35C 40 150 270 125C 40 220 270 Pull-down resistor k Negative sense inputs (SN1, SN2, SN3, SN4, SN5, SN6) 11.1 10/27 ISN Input pull-down current VSNX = VSPX 6V 15 780 A L9524C Table 5. Item 11.2 Electrical specifications Electrical characteristics (continued) Symbol RSN1-6 Parameter Pull down resistor Test condition Min. Typ. Max. 6V VSNX = VSPX 20V -40C 40 100 270 35C 40 150 270 125C 40 220 270 VVS 6V VOCT = 3.5V -40 Unit k Overcurrent threshold setting (OCT) 12.1 IOCT Input pull-up current -10 A 2.65 V Power MOSFET gate charge/discharge current setting (CUR) 13.1 VCUR 13.2 ICUR max Output voltage ICUR -150A 2.35 Current limitation VCUR 2V -500 -250 A VMS = 3V -60 -15 A 1 2 V 3 4 V 2.5 5 ms 50 250 s 400 950 s -1.5 1.5% %* VRMSref -2 2 2.5 Input pin for mode selection (MS) 14.1 IMS Pull-up current 14.2 VMS tr Transistor mode threshold 14.3 VMS tc Temperature compensation threshold VVS 6V Output timing 15.1 tdel 15.2 tgap 15.3 tsup Delay time (2) Gap between channels (2) Failure suppress time (2) Power regulation 16.1 VRMS Accuracy 8V VBAT 16V 30ms TCI 33ms tCI on/TCI 20% < 70C > 70C 1. not tested, guaranteed by design 2. time constants created digitally, verified by scan path test 11/27 Functional description L9524C 4 Functional description 4.1 Operating modes The L9524C can operate in a total of 6 modes. The selection is done by short-circuiting the appropriate pins and voltages as shown in the following table: Table 6. Mode Mode Description MS pin BAT pin IO pin CI pin 1 relay mode, go/no-go diagnostic interface protocol ground ground output statical signal 2 relay mode, serial diagnostic interface protocol ground battery output PWM signal 3 transistor mode, shunt sense, no power regulation CUR pin battery CUR pin PWM signal 4 transistor mode, shunt sense, power regulation CUR pin battery ground PWM signal 5 transistor mode, transistor sense, no power regulation open battery CUR pin PWM signal 6 transistor mode, transistor sense, power regulation open battery ground PWM signal Modes 1 and 2 are for relay usage (referred to as "relay mode") and modes 3 to 6 for transistors usage (referred to as "transistor mode"). In relay mode the protocol of the diagnostic interface (DO pin) can be selected from go/nogo protocol and serial protocol (see section "Diagnostic output" for protocol description). In transistor mode the protocol of the diagnostic interface is the serial protocol. It can be distinguished between using shunts for monitoring the current through the glow plugs (referred to as "shunt sense") or using the RDS(on) of the power MOSFET's themselves (referred to as "transistor sense"). In shunt sense mode the resistance of the shunt is assumed to be constant with respect to the temperature while in transistor sense mode the RDS(on) of the power MOSFET's is assumed to vary with respect to the temperature and therefore overcurrent monitoring is adjusted appropriately. In transistor mode there are two possibilities to control the output timing. In modes 3 and 5 the timing of the PWM control input signal determines the timing of the PWM signals applied to the external power MOSFET's ("no power regulation"). In modes 4 and 6 the timing of the PWM control input signal determines the power through the glow plugs ("power regulation") and the timing of the PWM signals applied to the external power MOSFET's is adjusted depending on the battery voltage (see section "Power regulation"). 12/27 L9524C Functional description Figure 3. Shunt sense versus transistor sense shunt sense transistor sense VBAT VBAT SPx SPx shunt L9524C L9524C Gx SNx Gx SNx glow plug glow plug 015 4.2 Supply The main supply pin of the L9524C is the VS pin. The voltage applied to it (VVS) is monitored Note: to switch off all glow plugs if it is less than VVS uv for at least tVS fil ("under voltage failure"), to switch off all glow plugs if it is greater than VVS ov for at least tVS fil ("over voltage failure"), to switch on all glow plugs if it is greater than VVS ld for at least tVS ld ("active clamping during load dump"), to ignore open-load failures if it is less than VVS ol. The glow plugs are switched on again if the corresponding switch-on condition disappears, except if the glow plugs are switched on because of load dump. Then they remain switched on until VVS is less than VVS ov for at least tVS fil. In modes 2 to 6, the L9524C is additionally supplied by the BAT pin. This auxiliary supply ensures that the external power MOSFET's are switched off if no main supply voltage is available at the VS pin. The BAT pin is additionally used to sense the battery voltage VBAT for power regulation in modes 4 and 6 (see section "Power regulation") and for detecting "battery under voltage failure" (fuse between battery and module is defect) if VBAT is less than VBAT uv for at least tBAT fil in modes 2 to 6. An additional supply voltage higher than the main supply voltage is generated by an internal charge pump which charges an external storage capacitor connected to the CP pin. This capacitor mainly supplies the gates of the external n-channel power MOSFET's. The charge pump voltage VCP is monitored and the glow plugs are switched off if it is less than VCP uv for at least tCP fil ("charge pump under voltage"). Afterwards, the glow plugs remain switched off even if the charge pump voltage becomes greater than VCP uv until they are explicitly switched on again by the CI (control input) pin. 13/27 Functional description 4.3 L9524C Control input The control input (CI) pin is resistively pulled up RCI to the supply voltage VVS such that VCI=VCI off and the glow plugs are switched off by default. The L9524C is controlled by transitions of VCI from VCI off to VCI on (falling edge) and vice versa (rising edge). Voltage level changes of VCI which last shorter than tCI fil are ignored. In transistor mode (modes 3 to 6) the L9524C expects a PWM signal at the CI pin. Each falling edge starts measuring its on time tCI on (time until next rising edge, i.e. length of this low pulse) and its period TCI (time until next falling edge). The end of a pulse group is detected if no falling edge occurs for a time greater than tCI to and the glow plugs are switched off. Therefore, it is not possible to switch on the glow plugs permanently with one exception: if the low voltage level of the first falling edge is greater than VCI to the glow plugs remain switched on as long as this low pulse lasts. Figure 4. VCI Control input signal in transistor mode (modes 3 to 6) tCI to TCI ignored (shorter than tCI fil ) tCI fil VCI off tCI fil 0.6 . V VS 0.4 . V VS VCI on glow plug 1 ON tCI on tCI to t tCI to tCI fil +t del tCI fil +t del OFF t Figure 5. VCI Permanent switch on of glow plugs at first falling edge in transistor mode (modes 3 to 6) tCI to tCI to VCI off 0.6 . VVS 0.4 . VVS VCI on VCI to glow plug 1 ON tCI to tCI to t OFF t 14/27 L9524C Functional description Though in mode 2 (relay mode, serial diagnostic interface protocol) the relay should be switched permanently the L9524C also expects a PWM signal at the CI pin since the serial diagnostic interface protocol is synchronized by falling edges of the CI signal (see section "Diagnostic output"). The relay then is switched on permanently if the off time (time between rising and falling edge) of the PWM signal is less than tIO sup since the relay output suppresses pulses shorter than tIO sup (see section "Relay output"). For the same reason the relay is switched off permanently if the on time (time between falling and rising edge) of the PWM signal is less than tIO sup. In all other cases the relay is switched according to the PWM signal at the CI pin. Figure 6. VCI Control input signal in mode 2 for permanent switch on TCI tIO sup tIO sup VCI off 0.6 . V VS 0.4 . V VS VCI on relay tCI fil +tdel t ON OFF t In mode 1 (relay mode, go/no-go diagnostic interface protocol) no edges are necessary for the go/no-go protocol. Therefore the relay is switched on if VCI = VCI on and it is switched off if VCI = VCI off. 4.4 Diagnostic output The diagnostic output stage of the L9524C (DO pin) consists of a current-limited low-side switch and a pull-up resistor RDO to the VS pin. The voltage level of a logical low signal VDOL is given by the drop across the low-side switch and the voltage level of a logical high signal is equal to VVS. The L9524C is able to detect the following failures (see sections "Supply", "Current monitoring", and "Switch monitoring"): open-load (6 glow plugs), overcurrent (6 glow plugs, stored until power-down), any switch is defect (4 switches), supply voltage (VVS) is too low ("under voltage"), supply voltage (VVS) is too high ("over voltage"), junction temperature (TJ) is too high, charge pump voltage (VCP) is too low ("charge pump under voltage"), and battery voltage (VBAT) is too low ("battery under voltage"). 15/27 Functional description L9524C In order to report the occurrence of any of the above-listed failures to the diesel engine management system the L9524C provides two protocols: go/no-go protocol for mode 1 and serial protocol for modes 2 to 6. The go/no-go protocol is only able to report if any of the above-listed failures occurred. This is done according to the following table: Table 7. Note: Go / no-go protocol description VCI VDO at "no failure" VDO at "any failure" VCI off VDOL VVS VCI on VVS VDOL overcurrent failures are stored until power-down. The serial protocol is able to report different kinds of failures and to assign them to the corresponding glow plugs. Therefore, occurring failures are written into an internal 8-bit failure register: Table 8. Failure register description Bit Meaning of high state (1) failure at glow plug 1 1 Open-load or overcurrent 2 Open-load or overcurrent (1) failure at glow plug 2 3 Open-load or overcurrent (1) failure at glow plug 3 4 Open-load or overcurrent (1) failure at glow plug 4 5 Open-load or overcurrent (1) failure at glow plug 5 6 Open-load or overcurrent (1) failure at glow plug 6 7 Overcurrent failure at any glow plug (1) or battery voltage (VBAT) is too low (2) ("battery undervoltage") 8 One or more of the following failures ("module failure"): any switch is defect supply voltage (VVS) is too low ("undervoltage") supply voltage (VVS) is too high ("overvoltage") junction temperature (TJ) is too high charge pump voltage (VCP) is too low ("charge pump undervoltage") battery voltage (VBAT) is too low (2) ("battery under voltage") 1. overcurrent failures are stored until power-down 2. if battery voltage is too low ("battery under voltage") bits 7 and 8 are high Bits 1 to 6 are assigned to the glow plugs. Depending on bit 7 they show open-load (bit 7 is low) or overcurrent failures (bit 7 is high). Bit 8 shows if there is any of the listed failures ("module failure"). In case of a battery under voltage failure bits 7 and 8 are high and all other bits are low as long as there is no overcurrent failure stored. For transmitting the contents of the failure register the PWM signal applied to the CI pin is used as clock input: at any falling edge of the CI signal (see section "Control input") the DO pin shows the value of the next bit of the bit stream after tDO del. 16/27 L9524C Functional description Each transmission frame consists of a beginning delimiter (one low bit) followed by the 8 bits of the failure register beginning with bit 1. After the ending delimiter (one high bit) the diagnostic output stage is inactive and is resistively pulled up to VVS. The L9524C starts transmitting the first frame at the very first falling edge of the CI signal after power-on. Since at that time the contents of the failure register are clear the first 9 bits (beginning delimiter followed by the contents of the 8-bit failure register) which are transmitted are always low. The L9524C repeats transmission of the frame every 32 falling edges of the CI signal. Only during the time when the diagnostic output stage is inactive (i.e. between the transmission of two frames) the contents of the failure register can be written. Figure 7. Serial diagnostic interface protocol VVS ... VCI 0 1 2 3 4 5 6 7 8 9 10 11 ... 31 0 t 1 2 3 4 5 6 7 8 9 10 VCI off ... VCI on t first frame 4.5 high bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 contents of failure register ... ending delimiter diagnostic output stage inactive beginning delimiter low high bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 contents of failure register (all bits='low' at 1st frame) ending delimiter beginning delimiter VDOL low VVS bit 1 VDO t frame Current monitoring The L9524C is able to monitor the current through 6 glow plugs by measuring the voltage drop across sense resistors. Therefore, there are 4 positive sense input pins (SP1, SP2, SP3, SP4) and 6 negative sense input pins (SN1, SN2, SN3, SN4, SN5, SN6). The sense input pins must be connected to the sense resistors according to the following table: Table 9. Sense input pin connection Sense resistor of glow plug Positive sense input pin Negative sense input pin 1 SP1 SN1 2 SP2 SN2 3 SP3 SN3 4 SP4 SN4 5 SP2 SN5 6 SP4 SN6 17/27 Functional description L9524C In relay mode (modes 1 and 2) the positive sense input pins are short-circuited since the relay is the only switch. In transistor mode (modes 3 to 6) glow plug 5 is switched with transistor 2 and glow plug 6 with transistor 4. Therefore only 4 positive sense input pins are necessary. If the voltage drop across the sense resistor is less than VOL for at least tOL fil an open-load failure is detected as long as VVS > VVS ol. If it is greater than VOC (see below for definition) for at least tOC fil an overcurrent failure is detected and the corresponding switch is switched off and remains switched off until power-down. The threshold for overcurrent failures VOC can be varied by the voltage applied to the OCT pin (see section "Overcurrent threshold variation"). In modes 1 to 4 the overcurrent threshold is constant with respect to the temperature (TCOC = 0). But in modes 5 and 6 the overcurrent threshold increases linearly with the temperature to compensate the first-order temperature coefficient of the RDS(on) of the external power MOSFET's which are used as sense resistors in these modes: Equation 1 VOC = VOC 0 (1 + TCOC ( + 40C)). 4.6 Switch monitoring The L9524C monitors the voltages across the glow plugs (using the negative sense input pins SN1, SN2, SN3, and SN4) to detect if the corresponding switches work properly or not. A switch is detected as defect if it is switched on but the voltage across the corresponding glow plug(s) is less than VSD for at least tSD fil or if it is switched off but the voltage across the glow plug(s) is greater than VSD for at least tSD fil. 4.7 Thermal shutdown If the junction temperature becomes greater than TJSD all glow plugs are switched off. They are switched on again if the junction temperature falls below TJSD. 4.8 Gate drivers The L9524C contains four gate drivers (Gx pins) for external n-channel power MOSFET's in high-side configuration. Each gate driver provides a slope control by charging and discharging the gates of the external power MOSFET's with constant currents (IG on or IG off). To adjust the slopes these currents can be varied using the CUR pin (see section "Gate charge/discharge current variation"). The charging current source is supplied by an external capacitor connected to the charge pump output (CP) pin. The gate-to-source voltages are limited internally and without supply voltage (VVS) the gates and the sources of the external power MOSFET's are short-circuited. During free-wheeling of inductive loads the gates of the external power MOSFET's are clamped to VG cl. As a result, the power MOSFET's become conducting and the energy in the inductive loads is recirculated through the power MOSFET's. 18/27 L9524C 4.9 Functional description Relay output In relay mode (modes 1 and 2) the IO pin is used as output pin to control an external relay driver (e.g. a low-side switch which drives the relay). If the output stage of the IO pin is switched on it behaves like a voltage source (VIO) with output resistance RIO. If it is switched off a pull-down current source is activated (IIO). The relay output suppresses pulses shorter than tIO sup such that the relay can be permanently switched by applying appropriate PWM signals to the CI pin (see section "Control input"). In transistor mode (modes 3 to 6) the IO pin is used as input pin. Left open it is pulled down to ground and the power regulation feature (see section "Power regulation") is activated (VIO < VIO pr). To deactivate the power regulation feature the IO pin must be connected to the CUR pin (VIO = VCUR > VIO pr). 4.10 Gate charge/discharge current variation The CUR pin provides a constant current-limited output voltage VCUR. The gate charge (or discharge) current is a multiple of the current flowing out of the CUR pin and can therefore be varied by applying a resistor to the CUR pin. In order to select the mode of operation the IO pin and/or the MS pin may be connected to the CUR pin (see section "Modes"). The IO pin contains a pull-down current source and the MS pin contains a pull-up current source. These currents are compensated if the corresponding pin is connected to the CUR pin in order not to affect the gate charge/discharge current. 4.11 Overcurrent threshold variation The overcurrent threshold VOC can be varied by connecting the OCT pin to an external resistive voltage divider between CUR pin and ground. If the OCT pin is left open it is pulled up to an internal supply voltage by a current source and a default value is used for the overcurrent threshold. This default value corresponds to the condition: VOCT = VCUR/6. In order not to de tune the voltage divider the pull-up current IOCT source is deactivated when any glow plug is switched on. 19/27 Functional description 4.12 L9524C Advanced run-off control In transistor mode (modes 3 to 6) the glow plugs are switched by an advanced run-off control. The target is to minimize changes in the load current. Therefore, the PWM signals applied to the glow plugs are phase-shifted to each other. There is a 5-step start-up procedure at the beginning of a switching sequence. In step 1 the phase shift between the glow plugs is set to a fixed value tdel. Therefore, all glow plugs are switched on once in the first period of the PWM control input signal (CI) and are heated up quite simultaneously. During the start-up procedure the phase shift becomes a value equal to the on time of one glow plug. As a result, after the start-up procedure the glow plugs are switched on one after the other to get minimal changes in the load current. Figure 8. 4.13 Timing diagram of advanced run-off control Output timing In transistor mode (modes 3 to 6) there is a delay tgap between switching off one glow plug and switching on the next one to avoid overlaps. Additionally, failures occurring during the slope (i.e. in the time period tsup after switching) are suppressed in all modes. Figure 9. 20/27 Output timing L9524C 4.14 Functional description Power regulation The power through each glow plug (here expressed by VRMS which is the root-mean-square voltage across one glow plug) depends on the battery voltage VBAT and the duty cycle tG on/TG of the PWM signal applied to the external power MOSFET's: Equation 2 t G on V RMS = V BAT -----------TG In order to regulate the power through the glow plugs the L9524C measures VBAT and adjusts tG on/TG of the gate drivers (G1...4) such that VRMS = VRMS ref, where VRMS ref represents the desired power through each glow plug. The desired power VRMS ref is given by the input duty cycle tCI on/TCI which represents the desired output duty cycle at a nominal battery voltage of 12V: Equation 3 t CI on V RMS ref = 12V ------------t CI As a result, the actual output duty cycle of the gate drivers is given by: Equation 4 t G on 12V 2 t CI on ------------ = -------------- -------------V T CI TG BAT Note: The L9524C varies both the on time tG on and the period TG of the PWM output signal to vary the duty cycle tG on/TG. The accuracy of the power regulation is given by VRMS = VRMS - VRMS ref. The output jitter (electrical characteristics Item 8.8) is not taken in considuration while the average is zero over some periodes. 21/27 Application diagrams 5 L9524C Application diagrams Figure 10. Mode 1: relay mode, go/no-go diagnostic interface protocol L9524 220N KL 87 CP GND KL 31 Vbatt BAT Vs KL 30 220N G1 G2 G3 G4 10K 470P SP1 Control 47R CI Diagnosis Rs SN1 100R DO SP2 47R Rs SN2 SP3 47R Rs SN3 IO SP4 MS 47R I CUR CUR Rs SN4 Rs SN5 Rs 47R V OCT SN6 OCT Glow plug KL 31 Figure 11. Mode 2: relay mode, serial diagnostic interface protocol L9524 KL87 220N Vs BAT CP GND KL31 470P 220R Vbatt KL30 220N G1 G2 G3 G4 10K 47R CI Diagnosis 470P SP1 Control Rs SN1 100R DO SP2 47R Rs SN2 SP3 47R IO MS ICUR CUR Rs SN3 SP4 47R Rs SN4 Rs SN5 Rs 47R VOCT OCT SN6 Glow plug KL31 22/27 L9524C Application diagrams Figure 12. Mode 3: transistor mode, shunt sense, no power regulation STB100NF04 L9524 KL87 470P 220N Vs BAT GND G1 STP85NF55 STB100NF04 STP85NF55 Vbatt 100N KL30 CP KL31 220R 100R 220N G2 G3 G4 10K 470P SP1 Control CI 47R Rs SN1 100R SP2 Diagnosis 47R DO Rs SN2 100R SP3 47R Rs SN3 IO SP4 MS 47R ICUR Rs SN4 CUR Rs SN5 Rs 47R VOCT SN6 OCT Glow plug KL31 Figure 13. Mode 4: transistor mode, shunt sense, power regulation L9524 KL87 STB100NF04 470P 220N 220R BAT STB100NF04 STP85NF55 STP85NF55 Vbatt 100N KL30 Vs CP GND KL31 G1 100R 220N G2 G3 G4 10K 470P SP1 Control 47R CI Rs SN1 100R SP2 Diagnosis 47R DO 100R Rs SN2 SP3 47R IO MS ICUR CUR Rs SN3 SP4 47R Rs SN4 Rs SN5 Rs 47R VOCT OCT SN6 Glow plug KL31 23/27 Application diagrams L9524C Figure 14. Mode 5: transistor mode, transistor sense, no power regulation L9524 KL87 470P 220N G1 STP85NF55 100N Vbatt KL30 CP GND KL31 220R BAT Vs 100R 220N G2 G3 G4 10K 470P SP1 Control CI 47R SN1 100R SP2 Diagnosis 47R DO SN2 100R SP3 47R SN3 IO SP4 MS 47R ICUR SN4 CUR SN5 VOCT 47R SN6 OCT Glow plug KL31 Figure 15. Mode 6: transistor mode, transistor sense, power regulation L9524 KL87 470P 220N Vs G1 STP85NF55 100N 100R 220N G2 G3 G4 10K 470P SP1 Control CI 47R SN1 100R SP2 Diagnosis 47R DO 100R SN2 SP3 47R IO MS ICUR CUR SN3 SP4 47R SN4 SN5 VOCT OCT SN6 47R Glow plug KL31 24/27 Vbatt KL30 CP GND KL31 220R BAT L9524C 6 Package information Package information In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 16. SO24 mechanical data and package dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 15.20 15.60 0.598 0.614 E 7.40 7.60 0.291 0.299 e 1.27 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 ddd Weight: 0.60gr 0.050 H k OUTLINE AND MECHANICAL DATA 0 (min.), 8 (max.) 0.10 0.004 (1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO24 0070769 C 25/27 Revision history 7 L9524C Revision history Table 10. Document revision history Date Revision 22-Sep-2006 1 Initial release 29-Sep-2007 2 Updated the Section 3.3: Electrical characteristics. 3 Modified the Figure 5 and Figure 7. Added the sub-title Section 4.3: Control input. Modified the values of the items 1.8, 6.4 and 7.2, and the parameter definition of the item 8.6 in the Section 3.3: Electrical characteristics. 9-Jan-2008 26/27 Description of changes L9524C Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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