January 2008 Rev 3 1/27
1
L9524C
Glow plug system control IC
Features
■Quad gate driver for external N-channel Power
MOSFETs in high-side configuration:
– Gates driven by PWM output signal
– Adjustable gate charge/discharge currents
– Limited gate-to-source voltages
– Negative clamping for inductive loads
– Advanced run-off control
– Regulation of the power through the glow
plugs
■Control output for external relay driver
■Battery-voltage-compatible two-wire interface
■Supply voltage monitoring with shutdown
■Battery voltage monitoring with shutdown
■Junction temperature monitoring with
shutdown
■Monitoring of currents through the glow plugs
with shutdown at overcurrent (adjustable
threshold)
■Monitoring of external switches
■Charge pump voltage monitoring with
shutdown
■Active clamping during load dump
Description
The L9524C is a control IC for up to six glow
plugs of diesel engines. The glow plugs are
switched by up to four external PWM-controlled
N-channel Power MOSFETs or a single relay in
high-side configuration.
Supply voltage, battery voltage, junction
temperature, switches, currents through the glow
plugs, and charge pump voltage are monitored.
A two-wire interface is used to communicate with
the diesel engine management system.
SO24
Table 1. Device summary
Order code Package Packing
L9524C SO24 Tube
L9524C-TR SO24 Tape and reel
www.st.com
Contents L9524C
2/27
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Control input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Switch monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.7 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.8 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.9 Relay output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 Gate charge/discharge current variation . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.11 Overcurrent threshold variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.12 Advanced run-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.13 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14 Power regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L9524C List of tables
3/27
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Go / no-go protocol description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Failure register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Sense input pin connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
List of figures L9524C
4/27
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Shunt sense versus transistor sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. Control input signal in transistor mode (modes 3 to 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Permanent switch on of glow plugs at first falling edge in transistor mode (modes 3 to 6) 14
Figure 6. Control input signal in mode 2 for permanent switch on . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Serial diagnostic interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Timing diagram of advanced run-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Mode 1: relay mode, go/no-go diagnostic interface protocol . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Mode 2: relay mode, serial diagnostic interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Mode 3: transistor mode, shunt sense, no power regulation . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Mode 4: transistor mode, shunt sense, power regulation . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Mode 5: transistor mode, transistor sense, no power regulation . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Mode 6: transistor mode, transistor sense, power regulation . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. SO24 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
L9524C Block diagram
5/27
1 Block diagram
Figure 1. Block diagram
G1
SP1
SN1
Channel 1
Gate
driver
Failure
monitor
G2
SP2
SN2
Channel 2
Gate
driver
Failure
monitor SN5
Channel 3
(same as channel 1)
G3
SN3
SP3
Channel 4
(same as channel 2)
G4
SN6
SP4
SN4
Mode input / relay output IO
CP
Charge
pump
Supply
voltage
monitor
Diagnostic
logic
Control
logic
Program
Diagnostic
output
Control
input
DO
CI
VS
BAT
MS
CUR
OCT
GND
Charge/discharge current
Overcurrent threshold
Voltage
controlled
oscillator
Reference
oscillator
Thermal
shutdown
Pins description L9524C
6/27
2 Pins description
Figure 2. Pin connection (top view)
Table 2. Pins description
Pins # Name Function
1 SP1 Positive sense input, glow plug 1
2 G1 Driver output for external high-side power MOSFET, transistor 1
3 SN1 Negative sense input, glow plug 1
4 SP2 Positive sense input, glow plugs 2 and 5
5 G2 Driver output for external high-side power MOSFET, transistor 2
6 SN5 Negative sense input, glow plug 5
7 SN2 Negative sense input, glow plug 2
8 BAT Battery voltage input
9 DO Diagnostic output
10 VS Supply voltage input
11 CP Charge pump output
12 OCT Overcurrent threshold setting
13 IO Transistor mode: input for selection of power regulation feature
Relay mode: output to control external relay driver
14 CUR Power MOSFET gate charge/discharge current setting
15 MS
Mode selection input: transistor modes (transistor sense / shunt sense) / relay mode
16 GND Ground pin
17 CI Control input
18 SN4 Negative sense input, glow plug 4
19 SN6 Negative sense input, glow plug 6
20 G4 Driver output for external high-side power MOSFET, transistor 4
21 SP4 Positive sense input, glow plugs 4 and 6
22 SN3 Negative sense input, glow plug 3
23 G3 Driver output for external high-side power MOSFET, transistor 3
24 SP3 Positive sense input, glow plug 3
SP1
G1
SN1
SP2
G2
SN2
SN5
BAT
DO GND
CI
SN4
G4
SN6
SP4
SN3
G3
SP3
1
3
2
4
5
6
7
8
9
22
21
20
19
18
16
17
15
23
10
24
VS MS
SO24
CP CUR
11 14
1312
OCT IO
L9524C Electrical specifications
7/27
3 Electrical specifications
3.1 Absolute maximum ratings
Warning: The device may become damaged if using externally applied
voltages or currents exceeding these limits!
All the pin of the IC are protected against ESD. the verification is performed according to:
AEC Q100-002 (HBM) and AEC Q100-011 (CDM).
3.2 Thermal data
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VVS Supply voltage range -0.3 to 45 V
|dVVS/dt| Supply voltage slope 10 V/μs
VCP Charge pump voltage range -0.3 to 45 V
VBAT
, VCI,
VSP1-4,
VSN1-6
Input pin voltage range (BAT, CI, SP1-4, SN1-6) -16 to 45 V
VOCT
, VCUR,
VMS, VIO
Input pin voltage range (OCT, CUR, MS, IO) -0.3 to 7 V
VDO, VG1-4 Output pin voltage range (DO, G1-4) -16 to 45 V
Table 4. Thermal data
Symbol Parameter Value Unit
TJOperating junction temperature -40 to 125 °C
TJSD Junction temperature thermal shutdown threshold 125 to 150 °C
Electrical specifications L9524C
8/27
3.3 Electrical characteristics
5V ≤ VVS;VBAT ≤ 18V, -40°C ≤ TJ ≤ 125°C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when current flows into the pin.
Table 5. Electrical characteristics
Item Symbol Parameter Test condition Min. Typ. Max. Unit
Supply (VS)
1.1 IVS Supply current 1520mA
VS = 12V 1 10 mA
1.2 VVS uv Undervoltage threshold 4 5 V
1.3 VVS uvh
Undervoltage threshold
hysteresis (1) 100 400 mV
1.4 VVS ol
Open-load detection
threshold 5.5 7.2 V
1.5 VVS ov Overvoltage threshold 18 22 V
1.6 VVS ovh
Overvoltage threshold
hysteresis (1) 0.4 1.6 V
1.7 VVS ld Load dump threshold 28 35 V
1.8 tVS fil Filter time (2) 12ms
1.9 tVS ld Load dump delay time (1) 10 μs
Supply (BAT)
2.1 IBAT leak Leakage current VVS ≤ 3V
0V ≤ VBAT ≤ 12V 05μA
2.2 RBAT
Internal pull-down
resistance
-40°C 25 43 150
kΩ30°C 25 65 150
125°C 25 106 150
2.3 VBAT uv
Battery undervoltage
threshold VMS > VMS tr (transistor mode) 1 2 V
2.4 tBAT fil Filter time (2) 300 760 μs
Charge pump (CP)
3.1 VCP Charge pump voltage ICP = -100μAVVS
+5V
VVS
+18V
3.2 ICP Charging current VCP = VVS + 5V -1500 -100 μA
3.3 VCP uv
Charge pump
undervoltage threshold
VVS
+3.5V
VVS
+5V
3.4 fCP
Charge pump frequency
(1) 0.6 7 MHz
3.5 tCP fil Filter time (2) 400 950 μs
L9524C Electrical specifications
9/27
Control input (CI)
4.1 VCI off Input “off” level 0.6 ·
VVS
4.2 VCI on Input “on” level 0.4 ·
VVS
4.3 VCI h Off-to-on hysteresis (1) 0.03 ·
VVS
0.04 ·
VVS
0.05 ·
VVS
4.4 VCI to Input “timeout” threshold 1 1.6 V
4.5 RCI
Internal pull-up
resistance
VCI ≤ VVS; -40°C 20 35 120
kΩVCI ≤ VVS; 30°C 20 53 120
VCI ≤ VVS; 125°C 20 87 120
4.6 tCI fil Filter time (2) 0.5 1 ms
4.7 tCI to PWM time-out (2) 50 100 ms
Diagnostic output (DO)
5.1 VDOL Output low voltage VVS ≥ 4.5V; IDO ≤ 5mA 0.3 1.5 V
5.2 RDO
Internal pull-up
resistance
VDO ≤ VVS; -40°C 20 30 120
kΩVDO ≤ VVS; 30°C 20 45 120
VDO ≤ VVS; 125°C 20 74 120
5.3 IDO max Current limitation 5 20 mA
Monitoring of currents through glow plugs (SP1-SN1, SP2-SN2, SP3-SN3, SP4-SN4, SP2-SN5, SP4-SN6)
6.1 ΔVOL Open-load threshold 6V ≤ VSPX;VSNX ≤ VVS + 3V 6.7 14.7 mV
6.2 ΔVOC 0 Overcurrent threshold
1.5V ≤ VSPX;VSNX ≤ VVS + 3V
VMS < VMS tc (shunt sense)
OCT pin open
150 185 mV
1.5V ≤ VSPX;VSNX ≤ VVS + 3V
VMS < VMS tc (shunt sense)
0V ≤ VOCT ≤ VCUR
VOCT ·
0.385
VOCT ·
0.445
1.5V ≤ VSPX;VSNX ≤ VVS + 3V
VMS>VMS tc (transistor sense)
ϑ = -40°C; OCT pin open
150 290 mV
1.5V ≤ VSPX;VSNX ≤ VVS + 3V
VMS>VMS tc (transistor sense)
ϑ = -40°C; 0V ≤ VOCT ≤ VCUR
VOCT ·
0.345
VOCT ·
0.485
6.3 TCOC
Overcurrent threshold
temperature coefficient
VMS < VMS tc (shunt sense) 1) 0K
-1
VMS>VMS tc (transistor sense)
OCT pin open 0.008 0.012 K-1
6.4 tOL fil Open-load filter time (2) VMS > VMS tr (transistor mode) 1 2 ms
Table 5. Electrical characteristics (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
Electrical specifications L9524C
10/27
6.5 tOC fil Overcurrent filter time (2) 400 950 μs
Monitoring of external switches (SN1, SN2, SN3, SN4)
7.1 VSD Switch defect threshold VVS ·
0.4
VVS ·
0.6
7.2 tSD fil
Switch defect filter time
(2) 12ms
Gate driver outputs (G1, G2, G3, G4)
8.1 VG off Gate off voltage IGX ≤ 100μAV
SNX
VSNX
+0.7V
8.2 VG on Gate on voltage VSNX = VVS
VVS
+5V
VVS
+10V
8.3 VG cl Gate clamping voltage VSNX = -20V -18 -16 V
8.4 IG off Gate discharge current ICUR = -125µA 270 540 µA
8.5 IG on Gate charge current ICUR = -125µA 270 540 µA
8.6 Slope Gate charge- discharge-
current IG/ICUR
-250μA ≤ ICUR ≤ -70µA 2.33 4.33
8.7 RGOutput resistance (1) 1kΩ
8.8 ΔtG on Jitter of output on time -300 300 μs
Mode input / relay output (IO)
9.1 VIO on Output on voltage IIO ≥ -100μA36V
9.2 RIO Output resistance IIO ≥ -1mA 100 500 W
9.3 IIO Input pull-down current VIO ≥ 1V 25 100 μA
VVS = 0V 50 500 μA
9.4 IIO max Current limitation -25 -5 mA
9.5 VIO pr
Power regulation
threshold 12V
9.6 tIO sup Pulse suppress time (2) 2.5 5 ms
Positive sense inputs (SP1, SP2, SP3, SP4)
10.1 ISP leak Leakage current VVS ≤ 3V 0 5 μA
10.2 ISP Input pull-down current VSNX = VSPX ≥ 6V 15 780 μA
10.3 RSP1-4 Pull-down resistor
6V ≤ VSNX = VSPX ≤ 20V
-40°C 40 100 270
kΩ
35°C 40 150 270
125°C 40 220 270
Negative sense inputs (SN1, SN2, SN3, SN4, SN5, SN6)
11.1 ISN Input pull-down current VSNX = VSPX ≥ 6V 15 780 μA
Table 5. Electrical characteristics (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
L9524C Electrical specifications
11/27
11.2 RSN1-6 Pull down resistor
6V ≤ VSNX = VSPX ≤ 20V
-40°C 40 100 270
kΩ
35°C 40 150 270
125°C 40 220 270
Overcurrent threshold setting (OCT)
12.1 IOCT Input pull-up current VVS ≥ 6V
VOCT = 3.5V -40 -10 μA
Power MOSFET gate charge/discharge current setting (CUR)
13.1 VCUR Output voltage ICUR ≥ -150μA 2.35 2.5 2.65 V
13.2 ICUR max Current limitation VCUR ≤ 2V -500 -250 μA
Input pin for mode selection (MS)
14.1 IMS Pull-up current VMS = 3V -60 -15 μA
14.2 VMS tr
Transistor mode
threshold 12V
14.3 VMS tc
Temperature
compensation threshold VVS ≥ 6V 3 4 V
Output timing
15.1 tdel Delay time (2) 2.5 5 ms
15.2 tgap
Gap between channels
(2) 50 250 μs
15.3 tsup Failure suppress time (2) 400 950 μs
Power regulation
16.1 ΔVRMS Accuracy
8V ≤ VBAT ≤ 16V
30ms ≤ TCI ≤ 33ms
tCI on/TCI ≥ 20%
< 70°C
-1.5 1.5% % ·
V
RMSref
> 70°C -2 2
1. not tested, guaranteed by design
2. time constants created digitally, verified by scan path test
Table 5. Electrical characteristics (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
Functional description L9524C
12/27
4 Functional description
4.1 Operating modes
The L9524C can operate in a total of 6 modes. The selection is done by short-circuiting the
appropriate pins and voltages as shown in the following table:
Modes 1 and 2 are for relay usage (referred to as “relay mode”) and modes 3 to 6 for
transistors usage (referred to as “transistor mode”).
In relay mode the protocol of the diagnostic interface (DO pin) can be selected from go/no-
go protocol and serial protocol (see section “Diagnostic output” for protocol description).
In transistor mode the protocol of the diagnostic interface is the serial protocol. It can be
distinguished between using shunts for monitoring the current through the glow plugs
(referred to as “shunt sense”) or using the RDS(on) of the power MOSFET’s themselves
(referred to as “transistor sense”). In shunt sense mode the resistance of the shunt is
assumed to be constant with respect to the temperature while in transistor sense mode the
RDS(on) of the power MOSFET’s is assumed to vary with respect to the temperature and
therefore overcurrent monitoring is adjusted appropriately.
In transistor mode there are two possibilities to control the output timing. In modes 3 and 5
the timing of the PWM control input signal determines the timing of the PWM signals applied
to the external power MOSFET’s (“no power regulation”). In modes 4 and 6 the timing of the
PWM control input signal determines the power through the glow plugs (“power regulation”)
and the timing of the PWM signals applied to the external power MOSFET’s is adjusted
depending on the battery voltage (see section “Power regulation”).
Table 6. Mode
Mode Description MS pin BAT pin IO pin CI pin
1 relay mode, go/no-go diagnostic interface protocol ground ground output statical signal
2 relay mode, serial diagnostic interface protocol ground battery output PWM signal
3 transistor mode, shunt sense, no power regulation CUR pin battery CUR
pin PWM signal
4 transistor mode, shunt sense, power regulation CUR pin battery ground PWM signal
5 transistor mode, transistor sense, no power regulation open battery CUR
pin PWM signal
6 transistor mode, transistor sense, power regulation open battery ground PWM signal
L9524C Functional description
13/27
Figure 3. Shunt sense versus transistor sense
4.2 Supply
The main supply pin of the L9524C is the VS pin. The voltage applied to it (VVS) is
monitored
●to switch off all glow plugs if it is less than VVS uv for at least tVS fil (“under voltage
failure”),
●to switch off all glow plugs if it is greater than VVS ov for at least tVS fil (“over voltage
failure”),
●to switch on all glow plugs if it is greater than VVS ld for at least tVS ld (“active clamping
during load dump”),
●to ignore open-load failures if it is less than VVS ol.
Note: The glow plugs are switched on again if the corresponding switch-on condition disappears,
except if the glow plugs are switched on because of load dump. Then they remain switched
on until VVS is less than VVS ov for at least tVS fil.
In modes 2 to 6, the L9524C is additionally supplied by the BAT pin. This auxiliary supply
ensures that the external power MOSFET’s are switched off if no main supply voltage is
available at the VS pin.
The BAT pin is additionally used to sense the battery voltage VBAT for power regulation in
modes 4 and 6 (see section “Power regulation”) and for detecting “battery under voltage
failure” (fuse between battery and module is defect) if VBAT is less than VBAT uv for at least
tBAT fil in modes 2 to 6.
An additional supply voltage higher than the main supply voltage is generated by an internal
charge pump which charges an external storage capacitor connected to the CP pin. This
capacitor mainly supplies the gates of the external n-channel power MOSFET’s. The charge
pump voltage VCP is monitored and the glow plugs are switched off if it is less than VCP uv
for at least tCP fil (“charge pump under voltage”). Afterwards, the glow plugs remain switched
off even if the charge pump voltage becomes greater than VCP uv until they are explicitly
switched on again by the CI (control input) pin.
glow plug
shunt
VBAT
Gx
SPx
SNx
L9524C
glow plug
VBAT
Gx
SPx
SNx
L9524C
shunt sense transistor sense
015
Functional description L9524C
14/27
4.3 Control input
The control input (CI) pin is resistively pulled up RCI to the supply voltage VVS such that
VCI=VCI off and the glow plugs are switched off by default. The L9524C is controlled by
transitions of VCI from VCI off to VCI on (falling edge) and vice versa (rising edge). Voltage
level changes of VCI which last shorter than tCI fil are ignored.
In transistor mode (modes 3 to 6) the L9524C expects a PWM signal at the CI pin. Each
falling edge starts measuring its on time tCI on (time until next rising edge, i.e. length of this
low pulse) and its period TCI (time until next falling edge). The end of a pulse group is
detected if no falling edge occurs for a time greater than tCI to and the glow plugs are
switched off. Therefore, it is not possible to switch on the glow plugs permanently with one
exception: if the low voltage level of the first falling edge is greater than VCI to the glow plugs
remain switched on as long as this low pulse lasts.
Figure 4. Control input signal in transistor mode (modes 3 to 6)
Figure 5. Permanent switch on of glow plugs at first falling edge in transistor mode
(modes 3 to 6)
V
CI
t
V
CI off
V
CI on
0.6
.
V
VS
0.4
.
V
VS
t
glow plug
1
ON
OFF
t
CI to
t
CI to
T
CI
t
CI on
t
CI to
t
CI fil
t
CI fil
t
CI fil
+t
del
t
CI fil
+t
del
ignored
(shorter than t
CI fil
)
V
CI
t
V
CI off
V
CI on
0.6
.
V
VS
0.4
.
V
VS
t
glow plug
1
ON
OFF
t
CI to
t
CI to
V
CI to
t
CI to
t
CI to
L9524C Functional description
15/27
Though in mode 2 (relay mode, serial diagnostic interface protocol) the relay should be
switched permanently the L9524C also expects a PWM signal at the CI pin since the serial
diagnostic interface protocol is synchronized by falling edges of the CI signal (see section
“Diagnostic output”). The relay then is switched on permanently if the off time (time between
rising and falling edge) of the PWM signal is less than tIO sup since the relay output
suppresses pulses shorter than tIO sup (see section “Relay output”). For the same reason the
relay is switched off permanently if the on time (time between falling and rising edge) of the
PWM signal is less than tIO sup. In all other cases the relay is switched according to the
PWM signal at the CI pin.
Figure 6. Control input signal in mode 2 for permanent switch on
In mode 1 (relay mode, go/no-go diagnostic interface protocol) no edges are necessary for
the go/no-go protocol. Therefore the relay is switched on if VCI = VCI on and it is switched off
if VCI = VCI off.
4.4 Diagnostic output
The diagnostic output stage of the L9524C (DO pin) consists of a current-limited low-side
switch and a pull-up resistor RDO to the VS pin. The voltage level of a logical low signal VDOL
is given by the drop across the low-side switch and the voltage level of a logical high signal
is equal to VVS.
The L9524C is able to detect the following failures (see sections “Supply”, “Current
monitoring”, and “Switch monitoring”):
●open-load (6 glow plugs),
●overcurrent (6 glow plugs, stored until power-down),
●any switch is defect (4 switches),
●supply voltage (VVS) is too low (“under voltage”),
●supply voltage (VVS) is too high (“over voltage”),
●junction temperature (TJ) is too high,
●charge pump voltage (VCP) is too low (“charge pump under voltage”), and
●battery voltage (VBAT) is too low (“battery under voltage”).
V
CI
t
V
CI off
V
CI on
0.6
.
V
VS
0.4
.
V
VS
t
relay
ON
OFF
T
CI
t
IO sup
t
IO sup
t
CI fil
+t
del
Functional description L9524C
16/27
In order to report the occurrence of any of the above-listed failures to the diesel engine
management system the L9524C provides two protocols: go/no-go protocol for mode 1 and
serial protocol for modes 2 to 6.
The go/no-go protocol is only able to report if any of the above-listed failures occurred. This
is done according to the following table:
Note: overcurrent failures are stored until power-down.
The serial protocol is able to report different kinds of failures and to assign them to the
corresponding glow plugs. Therefore, occurring failures are written into an internal 8-bit
failure register:
Bits 1 to 6 are assigned to the glow plugs. Depending on bit 7 they show open-load (bit 7 is
low) or overcurrent failures (bit 7 is high). Bit 8 shows if there is any of the listed failures
(“module failure”). In case of a battery under voltage failure bits 7 and 8 are high and all
other bits are low as long as there is no overcurrent failure stored.
For transmitting the contents of the failure register the PWM signal applied to the CI pin is
used as clock input: at any falling edge of the CI signal (see section “Control input”) the DO
pin shows the value of the next bit of the bit stream after tDO del.
Table 7. Go / no-go protocol description
VCI VDO at “no failure” VDO at “any failure”
VCI off VDOL VVS
VCI on VVS VDOL
Table 8. Failure register description
Bit Meaning of high state
1 Open-load or overcurrent (1) failure at glow plug 1
1. overcurrent failures are stored until power-down
2 Open-load or overcurrent (1) failure at glow plug 2
3 Open-load or overcurrent (1) failure at glow plug 3
4 Open-load or overcurrent (1) failure at glow plug 4
5 Open-load or overcurrent (1) failure at glow plug 5
6 Open-load or overcurrent (1) failure at glow plug 6
7Overcurrent failure at any glow plug (1) or
battery voltage (VBAT) is too low (2) (“battery undervoltage”)
2. if battery voltage is too low (“battery under voltage”) bits 7 and 8 are high
8
One or more of the following failures (“module failure”):
any switch is defect
supply voltage (VVS) is too low (“undervoltage”)
supply voltage (VVS) is too high (“overvoltage”)
junction temperature (TJ) is too high
charge pump voltage (VCP) is too low (“charge pump undervoltage”)
battery voltage (VBAT) is too low (2) (“battery under voltage”)
L9524C Functional description
17/27
Each transmission frame consists of a beginning delimiter (one low bit) followed by the 8 bits
of the failure register beginning with bit 1. After the ending delimiter (one high bit) the
diagnostic output stage is inactive and is resistively pulled up to VVS.
The L9524C starts transmitting the first frame at the very first falling edge of the CI signal
after power-on. Since at that time the contents of the failure register are clear the first 9 bits
(beginning delimiter followed by the contents of the 8-bit failure register) which are
transmitted are always low. The L9524C repeats transmission of the frame every 32 falling
edges of the CI signal. Only during the time when the diagnostic output stage is inactive (i.e.
between the transmission of two frames) the contents of the failure register can be written.
Figure 7. Serial diagnostic interface protocol
4.5 Current monitoring
The L9524C is able to monitor the current through 6 glow plugs by measuring the voltage
drop across sense resistors. Therefore, there are 4 positive sense input pins (SP1, SP2,
SP3, SP4) and 6 negative sense input pins (SN1, SN2, SN3, SN4, SN5, SN6). The sense
input pins must be connected to the sense resistors according to the following table:
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
low
high
high
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
low
beginning
delimiter
ending
delimiter
contents of failure register
(all bits='low' at 1st frame) contents of failure register
diagnostic
output
stage
inactive
beginning
delimiter
ending
delimiter
first frame frame
01234567891011 31 012345678910
...
V
VS
V
CI
V
CI off
V
CI on
V
DO
V
VS
V
DOL
t
t
t
...
...
...
Table 9. Sense input pin connection
Sense resistor of glow plug Positive sense input pin Negative sense input pin
1SP1SN1
2SP2SN2
3SP3SN3
4SP4SN4
5SP2SN5
6SP4SN6
Functional description L9524C
18/27
In relay mode (modes 1 and 2) the positive sense input pins are short-circuited since the
relay is the only switch. In transistor mode (modes 3 to 6) glow plug 5 is switched with
transistor 2 and glow plug 6 with transistor 4. Therefore only 4 positive sense input pins are
necessary.
If the voltage drop across the sense resistor is less than ΔVOL for at least tOL fil an open-load
failure is detected as long as VVS > VVS ol. If it is greater than ΔVOC (see below for definition)
for at least tOC fil an overcurrent failure is detected and the corresponding switch is switched
off and remains switched off until power-down. The threshold for overcurrent failures ΔVOC
can be varied by the voltage applied to the OCT pin (see section “Overcurrent threshold
variation”).
In modes 1 to 4 the overcurrent threshold is constant with respect to the temperature
(TCOC = 0). But in modes 5 and 6 the overcurrent threshold increases linearly with the
temperature ϑ to compensate the first-order temperature coefficient of the RDS(on) of the
external power MOSFET’s which are used as sense resistors in these modes:
Equation 1
ΔVOC = ΔVOC 0 (1 + TCOC (ϑ + 40°C)).
4.6 Switch monitoring
The L9524C monitors the voltages across the glow plugs (using the negative sense input
pins SN1, SN2, SN3, and SN4) to detect if the corresponding switches work properly or not.
A switch is detected as defect if it is switched on but the voltage across the corresponding
glow plug(s) is less than VSD for at least tSD fil or if it is switched off but the voltage across
the glow plug(s) is greater than VSD for at least tSD fil.
4.7 Thermal shutdown
If the junction temperature becomes greater than TJSD all glow plugs are switched off. They
are switched on again if the junction temperature falls below TJSD.
4.8 Gate drivers
The L9524C contains four gate drivers (Gx pins) for external n-channel power MOSFET’s in
high-side configuration. Each gate driver provides a slope control by charging and
discharging the gates of the external power MOSFET’s with constant currents (IG on or IG
off). To adjust the slopes these currents can be varied using the CUR pin (see section “Gate
charge/discharge current variation”). The charging current source is supplied by an external
capacitor connected to the charge pump output (CP) pin. The gate-to-source voltages are
limited internally and without supply voltage (VVS) the gates and the sources of the external
power MOSFET’s are short-circuited.
During free-wheeling of inductive loads the gates of the external power MOSFET’s are
clamped to VG cl. As a result, the power MOSFET’s become conducting and the energy in
the inductive loads is recirculated through the power MOSFET’s.
L9524C Functional description
19/27
4.9 Relay output
In relay mode (modes 1 and 2) the IO pin is used as output pin to control an external relay
driver (e.g. a low-side switch which drives the relay). If the output stage of the IO pin is
switched on it behaves like a voltage source (VIO) with output resistance RIO. If it is switched
off a pull-down current source is activated (IIO). The relay output suppresses pulses shorter
than tIO sup such that the relay can be permanently switched by applying appropriate PWM
signals to the CI pin (see section “Control input”).
In transistor mode (modes 3 to 6) the IO pin is used as input pin. Left open it is pulled down
to ground and the power regulation feature (see section “Power regulation”) is activated
(VIO <V
IO pr). To deactivate the power regulation feature the IO pin must be connected to
the CUR pin (VIO = VCUR > VIO pr).
4.10 Gate charge/discharge current variation
The CUR pin provides a constant current-limited output voltage VCUR. The gate charge (or
discharge) current is a multiple of the current flowing out of the CUR pin and can therefore
be varied by applying a resistor to the CUR pin.
In order to select the mode of operation the IO pin and/or the MS pin may be connected to
the CUR pin (see section “Modes”). The IO pin contains a pull-down current source and the
MS pin contains a pull-up current source. These currents are compensated if the
corresponding pin is connected to the CUR pin in order not to affect the gate
charge/discharge current.
4.11 Overcurrent threshold variation
The overcurrent threshold ΔVOC can be varied by connecting the OCT pin to an external
resistive voltage divider between CUR pin and ground. If the OCT pin is left open it is pulled
up to an internal supply voltage by a current source and a default value is used for the
overcurrent threshold. This default value corresponds to the condition: VOCT = VCUR/6. In
order not to de tune the voltage divider the pull-up current IOCT source is deactivated when
any glow plug is switched on.
Functional description L9524C
20/27
4.12 Advanced run-off control
In transistor mode (modes 3 to 6) the glow plugs are switched by an advanced run-off
control. The target is to minimize changes in the load current. Therefore, the PWM signals
applied to the glow plugs are phase-shifted to each other. There is a 5-step start-up
procedure at the beginning of a switching sequence. In step 1 the phase shift between the
glow plugs is set to a fixed value tdel. Therefore, all glow plugs are switched on once in the
first period of the PWM control input signal (CI) and are heated up quite simultaneously.
During the start-up procedure the phase shift becomes a value equal to the on time of one
glow plug. As a result, after the start-up procedure the glow plugs are switched on one after
the other to get minimal changes in the load current.
Figure 8. Timing diagram of advanced run-off control
4.13 Output timing
In transistor mode (modes 3 to 6) there is a delay tgap between switching off one glow plug
and switching on the next one to avoid overlaps. Additionally, failures occurring during the
slope (i.e. in the time period tsup after switching) are suppressed in all modes.
Figure 9. Output timing
L9524C Functional description
21/27
4.14 Power regulation
The power through each glow plug (here expressed by VRMS which is the root-mean-square
voltage across one glow plug) depends on the battery voltage VBAT and the duty cycle tG
on/TG of the PWM signal applied to the external power MOSFET’s:
Equation 2
In order to regulate the power through the glow plugs the L9524C measures VBAT and
adjusts tG on/TG of the gate drivers (G1...4) such that VRMS = VRMS ref, where VRMS ref
represents the desired power through each glow plug.
The desired power VRMS ref is given by the input duty cycle tCI on/TCI which represents the
desired output duty cycle at a nominal battery voltage of 12V:
Equation 3
As a result, the actual output duty cycle of the gate drivers is given by:
Equation 4
Note: The L9524C varies both the on time tG on and the period TG of the PWM output signal to
vary the duty cycle tG on/TG.
The accuracy of the power regulation is given by
Δ
VRMS = VRMS - VRMS ref.
The output jitter (electrical characteristics Item 8.8) is not taken in considuration while the
average is zero over some periodes.
VRMS VBAT
tG on
TG
------------⋅=
VRMS ref 12V tCI on
tCI
--------------⋅=
tG on
TG
------------ 12V
VBAT
--------------
⎝⎠
⎛⎞
2tCI on
TCI
--------------
⋅=
Application diagrams L9524C
22/27
5 Application diagrams
Figure 10. Mode 1: relay mode, go/no-go diagnostic interface protocol
Figure 11. Mode 2: relay mode, serial diagnostic interface protocol
KL87
KL31
KL31
Vbatt
KL30
Vs
GND
DO
CI
G1
G2
G3
G4
BAT
SP1
SN1
SP2
SN2
SP3
SN3
SP4
SN4
SN5
SN6
MS
CUR
OCT
IO
CP
Glow plug
470P
220N
220N
10K
100R
I
CUR
V
OCT
Diagnosis
Control
L9524
Rs
Rs
Rs
Rs
Rs
Rs
47R
47R
47R
47R
47R
KL87
KL31
KL31
Vbatt
KL30
Vs
GND G1
G2
G3
G4
BAT
SP1
SN1
SP2
SN2
SP3
SN3
SP4
SN4
SN5
SN6
MS
CUR
OCT
IO
CP
Glow plug
470P
220N
220N
V
OCT
L9524
Rs
Rs
Rs
Rs
Rs
Rs
47R
47R
47R
47R
47R
I
CUR
DO
CI
10K
100R
Diagnosis
Control
470P 220R
L9524C Application diagrams
23/27
Figure 12. Mode 3: transistor mode, shunt sense, no power regulation
Figure 13. Mode 4: transistor mode, shunt sense, power regulation
KL87
KL31
KL31
Vbatt
KL30
Vs
GND
DO
CI
G1
G2
G3
G4
BAT
SP1
SN1
SP2
SN2
SP3
SN3
SP4
SN4
SN5
SN6
MS
CUR
OCT
IO
CP
Glow plug
470P
220N
100R
100N
220N
10K
100R
ICUR
VOCT
Diagnosis
Control
100R
470P 220R
L9524
Rs
Rs
Rs
Rs
Rs
Rs
47R
47R
47R
47R
47R
STP85NF55STP85NF55
STB100NF04 STB100NF04
STP85NF55
KL87
KL31
KL31
Vbatt
KL30
Vs
GND G1
G2
G3
G4
BAT
SP1
SN1
SP2
SN2
SP3
SN3
SP4
SN4
SN5
SN6
MS
CUR
OCT
IO
CP
Glow plug
470P
220N
100R
100N
220N
ICUR
VOCT
470P
L9524
Rs
Rs
Rs
Rs
Rs
Rs
47R
47R
47R
47R
47R
220R STP85NF55
STB100NF04 STB100NF04
DO
CI
10K
100R
Diagnosis
Control
100R
Application diagrams L9524C
24/27
Figure 14. Mode 5: transistor mode, transistor sense, no power regulation
Figure 15. Mode 6: transistor mode, transistor sense, power regulation
STP85NF55
KL87
KL31
KL31
Vbatt
KL30
Vs
GND G1
G2
G3
G4
BAT
SP1
SN1
SP2
SN2
SP3
SN3
SP4
SN4
SN5
SN6
MS
CUR
OCT
IO
CP
Glow plug
470P
220N
100R
100N
220N
I
CUR
V
OCT
470P
L9524
47R
47R
47R
47R
220R
DO
CI
10K
100R
Diagnosis
Control
100R
47R
STP85NF55
KL87
KL31
KL31
Vbatt
KL30
Vs
GND G1
G2
G3
G4
BAT
SP1
SN1
SP2
SN2
SP3
SN3
SP4
SN4
SN5
SN6
MS
CUR
OCT
IO
CP
Glow plug
470P
220N
100R
100N
220N
I
CUR
V
OCT
470P
L9524
47R
47R
47R
47R
220R
DO
CI
10K
100R
Diagnosis
Control
100R
Glow plug
47R
L9524C Package information
25/27
6 Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 16. SO24 mechanical data and package dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.200
C 0.23 0.32 0.009 0.013
D
(1)
15.20 15.60 0.598 0.614
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO24
0070769 C
Weight: 0.60gr
Revision history L9524C
26/27
7 Revision history
Table 10. Document revision history
Date Revision Description of changes
22-Sep-2006 1 Initial release
29-Sep-2007 2 Updated the Section 3.3: Electrical characteristics.
9-Jan-2008 3
Modified the Figure 5 and Figure 7.
Added the sub-title Section 4.3: Control input.
Modified the values of the items 1.8, 6.4 and 7.2, and the
parameter definition of the item 8.6 in the Section 3.3:
Electrical characteristics.
L9524C
27/27
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