
MINI ANALOG SERIES CMOS COMPARATOR
Rev.2.1_00 S-89210A/89220A
Seiko Instruments Inc. 7
Measurement Circuit
1. Power supply voltage rejection ratio, input offset voltage
VOUT
VDD
VIN
+
VDD / 2
-
y Power supply voltage rejection ratio (PSRR)
Input offset voltage (VIO)
The input offset voltage (VIO) is defined as VIN − V
DD/2
when VOUT is changed by changing VIN to VDD/2 level.
The power supply voltage rejection ratio (PSRR) can be
calculated by following expression, with the value of VIO
measured at each VDD.
Measurement conditions:
When VDD = 1.8 V: VDD = VDD1, VIO = VIO1
When VDD = 5.0 V: VDD = VDD2, VIO = VIO2
PSRR = 20 log V
DD1
−
V
DD2
V
IO1
−
V
IO2
Figure 6
2. Common-mode input signal rejection ratio, common-mode input voltage range
VOUT
VDD
VIN1
+
VIN2
-
y Common-mode input signal rejection ratio (CMRR)
The common-mode input signal rejection ratio (CMRR)
can be calculated by the following expression, with the
offset voltage (VIO) set as VIN1 minus VIN2 after VOUT is
changed by changing VIN1.
Measurement conditions:
When VIN2 = VCMR (max.): VIN2 = VINH, VIO = VIO1
When VIN2 = VDD/2: VIN2 = VINL, VIO = VIO2
CMRR = 20 log V
INH
−
V
INL
V
IO1
−
V
IO2
y Common-mode input voltage range (VCMR)
The common-mode input voltage range is the range
of VIN2 in which VOUT satisfies the common-mode input
signal rejection ratio specifications.
Figure 7