SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUAR Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Inputs and Open-Drain Outputs Accept
Voltages Up to 5.5 V
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), Thin Shrink Small-Outline (PW)
Packages, and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and DIPs (J)
description
These hex buffers/drivers are designed for 1.65-V
to 5.5-V VCC operation.
The outputs of the ’LVC07A devices are open
drain and can be connected to other open-drain
outputs to implement active-low wired-OR or
active-high wired-AND functions. The maximum
sink current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V
(LVTTL), or 5-V (CMOS) devices. This feature
allows the use of these devices as translators in
a mixed-system environment.
The SN54LVC07A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74LVC07A is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer/driver)
INPUT
AOUTPUT
Y
H H
L L
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
SN54LVC07A ...J OR W PACKAGE
SN74LVC07A . . . D, DGV, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
6Y
NC
5A
NC
5Y
2A
NC
2Y
NC
3A
SN54LVC07A . . . FK PACKAGE
(TOP VIEW)
1Y
1A
NC
4Y
4A 6A
3Y
GND
NC VCC
NC – No internal connection
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUAR Y 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
1
1A 3
2A
1Y
2
5
3A 9
4A
2Y
4
11
5A 13
6A
3Y
6
4Y
8
5Y
10
6Y
12
1
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DGV, J, PW , and W packages.
logic diagram, each buffer/driver (positive logic)
AY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUAR Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54LVC07A SN74LVC07A
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 1.65 5.5 1.65 5.5 V
VCC = 1.65 V to 1.95 V 0.65 ×VCC 0.65 ×VCC
VIH
High level in
p
ut voltage
VCC = 2.3 V to 2.7 V 1.7 1.7
V
V
IH
High
-
le
v
el
inp
u
t
v
oltage
VCC = 2.7 V to 3.6 V 2 2
V
VCC = 4.5 V to 5.5 V 0.7 ×VCC 0.7 ×VCC
VCC = 1.65 V to 1.95 V 0.35 ×VCC 0.35 ×VCC
VIL
Low level in
p
ut voltage
VCC = 2.3 V to 2.7 V 0.7 0.7
V
V
IL
Lo
w-
le
v
el
inp
u
t
v
oltage
VCC = 2.7 V to 3.6 V 0.8 0.8
V
VCC = 4.5 V to 5.5 V 0.3 ×VCC 0.3 ×VCC
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 5.5 0 5.5 V
VCC = 1.65 V 4 4
VCC = 2.3 V 12 12
IOL Low-level output current VCC = 2.7 V 12 12 mA
VCC = 3 V 24 24
VCC = 4.5 V 24 24
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
SN54LVC07A SN74LVC07A
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP†MAX MIN TYP†MAX
UNIT
IOL = 100 µA1.65 V to 5.5 V 0.2 0.2
IOL = 4 mA 1.65 V 0.45 0.45
VOL
IOL =12mA
2.3 V 0.7 0.7
V
V
OL
I
OL =
12
mA
2.7 V 0.4 0.4
V
IOL =24mA
3 V 0.55 0.55
I
OL =
24
mA
4.5 V
IIVI = 5.5 V or GND 3.6 V ±5±5µA
ICC VI = VCC or GND, IO = 0 3.6 V 10 10 µA
∆ICC One input at VCC – 0.6 V,
Other inputs at VCC or GND 2.7 V to 3.6 V 500 500 µA
CiVI = VCC or GND 3.3 V 5 5 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUAR Y 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 4)
SN54LVC07A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 1 3.5 1 2.8 3 1 2.9 1 2.6 ns
switching characteristics over recommended operating free-air temperature range, (unless
otherwise noted) (see Figures 1 through 4)
SN74LVC07A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 1 3.5 1 2.8 3 1 2.9 1 2.6 ns
operating characteristics, TA = 25°C
PARAMETER TEST
CONDITIONS
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
CONDITIONS
TYP TYP TYP TYP
Cpd Power dissipation capacitance
per buffer/driver f = 10 MHz 1.8 2 2.5 3.78 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUAR Y 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
tPZL (see Note F)
tPLZ (see Note G)
tPHZ/tPZH
2 × VCC
2 × VCC
2 × VCC
TEST S1
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VCC
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at 2 × VCC
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VCC – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VCC
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUAR Y 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
tPZL (see Note F)
tPLZ (see Note G)
tPHZ/tPZH
2 × VCC
2 × VCC
2 × VCC
TEST S1
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VCC
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at 2 × VCC
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VCC – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VCC
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 2. Load Circuit and Voltage Waveforms
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUAR Y 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 AND 3.3 V ± 0.3 V
1.5 V
1.5 V
1.5 V1.5 V
1.5 V1.5 V
1.5 V
1.5 V
3 V
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at 6 V
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.3 V
2.7 V
0 V
2.7 V
0 V
0 V
tw
2.7 V 2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tPZL (see Note F)
tPLZ (see Note G)
tPHZ/tPZH
6 V
6 V
6 V
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at 1.5 V.
G. tPLZ is measured at VOL + 0.3 V.
6 V
0 V
2.7 V
1.5 V
tPHL
1.5 V 1.5 V 2.7 V
0 V
3 V
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V 1.5 V
tPLH
Figure 3. Load Circuit and Voltage Waveforms
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUAR Y 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 5 V ± 0.5 V
2 × VCC
1.5 V
VCC/2
VCC/2VCC/2
1.5 V1.5 V
1.5 V
1.5 V
3.5 V
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at 7 V
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.3 V
3.2 V
0 V
3 V
0 V
0 V
tw
3 V VCC
VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tPZL (see Note F)
tPLZ (see Note G)
tPHZ/tPZH
2 × VCC
2 × VCC
7 V
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.3 V.
0 V
3 V
1.5 V
tPHL
1.5 V 1.5 V 3 V
0 V
3.5 V
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V 1.5 V
tPLH
Figure 4. Load Circuit and Voltage Waveforms
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 2000, Texas Instruments Incorporated
