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FEATURES APPLICATIONS
DESCRIPTION
LPREF
bq24740
28LDQFN
TOP VIEW
DPMDET
SRN
BAT
CELLS
SRP
SRSET
IADAPT
LPMD
ACSET
CHGEN
ACN
ACP
ACDET
PVCC
BTST
HIDRV
REGN
PH
LODRV
PGND
IADSLP
AGND
VREF
VADJ
VDAC
EXTPWR
ISYNSET
1
2
3
4
5
6
7
8 9 10 11 12 13 14
15
16
17
18
19
20
21
22232425262728
bq24740
SLUS736 – DECEMBER 2006
Host-controlled Multi-chemistry Battery Charger with Low Input Power Detect
•Notebook and Ultra-Mobile Computers•NMOS-NMOS Synchronous Buck Converterwith 300 kHz Frequency and >95% Efficiency
•Portable Data-Capture Terminals•Portable Printers•30-ns Minimum Driver Dead-time and 99.5%Maximum Effective Duty Cycle
•Medical Diagnostics Equipment•Battery Bay Chargers•High-Accuracy Voltage and CurrentRegulation
•Battery Back-up Systems–±0.5% Charge Voltage Accuracy–±3% Charge Current Accuracy
The bq24740 is a high-efficiency, synchronous–±3% Adapter Current Accuracy
battery charger with integrated compensation and–±2% Input Current Sense Amp Accuracy
system power selector logic, offering low component•Integration
count for space-constrained multi-chemistry batterycharging applications. Ratiometric charge current– Internal Loop Compensation
and voltage programming allows very high regulation– Internal Soft Start
accuracies, and can be either hardwired with•Safety
resistors or programmed by the system– Input Overvoltage Protection (OVP)
power-management microcontroller using a DAC orGPIOs.– Dynamic Power Management (DPM) withStatus Indicator
The bq24740 charges two, three, or four series Li+cells, supporting up to 10 A of charge current, and is– Reverse-Conduction Protection Input FET
available in a 28-pin, 5x5-mm thin QFN package.•Supports Two, Three, or Four Li+ Cells•5 – 24 V AC/DC-Adapter Operating Range•Analog Inputs with Ratiometric Programmingvia Resistors or DAC/GPIO Host Control– Charge Voltage (4-4.512 V/cell)– Charge Current (up to 10 A, with 10-m Ωsense resistor)– Adapter Current Limit (DPM)•Status and Monitoring Outputs– AC/DC Adapter Present withProgrammable Voltage Threshold– Low Input-Power Detect with AdjustableThreshold and Hysteresis– DPM Loop Active– Current Drawn from Input Source•Battery Discharge Current Sense with NoAdapter, or Selectable Low-Iq mode•Supports Any Battery Chemistry: Li+, NiCd,NiMH, Lead Acid, etc.•Charge Enable•10- µA Off-State Current•28-pin, 5x5-mm QFN package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
VREF
RAC
0.010 W
RSR
(1) Pull-uprailcouldbeeitherVREForothersystemrail .
(2) SRSET/ACSET couldcomefromeitherDACorresistordividers .
Q1 (ACFET)
SI4435
Q3(BATFET)
SI4435
Controlledby
HOST
N
PP
ACN
ACP
ACDET
EXTPWR
SRSET
ACSET
VREF
DAC
CELLS
CHGEN
VDAC
VADJ
DAC
ADC IADAPT
HOST
PVCC
HIDRV
N
PH
BTST
REGN
LODRV
PGND
SRP
SRN
P
PACK+
PACK-
SYSTEM
ADAPTER+
ADAPTER-
EXTPWR
AGND
bq24740
C3
0.1 Fm
100pFC5
Q4
FDS6680A
Q5
FDS6680A
L1
D1 BAT54
C14
BAT
IADSLP
ISYNSET
DPMDET
LPMD
VREF
LPREF
R91.8MW
Q2 (ACFET)
SI4435
Controlledby
HOST C2
0.1 Fm
C8
1 Fm
C6
10 Fm
C7
10 Fm
0.010 W
8.2 Hm
C11
10 Fm
C1
10 Fm
C12
10 Fm
C13
0.1 Fm
0.1 Fm
C9
0.1 Fm
C10
1 Fm
C15
0.1 Fm
R7
200kW
R8
24.9kW
R6
33kW
R4
10kW
R5
10kW
C4
1 Fm
R2
66.5k
1%
W
R3
10kW
R1
432k
1%
W
PowerPad
C18
10 F
m
C17
10 F
m
C16
10 F
m
bq24740
SLUS736 – DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
The bq24740 features Dynamic Power Management (DPM) and input power limiting. These features reducebattery charge current when the input power limit is reached to avoid overloading the AC adapter whensupplying the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enablesprecise measurement of input current from the AC adapter to monitor the overall system power. If the adaptercurrent is above the programmed low-power threshold, a signal is sent to host so that the system optimizes itspower performance according to what is available from the adapter.
TYPICAL APPLICATION
V
IN
= 20 V, V
BAT
= 3-cell Li-Ion, I
CHARGE
= 3 A, I
ADAPTER_LIMIT
= 4 A
Figure 1. Typical System Schematic, Voltage and Current Programmed by DAC
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VREF
RAC
0.010 W
RSR
(1) Pull-uprailcouldbeeitherVREForothersystemrail .
(2) SRSET/ACSET couldcomefromeitherDACorresistordividers.
Q1 (ACFET)
SI4435
Q3(BATFET)
SI4435
Controlledby
HOST
N
PP
ACN
ACP
ACDET
EXTPWR
SRSET
ACSET
VREF
CELLS
CHGEN
VDAC
VADJ
IADAPT
HOST
PVCC
HIDRV
N
PH
BTST
REGN
LODRV
PGND
SRP
SRN
P
PACK+
PACK-
SYSTEM
ADAPTER+
ADAPTER-
EXTPWR
AGND
bq24740
C3
0.1 Fm
100pFC5
Q4
FDS6680A
Q5
FDS6680A
L1
D1 BAT54
C14
BAT
IADSLP
ISYNSET
DPMDET
LPMD VREF
LPREF
R9 1.8MW
Q2 (ACFET)
SI4435
Controlledby
HOST C2
0.1 Fm
C8
1 Fm
C6
10 Fm
C7
10 Fm
0.010 W
8.2 Hm
C11
10 Fm
C1
10 Fm
C12
10 Fm
C13
0.1 Fm
0.1 Fm
C9
0.1 Fm
C10
1 Fm
C15
0.1 Fm
R7
200kW
R8
24.9kW
R6
33kW
R4
10kW
R5
10kW
C4
1 Fm
R2
66.5k
1%
W
R3
10kW
R1
432k
1%
W
PowerPad
ADC
R10
100kW
R9
42kW
R12100kW
R11
66.5kW
GPIO
C18
10 F
m
C17
10 F
m
C16
10 F
m
bq24740
SLUS736 – DECEMBER 2006
A. V
IN
= 20 V, V
BAT
= 3-cell Li-Ion, I
CHARGE
= 3 A, I
ADAPTER_LIMIT
= 4 A
Figure 2. Typical System Schematic, Voltage and Current Programmed by Resistor
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VREF
RAC
0.010 W
RSR
0.010 W
(1) Pull-uprailcouldbeeitherVREForothersystemrail .
(2) SRSET/ACSET couldcomefromeitherDACorresistordividers .
Q1 (ACFET)
SI4435
Q3(BATFET)
SI4435
Controlledby
HOST
N
PP
ACN
ACP
ACDET
EXTPWR
SRSET
ACSET
VREF
DAC
CELLS
CHGEN
VDAC
VADJ
DAC
ADC IADAPT
HOST
PVCC
HIDRV
N
PH
BTST
REGN
LODRV
PGND
SRP
SRN
P
PACK+
PACK-
SYSTEMADAPTER +
ADAPTER -
/EXTPWR
AGND
bq24740
10 Fm
C1
432 kW
1%
66.5kW
1%
R1
R2
10kWR3
1 FmC4
C2 C3
100 pFC5
1 FmC8
Q4
FDS6680A
Q5
FDS6680A
0.1 Fm
C9 L1
8.2 Hm
D1 BAT54
1 Fm
C10
C14
0.1 Fm
C13
0.1 Fm
C12
10 Fm
C7
10 Fm
BAT
IADSLP
ISYNSET
R6
33 kW
DPMDET
R4 10 kW
LPMD
VREF
LPREF
R7
200 kW
R8
24.9 kW
R9
1.8 MW
C11
10 Fm
Q2 (ACFET)
SI4435
Controlledby
HOST
10 Fm
C6
C15
0.1 Fm
0.1 Fm
R5 10 kW
C19
10 F
m
C18
10 F
m
C17
10 F
m
0.1 Fm
PowerPad
PACKAGE THERMAL DATA
bq24740
SLUS736 – DECEMBER 2006
V
IN
= 20 V, V
BAT
= 3-cell Li-Ion, I
CHARGE
= 3 A, I
ADAPTER_LIMIT
= 4 A
Figure 3. Typical System Schematic: Sensing Battery Discharge Current, When Adapter Removed. (SetIADSLP at logic high)
ORDERING INFORMATION
Part number Package Ordering Number Quantity(Tape and Reel)
bq24740RHDR 3000bq24740 28-PIN 5 x 5 mm QFN
bq24740RHDT 250
PACKAGE θ
JA
T
A
= 70 °C POWER RATING DERATING FACTOR ABOVE T
A
= 25 °C
QFN – RHD
(1) (2)
39 °C/W 2.36 W 0.028 W/ °C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This isconnected to the ground plane by a 2x3 via matrix.
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bq24740
SLUS736 – DECEMBER 2006
Table 1. TERMINAL FUNCTIONS – 28-PIN QFN
TERMINAL
DESCRIPTIONNAME NO.
CHGEN 1 Charge enable active-low logic input. LO enables charge. HI disables charge.Adapter current sense resistor, negative input. An optional 0.1- µF ceramic capacitor is placed from ACN pin to AGNDACN 2 for common-mode filtering. An optional 0.1- µF ceramic capacitor is placed from ACN to ACP to providedifferential-mode filtering.ACP 3 Adapter current sense resistor, positive input. (See comments with ACN description)Low power mode detect active-high open-drain logic output. Place a 10-k Ωpullup resistor from LPMD pin to thepullup-voltage rail. Place a positive-feedback resistor from LPMD pin to LPREF pin for programming hysteresis (seeLPMD 4
design example for calculation). The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. Theoutput is LO when IADAPT pin voltage is higher than LPREF pin voltage.Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider fromadapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. TheACDET 5
I
ADAPT
current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V. Input overvoltage, ACOV,disables charge and ACDRV when ACDET > 3.1 V. ACOV does not latchAdapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input currentregulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDACACSET 6
to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supplyto the VDAC pin.Low power voltage set input. Connect a resistor divider from VREF to LPREF and AGND to program the reference forthe LOPWR comparator. The LPREF-pin voltage is compared to the IADAPT-pin voltage and the logic output is givenLPREF 7
on the LPMD open-drain pin. Connecting a positive-feedback resistor from LPREF pin to LPMD pin programs thehysteresis.
Enable IADAPT to enter sleep mode; active-low logic input. Allows low I
q
sleep mode when adapter not detected.Logic low turns off the Input Current Sense Amplifier (IADAPT) when adapter is not detected and ACDET pin is <0.6IADSLP 8
V - allows lower battery discharge current. Logic high keeps IADAPT current-sense amplifier on when adapter is notdetected and ACDET pin is <0.6 V - this allows measuring battery discharge current.Analog ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the powerAGND 9
pad underneath the IC.3.3-V regulated voltage output. Place a 1- µF ceramic capacitor from VREF to AGND pin close to the IC. This voltageVREF 10
could be used for ratiometric programming of voltage and current regulation.Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Batteryvoltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ,VDAC 11 SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET pinsto AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the outputto VADJ, SRSET, or ACSET.Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltageregulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting theVADJ 12
output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs thedefault of 4.2 V per cell.Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmedEXTPWR 13 threshold, OR input current is greater than 1.25 A with 10-m Ωsense resistor. Connect a 10-k Ωpullup resistor fromEXTPWR pin to pullup supply rail.Synchronous mode voltage set input. Place a resistor from ISYNSET to AGND to program the charge undercurrentISYNSET 14 threshold to force non-synchronous converter operation at low output current, and to prevent negative inductorcurrent. Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle).Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place aIADAPT 15
100-pF or less ceramic decoupling capacitor from IADAPT to AGND.Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge currentSRSET 16 regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting theoutput of an external DAC to SRSET pin and connect the DAC supply to VDAC pin.Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BATBAT 17 pin to accurately sense the battery pack voltage. Place a 0.1- µF capacitor from BAT to AGND close to the IC to filterhigh-frequency noise.Charge current sense resistor, negative input. An optional 0.1- µF ceramic capacitor is placed from SRN pin to AGNDSRN 18 for common-mode filtering. An optional 0.1- µF ceramic capacitor is placed from SRN to SRP to providedifferential-mode filtering.SRP 19 Charge current sense resistor, positive input. (See comments for SRN.)CELLS 20 2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.
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ABSOLUTE MAXIMUM RATINGS
bq24740
SLUS736 – DECEMBER 2006
Table 1. TERMINAL FUNCTIONS – 28-PIN QFN (continued)
TERMINAL
DESCRIPTIONNAME NO.
Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates inputDPMDET 21 current is being limited by reducing the charge current. Connect 10-k Ωpullup resistor from DPMDET to VREF or adifferent pullup-supply rail.Power ground. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of inputPGND 22
and output capacitors of the charger. Only connect to AGND through the power pad underneath the IC.LODRV 23 PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.PWM low side driver positive 6-V supply output. Connect a 1- µF ceramic capacitor from REGN to PGND, close to theREGN 24
IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power MOSFETPH 25 drain, high-side power MOSFET source, and output inductor). Connect the 0.1- µF bootstrap capacitor from from PH toBTST.HIDRV 26 PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.PWM high side driver positive supply. Connect a 0.1- µF bootstrap ceramic capacitor from BTST to PH. Connect aBTST 27
small bootstrap Schottky diode from REGN to BTST.IC power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFETPVCC 28 and source of reverse-blocking power P-channel MOSFET. Place a 1- µF ceramic capacitor from PVCC to PGND pinclose to the IC.
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE UNIT
PVCC, ACP, ACN, SRP, SRN, BAT –0.3 to 30PH –1 to 30REGN, LODRV, VADJ, ACSET, SRSET, ACDET, ISYNSET, LPMD, –0.3 to 7LPREF, CHGEN, CELLS, EXTPWR, DPMDETVoltage range
VVDAC –0.3 to 5.5VREF –0.3 to 3.6BTST, HIDRV with respect to AGND and PGND, IADAPT –0.3 to 36Maximum difference voltage ACP–ACN, SRP–SRN, AGND–PGND –0.5 to 0.5Junction temperature range –40 to 155
°CStorage temperature range –55 to 155
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult PackagingSection of the data book for thermal limitations and considerations of packages.
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RECOMMENDED OPERATING CONDITIONS
PACKAGE THERMAL DATA
ELECTRICAL CHARACTERISTICS
bq24740
SLUS736 – DECEMBER 2006
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PH –1 24PVCC, ACP, ACN, SRP, SRN, BAT 0 24REGN, LODRV 0 6.5VREF 0 3.3VDAC, IADAPT 0 3.6Voltage range
VACSET, SRSET, ACDET, ISYNSET, LPMD, LPREF, CHGEN, CELLS, 0 5.5EXTPWR, DPMDETVADJ 0 6.5BTST, HIDRV with respect to AGND and PGND 0 30AGND, PGND –0.3 0.3Maximum difference voltage: ACP–ACN, SRP–SRN 5.5Junction temperature range –40 125
°CStorage temperature range –55 150
PACKAGE θ
JA
T
A
= 70 °C POWER RATING DERATING FACTOR ABOVE T
A
= 25 °C
QFN– RHD
(1)
39 °C/W 2.36W 0.028 W/ °C
(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This isconnected to the ground plane by a 2x3 via matrix.
7.0 V ≤V
PVCC
≤24 V, 0 °C < T
J
< +125 °C, typical values are at T
A
= 25 °C, with respect to AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CONDITIONS
V
PVCC_OP
PVCC Input voltage operating range 5.0 24.0 V
CHARGE VOLTAGE REGULATION
V
BAT_REG_RNG
BAT voltage regulation range 4V-4.512V per cell, times 2,3,4 cell 8 18 VV
VDAC_OP
VDAC reference voltage range 2.6 3.6 VV
ADJ_OP
VADJ voltage range 0 REGN VCharge voltage regulation accuracy 8 V, 8.4 V, 9.024 V –0.5 0.512 V, 12.6 V, 13.536 V –0.5 0.5 %16 V, 16.8 V, 18.048 V –0.5 0.5Charge voltage regulation set to default to VADJ connected to REGN, 8.4 V, –0.5 0.5
%4.2 V per cell 12.6 V, 16.8 V
CHARGE CURRENT REGULATION
V
IREG_CHG
Charge current regulation differential V
IREG_CHG
= V
SRP
– V
SRN
0 100
mVvoltage rangeV
SRSET_OP
SRSET voltage range 0 VDAC VV
IREG_CHG
= 40–100 mV –3 3V
IREG_CHG
= 20 mV –5 5Charge current regulation accuracy %V
IREG_CHG
= 5 mV –25 25V
IREG_CHG
= 1.5 mV –33 33
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bq24740
SLUS736 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)7.0 V ≤V
PVCC
≤24 V, 0 °C < T
J
< +125 °C, typical values are at T
A
= 25 °C, with respect to AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENT REGULATION
V
IREG_DPM
Adapter current regulation differential V
IREG_DPM
= V
ACP
– V
ACN
0 200 mVvoltage rangeV
ACSET_OP
ACSET voltage range 0 2 VV
IREG_DPM
= 40–100 mV –3 3V
IREG_DPM
= 20 mV –5 5Input current regulation accuracy %V
IREG_DPM
= 5 mV –25 25V
IREG_DPM
= 1.5 mV –33 33
VREF REGULATOR
V
VREF_REG
VREF regulator voltage V
ACDET
> 0.6 V, 0-30 mA 3.267 3.3 3.333 VI
VREF_LIM
VREF current limit V
VREF
= 0 V, V
ACDET
> 0.6 V 35 75 mA
REGN REGULATOR
V
REGN_REG
REGN regulator voltage V
ACDET
> 0.6 V, 0-75 mA, PVCC > 10 5.6 5.9 6.2 VVI
REGN_LIM
REGN current limit V
REGN
= 0 V, V
ACDET
> 0.6 V 90 135 mA
ADAPTER CURRENT SENSE AMPLIFIER
V
ACP/N_OP
Input common mode range Voltage on ACP/SRN 0 24 VV
IADAPT
IADAPT output voltage range 0 2 VI
IADAPT
IADAPT output current 0 1 mAA
IADAPT
Current sense amplifier voltage gain A
IADAPT
= V
IADAPT
/ V
IREG_DPM
20 V/VV
IREG_DPM
= 40–100 mV –2 2V
IREG_DPM
= 20 mV –3 3Adapter current sense accuracy %V
IREG_DPM
= 5 mV –25 25V
IREG_DPM
= 1.5 mV –30 30I
IADAPT_LIM
Output current limit V
IADAPT
= 0 V 1 mAC
IADAPT_MAX
Maximum output load capacitance For stability with 0 mA to 1 mA load 100 pF
ACDET COMPARATOR
V
PVCC-BAT_OP
Differential Voltage from PVCC to BAT –20 24 VV
ACDET_CHG
ACDET adapter-detect rising threshold Min voltage to enable charging, 2.376 2.40 2.424 VV
ACDET
risingV
ACDET_CHG_HYS
ACDET falling hysteresis V
ACDET
falling 40 mVACDET rising deglitch
(1)
VACDET rising 518 700 908 msACDET falling deglitch VACDET falling 10 µsV
ACDET_BIAS
ACDET enable-bias rising threshold Min voltage to enable all bias, V
ACDET
0.56 0.62 0.68 VrisingV
ACDET_BIAS_HYS
Adapter present falling hysteresis V
ACDET
falling 20 mVACDET rising deglitch
(1)
V
ACDET
rising 10
µsACDET falling deglitch V
ACDET
falling 10
INPUT OVERVOLTAGE COMPARATOR (ACOV)
V
ACOV
AC Over-voltage rising threshold on 3.007 3.1 3.193 VACDET
(See ACDET in erminal Functions )V
ACOV_HYS
AC Over-voltage rising deglitch 1.3
msAC Over-voltage falling deglitch 1.3
(1) Verified by design.
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bq24740
SLUS736 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)7.0 V ≤V
PVCC
≤24 V, 0 °C < T
J
< +125 °C, typical values are at T
A
= 25 °C, with respect to AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC CURRENT DETECT COMPARATOR (INPUT UNDER_CURRENT)
V
ACIDET
Adapter current detect rising threshold V
ACI
= I
AC
×R
AC
×20, falling edge 200 250 300 mVV
ACIDET_HYS
Adapter current detect hysteresis Rising edge 50 mV
PVCC / BAT COMPARATOR (REVERSE DISCHARGING PROTECTION)
V
PVCC-BAT_FALL
PVCC to BAT falling threshold V
PVCC
– V
BAT
to turn off ACFET 140 185 240 mVV
PVCC-BAT__HYS
PVCC to BAT hysteresis 50 mVPVCC to BAT Rising Deglitch V
PVCC
– V
BAT
> V
PVCC-BAT_RISE
10
µsPVCC to BAT Falling Deglitch V
PVCC
– V
BAT
< V
PVCC-BAT_FALL
6
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)
V
UVLO
AC Under-voltage rising threshold Measure on PVCC 3.5 4 4.5 VV
UVLO_HYS
AC Under-voltage hysteresis, falling 260 mV
BAT OVER-VOLTAGE COMPARATOR
V
OV_RISE
Over-voltage rising threshold
(2)
104As percentage of V
BAT_REG
%V
OV_FALL
Over-voltage falling threshold
(2)
102
CHARGE OVER-CURRENT COMPARATOR
V
OC
Charge over-current falling threshold As percentage of I
REG_CHG
145 %Minimum Current Limit (SRP-SRN) 50 mV
INPUT CURRENT LOW-POWER MODE COMPARATOR
V
ACLP_HYS
AC low power hysteresis 2.8
mVV
ACLP_OFFSET
AC low power rising threshold 1
THERMAL SHUTDOWN COMPARATOR
T
SHUT
Thermal shutdown rising temperature Temperature Increasing 155
°CT
SHUT_HYS
Thermal shutdown hysteresis, falling 20
PWM HIGH SIDE DRIVER (HIDRV)
R
DS_HI_ON
High side driver turn-on resistance V
BTST
– V
PH
= 5.5 V, tested at 100 mA 3 6
ΩR
DS_HI_OFF
High side driver turn-off resistance V
BTST
– V
PH
= 5.5 V, tested at 100 mA 0.7 1.4V
BTST_REFRESH
Bootstrap refresh comparator threshold V
BTST
– V
PH
when low side refresh 4 Vvoltage pulse is requested
PWM LOW SIDE DRIVER (LODRV)
R
DS_LO_ON
Low side driver turn-on resistance REGN = 6 V, tested at 100 mA 3 6
ΩR
DS_LO_OFF
Low side driver turn-off resistance REGN = 6 V, tested at 100 mA 0.6 1.2
PWM DRIVERS TIMING
Driver Dead Time — Dead time when 30 nsswitching between LODRV and HIDRV.No load at LODRV and HIDRV
PWM OSCILLATOR
F
SW
PWM switching frequency 240 360 kHzV
RAMP_HEIGHT
PWM ramp height As percentage of PVCC 6.6 %PVCC
(2) Verified by design.
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bq24740
SLUS736 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)7.0 V ≤V
PVCC
≤24 V, 0 °C < T
J
< +125 °C, typical values are at T
A
= 25 °C, with respect to AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENT
I
OFF_STATE
Total off-state battery current from SRP, V
BAT
= 16.8 V, V
ACDET
< 0.6 V, 7 10SRN, BAT, VCC, BTST, PH, etc. V
PVCC
> 5 V, T
J
= 85 °C
µAV
BAT
= 16.8 V, V
ACDET
< 0.6 V, 7 11V
PVCC
> 5 V, T
J
= 125 °CI
BAT_ON
Battery on-state quiescent current V
BAT
= 16.8V, 0.6V < V
ACDET
< 2.4V, 1 mAV
PVCC
> 5VI
BAT_LOAD_CD
Internal battery load current, charge Charge is disabled: 3 5 mAdisbled V
BAT
= 16.8 V, V
ACDET
> 2.4 V,V
PVCC
> 5 VI
BAT_LOAD_CE
Internal battery load current, charge Charge is enabled: 6 10 12 mAenabled V
BAT
= 16.8 V, V
ACDET
> 2.4 V,V
PVCC
> 5 VI
AC
Adapter quiescent current V
PVCC
= 20 V, charge disabled 2.8 4 mAI
AC_SWITCH
Adapter switching quiescent current V
PVCC
= 20 V, Charge enabled, 25 mAconverter running, total gate charge =2×10 nC
INTERNAL SOFT START (8 steps to regulation current)
Soft start steps 8 stepSoft start step time 1.7 ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up Delay from when adapter is detected 518 700 908 msto when the charger is allowed to turnon
ISYNSET AMPLIFIER AND COMPARATOR (SYNCHRONOUS TO NON-SYSNCHRONOUS TRANSITION)
Accuracy 5 mV –20 20 %A
ISYNSET
Gain ISYNSET amplifier gain 250 V/IISYNSET pin voltage 1 VV
ISYNSET
ISYNSET rising deglitch 20 µsISYNSET falling deglitch 640 µs
LOGIC IO PIN CHARACTERISTICS ( CHGEN, IADSLP )
V
IN_LO
Input low threshold voltage 0.8 VV
IN_HI
Input high threshold voltage 2.1V
BIAS
Input bias current V
CHGEN
= 0 to V
REGN
1µA
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
V
IN_LO
Input low threshold voltage, 3 cells CELLS voltage falling edge 0.5V
IN_MID
Input mid threshold voltage, 2 cells CELLS voltage rising for MIN, 0.8 1.8
VCELLS voltage falling for MAXV
IN_HI
Input high threshold voltage, 4 cells CELLS voltage rising 2.5I
BIAS_FLOAT
Input bias float current for 2-cell selection V –1 1 µA= 0 to V
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( EXTPWR)
V
OUT_LO
Output low saturation voltage Sink Current = 4 mA 0.5 VDelay, EXTPWR falling 518 700 908 msDelay, EXTPWR rising 10 µs
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( DPMDET, LPMD)
V
OUT_LO
Output low saturation voltage Sink Current = 5 mA 0.5 VDelay, rising/falling 10 ms
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TYPICAL CHARACTERISTICS
-0.20
-0.10
0
0.10
0.20
0.30
0.40
0.50
0 10 20 30 40 50
VREF-LoadCurrent-mA
RegulationError-%
PVCC=10V
PVCC=20V
-3
-2.50
-2
-1.50
-1
-0.50
0
0 10 20 30 40 50 60 70 80
REGN-LoadCurrent-mA
RegulationError-%
PVCC=10V
PVCC=20V
bq24740
SLUS736 – DECEMBER 2006
Table of Graphs
(1)
Y X FIgure
VREF Load and Line Regulation vs Load Current Figure 4REGN Load and Line Regulation vs Load Current Figure 5BAT Voltage vs VADJ/VDAC Ratio Figure 6Charge Current vs SRSET/VDAC Ratio Figure 7Input Current vs ACSET/VDAC Ratio Figure 8BAT Voltage Regulation Accuracy vs Charge Current Figure 9BAT Voltage Regulation Accuracy Figure 10Charge Current Regulation Accuracy Figure 11Input Current Regulation (DPM) Accuracy Figure 12V
IADAPT
Input Current Sense Amplifier Accuracy Figure 13Input Regulation Current (DPM), and Charge Current vs System Current Figure 14Transient System Load (DPM) Response Figure 15Charge Current Regulation vs BAT Voltage Figure 16Efficiency vs Battery Charge Current Figure 17Battery Removal (from Constant Current Mode) Figure 18REF and REGN Startup Figure 19Charger on Adapter Removal Figure 20Charge Enable / Disable and Current Soft-Start Figure 21Nonsynchronous to Synchronous Transition Figure 22Synchronous to Nonsynchronous Transition Figure 23Near 100% Duty Cycle Bootstrap Recharge Pulse Figure 24Battery Shorted Charger Response, Over Current Protection (OCP) and Charge Current Regulation Figure 25Continuous Conduction Mode (CCM) Switching Waveforms Figure 26Discontinuous Conduction Mode (DCM) Switching Waveforms Figure 27
(1) Test results based on Figure 2 application schematic. V
IN
= 20 V, V
BAT
= 3-cell LiIon, I
CHG
= 3 A, I
ADAPTER_LIMIT
= 4 A, T
A
= 25 °C, unlessotherwise specified.
VREF LOAD AND LINE REGULATION REGN LOAD AND LINE REGULATIONvs vsLoad Current LOAD CURRENT
Figure 4. Figure 5.
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0
1
2
3
4
5
6
7
8
9
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
SRSET/VDACRatio
ChargeCurrentRegulation- A
SRSET Varied,
4-Cell,
Vbat=16V
16
16.2
16.4
16.6
16.8
17
17.2
17.4
17.6
17.8
18
18.2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VADJ/VDACRatio
VoltageRegulation-V
VADJ=0-VDAC,
4-Cell,
NoLoad
0
1
2
3
4
6
7
8
9
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
ACSET/VDACRatio
InputCurrentRegulation- A
ACSET Varied,
4-Cell,
Vbat=16V
5
SRSET Varied
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
0 2 4 6 8
I Setpoint- A
(CHRG) -
RegulationError-%
4-Cell,VBAT =16V
VADJ=0-VDAC
-0.10
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
16.5 17 17.5 18 18.5 19
V -Setpoint-V
(BAT)
RegulationError-%
4-Cell,noload
bq24740
SLUS736 – DECEMBER 2006
BAT VOLTAGE CHARGE CURRENTvs vsVADJ/VDAC RATIO SRSET/VDAC RATIO
Figure 6. Figure 7.
INPUT CURRENT BAT VOLTAGE REGULATION ACCURACYvs vsACSET/VDAC RATIO CHARGE CURRENT
Figure 8. Figure 9.
BAT VOLTAGE REGULATION ACCURACY CHARGE CURRENT REGULATION ACCURACY
Figure 10. Figure 11.
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ACSET Varied
-2
-1
0
1
2
3
4
5
6
7
8
9
10
0 1 2 3 4 5 6
InputCurrentRegulationSetpoint- A
RegulationError-%
4-Cell,VBAT =16V
Iadapt AmplifierGain
-25
-20
-15
-10
-5
0
5
0 1 2 3 4 5 6 7 8 9 10
I - A
(ACPWR)
PercentError
V =20V,CHG=EN
I
V =20V,CHG=DIS
I
V =20V,
4-Cell,
V =16V
I
bat
0
1
2
3
4
5
0 1 2 3 4
SystemCurrent- A
IchrgandIin- A
InputCurrent
ChargeCurrent
0
1
2
3
4
5
0 2 4 6 8 10 12 14 16 18
BatteryVoltage-V
ChargeCurrent- A
Ichrg_set=4 A
70
80
90
100
02000 4000 6000 8000
BatteryChargeCurrent-mA
Efficiency-%
V =12.6V
reg
V =16.8V
(BAT)
V =8.4V
reg
bq24740
SLUS736 – DECEMBER 2006
INPUT CURRENT REGULATION (DPM) ACCURACY V
IADAPT
INPUT CURRENT SENSE AMPLIFIER ACCURACY
Figure 12. Figure 13.
INPUT REGULATION CURRENT (DPM), AND CHARGECURRENT
vsSYSTEM CURRENT TRANSIENT SYSTEM LOAD (DPM) RESPONSE
Figure 14. Figure 15.
CHARGE CURRENT REGULATION EFFICIENCYvs vsBAT VOLTAGE BATTERY CHARGE CURRENT
Figure 16. Figure 17.
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bq24740
SLUS736 – DECEMBER 2006
BATTERY REMOVAL REF AND REGN STARTUP
Figure 18. Figure 19.
CHARGE ENABLE / DISABLE AND CURRENTCHARGER ON ADAPTER REMOVAL SOFT-START
Figure 20. Figure 21.
NONSYNCHRONOUS TO SYNCHRONOUS TRANSITION SYNCHRONOUS TO NONSYNCHRONOUS TRANSITION
Figure 22. Figure 23.
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bq24740
SLUS736 – DECEMBER 2006
BATTERY SHORTED CHARGER RESPONSE,NEAR 100% DUTY CYCLE BOOTSTRAP RECHARGE OVERCURRENT PROTECTION (OCP) AND CHARGEPULSE CURRENT REGULATION
Figure 24. Figure 25.
CONTINUOUS CONDUCTION MODE (CCM) SWITCHING DISCONTINUOUS CONDUCTION MODE (DCM)WAVEFORMS SWITCHING WAVEFORMS
Figure 26. Figure 27.
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bq24740
IADAPT
BTST
HIDRV
PH
REGN
LODRV
PGND
ACP
ACN
BAT
SRP
6VLDO
V(ACP-ACN)
+
-
V(SRP-SRN)
COMP
ERROR
AMPLIFIER
V(IADAPT)
+
-20x
ACP
ACN
ENA_BIAS
20 Am
IIN_ER
BAT_ER
ICH_ER
1V
20 Am
IIN_REG
VBAT_REG
IBAT_REG
SRN
10mA
DC-DC
CONVERTER
PWMLOGIC
PVCC
PH
4V +
_
BTST REFRESH
CBTST
CHGEN
155°C
ICTj TSHUT
LEVEL
SHIFTER
+
-
+
-
+
-
+
+
-
+
-
+
-
BAT_SHORT
ACOP
SYNCH
V(SRP-SRN) CHG_OCP
145%XIBAT_REG
SRSET
VADJ
VDAC
ACSET
VBAT_REG
IBAT_REG
IIN_REG
VBATSET
IBATSET
IINSET
RATIO
PROGRAM
20X
BAT BAT_OVP
+
–
104%XVBAT_REG
CHRG_ON
ACDET ACOV
+
-
3.1V
VREF 3.3V
LDO PVCC
DPMDET
DPM_LOOP_ON
EXTPWR
UVLO
+
PVCC
+
-
4V
LPREF
+
V(IADAPT)
LPMD
AGND
PVCC
CHGEN
ACDET
ACIGOOD
+
-
V(IADAPT)
SYNCH
+
-
V(SRP -SRN)
BAT BAT_SHORT
+
-
2.9V/Cell
+
ISYNSET
+
-
250mV
FBO
EAI EAO
0.6V
+
-
ENA_BIAS
ENA_BIAS_CMP
ACVGOOD
2.4V
+
-
IADSLP /IADSLP
Delay
Rising
700ms
–
+
–
+
–
–
–
–
–
CELLS 2,3,4
bq24740
SLUS736 – DECEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
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TYPICAL APPLICATIONS
DETAILED DESCRIPTION
BATTERY VOLTAGE REGULATION
VBATT +cell count ƪ4V )ǒ0.5 VVADJ
VVDACǓƫ
(1)
BATTERY CURRENT REGULATION
ICHARGE +VSRSET
VVDAC
0.10
RSR
(2)
INPUT ADAPTER CURRENT REGULATION
bq24740
SLUS736 – DECEMBER 2006
The bq24740 uses a high-accuracy voltage regulator for charging voltage. Internal default battery voltage settingV
BATT
=4.2 V ×cell count. The regulation voltage is ratio-metric with respect to VADC. The ratio of VADJ andVDAC provides extra 12.5% adjust range on V
BATT
regulation voltage. By limiting the adjust range to 12.5% ofthe regulation voltage, the external resistor mismatch error is reduced from ±1% to ±0.1%. Therefore, an overallvoltage accuracy as good as 0.5% is maintained, while using 1% mis-match resistors. Ratio-metric conversionalso allows compatibility with D/As or microcontrollers ( µC). The battery voltage is programmed through VADJand VDAC using Equation 1 .
The input voltage range of VDAC is between 2.6 V and 3.6 V. VADJ is set between 0 and VDAC. V
BATT
defaultsto 4.2 V ×cell count when VADJ is connected to REGN.
CELLS pin is the logic input for selecting cell count. Connect CELLS to charge 2,3, or 4 Li+ cells. Whencharging other cell chemistries, use CELLS to select an output voltage range for the charger.CELLS CELL COUNT
Float 2AGND 3VREF 4
The per-cell battery termination voltage is function of the battery chemistry. Consult the battery manufacturer todetermine this voltage.
The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to thebattery as possible, or directly on the output capacitor. A 0.1- µF ceramic capacitor from BAT to AGND isrecommended to be as close to the BAT pin as possible to decouple high frequency noise.
The SRSET input sets the maximum charging current. Battery current is sensed by resistor R
SR
connectedbetween SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 0.010Ωsense resistor, the maximum charging current is 10 A. SRSET is ratio-metric with respect to VDAC usingEquation 2 :
The input voltage range of SRSET is between 0 and V
DAC
, up to 3.6 V.
The SRP and SRN pins are used to sense across R
SR
with default value of 10 m Ω. However, resistors of othervalues can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulationaccuracy; but, at the expense of higher conduction loss.
The total input from an AC adapter or other DC sources is a function of the system supply current and thebattery charging current. System current normally fluctuates as portions of the systems are powered up or down.Without Dynamic Power Management (DPM), the source must be able to supply the maximum system currentand the maximum charger input current simultaneously. By using DPM, the input current regulator reduces thecharging current when the input current exceeds the input current limit set by ACSET. The current capability ofthe AC adapter can be lowered, reducing system cost.
Similar to setting battery regulation current, adapter current is sensed by resistor R
AC
connected between ACPand ACN. Its maximum value is set ACSET, which is ratio-metric with respect to VDAC, using Equation 3 .
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IADAPTER +VACSET
VVDAC
0.10
RAC
(3)
ADAPTER DETECT AND POWER UP
ENABLE AND DISABLE CHARGING
AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
bq24740
SLUS736 – DECEMBER 2006
The input voltage range of ACSET is between 0 and V
DAC
, up to 3.6 V.
The ACP and ACN pins are used to sense R
AC
with default value of 10m Ω. However, resistors of other valuescan also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulationaccuracy; but, at the expense of higher conduction loss.
An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detectthreshold should typically be programmed to a value greater than the maximum battery voltage and lower thanthe minimum allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sensethe true adapter input voltage whether the ACFET is on or off. Before adapter is detected, BATFET stays on andACFET turns off.
If PVCC is below 5 V, the device is disabled, and both ACFET and BATFET turn off.
If ACDET is below 0.6 V but PVCC is above 5 V, part of the bias is enabled, including a crude bandgapreference, ACFET drive and BATFET drive. IADAPT is disabled and pulled down to GND. The total quiescentcurrent is less than 10 µA.
Once ACDET rises above 0.6 V and PVCC is above 5 V, all the bias circuits are enabled and REGN outputgoes to 6 V and VREF goes to 3.3 V. IADAPT becomes valid to proportionally reflect the adapter current.
When ACDET keeps rising and passes 2.4 V, a valid AC adapter is present. 500ms later, the following occurs:•ACGOOD becomes high through external pull-up resistor to the host digital voltage rail;•Charger turns on if all the conditions are satisfied and STAT becomes valid. (refer to Enable and DisableCharging)
The following conditions have to be valid before charge is enabled:•CHGEN is LOW;•Adapter is detected;•Adapter is higher than PVCC-BAT threshold;•Adapter is not over voltage;•500ms delay is complete after adapter detected;•REGNGOOD and VREFGOOD are valid;•Thermal Shut (TSHUT) is not valid;
One of the following conditions will stop on-going charging:•CHGEN is HIGH;•Adapter is removed;•Adapter is less than 250mV above battery;•Adapter is over voltage;•Adapter is over current;•TSHUT IC temperature threshold is reached (145 °C on rising-edge with 15 °C hysteresis).
The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensurethere is no overshoot or stress on the output capacitors or the power converter. The soft-start consists ofstepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.Each step lasts around 1ms, for a typical rise time of 8 ms. No external components are needed for this function.
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CONVERTER OPERATION
Where resonant frequency, f
o
, is given by:
fo+1
2pLoCo
Ǹ
where (from Figure 1 schematic)
SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION
bq24740
SLUS736 – DECEMBER 2006
The synchronous buck PWM converter uses a fixed frequency (300 kHz) voltage mode with feed-forward controlscheme. A type III compensation network allows using ceramic capacitors at the output of the converter. Thecompensation input stage is connected internally between the feedback output (FBO) and the error amplifierinput (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and erroramplifier output (EAO). The LC output filter is selected to give a resonant frequency of 8–12.5 kHz nominal.
•C
O
= C11 + C12•L
O
= L1
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of theconverter. The ramp height is one-fifteenth of the input adapter voltage making it always directly proportional tothe input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, andsimplifies the loop compensation. The ramp is offset by 250 mV in order to allow zero percent duty-cycle, whenthe EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in orderto get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle whileensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pinvoltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off andthe low-side n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor.Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall lowagain due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued.
The 300 kHz fixed frequency oscillator keeps tight control of the switching frequency under all conditions of inputvoltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out ofthe audible noise region. The charge current sense resistor R
SR
should be placed with at least half or more ofthe total output capacitance placed before the sense resistor contacting both sense resistor and the outputinductor; and the other half or remaining capacitance placed after the sense resistor. The output capacitanceshould be divided and placed onto both sides of the charge current sense resistor. A ratio of 50:50 percent givesthe best performance; but the node in which the output inductor and sense resistor connect should have aminimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switchingnoise and give better current sense accuracy. The type III compensation provides phase boost near thecross-over frequency, giving sufficient phase margin.
The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET value.Otherwise, the charger operates in synchronous mode.
During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel powerMOSFET is off. The internal gate drive logic ensures there is break-before-make switching to preventshoot-through currents. During the 30ns dead time where both FETs are off, the back-diode of the low-sidepower MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipationlow, and allows safely charging at high currents. During synchronous mode the inductor current is alwaysflowing and operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system.
During non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after thebreak-before-make dead-time, the low-side n-channel power MOSFET will turn-on for around 80ns, then thelow-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-sidepower MOSFET is turned on again. The 80ns low-side MOSFET on-time is required to ensure the bootstrapcapacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This isimportant for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains avoltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection betweenhigh and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value.After the 80 ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring. Theinductor current is blocked by the off low-side MOSFET, and the inductor current will become discontinuous.This mode is called Discontinuous Conduction Mode (DCM).
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ISYNSET CONTROL (CHARGE UNDER-CURRENT)
IRIPPLE_MAX
2vISYN vIRIPPLE_MAX
and IRIPPLE_MAX +
ǒVIN_MAX *VBAT_MINǓ ǒVBAT_MIN
VIN_MAX Ǔ ǒ1
fsǓ
LMIN
(4)
HIGH ACCURACY IADAPT USING CURRENT SENSE AMPLIFIER (CSA)
INPUT OVER VOLTAGE PROTECTION (ACOV)
bq24740
SLUS736 – DECEMBER 2006
During the DCM mode the loop response automatically changes and has a single pole system at which the poleis proportional to the load current, because the converter does not sink current, and only the load provides acurrent sink. This means at very low currents the loop response is slower, as there is less sinking currentavailable to discharge the output voltage. At very low currents during non-synchronous operation, there may bea small amount of negative inductor current during the 80 ns recharge pulse. The charge should be low enoughto be absorbed by the input capacitance.
Whenever the converter goes into 0% duty-cycle mode, and BTST – PH < 4 V, the 80-ns recharge pulse occurson LODRV, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (no 80-nsrecharge pulse), and there is no discharge from the battery.
In bq24740, ISYN is internally set as the charge current threshold at which the charger changes fromnon-synchronous operation into synchronous operation. The low side driver turns on for only 80 ns to charge theboost cap. This is important to prevent negative inductor current, which may cause a boost effect in which theinput voltage increases as power is transferred from the battery to the input capacitors. This can lead to anover-voltage on the PVCC node and potentially cause some damage to the system. This programmable valueallows setting the current threshold for any inductor current ripple, and avoiding negative inductor current. Theminimum synchronous threshold should be set from ½ the inductor current ripple to the full ripple current, wherethe inductor current ripple is given by
where
V
IN_MAX
: maximum adapter voltageV
BAT_MIN
: minimum BAT voltagef
S
: switching frequencyL
MIN
: minimum output inductor
The ISYNSET comparator, or charge under-current comparator, compares the voltage between SRP-BAT andinternal threshold on the cycle-to-cycle base. The threshold is set to 13 mV on the falling edge with 8 mVhysteresis on the rising edge with 10% variation.
An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by thehost or some discrete logic through the analog voltage output of the IADAPT pin. The CSA amplifies the inputsensed voltage of ACP – ACN by 20x through the IADAPT pin. The IADAPT output is a voltage source 20 timesthe input differential voltage. Once PVCC is above 5 V and ACDET is above 0.6V, IADAPT no longer stays atground, but becomes active. If the user wants to lower the voltage, they could use a resistor divider from IOUTto AGND, and still achieve accuracy over temperature as the resistors can be matched their thermal coefficients.
A 200-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additionalRC filter is optional, after the 200-pF capacitor, if additional filtering is desired. Note that adding filtering alsoadds additional response delay.
ACOV provides protection to prevent system damage due to high input voltage. The controller enters ACOVwhen ACDET > 3.1 V. Charge is disabled, the adapter is disconnected from the system by turning off ACDRV,and the battery is connected to the system by turning on BATDRV. ACOV is not latched—normal operationresumes when the ACDET voltage returns below 3.1 V. ACOV threshold is 130% of the adapter-detectthreshold.
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INPUT UNDER VOLTAGE LOCK OUT (UVLO)
INPUT CURRENT LOW-POWER MODE DETECTION
20kW
1kW
Adaptor
CurrentSense
Amplifier
IADAPT Error
Amplifier
Disable
+
-
ACDET
Comparator
ACDET_DET
2.4V
t_dg
rising
700ms
ACDET_DG
ACDET +
-
LOPWRMODE
Comparator
LOPWR_DET+
-
IADAPT
LPREF
LPMD
+
-
ACP
ACN
EXT_PWR_DG EXTPWR
LOIAC
Comparator
LOIAC_DET
+
-
250mV
TO ACDET
Logic
ProgramHysteresisofcomparator
byputtingaresistorinfeedback
fromLPMDpinto LPREFpin.
IADAPT
Disable
BATTERY OVER-VOLTAGE PROTECTION
CHARGE OVER-CURRENT PROTECTION
bq24740
SLUS736 – DECEMBER 2006
The system must have a minimum 5V PVCC voltage to allow proper operation. This PVCC voltage could comefrom either input adapter or battery, using a diode-OR input. When the PVCC voltage is below 5 V the biascircuits REGN and VREF stay inactive, even with ACDET above 0.6 V.
In order to optimize the system performance, the HOST keeps an eye on the adapter current. Once the adaptercurrent is above threshold set via LPREF, LPMD pin sends signal to HOST. The signal alarms the host thatinput power has exceeded the programmed limit, allowing the host to throttle back system power by reducingclock frequency, lowering rail voltages, or disabling certain parts of the system. The LPMD pin is an open-drainoutput. Connect a pull-up resistor to LPMD. The output is logic HI when the IADAPT output voltage (IADAPT =20 x V
ACP-ACN
) is lower than the LPREF input voltage. The LPREF threshold is set by an external resistor dividerusing VREF. A hysteresis can be programmed by a positive feedback resistor from LPMD pin to the LPREF pin.
Figure 28. EXTPWR, LPREF and LPMD Logic
The converter stops switching when BAT voltage goes above 104% of the regulation voltage. The converter willnot allow the high-side FET to turn on until the BAT voltage goes below 102% of the regulation voltage. Thisallows one-cycle response to an overvoltage condition, such as when the load is removed or the battery isdisconnected. A 10-mA current sink from BAT to PGND is on only during charge, and allows discharging thestored output-inductor energy into the output capacitors.
The charger has a secondary over-current protection. It monitors the charge current, and prevents the currentfrom exceeding 145% of regulated charge current. The high-side gate drive turns off when the over-current isdetected, and automatically resumes when the current falls below the over-current threshold.
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THERMAL SHUTDOWN PROTECTION
Status Outputs ( EXTPWR, LPMD, DPMDET pin)
bq24740
SLUS736 – DECEMBER 2006
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to theambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off andself-protects whenever the junction temperature exceeds the TSHUT threshold of 145 °C. The charger stays offuntil the junction temperature falls below 130 °C.
Four status outputs are available, and they all, except for LPMD, require external pull up resistors to pull the pinsto system digital rail for a high level.
EXTPWR open-drain output goes low under either of the two conditions:1. ACDET is above 2.4 V2. Adapter current is above 1.25 A using a 10-m Ωsense resistor (IADAPT voltage above 250 mV). Internally,the AC current detect comparator looks between IADAPT and an internal 250-mV threshold. It indicates agood adapter is connected because of valid voltage or current.
STAT open-drain output goes low when charging. A high level on STAT indicates the charger is not charging;therefore, either, CHGEN pin is not low, or the charger is not able to charge because input voltage is stillpowering up and the 700-ms delay has not finished, or because of a fault condition such as overcurrent, inputover voltage, or TSHUT over temperature.
LPMD push-pull output goes low when the input current is higher than the programmed threshold via LPREFpin. Hysteresis can be programmed by putting a resistor from LPREF pin to LPMD pin.
DPMDET open-drain output goes low when the DPM loop is active to reduce the battery charge current (after a10-ms delay).
Table 2. Component List for Typical System Circuit of Figure 1
PART DESIGNATOR QTY DESCRIPTION
Q1, Q2, Q3 3 P-channel MOSFET, –30V,-6A, SO-8, Vishay-Siliconix, Si4435Q4, Q2 2 N-channel MOSFET, 30V, 12.5A, SO-8, Fairchild, FDS6680AD1 1 Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54CR
AC
, R
SR
2 Sense Resistor, 10 m Ω, 1%, 1W, 2010, Vishay-Dale, WSL2010R0100FL1 1 Inductor, 10 µH, 7A, 31m Ω, Vishay-Dale, IHLP5050FD-01C1, C6, C7, C11, C12 5 Capacitor, Ceramic, 10 µF, 35V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E106MC4, C8, C10 3 Capacitor, Ceramic, 1 µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105KC2, C3, C9, C13, C14, C15 6 Capacitor, Ceramic, 0.1 µF, 50V, 10%, X7R, 0805, Kemet, C0805C104K5RACTUR3, R4, R5 4 Resistor, Chip, 10 k Ω, 1/16W, 5%, 0402R1 1 Resistor, Chip, 432 k Ω, 1/16W, 1%, 0402R2 1 Resistor, Chip, 66.5 k Ω, 1/16W, 1%, 0402R6 1 Resistor, Chip, 33 k Ω, 1/16W, 1%, 0402R7 1 Resistor, Chip, 200 k Ω, 1/16W, 1%, 0402R8 1 Resistor, Chip, 24.9 k Ω, 1/16W, 1%, 0402R9 1 Resistor, Chip, 1.8 M Ω, 1/16W, 1%, 0402
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APPLICATION INFORMATION
Input Capacitance Calculation
C1 C8
Ri Li Ci
Vi Vc
Ii
C1 C8
Ri Li Ci
Vi
Ii
÷
÷
ø
ö
ç
ç
è
æw×w-w-
w××
+
w××
w×
+=
-
tcostsin
L2
R
e
CZ
V
CZ
V
)0(V)t(V
i
i
t
L2
R
2
0i0
i
2
0i0
i
CC i
i
(5)
where
i
i
0C
L
Z=
,
2
i
i
ii L2
R
CL
1
÷
÷
ø
ö
ç
ç
è
æ
-=w
, and
ii
0CL
1
=w
bq24740
SLUS736 – DECEMBER 2006
During the adapter hot plug-in, the ACDRV has not been enabled. The AC switch is off and the simplifiedequivalent circuit of the input is shown in Figure 29 .
A. Ri and Li are the equivalent input inductance and resistance. C1 and C8 are the input capacitance.
Figure 29. Simplified Equivalent Circuit During Adapter Insertion
The voltage on the input capacitor(s) is given by:
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0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
5
10
15
20
25
30
35
Ci=20 Fm
Ci=40 Fm
Ri=0.21 ,
Li=9.3 H
W
m
(a)VcwithvariousCivalues
InputCapacitorVoltage-V
Time-ms
Li=12 Fm
Ri=0.15 ,
Ci=40 F
W
m
(b)VcwithvariousLivalues
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
5
10
15
20
25
30
35
InputCapacitorVoltage-V
Li=5 Fm
Time-ms
Ri=0.50 W
Li=9.3 H,
Ci=40 F
m
m
(c)VcwithvariousRivalues
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
5
10
15
20
25
30
35
InputCapacitorVoltage-V
Ri=0.15 W
Time-ms
bq24740
SLUS736 – DECEMBER 2006
APPLICATION INFORMATION (continued)For a typical notebook charger application, the total stray inductance of the adapter output wire and the PCBconnections is normally 5–12 µH, and the total effective resistance of the input connections is 0.15–0.5 Ω.Figure 30 (a) demonstrates that a higher Ci helps to damp the voltage spike. Figure 30 (b) demonstrates theeffect of the input stray inductance Li on the input voltage spike. The dashed curve in Figure 30 (b) representsthe worst case for Ci=40 µF. Figure 30 (c) shows how the resistance helps to suppress the input voltage spike.
Figure 30. Parametric Study Of The Input Voltage
Minimizing the input stray inductance, increasing the input capacitance and using high-ESR input capacitorshelps to suppress the input voltage spike.
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Ci=20 FmCi=40 Fm
(c ) Ci = 49 ( 4 7 el e ct r ol y ti c an d 2x ceramic)m m mF F F
bq24740
SLUS736 – DECEMBER 2006
APPLICATION INFORMATION (continued)Figure 31 shows the measured input voltages and currents with different input capacitances. The voltage spikedrops by about 5 V after increasing Ci from 20 µF to 40 µF. The input voltage spike has been dramaticallydamped by using a 47 F electrolytic capacitor.
Figure 31. Adapter DC Side Hot Plug-In With Various Input Capacitances
Since the input voltage to the IC is PVCC which is 0.7 V (diode voltage drop) lower than Vc during the adapterinsertion, a 40- µF input capacitance is normally adequate to keep the PVCC voltage well below the maximumvoltage rating under normal conditions. In case of a higher input stray inductance, the input capacitance may beincreased accordingly. An electrolytic capacitor will help reduce the input voltage spike due to its high ESR.
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PCB Layout Design Guideline
(a)TopLayer
(b)BottomLayer
bq24740
SLUS736 – DECEMBER 2006
APPLICATION INFORMATION (continued)
1. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on theother layers.2. The control stage and the power stage should be routed separately. At each layer, the signal ground and thepower ground are connected only at the power pad.3. The AC current-sense resistor must be connected to ACP (pin 3) and ACN (pin 2) with a Kelvin contact. Thearea of this loop must be minimized. The decoupling capacitors for these pins should be placed as close tothe IC as possible.4. The charge-current sense resistor must be connected to SRP (pin 19), SRN (pin 18) with a Kelvin contact.The area of this loop must be minimized. The decoupling capacitors for these pins should be placed as closeto the IC as possible.5. Decoupling capacitors for PVCC (pin 28), VREF (pin 10), REGN (pin 24) should be placed underneath the IC(on the bottom layer) with the interconnections to the IC as short as possible.6. Decoupling capacitors for BAT (pin 17), IADAPT (pin 15) must be placed close to the corresponding IC pinswith the interconnections to the IC as short as possible.7. Decoupling capacitor CX for the charger input must be placed very close to the Q4 drain and Q5 source.
Figure 32 shows the recommended component placement with trace and via locations.
Figure 32. Layout Example
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TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2007
Pack Materials-Page 1
Device Package Pins Site Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ24740RHDR RHD 28 MLA 330 12 5.3 5.3 1.5 8 12 PKGORN
T2TR-MS
P
BQ24740RHDT RHD 28 MLA 180 12 5.3 5.3 1.5 8 12 PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
BQ24740RHDR RHD 28 MLA 346.0 346.0 29.0
BQ24740RHDT RHD 28 MLA 190.0 212.7 31.75
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2007
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2007
Pack Materials-Page 3
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