Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Synchronous Buck PWM Controller
•Single 12V Power Supply Required
•Fast Transient Response
- 0~90% Duty Ratio
•0.8V Reference with 1% Accuracy
•Shutdown Function by Controlling COMP Pin Volt-
age
•Internal Soft-Start (3.4ms) Function
•Voltage Mode PWM Control Design
•Under-Voltage Protection
•Over-Current Protection
- Sense Low Side MOSFET’s RDS(ON)
•300kHz Fixed Switching Frequency
•SOP-8 Package
•Lead Free and Green Devices Available
(RoHS Compliant)
Features
Applications
General Description
The APW7065 uses fixed 300kHz switching frequency,
voltage mode, and synchronous PWM controller which
drives dual N-channel MOSFETs. The device integrates
the control, monitoring and protection functions into a
single package, provides one controlled power output
with under-voltage and over-current protections.
The APW7065 provides excellent regulation for output load
variation. The internal 0.8V temperature-compensated
reference voltage is designed to meet the requirement of
low output voltage applications. An built-in digital soft-
start with fixed soft-start interval prevents the output volt-
age from overshoot as well as limiting the input current.
The APW7065 with excellent protection functions: POR,
OCP and UVP. The Power-On-Reset (POR) circuit can
monitor VCC supply voltage exceeds its threshold volt-
age while the controller is running, and a built-in digital
soft-start provides output with controlled voltage rise. The
Over-Current Protection (OCP) monitors the output cur-
rent by using the voltage drop across the lower MOSFET’s
RDS(ON), comparing with internal VOCP (0.29V), when the
output current reaches the trip point, the controller will
run the soft-start function until the fault events are
removed. The Under-Voltage Protection (UVP) monitors
the voltage of FB pin for short-circuit protection, when the
VFB is less than 50% of VREF (0.4V), the controller will shut-
down the IC directly.
Pin Configuration
•Graphics Card
•Mother Board
Simplified Application Circuit
VOUT
12V VIN
L
APW7065
1
2
3
4
8
7
6
5
PHASE
COMP
FB
VCC
BOOT
UGATE
GND
LGATE
SOP-8
(Top View)
APW7065
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw2
Symbol Parameter Rating Unit
VCC VCC to GND -0.3 ~ 16 V
BOOT BOOT to PHASE -0.3 ~ 16 V
UGATE UGATE to PHASE <400ns Pulse Width
>400ns Pulse Width -5 ~ BOOT+5
-0.3 ~ BOOT+0.3 V
LGATE LGATE to GND <400ns Pulse Width
>400ns Pulse Width -5 ~ VCC+5
-0.3 ~ VCC+0.3 V
PHASE PHASE to GND <200ns Pulse Width
>200ns Pulse Width -10 ~ 30
-0.3 ~ 16 V
COMP, FB COMP, FB to GND -0.3 ~ 7 V
TJ Junction Temperature Range -20 ~ 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Absolute Maximum Ratings (Note 1)
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Thermal Resistance in Free Air (Note 2) SOP-8
75 oC/W
θJC Junction-to-Case Thermal Resistance SOP-8
28 oC/W
Ordering and Marking Information
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
APW7065
Handling Code
Temperature Range
Package Code
APW7065 K : APW7065
XXXXX XXXXX - Date Code
Assembly Material
Package Code
K : SOP-8
Operating Ambient Temperature Range
E : -20 to 70 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw3
Symbol
Parameter Range Unit
VCC VCC Supply Voltage 10.8 ~ 13.2 V
VOUT Converter Output Voltage 0.8 ~ 5 V
VIN Converter Input Voltage 2.9 ~ 13.2 V
IOUT Converter Output Current 0 ~ 20 A
TA Ambient Temperature Range -20 ~ 70 oC
TJ Junction Temperature Range -20 ~ 125 oC
Recommended Operating Conditions
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC=12V, and TA =-20~70oC. Typlcal values are at TA=25oC.
APW7065
Symbol
Parameter Test Conditions Min. Typ. Max.
Unit
SUPPLY CURRENT
IVCC VCC Nominal Supply Current UGATE and LGATE Open - 5 10 mA
VCC Shutdown Supply Current UGATE, LGATE = GND - 1 2 mA
POWER-ON-RESET
Rising VCC Threshold 9 9.5 10 V
Falling VCC Threshold 7.5 8 8.5 V
COMP Shutdown Threshold - 1.2 - V
COMP Shutdown Hysteresis - 0.1 - V
OSCILLATOR
FOSC Free Running Frequency 255 300 345 kHz
∆VOSC Ramp Amplitude - 1.6 - VP-P
REFERENCE VOLTAGE
VREF Reference Voltage Measured at FB Pin - 0.8 - V
Accuracy TA =-20~70°C -1.0 - +1.0 %
ERROR AMPLIFIER
Gain Open Loop Gain RL=10k, CL=10pF (Note 3) - 88 - dB
GBWP Open Loop Bandwidth RL=10k, CL=10pF (Note 3) - 15 - MHz
SR Slew Rate RL=10k, CL=10pF (Note 3) - 6 - V/µs
FB Input Current VFB = 0.8V (Note 3) - 0.1 1 µA
VCOMP COMP High Voltage - 5.5 - V
VCOMP COMP Low Voltage - 0 - V
ICOMP COMP Source Current VCOMP=2V - 5 - mA
ICOMP COMP Sink Current VCOMP=2V - 5 - mA
GATE DRIVERS
IUGATE Upper Gate Source Current BOOT = 12V, VUGATE -VPHASE = 2V
- 2.6 - A
IUGATE Upper Gate Sink Current BOOT = 12V, VUGATE -VPHASE = 2V
- 1.05 - A
ILGATE Lower Gate Source Current VCC = 12V, VLGATE = 2V - 4.9 - A
ILGATE Lower Gate Sink Current VCC = 12V, VLGATE = 2V - 1.4 - A
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw4
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC=12V, and TA =-20~70oC. Typlcal values are at TA=25oC.
APW7065
Symbol
Parameter Test Conditions Min. Typ. Max.
Unit
GATE DRIVERS (CONT.)
RUGATE Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A - 2 3 Ω
RUGATE Upper Gate Sink Impedance BOOT = 12V, IUGATE = 0.1A - 1.6 2.4 Ω
RLGATE Lower Gate Source Impedance VCC = 12V, ILGATE = 0.1A - 1.3 1.95 Ω
RLGATE Lower Gate Sink Impedance VCC = 12V, ILGATE = 0.1A - 1.25 1.88 Ω
TD Dead Time - 20 - ns
PROTECTIONS
VOCP Over-Current Reference Voltage TA =-20~70°C 0.27 0.29 0.31 V
VUVP Under-Voltage Threshold Trip Point Percent of VREF 45 50 55 %
SOFT-START
TSS Soft-Start Interval 2 3.4 5 ms
Note 3: Guaranteed by design.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw5
Typical Operating Characteristics
Power OnPower Off
CH1
CH2
CH3
CH1
CH2
CH3
CH4 CH4
CH1: VCC (5V/div)
CH2: VFB (1V/div)
CH3: Vo (1V/div)
CH4: Ug (20/Vdiv)
Time: 10ms/div
CH1: VCC (5V/div)
CH2: VFB (1V/div)
CH3: Vo (1V/div)
CH4: Ug (20/Vdiv)
Time: 10ms/div
ENShutdown
CH1
CH2
CH3
CH1
CH2
CH3
CH4
CH4
CH1: VCOMP (2V/div)
CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg (10Vdiv)
Time: 5ms/div
CH1: VCOMP (2V/div)
CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg (10Vdiv)
Time: 20us/div
VCC=12V, VIN=12V
VO=1.2V, L=1µH
VCC=12V, VIN=12V
VO=1.2V, L=1µH
VCC=12V, VIN=12V
VO=1.2V, L=1µH
VCC=12V, VIN=12V
VO=1.2V, L=1µH
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw6
UGATE Rising UGATE Falling
CH1
CH2
CH3
CH1
CH2
CH3
CH1: Ug (20V/div)
CH2: Lg (5V/div)
CH3: Phase (10V/div)
Time: 50ns/div
CH1: Ug (20V/div)
CH2: Lg (5V/div)
CH3: Phase (10V/div)
Time: 50ns/div
Typical Operating Characteristics (Cont.)
0
Load Transient Response Under Voltage Protection
CH1
CH2
CH1
CH2
CH3
CH4
CH1: IL (10A/div)
CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg (10V/div)
Time: 100us/div
CH1: Vo (500mV/div,AC)
CH2:Io (5A/div)
Time: 1ms/div
0A
10A
VCC=12V, VIN=12V
VO=1.2V, L=1µH
VCC=12V, VIN=12V
VO=1.2V, L=4.7µH
VCC=12V, VIN=12V
VO=1.2V, L=1µH
IOUT=5A
VCC=12V, VIN=12V
VO=1.2V, L=1µH
IOUT=5A
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw7
Over Current Protection Short Test
CH1
CH2
CH3
CH1
CH2
CH3
CH4
CH1: IL (10A/div)
CH2: Vo (2V/div)
CH3: Ug (20V/div)
CH4: Lg (10V/div)
Time: 2ms/div
CH4
CH1: IL (10A/div)
CH2: Vo (2V/div)
CH3: Ug (20V/div)
CH4: Lg (10V/div)
Time: 5ms/div
Typical Operating Characteristics (Cont.)
0.792
0.794
0.796
0.798
0.8
0.802
0.804
-40 -20 020 40 60 80 100 120
275
280
285
290
295
300
305
310
-40 -20 0 20 40 60 80 100 120
Switching Frequency vs. Junction TemperatureReference Voltage vs. Junction Temperature
Junction Temperature (°C )
Switching Frequency(kHz)
Junction Temperature (°C )
Reference Voltage(V)
VCC=12V VCC=12V
VCC=12V, VIN=12V, VO=1.2V, L=1µH
L_side: APM2023, RDS(ON)=17mΩ
VCC=12V, VIN=12V
VO=1.2V, L=1µH
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw8
0
0.5
1
1.5
2
2.5
3
3.5
0 2 4 6 8 10 12
0
0.5
1
1.5
2
2.5
3
0246810 12
UGATE Source Current vs. UGATE VoltageUGATE Sink Current vs. UGATE Voltage
UGATE Voltage (V)
UGATE Source Current (A)
UGATE Voltage (V)
UGATE Sink Current (A)
VBOOT=12V
VBOOT=12V
Typical Operating Characteristics (Cont.)
0
0.5
1
1.5
2
2.5
3
3.5
0 2 4 6 8 10 12
0
1
2
3
4
5
6
0 2 4 6 8 10 12
LGATE Source Current vs. LGATE VoltageLGATE Sink Current vs. LGATE Voltage
LGATE Voltage (V)
LGATE Source Current (A)
LGATE Sink Current (A)
LGATE Voltage (V)
VCC=12V
VCC=12V
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw9
Pin Description
PIN
NO. NAME FUNCTION
1 BOOT A bootstrap circuit with a diode connected to VCC is used to
create a voltage suitable to drive a
logic-level N-channel MOSFET.
2 UGATE Connect this pin to the high-side N-channel MOSFET gate. This pin provides gate drive f
or the
high-side MOSFET.
3 GND The GND terminal provides return path for the IC bias current and the low-
side MOSFET driver
pull-low current. Connect the pin to the system ground via very low impedance layout on PCBs.
4 LGATE Connect this pin to the low-side N-
low-side MOSFET.
5 VCC
Connect this pin to a 12V supply voltage. This pin provides bias supply for the control circuitry and
the low-side MOSFET driver. The voltage at this pin is monitored for the Power-
On Reset (POR)
purpose. It is recommended that a decoupling capacitor (1 to 10µ
F) be connected to GND for
noise decoupling.
6 FB
This pin is the inverting input of the internal error amplifier. Connect this pin to the output (VOUT
) of
the converter via an external resistor divider for closed-loop operation. The output voltage set b
y
the resistor divider is determined using the following formula :
+×= R2
R1
10.8VOUT
where R1 is the resistor connected from VOUT
to FB , and R2 is the resistor connected from FB to
GND. The FB pin is also monitored for under voltage events.
7 COMP
This pin is the output of PWM error amplifier. It is used to set the compensation components. In
addition, if the pin is pulled below 1.2V, it will disable the device.
8 PHASE This pin is the return path for the upper gate driver. Connect this pin to the
upper MOSFET source.
This pin is also used to monitor the voltage drop across the MOSFET for over-current protection.
Typical Application Circuit
VOUT
470µFx2
VCC BOOT
UGATE
PHASE
LGATE
GND
FB
12V VIN
COMP
0.1µFAPM2509
APM2506
1µF1µF
1µH
470µF
1µH
470µFx2
2K
1K
18R 68nF
8.2nF 33nF
2.7K
1
2
3
4
5
6
78
2.2R
1N4148
2N7002
(12V)
(1.2V)
ON/OFF
Q1
Q2
Q3
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw10
Block Diagram
Gate
Control
Oscillator
Digital
Soft Start
Power-
On-Reset
PHASE
LGATE
FB
GNDVCC
BOOT
UGATE
50%VREF
Error Amp PWM
Comparator
U.V.P
Comparator
Sawtooth
Wave
:2
COMP
0.29V
O.C.P
Comparator
VREF
FOSC
300kHz
Sense Low Side
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw11
Function Description
Figure 2. shows more detail of the FB voltage ramp. The
FB voltage soft-start ramp is formed with many small
steps of voltage. The voltage of one step is about 12.5mV
in FB, and the period of one step is about 16/FOSC. This
method provides a controlled voltage rise and prevents
the large peak current to charge output capacitor.
Power-On-Reset (POR)
The Power-On-Reset (POR) function of APW7065 con-
tinually monitors the input supply voltage (VCC) and the
COMP pin. The supply voltage (VCC) must exceed its
rising POR threshold voltage. The POR function initiates
soft-start operation after VCC and COMP voltages exceed
their POR thresholds. For operation with a single +12V
power source, VIN and VCC are equivalent and the +12V
power source must exceed the rising VCC threshold. The
POR function inhibits operation at disabled status (VCOMP
is less than 1.2V). With both input supplies above their
POR thresholds, the device initiates a soft-start interval.
Soft-Start
The APW7065 has a built-in digital soft-start to control the
output voltage rise and limit the current surge during the
start-up. In Figure 1, when VCC exceeds rising POR
threshold voltage, it will delay 2048/Fosc seconds and
then begin soft start. During soft-start, an internal ramp
connected to the one of the positive inputs of the Gm
amplifier rises up from 0V to 2V to replace the reference
voltage (0.8V) until the ramp voltage reaches the refer-
ence voltage. The soft-start interval is decided by the os-
cillator frequency (300kHz). The formulation is given by:
Tdelay=t2-t1=2048/FOSC=6.8ms
Tsoft-start=t3-t2=1024/FOSC=3.4ms
t1
Voltage(V)
Time
VCC
VOUT
t2t3
Figure 1.Soft Start Interval
Voltage(V) FB
12.5mV
16/Fosc
Time
Figure 2.The Controlled Stepped FB Voltage During Soft-
Start
Over-Current Protection
The over-current protection monitors the output current
by using the voltage drop across the lower MOSFET’s
RDS(ON) and this voltage drop will be compared with the
internal 0.29V reference voltage. If the voltage drop across
the lower MOSFET’s RDS(ON) is larger than 0.29V, an over-
current condition is detected. The threshold of the over
current limit is given by:
For the over-current is never occurred in the normal oper-
ating load range; the variation of all parameters in the
above equation should be determined.
)ON(DS
Limit R29.0
I=
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw12
Function Description (Cont.)
- The MOSFET’s RDS(ON) is varied by temperature and gate
to source voltage, the user should determine the maxi-
mum RDS(ON) in manufacturer’s datasheet.
- The minimum Vocset should be used in the above
equation.
- Note that the ILIMIT is the current flow through the lower
MOSFET; ILIMIT must be greater than maximum output
current add the half of inductor ripple current.
Over-Current Protection (Cont.)
Shutdown and Enable
Pulling the COMP voltage to GND by an open drain
transistor, shown in typical application circuit, shutdown
the APW7065 PWM controller. In shutdown mode, the
UGATE and LGATE turn off and pull to PHASE and GND
respectively.
Under Voltage Protection
The FB pin is monitored during converter operation by
the internal Under Voltage (UV) comparator. If the FB volt-
age drops below 50% of the reference voltage (50% of
0.8V=0.4V), a fault signal is internally generated, and the
device turns off both high-side and low-side MOSFET
and the converter’s output is latched to be floating.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw13
Application Information
Where ROUT is the resistor connected from VOUT to FB and
RGND is the resistor connected from FB to GND.
Output Voltage Selection
The output voltage can be programmed with a resistive
divider. Use 1% or better resistors for the resistive divider
is recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 0.8V. The
output voltage is determined by:
+×= GND
OUT
OUT R
R
10.8V
Output Inductor Selection
The inductor value determines the inductor ripple current
and affects the load transient response. Higher inductor
value reduces the inductor’s ripple current and induces
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
∆VOUT = IRIPPLE x ESR
where FS is the switching frequency of the regulator.
Although increase of the inductor value reduces the ripple
current and voltage, a tradeoff will exist between the
inductor’s ripple current and the regulator load transient
response time.
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current.
The maximum ripple current occurs at the maximum in-
put voltage. A good starting point is to choose the ripple
current to be approximately 30% of the maximum output
current. Once the inductance value has been chosen,
select an inductor that is capable of carrying the required
peak current without going into saturation. In some types
of inductors, especially core that is made of ferrite, the
ripple current will increase abruptly when it saturates.
This will result in a larger output ripple voltage.
IN
OUT
S
OUTIN
RIPPLE V
V
LFVV
I×
×
−
=
Output Capacitor Selection
Higher capacitor value and lower ESR reduce the output
ripple and the load transient drop. Therefore, selecting
high performance low ESR capacitors is intended for
switching regulator applications. In some applications,
multiple capacitors have to be paralleled to achieve the
desired ESR value. A small decoupling capacitor in par-
allel for bypassing the noise is also recommended, and
the voltage rating of the output capacitors also must be
considered. If tantalum capacitors are used, make sure
they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Input Capacitor Selection
The input capacitor is chosen based on the voltage rat-
ing and the RMS current rating. For reliable operation,
select the capacitor voltage rating to be at least 1.3 times
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power up, the input
capacitors have to handle large amount of surge current.
If tantalum capacitors are used, make sure they are surge
tested by the manufactures. If in doubt, consult the ca-
pacitors manufacturer. For high frequency decoupling, a
ceramic capacitor 1µF can be connected between the
drain of upper MOSFET and the source of lower MOSFET.
MOSFET Selection
The selection of the N-channel power MOSFETs are de-
termined by the RDS(ON), reverse transfer capacitance (CRSS)
and maximum output current requirement. There are two
components of loss in the MOSFETs: conduction loss
and transition loss. For the upper and lower MOSFET,
the losses are approximately given by the following:
PUPPER = IOUT2 (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS
PLOWER = IOUT 2(1+ TC)(RDS(ON))(1-D)
Where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction loss while the
upper MOSFET include an additional transition loss. The
switching internal, tSW, is a function of the reverse transfer
capacitance CRSS. The (1+TC) term is to factor in the tem-
perature dependency of the RDS(ON) and can be extracted
from the “RDS(ON) vs Temperature” curve of the power
MOSFET.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw14
PWM Compensation
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB and VOUT should
be added. The compensation network is shown in Fig-
ure 6. The output LC filter consists of the output inductor
and output capacitors. The transfer function of the LC
filter is given by:
Application Information (Cont.)
1CESRsCLsCESRs1
GAIN OUTOUT
2OUT
LC +××+×× ××+
=
The poles and zero of this transfer functions are:
OUT
LC CL2 1
F××π×
=
OUT
ESR CESR21
F××π×
=
The FLC is the double poles of the LC filter, and FESR is the
zero introduced by the ESR of the output capacitor.
PHASE LOUTPUT
COUT
ESR
Figure 3. The Output LC Filter
FLC
FESR
-40dB/dec
-20dB/dec
Frequency(Hz)
GAIN (dB)
Figure 4. The LC Filter GAIN and Frequency
The PWM modulator is shown in Figure 5. The input is
the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM modula-
tor is given by:
OSC
IN
PWM V
V
GAIN ∆
=
Figure 5. The PWM Modulator
Output of Error
Amplifier
ΔVOSC PWM
Comparator
Driver
Driver
PHASE
VIN
OSC
The compensation network is shown in Figure 6. It pro-
vides a close loop transfer function with the highest zero
crossover frequency and sufficient phase margin. The
transfer function of error amplifier is given by:
( )
×
+×
×× +
+
×+
+×
×
+
×
×× +
=
+
+
==
C3R3 1
s
C2C1R2 C2C1
ss
C3R3R1 1
s
C2R21
s
C1R3R1 R3R1
sC3
1
R3R1//
sC2
1
R2//
sC1
1
V
V
GAIN OUT
COMP
AMP
The poles and zeros of the transfer function are:
( )
C3R321
F
C2C1 C2C1
R22
1
F
C3R3R121
F
C2R221
F
P2
P1
Z2
Z1
××π×
=
+
×
××π×
=
×+×π×
=
××π×
=
VREF
VOUT VCOMP
R1
R3C3R2C2
C1
FB
Figure 6. Compensation Network
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw15
The closed loop gain of the converter can be written as:
GAINLC X GAINPWM X GAINAMP
Figure 7. shows the asymptotic plot of the closed loop
converter gain, and the following guidelines will help to
design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.
1.Choose a value for R1, usually between 1K and 5K.
2.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) X FS >FO>FESR
Use the following equation to calculate R2:
3.Place the first zero FZ1 before the output LC filter double
pole frequency FLC.
FZ1 = 0.75 X FLC
Calculate the C2 by the equation:
4.Set the pole at the ESR zero frequency FESR:
FP1 = FESR
Calculate the C1 by the equation:
5.Set the second pole FP2 at the half of the switching fre-
quency and also set the second zero FZ2 at the output LC
filter double pole FLC. The compensation gain should not
exceed the error amplifier open loop gain, check the com-
pensation gain at FP2 with the capabilities of the error
amplifier.
FP2 = 0.5 X FS
FZ2 = FLC
Combine the two equations will get the following compo-
nent calculations:
Figure 7. Converter Gain and Frequency
Application Information (Cont.)
PWM Compensation (Cont.)
R1
F
F
V
V
R2 LC
O
IN
OSC ××
∆
=
0.75FR221
C2 LC ×××π×
=
1FC2R22C2
C1 ESR −×××π×
=
1
F2FR1
R3
LC
S−
×
=
S
FR3
1
C3 ××π
=
FLC
Frequency(Hz)
GAIN (dB)
20log
(R2/R1) 20log
(VIN/ΔVOSC)
FZ1 FZ2 FP1 FP2
FESR
PWM & Filter
Gain
Converter Gain
Compensation
Gain
Layout Consideration
In any high switching frequency converter, a correct lay-
out is important to ensure proper operation of the
regulator. With power devices switching at 300kHz,the
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off, the MOSFET is car-
rying the full load current. During turn-off, current stops
flowing in the MOSFET and is free-wheeling by the lower
MOSFET and parasitic diode. Any parasitic inductance of
the circuit generates a large voltage spike during the
switching interval. In general, using short and wide printed
circuit traces should minimize interconnecting imped-
ances and the magnitude of voltage spike. And signal
and power grounds are to be kept separate till combined
using ground plane construction or single point
grounding. Figure 8. illustrates the layout, with bold lines
indicating high current paths; these traces must be short
and wide. Components along the bold lines should be
placed lose together. Below is a checklist for your layout:
- Keep the switching nodes (UGATE, LGATE and PHASE)
away from sensitive small signal nodes since these
nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw16
Figure 8.Layout Guidelines
Application Information (Cont.)
Layout Consideration (Cont.)
- The traces from the gate drivers to the MOSFETs (UG,
LG) should be short and wide.
- Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimiz-
ing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node.
- Decoupling capacitor, compensation component, the
resistor dividers, and boot capacitors should be close
their pins. (For example, place the decoupling ceramic
capacitor near the drain of the high-side MOSFET as
close as possible. The bulk capacitors are also placed
near the drain).
- The input capacitor should be near the drain of the up-
per MOSFET; the output capacitor should be near the
loads. The input capacitor GND should be close to the
output capacitor GND and the lower MOSFET GND.
- The drain of the MOSFETs (VIN and PHASE nodes) should
be a large plane for heat sinking.
VCC
BOOT
PHASE
UGATE
LGATE
VIN
VOUT
L
O
A
D
APW7065
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw17
Package Information
SOP-8
D
e
E
E1
SEE VIEW A
cb
h X 45
°
A
A1A2
L
VIEW A
0.25
SEATING PLANE
GAUGE PLANE
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
S
Y
M
B
O
LMIN. MAX.
1.75
0.10
0.17 0.25
0.25
A
A1
c
D
E
E1
e
h
L
MILLIMETERS
b0.31 0.51
SOP-8
0.25 0.50
0.40 1.27
MIN. MAX.
INCHES
0.069
0.004
0.012 0.020
0.007 0.010
0.010 0.020
0.016 0.050
0
0.010
1.27 BSC 0.050 BSC
A2 1.25 0.049
0
°
8
°
0
°
8
°
3.80
5.80
4.80
4.00
6.20
5.00 0.189 0.197
0.228 0.244
0.150 0.157
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw18
Application A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOP-8
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
(mm)
Carrier Tape & Reel Dimensions
Devices Per Unit
Package Type Unit Quantity
SOP- 8 Tape & Reel 2500
H
T1
A
d
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw19
Taping Direction Information
Classification Profile
SOP-8
USER DIRECTION OF FEED
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw20
Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
APW7065
www.anpec.com.tw21
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838