PRELIMINARY
Publicati on# 20818 Rev: CAmendment/+2
Issue Date: March 1998
Am29F002/Am29F002N
2 Megabit (256 K x 8-Bit)
CMOS 5.0 Volt-onl y Boot Sec tor Flash Memory
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■High performan c e
— Access times as fast as 55 ns
■Low power consumption (typical values at 5
MHz)
— 1 µA standby mode current
— 20 mA read current
— 30 mA program/erase current
■Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
Temporary Sector Unprotect feature allows code
changes in prev iously locked sectors
■Top or bottom boot block configurations
available
■Embe dded Algorithms
— Embedded Erase algorithm automatically
preprogr ams and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specif ied addresses
■Minimum 100,000 write cycle guarantee per
sector
■Package option
— 32-pin PDIP
— 32-pin TSOP
— 32-pin PLCC
■Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■Erase Suspend/Erase Resume
— Suspends an er ase operati on to read dat a from,
or progr am data to, a sector that is not being
erased, then res umes the erase operation
■Hardware reset pin (RESET#)
— Hardware method t o reset the device to reading
array data (not available on Am29F002N)
2 Am29F002/Am29F002N
PRELIMINARY
GENERAL DESCRIPTION
The Am29F002 Family consists of 2 Mbit, 5.0 volt-only
Flash memory devices organized as 262,144 bytes.
The Am29F002 offers the RESET# function, the
Am29F002N does not. The data appears on DQ7–
DQ0. The device is offered in 32-pin PLCC, 32-pin
TSOP, and 32-pin PDIP packages. This device is
designed to be programmed in-system with the
standard system 5.0 volt VCC supply. No VPP is
required for write or erase operations. The device can
also be programmed in standard EPROM program-
mers.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to
operate wit hout wait st ates. To eliminate bus c ontention
the device has separate chip enable (CE#), write
enable ( WE#) and output enab le (OE#) controls.
The de vice requires only a single 5.0 volt power sup-
ply for both read and wr ite functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The de vice is entirely command set compatib le with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms t he arra y (if it is not already progr ammed)
bef ore ex ecuting the e rase operation. During er ase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.
The sector erase arch itecture all ows memory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure . True bac kgro und eras e can thus be achiev ed.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading arr a y data. The RESET# pin ma y be tied to the
system reset circuitr y. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memor y.
(This feature is not available on the Am29F002N.)
The system can place the device into the standby
mode. Power consumption is greatly reduced in this
mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
Am29F002/Am29F002N 3
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note: S ee “AC Characterist ics ” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29F002/Am29F002N
Speed Option VCC = 5.0 V ± 5% -55
VCC = 5.0 V ± 10% -70 -90 -120
Max access time, ns (tACC)55 70 90 120
Max CE# access time, ns (tCE)55 70 90 120
Max OE# access time, ns (tOE)30 30 35 50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
CE#
OE#
STB
STB
DQ0
–
DQ7
Sector Switches
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A17
20818C-1
n/a Am29F00N
4 Am29F002/Am29F002N
PRELIMINARY
CONNECTION DIAGRAMS
3
4
5
2
1
9
10
11
12
13
27
26
25
24
23
7
8
22
21
6
32
31
20
14
30
29
28
15
16
19
18
17
A6
A5
A4
A3
A2
A1
A0
A16
DQ0
A15
A12
A7
DQ1
DQ2
VSS
A8
A9
A11
OE#
A10
CE#
DQ7
VCC
WE#
DQ6
A17
A14
A13
DQ5
DQ4
DQ3
NC
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A11
A9
A8
A13
A14
A17
WE#
VCC
RESET#
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
131 30
2
3
4
5
6
7
8
9
10
11
12
13 17 18 19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
RESET#
VCC
WE#
A17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
20818C-2
PDIP
Standard TSOP
PLCC
NC on Am 29F00N
NC on Am29F00N
NC on A m 29F00N
RESET#
Am29F002/Am29F002N 5
PRELIMINARY
PIN CONFIGURATION
A0–A17 = 18 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
(not available on Am29F002N)
VCC = +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS = De vice ground
NC = Pin not connected internally
LOGIC SYMBOL
20818C-3
18 8
DQ0–DQ7
A0–A17
CE#
OE#
WE#
RESET#
N/C on Am 29F002N
6 Am29F002/Am29F002N
PRELIMINARY
ORDERING INFORMATION
Standard Pr o duct
AMD standard products are available in several packages and operating ranges. The order number (Valid C ombi-
nation) is for med by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm a vailability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29F002/Am29F002N
2 Megabit (256 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Am29F002 -70 P C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
E=Extended (–55°C to +125°C)
PACKAG E TY PE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
B
T
Valid Combinations
Am29F002T-55
Am29F002B-55
Am29F002NT-55
Am29F002NB-55
PC, JC, JI, EC, EI
Am29F002T-70
Am29F002B-70
Am29F002NT-70
Am29F002NB-70
PC, PI, JC, JI, EC, EI
Am29F002T-90
Am29F002B-90
Am29F002NT-90
Am29F002NB-90 PC, PI, PE,
JC, JI, JE,
EC, EI, EE
Am29F002T-120
Am29F002B-120
Am29F002NT-120
Am29F002NB-120
Am29F002/Am29F002N 7
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The regi st er is composed of l atches that store the
commands, along with the address and data infor ma-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in fur ther detail.
Table 1. Am29F002/Am29F002N Device Bus Operati ons
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0
±
0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information. This function requires the
RESET# pin and is therefore not available on the Am29F002N device.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device . OE# is the output control
and gates arra y dat a to the output pins. WE# should re-
main at VIH.
The internal state machine is set for reading array
data upon device power-up , or after a hardware reset.
This ensures that no spur ious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command reg ister contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE # to V IH.
An erase oper at ion can er ase one sect or, multiple sec-
tors, or the entire de vice. The Sector Address Tables in-
dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the Command Defini-
tions section f or details on erasing a sector or th e entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and Autoselect
Command Sequence sections for more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tabl es and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or prog ram opera tion, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Sta ndard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Operation CE# OE# WE# RESET#
(n/a Am29F002N) A0–A17 DQ0–DQ7
Read L L H H AIN DOUT
Write L H L H AIN DIN
CMOS Sta ndby VCC ± 0.5 V X X H X High-Z
TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Reset (n/a on Am29F002N) X X X L X High-Z
Temporary Sector Unprotect
(See Note) XXX V
ID XX
8 Am29F002/Am29F002N
PRELIMINARY
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to t he device ,
it can place the device in the standby mode. In this
mode, current co nsumption is g reat ly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The de vice enters the CMOS standb y mode when CE#
and RESET# pins (CE# only on the Am29F002N) are
both held at VCC ± 0.5 V. (Note that this is a more re-
stricted voltage range than VIH.) The device enters the
TTL standb y mode when CE# and RESET# pins (CE#
only on the Am29F002N) ar e both held at VIH. The de-
vice requires standard access time (tCE) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is dr iven low. Refer to the next section, “RE-
SET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics tables represents the
standby current specification.
RESET#: Hardware Reset Pin
Note: The RESET# pin is not available on the
Am29F002N.
The RESET# pin p rovides a hard ware method of reset-
ting the device t o reading arr ay dat a. When the sy stem
drives the RESET# pin low for at least a period of tRP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the de vice is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS ±
0.5 V, the device enters the CMOS stan dby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the de vice is
disabled. The output pins are plac ed in the h igh imped-
ance state.
Table 2. Am29F002/A m29F002N Top Boot Block Sector Address Table
Sector A17 A16 A15 A14 A13 Sector Size
(Kbytes) Address Range
(in hexadecimal )
SA0 0 0 X X X 64 00000h–0FFFFh
SA1 0 1 X X X 64 10000h–1FFFFh
SA2 1 0 X X X 64 20000h–2FFFFh
SA3 1 1 0 X X 32 30000h–37FFFh
SA4 1 1 1 0 0 8 38000h–39FFFh
SA5 1 1 1 0 1 8 3A000h–3BFFFh
SA6 1 1 1 1 X 16 3C000h–3FFFFh
Am29F002/Am29F002N 9
PRELIMINARY
Table 3. Am29F002/Am29F002N Bottom Boot Block Sector Address Table
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended f or programming equipment
to automatically match a de vice to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Aut oselect Codes (High Voltage Method) tabl e. In addi-
tion, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don’t care . When all
necessary b its hav e been set as required, the progr am-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
Table 4. Am29F002/Am29F002N A u tosel ect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disabl es both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously pro-
tected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are pro vided in the
supplements, publication numbers 20819 and 21183.
Sector A17 A16 A15 A14 A13 Sector Size
(Kbytes) Address Range
(in hexadecimal )
SA00000X 16 00000h–03FFFh
SA1 0 0 0 1 0 8 04000h–05FFFh
SA2 0 0 0 1 1 8 06000h–07FFFh
SA3 0 0 1 X X 32 08000h–0FFFFh
SA4 0 1 X X X 64 10000h–1FFFFh
SA5 1 0 X X X 64 20000h–2FFFFh
SA6 1 1 X X X 64 30000h–3FFFFh
Description CE# OE# WE#
A17
to
A13
A12
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL 01h
Device ID:
Am29F002/Am29F002N
(Top Boot Block)
LLH
XXV
ID XLXLH B0h
LLH
Device ID:
Am29F002/Am29F002N
(Bottom Boot Block)
LLH
XXV
ID XLXLH 34h
LLH
Sector Protec tion Ver if icat ion L L H SA X VID XLXHL
01h
(protected)
00h
(unprotected)
10 Am29F002/Am29F002N
PRELIMINARY
Contact an AMD representat ive to obtain a copy of the
appropriate document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possib le to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
Note: This feature requites the RESET# pin and is
therefore not available on the Am29F002N.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system.
The Sector Unpr otect mode is activ at ed by setting the
RESET# pin to VID. During this mode, formerly pro-
tected sectors can be programmed or erased by se-
lecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are prot ected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
Figure 1. Temporary Sector Unpr otect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection meas ures pre vent a ccidental eras ure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Low V CC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-do wn. The command register and
all internal program/er ase circuits are disabled, and the
dev ice resets . Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or W E# = VIH. To initiate a wr ite cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up , the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on po wer-up.
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect
Completed (Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
20818C-4
Am29F002/Am29F002N 11
PRELIMINARY
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates de vice op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Charac teristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accept s an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a progr amming operation in the Erase
Suspend mode, th e system ma y once again read array
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more information
on this mode.
The system
must
issue the reset command to re-en-
abl e the de vice f or reading arr ay data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” se ctio n , next.
See also “Requirements for Reading Arra y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the aut oselect mode , the re set command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command retur ns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the man uf acturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements . This method is an alternativ e to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrie v es the manu-
facturer cod e. A read cycle a t ad dress X X 01h returns
the device code. A read cycle containing a secto r ad-
dress (SA) and the address 02h in returns 01h if that
sector i s pr ot ected, o r 0 0h if it i s unp rotect e d. Refer to
the Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading arra y data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated b y writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is
not
required to provide further
controls or timings. The device automatically provides
internally generated progr am pulses and v erify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
progr am command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the stat us of the p rogra m operation by using DQ7
or DQ6. See “Write Operation Status” for information
on these status bits.
12 Am29F002/Am29F002N
PRELIMINARY
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. On the
Am29F002 only, note that a hard ware reset during the
sector erase operation immediately term inates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempt ing to do so ma y halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. Howe ver, a succeeding read will show that the
data is still “0”. Only erase operations can con vert a “0”
to a “1”.
Note: See the appropriate Command Definitions table for
program comma nd seq ue nce.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-b us-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles ar e then followed b y the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogr am prior to erase. The Embedded Erase algo-
rithm automatically preprogr ams and verifies the entire
memor y for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. On the Am29F002
only, note that a hardware reset during the sector
erase operation immediately terminates the operation.
The Sector Erase command sequence should be rein-
itiated once the device has returned to reading array
data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status
bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses ar e no long er latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters , and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does
not
require the system to preprogr am
the memory prior to er ase. The Embedded Erase algo-
rithm automatically progr ams and verifies the s ector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
ma y be done in any sequence , and the number of sec-
tors ma y be from one sector to al l sectors. The time be-
tween these additional cycles mus t be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The inte rrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
20818C-5
Am29F002/Am29F002N 13
PRELIMINARY
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All oth er commands
are ignored. On the Am29F002 only, note that a hard-
ware reset during the sector erase operation immedi-
ately terminates the operation. The Sector Erase
command sequence should be reinitiated once the de-
vice has returned to reading arra y dat a, to ensure data
integrity.
When the Embedded Erase algorithm is complete, the
dev ice returns to reading arra y data and addresses are
no longer latched. The system can determine the sta-
tus of the erase opera tion b y using DQ7, DQ6, or DQ2.
Refer to “Write Operation Status” for information on
these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “A C Char acteristics ” section f or par amet ers , and to
the Sector Er ase Oper ations Timing dia gr am for timing
waveforms.
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
20818C-6
14 Am29F002/Am29F002N
PRELIMINARY
Erase Suspend/Erase Resume Commands
The Erase Suspend c ommand allo ws the s ystem to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and s uspends t he er ase oper at ion. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during a
sector erase oper ation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected f or eras ure. (The de vice “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the s ector erase oper ati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Am29F002/Am29F002N 15
PRELIMINARY
Table 5. Am29F002/Am29F002N Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read op eration.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be v erified (in autoselect mode) or
erased. Address bits A17–A13 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadec imal.
3. Except when reading arra y or autoselect data, all b us cycles
are write operations.
4. Address bits A17–A12 are don’t care s for unlock and
command cycles, except when PA or SA is required.
5. No unlock or command cycles required when reading array
data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a
read cycle.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Sus pend command is valid on ly during a
sector erase operation.
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Auto-
select
(Note 7)
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID,
Top Boot Block 4 555 AA 2AA 55 555 90 X01 B0
Device ID,
Bottom Boot Block 4 555 AA 2AA 55 555 90 X01 34
Sector Protect Verify
(Note 8) 4 555 AA 2AA 55 555 90 (SA)
X02 00
01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspen d (Note 9) 1 XXX B0
Erase Resume (N ote 10) 1 XXX 30
Cycles
16 Am29F002/Am29F002N
PRELIMINARY
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 6 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# P olling is v alid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is activ e f or ap-
proximately 2 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When t he Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous t o the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an er ase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , t hen th e de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid dat a at DQ7–
DQ0 on the
following
read cycles . This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
20818C-7
Figure 4. Data# Polling Algorithm
Am29F002/Am29F002N 17
PRELIMINARY
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or er ase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles f or appr o x ima tely 100 µs , then ret urns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the de vice is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status tab le shows the out puts for
Toggle Bit I on DQ6. Ref er to Figure 5 f or the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the Embedded Er as e alg orithm is in pr og ress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode info rmation. Ref er t o Table 6 to c ompare output s
for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchart
form , and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagr am. The DQ2 vs. DQ6 figure sho ws the dif-
ferences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bi t is togg ling. Typically, a
system w ould note and store the v alue of the toggle bit
after the first read. After the second read, the system
would co mpare the ne w v alue of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can r ead arra y data on DQ7–DQ0 on the f ollowing
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
dev ice did not complete the operat ion successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 t hrough successive read cycles, de-
termining the statu s as described in the previous para-
graph. Alternatively, it may choose to perform other
syst em task s. In thi s case , the syst em m ust st art at the
beginning of the algorithm when it ret urns to determine
the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the pro gram or er ase cycle w as
not successfully completed.
18 Am29F002/Am29F002N
PRELIMINARY
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that i s pre viously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system ma y read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tiona l sector s are selected f or erasure, the ent ire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the s ystem can gua rant ee that t he ti me betw een ad-
ditional sector erase commands will always be less
than 50 µs . See also the “Sect or Erase Command Se-
quence” section.
After the sector erase command sequence is written,
the system should re ad the s tatus on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence , and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other th an Er ase Su spend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the s ystem softw are should chec k the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 6 sho ws the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
20818C-8
Figure 5. Toggle Bit Algorithm
(Notes
1, 2)
(Note 1)
Am29F002/Am29F002N 19
PRELIMINARY
Table 6. Write Operation Status
Notes:
1. DQ7 and DQ2 require a valid address when reading status inf ormation. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
Operation DQ7
(Note 1) DQ6 DQ5
(Note 2) DQ3 DQ2
(Note 1)
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle
Embedded Erase Algorithm 0 Toggle 0 1 Toggle
Erase
Suspend
Mode
Reading with in Erase
Suspend ed Sec tor 1 No toggle 0 N/A Toggle
Reading with in Non -Eras e
Suspend ed Sec tor Data Data Data Data Data
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A
20 Am29F002/Am29F002N
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is
V
CC +0.5 V.
During voltage transitions, input or I/O pins may overshoot
to VCC +2.0 V for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot VSS to –2.0 V f or periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may ov ershoot to +13.5 V for periods
up to 20 ns. (RESET# is not available on Am29F002N.)
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 6. M aximum Negative Overshoot
Waveform
Figure 7. Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ± 5% devices. . . . . . . . . . .+4.75 V to +5.25 V
VCC for ± 10% device s. . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20818C-9
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
20818C-10
Am29F002/Am29F002N 21
PRELIMINARY
DC CHARACTERISTICS
TTL/NMOS Compatible
Notes:
1. RESET# is not available on Am29F002N.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA
ILIT A9, OE#, RESET# Input Load Current
(Notes 1, 4) VCC = VCC max;
A9, OE#, RESET# = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current (Note 2) CE# = VIL, OE# = VIH 20 30 mA
ICC2 VCC Active Write Current (Notes 3, 4) CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current VCC = VCC max, CE#, OE# = VIH 0.4 1 mA
ICC4 VCC Reset Current (Note 1) VCC = VCC max; RESET# = VIL 0.4 1 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2.0 VCC
+ 0.5 V
VID Voltage for Autoselect and Temporary
Sector Unprotect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 12 mA, VCC = VCC min 0.45 V
VOH Output High Voltage IOH = –2.5 mA, VCC = VCC min 2.4 V
VLKO Low VCC Lock-Out Voltage 3.2 4.2 V
22 Am29F002/Am29F002N
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. RESET# is not available on Am29F002N.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. ICC3 and ICC4 = 20
µ
A max at extended temperature (>+ 85
°
C).
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9, OE#, RESET#
Input Load Current (Notes 1, 4) VCC = VCC max;
A9, OE#, RESET# = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Note 2) CE# = VIL, OE# = VIH 20 30 mA
ICC2 VCC Active Write Current
(Notes 3, 4) CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current (Note 5) VCC = VCC max; CE# = VCC±0.5 V 1 5 µA
ICC4 VCC Reset Current (Notes 1, 5) VCC = VCC max; RESET# = VIL 15µA
V
IL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 12 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC mi n V
CC–0.4
VLKO Low VCC Lock-Out Voltage 3.2 4.2 V
Am29F002/Am29F002N 23
PRELIMINARY
TEST CONDITIONS
Table 7. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
5.0 V
Device
Under
Test
20818C-11
Figure 8. Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition -55 All
others Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap aci tan ce) 30 100 pF
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement
reference levels 1.5 0.8, 2.0 V
Output timing measurement
reference levels 1.5 0.8, 2.0 V
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
24 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
Parameter
Description
Speed Option
JEDEC S td Test Setup -55 -70 -90 -120 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL Max 55 70 90 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 ns
tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 15 20 20 30 ns
tGHQZ tDF Output Enable to Output High Z
(Note 1) Max15202030ns
t
OEH
Output Enable
Hold Time
(Note 1)
Read Min 0 ns
Toggle and
Data# Polling Min 10 ns
tAXQX tOH Output Hold Time F rom Addresses, CE#
or OE#, Whichev er Occurs First (Note 1) Min 0 ns
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
RESET#
n/a Am29F002N
tDF
tOH
20818C-12
Figure 9. Read Operations Timings
25 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested. RESET# is not available on Am29F002N.
Parameter
Description All Speed OptionsJEDEC Std Test Setup Unit
tREADY RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note) Max 20 µs
tREADY RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See Note) Min 50 ns
RESET#
n/a Am29F002N tRP
tReady
Reset Timings NOT during Embedded Algorithms
CE#, OE#
tRH
Reset Timings during Embedded Algorithms
RESET#
n/a Am29F002N tRP
20818C-13
Figure 10. RESET# Timings
Am29F002/Am29F002N 26
PRELIMINARY
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter
-55 -70 -90 -120JEDEC Std. Description Unit
tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 45 45 45 50 ns
tDVWH tDS Data Setup Time Min 25 30 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 30 35 45 50 ns
tWHWL tWPH Write Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
27 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
OE#
WE#
CE#
VCC
Data
Addresses
tDS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555h PA PA
Read Status Data (last two cycles)
A0h
tGHWL
tCS
Status DOUT
Program Command Sequence (last two cycles)
tCH
PA
Notes:
1. PA = program addre ss, PD = program data, DOUT is the true data at the program address.
20818C-14
Figure 11. Program Operation Timings
Am29F002/Am29F002N 28
PRELIMINARY
AC CHARACTERISTICS
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tGHWL
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
20818C-15
Figure 12. Ch ip/Sector Erase Operation Timings
29 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0–DQ6
Complement True
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
t
ACC
t
RC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
20818C-16
Figure 13. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
tOE
DQ6/DQ2
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
tACC
tRC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note: V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
20818C-17
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
Am29F002/Am29F002N 30
PRELIMINARY
AC CHARACTERISTICS
Temporary Sector Unprotect (Am29F002 only)
Note: Not 100% tested.
Parameter
All Speed OptionsJEDEC Std. Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
20818C-18
Figure 15. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Pro gra m
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
tVIDR
12 V
0 or 5 V
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
0 or 5 V
20818C-19
Figure 16. Temporary Sector Unpr otect Timing Diag ram (Am29F002 only)
31 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter
-55 -70 -90 -120JEDEC Std. Description Unit
tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 45 45 50 ns
tDVEH tDS Data Setup Time Min 25 30 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width M in 3 0 3 5 45 50 ns
tEHEL tCPH CE# Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
Am29F002/Am29F002N 32
PRELIMINARY
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, DOUT = data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
20818C-20
Figure 17. A lternate CE# Controlled Write Operation Timings
33 Am29F002/Am29F002N
PRELIMINARY
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 5.0 V VCC, 100,0 00 cyc les. Additio na lly,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. RESET# not available on Am29F002N.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 1 8 s Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 7 s
Byte Programming Time 7 300 µs Excludes system level
overhead (Note 5)
Chip Programming Time (Note 3) 1.8 5.4 s
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE #, and RESE T#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Am29F002/Am29F002N 34
PRELIMINARY
PLCC AND PDIP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25
°
C, f = 1.0 MHz.
DATA RETENTION
Parameter
Symbol Parameter Description Test Conditions Typ Max Unit
CIN Input Capacitance VIN = 0 4 6 pF
COUT Output Capacitance VOUT = 0 8 12 pF
CIN2 Control Pin Capacitance VPP = 0 8 12 pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C 10 Years
125°C 20 Years
35 Am29F002/Am29F002N
PRELIMINARY
PH YS ICAL DIMENSIONS
PD 032
32-Pin Plastic DIP (measured in inches)
PL 032
32-Pin Plastic Leaded Chip Carrier (measured in inches)
Pin 1 I.D.
1.640
1.670
.530
.580
.005 MIN
.045
.065
.090
.110
.140
.225
.120
.160 .016
.022
SEATING PLANE
.015
.060
16-038-S_AG
PD 032
EC75
5-28-97 lv
32 17
16 .630
.700
0°
10°
.600
.625
.009
.015
.050 REF.
.026
.032 TOP VIEW
Pin 1 I.D.
.485
.495
.447
.453
.585
.595
.547
.553
16-038FPO-5
PL 032
DA79
6-28-94 ae
SIDE VIEW
SEATING
PLANE
.125
.140
.009
.015
.080
.095
.042
.056
.013
.021
.400
REF. .490
.530
Am29F002/Am29F002N 36
PRELIMINARY
PH YSICAL DIMENSI ONS (continued)
TS 032
32-Pin Standard Thin Small Package (measured in millimeters)
Pin 1 I.D.
1
18.30
18.50
7.90
8.10
0.50 BSC
0.05
0.15
0.95
1.05
16-038-TSOP-2
TS 032
DA95
3-25-97 lv
19.80
20.20
1.20
MAX
0.50
0.70
0.10
0.21
0°
5°
0.08
0.20
37 Am29F002/Am29F002N
PRELIMINARY
REVISION SUMMARY FOR AM29F002/AM29F002N
Revision C
Global
Made form atting and layout consistent with other data
sheets. Used updated common tables and diagrams.
Combined Am29F002 and Am29F002N into a single
data sheet.
Revision C+1
Figure 17, Alternate CE# Controlled Write
Opera tions Timings
Remov ed the R Y/BY# wav erf orm and tBUSY parameter.
The RY/BY# pin is not available on this device.
Revision C+2
Blo ck D i agra m
Corrected diagram by adding paths from the timer to
the PGM and Erase Voltage Generators.
Table 3, Bottom Boot Block Sector Addresses
Corrected adddress bit A15 for sector SA2 to “0.”
Table 5, Command Definitions
Deleted the lower row of addresses in the Sector Pro-
tect Verify command definitions.
In the legend, correct ed the definit ion f o r SA to indicate
that address bits A17–A13 uniquely select a sector.
Deleted Note 4.
DC Characteris tics
Added Note 4 reference to ILIT. Corrected maximum
currents for ICC1 and ICC2, typical currents for ICC3 and
ICC4, test conditions for ICC4 and VOL.
In TTL/NMOS table, deleted Note 5.
In CMOS tabl e, corr ected IOH current for VOH.
AC Characteristics
Read Operations:
Corrected tDF specifications for -55
speed option.
Erase/Program Operations:
Corrected the notes refe r-
ence for tWHWH1 and tWHWH2. These parameters are
100% tested. Corrected the note reference for tVCS.
This parameter is not 100% tested. Removed -150
specifications . Corrected tDS and tWP f or -55 speed op-
tion, tAH for -90 speed option.
Alternate CE# Controlled Erase/Program Operations:
Corrected the not es ref erence for tWHWH1 and tWHWH2.
These parameters are 100% tested. This parameter is
not 100% tested. Removed -150 specifications. Cor-
rected tDS and tCP for -55 speed option.
Temporary Sector Unprotect Table
Added note reference for tVIDR. This parameter is not
100% tested.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
