PD - 95087A IRLR/U3410PbF l l l l l l l l Logic Level Gate Drive Ultra Low On-Resistance Surface Mount (IRLR3410) Straight Lead (IRLU3410) Advanced Process Technology Fast Switching Fully Avalanche Rated Lead-Free HEXFET(R) Power MOSFET D VDSS = 100V RDS(on) = 0.105 G ID = 17A S Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. D-PAK TO-252AA I-PAK TO-251AA Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. Units 17 12 60 79 0.53 16 150 9.0 7.9 5.0 -55 to + 175 A W W/C V mJ A mJ V/ns C 300 (1.6mm from case ) Thermal Resistance Parameter RJC RJA RJA www.irf.com Junction-to-Case Junction-to-Ambient (PCB mount) ** Junction-to-Ambient Typ. Max. Units --- --- --- 1.9 50 110 C/W 1 12/7/04 IRLR/U3410PbF Electrical Characteristics @ TJ = 25C (unless otherwise specified) V(BR)DSS/TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current V(BR)DSS Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time LD Internal Drain Inductance LS Internal Source Inductance Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance IGSS Min. Typ. Max. Units Conditions 100 --- --- V VGS = 0V, ID = 250A --- 0.122 --- V/C Reference to 25C, I D = 1mA --- --- 0.105 VGS = 10V, ID = 10A --- --- 0.125 W VGS = 5.0V, ID = 10A --- --- 0.155 VGS = 4.0V, ID = 9.0A 1.0 --- 2.0 V VDS = VGS, ID = 250A 7.7 --- --- S VDS = 25V, ID = 9.0A --- --- 25 VDS = 100V, VGS = 0V A --- --- 250 VDS = 80V, VGS = 0V, TJ = 150C --- --- 100 VGS = 16V nA --- --- -100 VGS = -16V --- --- 34 ID = 9.0A --- --- 4.8 nC VDS = 80V --- --- 20 VGS = 5.0V, See Fig. 6 and 13 --- 7.2 --- VDD = 50V --- 53 --- ID = 9.0A ns --- 30 --- RG = 6.0, VGS = 5.0V --- 26 --- RD = 5.5, See Fig. 10 Between lead, 4.5 nH 6mm (0.25in.) G from package --- 7.5 --- and center of die contact --- 800 --- VGS = 0V --- 160 --- pF VDS = 25V --- 90 --- = 1.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 17 --- --- showing the A G integral reverse --- --- 60 p-n junction diode. S --- --- 1.3 V TJ = 25C, IS = 9.0A, VGS = 0V --- 140 210 ns TJ = 25C, IF =9.0A --- 740 1100 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) VDD = 25V, starting TJ = 25C, L = 3.1mH RG = 25, IAS = 9.0A. (See Figure 12) Pulse width 300s; duty cycle 2% Uses IRL530N data and test conditions ISD 9.0A, di/dt 540A/s, VDD V(BR)DSS, This is applied for I-PAK, LS of D-PAK is measured between lead and TJ 175C center of die contact ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 2 www.irf.com IRLR/U3410PbF 100 100 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V ID , Drain-to-Source Current (A) ID , Drain-to-Source Current (A) 10 1 2.5V 20s PULSE WIDTH T J = 25C 0.1 0.1 1 10 10 2.5V 1 A 100 3.0 R DS(on) , Drain-to-Source On Resistance (Normalized) I D , Drain-to-Source Current (A) TJ = 25C TJ = 175C 10 1 V DS = 50V 20s PULSE WIDTH 4 5 6 7 8 9 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 10 A 100 Fig 2. Typical Output Characteristics 100 3 1 VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 0.1 20s PULSE WIDTH T J = 175C 0.1 0.1 VDS , Drain-to-Source Voltage (V) 2 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP TOP 10 A I D = 15A 2.5 2.0 1.5 1.0 0.5 VGS = 10V 0.0 -60 -40 -20 0 20 40 60 A 80 100 120 140 160 180 TJ , Junction Temperature (C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRLR/U3410PbF 1400 V GS , Gate-to-Source Voltage (V) 1200 800 600 Coss 400 Crss 200 0 1 10 I D = 9.0A 100 A 9 6 3 FOR TEST CIRCUIT SEE FIGURE 13 0 0 VDS , Drain-to-Source Voltage (V) 20 30 40 50 A Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) I D , Drain Current (A) ISD , Reverse Drain Current (A) 10 Q G , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage TJ = 175C 10 TJ = 25C VGS = 0V 1 0.4 0.6 0.8 1.0 1.2 VSD , Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 V DS = 80V V DS = 50V V DS = 20V 12 Ciss 1000 C, Capacitance (pF) 15 V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd A 1.4 100 10s 10 100s 1ms TC = 25C TJ = 175C Single Pulse 1 1 10ms 10 100 A 1000 VDS , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRLR/U3410PbF 20 RD V DS VGS ID , Drain Current (A) 15 D.U.T. RG + -VDD 5.0V 10 Pulse Width 1 s Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit 5 VDS 90% 0 25 50 75 100 125 150 175 TC , Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 0.10 PDM 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 15V L VDS D.U.T RG IAS 10V tp DRIVER + V - DD A 0.01 Fig 12a. Unclamped Inductive Test Circuit EAS , Single Pulse Avalanche Energy (mJ) IRLR/U3410PbF 350 TOP 300 BOTTOM ID 3.7A 6.4A 9.0A 250 200 150 100 50 0 VDD = 25V 25 V(BR)DSS 50 75 100 125 150 Starting TJ , Junction Temperature (C) tp Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K QG 12V .2F .3F 5.0 V QGS D.U.T. QGD + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform 6 IG A 175 ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRLR/U3410PbF Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + - - + RG * * * * Driver Gate Drive Period P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test D= - VDD P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS www.irf.com 7 IRLR/U3410PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WIT H ASS EMBLY LOT CODE 1234 ASS EMBLED ON WW 16, 1999 IN T HE AS S EMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO Note: "P" in as sembly line pos ition indicates "Lead-Free" IRFU120 12 916A 34 AS S EMBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR INT ERNAT IONAL RECT IFIER LOGO PART NUMBER IRFU120 12 AS S EMBLY LOT CODE 8 34 DAT E CODE P = DES IGNATES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S IT E CODE www.irf.com IRLR/U3410PbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRFU120 WIT H AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN T HE AS S EMBLY LINE "A" INT ERNAT IONAL RECT IFIER LOGO PART NUMBER IRF U120 919A 56 78 AS S EMBLY LOT CODE Note: "P" in assembly line position indicates "Lead-Free" DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR INT ERNAT IONAL RECT IFIER LOGO PART NUMBER IRFU120 56 AS S EMBLY LOT CODE www.irf.com 78 DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBLY S IT E CODE 9 IRLR/U3410PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 10 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/