IRLR/U3410PbF
HEXFET® Power MOSFET
S
D
G
VDSS = 100V
RDS(on) = 0.105Ω
ID = 17A
Description
12/7/04
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 17
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 12 A
IDM Pulsed Drain Current 60
PD @TC = 25°C Power Dissipation 79 W
Linear Derating Factor 0.53 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy 150 mJ
IAR Avalanche Current 9.0 A
EAR Repetitive Avalanche Energy 7.9 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Absolute Maximum Ratings
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.9
RθJA Junction-to-Ambient (PCB mount) ** ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110
Thermal Resistance
D-PAK
TO-252AA
I-PAK
TO-251AA
lLogic Level Gate Drive
lUltra Low On-Resistance
lSurface Mount (IRLR3410)
lStraight Lead (IRLU3410)
lAdvanced Process Technology
lFast Switching
lFully Avalanche Rated
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
The D-PAK is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for through-
hole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
PD - 95087A
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lLead-Free
IRLR/U3410PbF
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Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.122 ––– V/°C Reference to 25°C, ID = 1mA
––– ––– 0.105 VGS = 10V, ID = 10A
––– ––– 0.125 W VGS = 5.0V, ID = 10A
––– ––– 0.155 VGS = 4.0V, ID = 9.0A
VGS(th) Gate Threshold Voltage 1.0 ––– 2.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 7.7 ––– ––– S VDS = 25V, ID = 9.0A
––– ––– 25 µA VDS = 100V, VGS = 0V
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 16V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
QgTotal Gate Charge ––– ––– 34 ID = 9.0A
Qgs Gate-to-Source Charge ––– ––– 4.8 nC VDS = 80V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 20 VGS = 5.0V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 7.2 ––– VDD = 50V
trRise Time ––– 53 ––– ns ID = 9.0A
td(off) Turn-Off Delay Time ––– 30 ––– RG = 6.0Ω, VGS = 5.0V
tfFall Time ––– 26 ––– RD = 5.5Ω, See Fig. 10
Between lead,
6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 800 ––– VGS = 0V
Coss Output Capacitance ––– 160 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 90 ––– ƒ = 1.0MHz, See Fig. 5
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
nH
IGSS
S
D
G
LSInternal Source Inductance ––– 7.5 –––
RDS(on) Static Drain-to-Source On-Resistance
LDInternal Drain Inductance 4.5
IDSS Drain-to-Source Leakage Current
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 9.0A, VGS = 0V
trr Reverse Recovery Time ––– 140 210 ns TJ = 25°C, IF =9.0A
Qrr Reverse RecoveryCharge ––– 740 1100 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
A
17
60
Notes:
VDD = 25V, starting TJ = 25°C, L = 3.1mH
RG = 25Ω, IAS = 9.0A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
ISD ≤ 9.0A, di/dt ≤ 540A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
This is applied for I-PAK, LS of D-PAK is measured between lead and
center of die contact
Uses IRL530N data and test conditions
Pulse width ≤ 300µs; duty cycle ≤ 2%
IRLR/U3410PbF
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Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics
0.1
1
10
100
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
DS
A
20µs PULSE WIDTH
T = 25°C
J
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
0.1
1
10
100
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
DS
A
20µs PULSE WIDTH
T = 175°C
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
J
0.1
1
10
100
2345678910
T = 25°C
J
GS
V , Gate-to-Source Voltage (V)
D
I , Drain-to-Source Current (A)
V = 50V
20µs PULSE WIDTH
T = 175°C
J
A
DS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , Junction Temperature (°C)
R , Drain-to-Source On Resistance
DS(on)
(Normalized)
V = 10V
GS
A
I = 15A
D
IRLR/U3410PbF
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
3
6
9
12
15
0 1020304050
Q , Total Gate Charge (nC)
G
V , Gate-to-Source Voltage (V)
GS
V = 80V
V = 50V
V = 20V
DS
DS
DS
A
FOR TEST CIRCUIT
SEE FIGURE 13
I = 9.0A
D
1
10
100
0.4 0.6 0.8 1.0 1.2 1.4
T = 25°C
J
V = 0V
GS
V , Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
A
T = 175°C
J
1
10
100
1000
1 10 100 1000
V , Drain-to-Source Voltage (V)
DS
I , Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
D
DS(on)
10µs
100µs
1ms
10ms
A
T = 25°C
T = 175°C
Single Pulse
C
J
0
200
400
600
800
1000
1200
1400
1 10 100
C, Capacitance (pF)
DS
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
IRLR/U3410PbF
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Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
5.0V
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
25 50 75 100 125 150 175
0
5
10
15
20
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
IRLR/U3410PbF
6www.irf.com
QG
QGS QGD
VG
Charge
5.0 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
10V
0
50
100
150
200
250
300
350
25 50 75 100 125 150 175
J
E , Single Pulse Avalanche Energy (mJ)
AS
A
Starting T , Junction Temperature (°C)
V = 25V
I
TOP 3.7A
6.4A
BOTTOM 9.0A
DD
D
IRLR/U3410PbF
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRLR/U3410PbF
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D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
12
IN THE ASSEMBLY LINE "A"
ASS EMBL ED ON WW 16, 1999
EXAMPLE:
WIT H AS S E MB L Y
T HIS IS AN IRF R120
LOT CODE 1234
YEAR 9 = 1999
DAT E CODE
WE E K 16
PART NUMBER
LOGO
INT ERNAT IONAL
RECTIFIER
ASSEMBLY
LOT CODE
916A
IRF U120
34
YEAR 9 = 1999
DAT E CODE
OR
P = DE S I GN AT E S L E AD- F R E E
PRODUCT (OPTIONAL)
Note: "P" in as sembly line position
i ndicates "L ead- F r ee"
12 34
WE E K 16
A = ASSEMBLY SITE CODE
PART NUMBER
IRFU120
LINE A
LOGO
LOT CODE
ASSEMBLY
INTERNATIONAL
RECTIFIER
IRLR/U3410PbF
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I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
ASSEMBLY
EXAMPLE:
WITH ASSEMBLY
THIS IS AN IRFU120
YEAR 9 = 1999
DAT E CODE
LINE A
WEEK 19
IN THE ASSEMBLY LINE "A"
AS S E MBLE D ON WW 19, 1999
LOT CODE 5678
PART NUMBER
56
IRF U120
INTERNATIONAL
LOGO
RECTIFIER
LOT CODE
919A
78
Note: "P" in ass embly line
position indicates "Lead-Free"
OR
56 78
ASSEMBLY
LOT CODE
RECTIFIER
LOGO
INTERNATIONAL
IRFU120
PART NUMBER
WE E K 19
DAT E CODE
YEAR 9 = 1999
A = ASSEMBLY SITE CODE
P = DE S I GNAT E S L E AD- F R E E
PRODUCT (OPTIONAL)
IRLR/U3410PbF
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Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
