Rev. A - May 7, 1999 1
TSC80251G2D
8/16-bit Microcontroller with Serial Communication
Interfaces
1. Description
The TSC80251G2D products are derivatives of the
TEMIC Microcontroller family based on the 8/16-bit
C251 Architecture. This family of products is tailored
to 8/16-bit microcontroller applications requiring an
increased instruction throughput, a reduced operating
frequency or a larger addressable memory space. The
architecture can provide a significant code size reduction
when compiling C programs while fully preserving the
legacy of C51 assembly routines.
The TSC80251G2D derivatives are pin and software
compatible with standard 80C51/Fx/Rx/Rx+ with
extended on-chip data memory (1 Kbyte RAM) and up
to 256 Kbytes of external code and data. Additionally,
the TSC83251G2D and TSC87251G2D provide on-chip
code memory: 32 Kbytes ROM and 32 Kbytes EPROM/
OTPROM respectively.
They provide transparent enhancements to Intel’s
8xC251Sx family with an additional Synchronous Serial
Link Controller (SSLC supporting I2C, µWire and SPI
protocols), a Keyboard interrupt interface, a dedicated
Baud Rate Generator for UART, and Power Management
features.
TSC80251G2D derivatives are optimized for speed and
for low power consumption on a wide voltage range.
Note:
This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device usage, please request
the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide.
2. Typical Applications
●ISDN Terminals
●High-Speed Modems
●PABX (SOHO)
●Line Cards
●DVD ROM and Players
●Printers
●Plotters
●Scanners
●Banking Machines
●Barcode Readers
●Smart Cards Readers
●High-End Digital Monitors
●High-End Joysticks
2 Rev. A - May 7, 1999
TSC80251G2D
3. Features
●Pin and Software Compatibility with Standard 80C51
Products and 80C51Fx/Rx/Rx+
●Plug-In Replacement of Intel’s 8xC251Sx
●C251 core: Intel’s MCS®251 D-step Compliance
•40-byte register file
•Registers accessible as Bytes, Words or Dwords
•Three-stage instruction pipeline
•16-bit internal code fetch
●Enriched C51 Instruction Set
•16-bit and 32-bit ALU
•Compare and conditional jump instructions
•Expanded set of move instructions
●Linear Addressing
●1 Kbyte of On-Chip RAM
●External Memory Space (Code/Data) Programmable
from 64 Kbytes to 256 Kbytes
●TSC87251G2D: 32 Kbytes of On-Chip EPROM/
OTPROM
•SINGLE PULSE Programming Algorithm
●TSC83251G2D: 32 Kbytes of On-Chip Masked ROM
●TSC80251G2D: ROMless Version
●Four 8-bit Parallel I/O Ports (Ports 0, 1, 2 and 3 of
the standard 80C51)
●Serial I/O Port: full duplex UART (80C51
compatible) with independent Baud Rate Generator
●SSLC: Synchronous Serial Link Controller
•I2C multi-master protocol
•µWire and SPI master and slave protocols
●Three 16-bit Timers/Counters (Timers 0, 1 and 2 of
the standard 80C51)
●EWC: Event and Waveform Controller
•Compatible with Intel’s Programmable Counter
Array (PCA)
•Common 16-bit timer/counter reference with four
possible clock sources (Fosc/4, Fosc/12, Timer 1
and external input)
•Five modules, each with four programmable
modes:
- 16-bit software timer/counter
- 16-bit timer/counter capture input and
software pulse measurement
- High-speed output and 16-bit software pulse
width modulation (PWM)
- 8-bit hardware PWM without overhead
•16-bit watchdog timer/counter capability
●Secure 14-bit Hardware Watchdog Timer
●Power Management
•Power-On reset (integrated on the chip)
•Power-Off flag (cold and warm resets)
•Software programmable system clock
•Idle mode
•Power-Down mode
●Keyboard Interrupt Interface on Port 1
●Non Maskable Interrupt Input (NMI)
●Real-Time Wait States Inputs (WAIT#/AWAIT#)
●ONCE mode and full speed Real-Time In-Circuit
Emulation support (Third Party Vendors)
●High Speed Versions:
•4.5 to 5.5 V
•16 MHz and 24 MHz
•Typical operating current: 35 mA @ 24 MHz
24 mA @ 16 MHz
•Typical power-down current: 2 µA
●Low Voltage Version:
•2.7 to 5.5 V
•16 MHz
•Typical operating current: 11 mA @ 3V
•Typical power-down current: 1 µA
●Temperature Ranges:
•Commercial (0°Cto+70°C)
•Industrial (-40°Cto+85°C)
•Option: extended range (-55°C to +125°C)
●Packages:
•PDIL 40, PLCC 44 and VQFP 44
•CDIL 40 and CQPJ 44 with window
•Options: known good dice and ceramic packages
Rev. A - May 7, 1999 3
TSC80251G2D
4. Block Diagram
Figure 1. TSC80251G2D Block Diagram
16-bit Memory Code
16-bit Memory Address
16-bit Instruction Bus
24-bit Program Counter Bus
8-bit Data Bus
24-bit Data Address Bus
8-bit Internal Bus
Peripheral Interface Unit
VDD VSS VSS1
P3(A16) P1(A17)P2(A15-8) P0(AD7-0)
RST
XTAL2
XTAL1
NMI
EA#/VPP
ALE/PROG#
PSEN# Timers 0, 1 and 2
Event and Waveform
Controller
I2C/SPI/µWire
Controller
Watchdog Timer
Power Management
Clock Unit
Clock System Prescaler
Keyboard Interface
Bus Interface Unit
CPU
PORTS 0-3
Interrupt Handler
Unit
RAM
1 Kbyte
ROM
UART
Baud Rate Generator
AWAIT#
EPROM
OTPROM
32 Kbytes
VSS2
4 Rev. A - May 7, 1999
TSC80251G2D
5. Pin Description
5.1 Pinout
Figure 2. TSC80251G2D 40-pin DIP package
Figure 3. TSC80251G2D 44-pin PLCC Package
TSC80251G2D
7
8
9
10
11
12
13
14
16
15
17
18
19
20
1
2
3
4
5
634
33
32
31
30
29
28
27
25
26
24
23
22
21
40
39
38
37
36
35P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
P1.4/CEX1/SS#
P1.3/CEX0
P1.2/ECI
P1.1/T2EX
P1.0/T2 VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
PSEN#
ALE/PROG#
P2.7/A15
P2.6/A14
P2.5/A13
P3.7/A16/RD#
XTAL2
XTAL1
VSS P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12P3.6/WR#
TSC80251G2D
P1.4/CEX1/SS#
P1.3/CEX0
P1.2/ECI
P1.1/T2EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P3.7/A16/RD#
XTAL2
XTAL1
VSS
VSS2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P3.6/WR#
39
38
37
36
35
34
33
32
29
30
31
7
8
9
10
11
12
13
14
17
16
15
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
44
43
42
41
40
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
PSEN#
ALE/PROG#
NMI
P2.7/A15
P2.6/A14
P2.5/A13
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
1
Rev. A - May 7, 1999 5
TSC80251G2D
Figure 4. TSC80251G2D 44-pin VQFP Package
Table 1. TSC80251G2D Pin Assignment
DIP PLCC VQFP Name DIP PLCC VQFP Name
1 39 VSS1 23 17 VSS2
1 2 40 P1.0/T2 21 24 18 P2.0/A8
2 3 41 P1.1/T2EX 22 25 19 P2.1/A9
3 4 42 P1.2/ECI 23 26 20 P2.2/A10
4 5 43 P1.3/CEX0 24 27 21 P2.3/A11
5 6 44 P1.4/CEX1/SS# 25 28 22 P2.4/A12
6 7 1 P1.5/CEX2/MISO 26 29 23 P2.5/A13
7 8 2 P1.6/CEX3/SCL/SCK/WAIT# 27 30 24 P2.6/A14
8 9 3 P1.7/A17/CEX4/SDA/MOSI/WCLK 28 31 25 P2.7/A15
9 10 4 RST 29 32 26 PSEN#
10 11 5 P3.0/RXD 30 33 27 ALE/PROG#
12 6 AWAIT# 34 28 NMI
11 13 7 P3.1/TXD 31 35 29 EA#/VPP
12 14 8 P3.2/INT0# 32 36 30 P0.7/AD7
13 15 9 P3.3/INT1# 33 37 31 P0.6/AD6
14 16 10 P3.4/T0 34 38 32 P0.5/AD5
15 17 11 P3.5/T1 35 39 33 P0.4/AD4
16 18 12 P3.6/WR# 36 40 34 P0.3/AD3
17 19 13 P3.7/A16/RD# 37 41 35 P0.2/AD2
18 20 14 XTAL2 38 42 36 P0.1/AD1
19 21 15 XTAL1 39 43 37 P0.0/AD0
20 22 16 VSS 40 44 38 VDD
TSC80251G2D
P1.4/CEX1/SS#
P1.3/CEX0
P1.2/ECI
P1.1/T2EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P3.7/A16/RD#
XTAL2
XTAL1
VSS
VSS2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P3.6/WR#
33
32
31
30
29
28
27
26
23
24
25
1
2
3
4
5
6
7
8
11
10
9
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
PSEN#
ALE/PROG#
NMI
P2.7/A15
P2.6/A14
P2.5/A13
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
6 Rev. A - May 7, 1999
TSC80251G2D
5.2 Signals Table 2. Product Name Signal Descriptions
Signal
Name Type Description Alternate
Function
A17 O 18th Address Bit
Output to memory as 18th external address bit (A17) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15).
P1.7
A16 O 17th Address Bit
Output to memory as 17th external address bit (A16) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15).
P3.7
A15:8(1) OAddress Lines
Upper address lines for the external bus. P2.7:0
AD7:0(1) I/O Address/Data Lines
Multiplexed lower address lines and data for the external memory. P0.7:0
ALE O Address Latch Enable
ALE signals the start of an external bus cycle and indicates that valid address information
are available on lines A16/A17 and A7:0. An external latch can use ALE to demultiplex the
address from address/data bus.
AWAIT# I Real-time Asynchronous Wait States Input
When this pin is active (low level), the memory cycle is stretched until it becomes high.
When using the Product Name as a pin-for-pin replacement for a 8xC51 product, AWAIT#
can be unconnected without loss of compatibility or power consumption increase (on-chip
pull-up).
Not available on DIP package.
CEX4:0 I/O PCA Input/Output pins
CEXx are input signals for the PCA capture mode and output signals for the PCA compare
and PWM modes.
P1.7:3
EA# I External Access Enable
EA# directs program memory accesses to on-chip or off-chip code memory.
For EA#= 0, all program memory accesses are off-chip.
For EA#= 1, an access is on-chip ROM if the address is within the range of the on-chip
ROM; otherwise the access is off-chip. The value of EA# is latched at reset.
For devices without ROM on-chip, EA# must be strapped to ground.
ECI O PCA External Clock input
ECI is the external clock input to the 16-bit PCA timer. P1.2
MISO I/O SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in
slave mode, MISO outputs data to the master controller.
P1.5
MOSI I/O SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in
slave mode, MOSI receives data from the master controller.
P1.7
INT1:0# I External Interrupts 0 and 1
INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are
set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0
are set by a low level on INT1#/INT0#.
P3.3:2
NMI I Non Maskable Interrupt
Holding this pin high for 24 oscillator periods triggers an interrupt.
When using the Product Name as a pin-for-pin replacement for a 8xC51 product, NMI can
be unconnected without loss of compatibility or power consumption increase (on-chip pull-
down).
Not available on DIP package.
P0.0:7 I/O Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high impedance inputs. To avoid any paraitic current consumption, Floating
P0 inputs must be polarized to VDD or VSS.
AD7:0
Rev. A - May 7, 1999 7
TSC80251G2D
P1.0:7 I/O Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides interrupt capability
for a keyboard interface.
P2.0:7 I/O Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups. A15:8
P3.0:7 I/O Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
PROG# I Programming Pulse input
The programming pulse is applied to this input for programming the on-chip EPROM/
OTPROM.
PSEN# O Program Store Enable/Read signal output
PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in
UCONFIG0 byte (see Table 13, Page 15).
RD# O Read or 17th Address Bit (A16)
Read signal output to external data memory depending on the values of bits RD0 and RD1
in UCONFIG0 byte (see Table 13, Page 15).
P3.7
RST I Reset input to the chip
Holding this pin high for 64 oscillator periods while the oscillator is running resets the device.
The Port pins are driven to their reset conditions when a voltage greater than VIH1 is applied,
whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset by connecting
a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal
operation.
RXD I/O Receive Serial Data
RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1,
2 and 3.
P3.0
SCL I/O I2C Serial Clock
When I2C controller is in master mode, SCL outputs the serial clock to slave peripherals.
When I2C controller is in slave mode, SCL receives clock from the master controller.
P1.6
SCK I/O SPI Serial Clock
When SPI is in master mode, SCK outputs clock to the slave peripheral. When SPI is in
slave mode, SCK receives clock from the master controller.
P1.6
SDA I/O I2C Serial Data
SDA is the bidirectional I2C data line. P1.7
SS# I SPI Slave Select Input
When in Slave mode, SS# enables the slave mode. P1.4
T1:0 I/O Timer 1:0 External Clock Inputs
When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count.
T2 I/O Timer 2 Clock Input/Output
For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock-out mode,
T2 is the clock output.
P1.0
T2EX I Timer 2 External Input
In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-
reload mode, a falling edge causes the timer 2 register to be reloaded. In the up-down counter
mode, this signal determines the count direction: 1= up, 0= down.
P1.1
TXD O Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1,
2 and 3.
P3.1
VDD PWR Digital Supply Voltage
Connect this pin to +5V or +3V supply voltage.
VPP I Programming Supply Voltage
The programming supply voltage is applied to this input for programming the on-chip EPROM/
OTPROM.
Signal
Name Type Description Alternate
Function
8 Rev. A - May 7, 1999
TSC80251G2D
Note:
1. The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the Non-Page mode chip configuration. If the chip is configured in Page mode
operation, port 0 carries the lower address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data (D7:0).
VSS GND Circuit Ground
Connect this pin to ground.
VSS1 GND Secondary Ground 1
This ground is provided to reduce ground bounce and improve power supply bypassing.
Connection of this pin to ground is recommended. However, when using the TSC80251G2D
as a pin-for-pin replacement for a 8xC51 product, VSS1 can be unconnected without loss of
compatibility.
Not available on DIP package.
VSS2 GND Secondary Ground 2
This ground is provided to reduce ground bounce and improve power supply bypassing.
Connection of this pin to ground is recommended. However, when using the TSC80251G2D
as a pin-for-pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of
compatibility.
Not available on DIP package.
WAIT# I Real-time Synchronous Wait States Input
The real-time WAIT# input is enabled by setting RTWE bit in WCON (S:A7h). During bus
cycles, the external memory system can signal ‘system ready’ to the microcontroller in real
time by controlling the WAIT# input signal.
P1.6
WCLK O Wait Clock Output
The real-time WCLK output is enabled by setting RTWCE bit in WCON (S:A7h). When
enabled, the WCLK output produces a square wave signal with a period of one half the
oscillator frequency.
P1.7
WR# O Write
Write signal output to external memory. P3.6
XTAL1 I Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external
oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal
timing.
XTAL2 O Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external
oscillator is used, leave XTAL2 unconnected.
Signal
Name Type Description Alternate
Function
Rev. A - May 7, 1999 9
TSC80251G2D
6. Address Spaces
The TSC80251G2D derivatives implement four different address spaces:
●On-chip ROM program/code memory (not present in ROMless devices)
●On-chip RAM data memory
●Special Function Registers (SFRs)
●Configuration array
6.1 Program/Code Memory
The TSC83251G2D and TSC87251G2D implement 32 Kbytes of on-chip program/code memory. Figure 5 shows
the split of the internal and external program/code memory spaces. If EA# is tied to a high level, the 32-Kbyte
on-chip program memory is mapped in the lower part of segment FF: where the C251 core jumps after reset. The
rest of the program/code memory space is mapped to the external memory. If EA# is tied to a low level, the
internal program/code memory is not used and all the accesses are directed to the external memory.
The TSC83251G2D products provide the internal program/code memory in a masked ROM memory while the
TSC87251G2D products provide it in an EPROM memory. For the TSC80251G2D products, there is no internal
program/code memory and EA# must be tied to a low level.
Figure 5. Program/Code Memory Mapping
Notes:
Special care should be taken when the Program Counter (PC) increments:
1. If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper eight
bytes of the on-chip ROM (FF:7FF8h-FF:7FFFh). Because of its pipeline capability, the TSC80251G2D derivative may attempt to prefetch
code from external memory (at an address above FF:7FFFh) and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these
8 bytes does not affect Ports 0 and 2.
2. When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for compatibility with the C51 Architecture). When PC
increments beyond the end of segment FE:, it continues at the reset address FF:0000h (linearity). When PC increments beyond the end of
segment 01:, it loops to the beginning of segment 00: (this prevents from its going into the reserved area).
On-chip ROM/EPROM
Code Memory
Program/code
Segments
Program/code
External Memory Space
32 KbytesEA#= 0 EA#= 1
32 Kbytes
32 Kbytes
Reserved
64 Kbytes
128 Kbytes
FF:FFFFh
FF:8000h
FF:7FFFh
FF:0000h
FE:FFFFh
FE:0000h
FD:FFFFh
01:FFFFh
01:0000h
02:0000h
00:FFFFh
00:0000h
10 Rev. A - May 7, 1999
TSC80251G2D
6.2 Data Memory
The TSC80251G2D derivatives implement 1 Kbyte of on-chip data RAM. Figure 6 shows the split of the internal
and external data memory spaces. This memory is mapped in the data space just over the 32 bytes of registers
area (see TSC80251 Programmers’ Guide). Hence, the part of the on-chip RAM located from 20h to FFh is bit
addressable. This on-chip RAM is not accessible through the program/code memory space.
For faster computation with the on-chip ROM/EPROM code of the TSC83251G2D/TSC87251G2D, its upper 16
Kbytes are also mapped in the upper part of the region 00: if the On-Chip Code Memory Map configuration bit
is cleared (EMAP# bit in UCONFIG1 byte, see Figure 8). However, if EA# is tied to a low level, the TSC80251G2D
derivative is running as a ROMless product and the code is actually fetched in the corresponding external memory
(i.e. the upper 16 Kbytes of the lower 32 Kbytes of the segment FF:). If EMAP# bit is set, the on-chip ROM is
not accessible through the region 00:.
All the accesses to the portion of the data space with no on-chip memory mapped onto are redirected to the external
memory.
Figure 6. Data Memory Mapping
6.3 Special Function Registers
The Special Function Registers (SFRs) of the TSC80251G2D derivatives fall into the categories detailed in Table 3
to Table 11.
SFRs are placed in a reserved on-chip memory region S: which is not represented in the data memory mapping
(Figure 6). The relative addresses within S: of these SFRs are provided together with their reset values in Table 12.
They are upward compatible with the SFRs of the standard 80C51 and the Intel’s 80C251Sx family. In this table,
the C251 core registers are identified by Note 1 and are described in the TSC80251 Programmer’s Guide. The
other SFRs are described in the TSC80251G1D Design Guide. All the SFRs are bit-addressable using the C251
instruction set.
On-chip ROM/EPROM
Code MemoryData Segments
Data External
Memory Space
16 Kbytes
EA#= 0 EA#= 1
32 Kbytes
32 Kbytes
Reserved
64 Kbytes
≈47 Kbytes
FF:FFFFh
FF:8000h
FF:7FFFh
FF:0000h
FE:FFFFh
FE:0000h
FD:FFFFh
01:FFFFh
01:0000h
02:0000h
00:FFFFh
00:0420h 32 bytes reg.
RAM Data
1 Kbyte
16 Kbytes
00:C000h
00:BFFFh
EMAP#= 1
EMAP#= 0
16 Kbytes
64 Kbytes
Rev. A - May 7, 1999 11
TSC80251G2D
Table 3. C251 Core SFRs
Note:
1. These SFRs can also be accessed by their corresponding registers in the register file.
Table 4. I/O Port SFRs
Table 5. Timers SFRs
Table 6. Serial I/O Port SFRs
Table 7. SSLC SFRs
Mnemonic Name Mnemonic Name
ACC(1) Accumulator SPH(1) Stack Pointer High - MSB of SPX
B(1) B Register DPL(1) Data Pointer Low byte - LSB of DPTR
PSW Program Status Word DPH(1) Data Pointer High byte - MSB of DPTR
PSW1 Program Status Word 1 DPXL(1) Data Pointer Extended Low byte of DPX - Region
number
SP(1) Stack Pointer - LSB of SPX
Mnemonic Name Mnemonic Name
P0 Port 0 P2 Port 2
P1 Port 1 P3 Port 3
Mnemonic Name Mnemonic Name
TL0 Timer/Counter 0 Low Byte TMOD Timer/Counter 0 and 1 Modes
TH0 Timer/Counter 0 High Byte T2CON Timer/Counter 2 Control
TL1 Timer/Counter 1 Low Byte T2MOD Timer/Counter 2 Mode
TH1 Timer/Counter 1 High Byte RCAP2L Timer/Counter 2 Reload/Capture Low Byte
TL2 Timer/Counter 2 Low Byte RCAP2H Timer/Counter 2 Reload/Capture High Byte
TH2 Timer/Counter 2 High Byte WDTRST WatchDog Timer Reset
TCON Timer/Counter 0 and 1 Control
Mnemonic Name Mnemonic Name
SCON Serial Control SADDR Slave Address
SBUF Serial Data Buffer BRL Baud Rate Reload
SADEN Slave Address Mask BDRCON Baud Rate Control
Mnemonic Name Mnemonic Name
SSCON Synchronous Serial control SSADR Synchronous Serial Address
SSDAT Synchronous Serial Data SSBR Synchronous Serial Bit Rate
SSCS Synchronous Serial Control and Status
12 Rev. A - May 7, 1999
TSC80251G2D
Table 8. Event Waveform Control SFRs
Table 9. System Management SFRs
Table 10. Interrupt SFRs
Table 11. Keyboard Interface SFRs
Mnemonic Name Mnemonic Name
CCON EWC-PCA Timer/Counter Control CCAP0L EWC-PCA Compare Capture Module 0 Low Register
CMOD EWC-PCA Timer/Counter Mode CCAP1L EWC-PCA Compare Capture Module 1 Low Register
CL EWC-PCA Timer/Counter Low Register CCAP2L EWC-PCA Compare Capture Module 2 Low Register
CH EWC-PCA Timer/Counter High Register CCAP3L EWC-PCA Compare Capture Module 3 Low Register
CCAPM0 EWC-PCA Timer/Counter Mode 0 CCAP4L EWC-PCA Compare Capture Module 4 Low Register
CCAPM1 EWC-PCA Timer/Counter Mode 1 CCAP0H EWC-PCA Compare Capture Module 0 High Register
CCAPM2 EWC-PCA Timer/Counter Mode 2 CCAP1H EWC-PCA Compare Capture Module 1 High Register
CCAPM3 EWC-PCA Timer/Counter Mode 3 CCAP2H EWC-PCA Compare Capture Module 2 High Register
CCAPM4 EWC-PCA Timer/Counter Mode 4 CCAP3H EWC-PCA Compare Capture Module 3 High Register
CCAP4H EWC-PCA Compare Capture Module 4 High Register
Mnemonic Name Mnemonic Name
PCON Power Control CKRL Clock Reload
POWM Power Management WCON Synchronous Real-Time Wait State Control
Mnemonic Name Mnemonic Name
IE0 Interrupt Enable Control 0 IPL0 Interrupt Priority Control Low 0
IE1 Interrupt Enable Control 1 IPH1 Interrupt Priority Control High 1
IPH0 Interrupt Priority Control High 0 IPL1 Interrupt Priority Control Low 1
Mnemonic Name Mnemonic Name
P1IE Port 1 Input Interrupt Enable P1LS Port 1 Level Selection
P1F Port 1 Flag
Rev. A - May 7, 1999 13
TSC80251G2D
Table 12. SFR Addresses and Reset Values
Notes:
1. These registers are described in the TSC80251 Programmer’s Guide (C251 core registers).
2. In I2C and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in I2C mode and 0000 0100 in SPI mode.
3. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000 0000 in write mode.
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h CH
0000 0000 CCAP0H
0000 0000 CCAP1H
0000 0000 CCAP2H
0000 0000 CCAP3H
0000 0000 CCAP4H
0000 0000 FFh
F0h B(1)
0000 0000 F7h
E8h CL
0000 0000 CCAP0L
0000 0000 CCAP1L
0000 0000 CCAP2L
0000 0000 CCAP3L
0000 0000 CCAP4L
0000 0000 EFh
E0h ACC(1)
0000 0000 E7h
D8h CCON
00X0 0000 CMOD
00XX X000 CCAPM0
X000 0000 CCAPM1
X000 0000 CCAPM2
X000 0000 CCAPM3
X000 0000 CCAPM4
X000 0000 DFh
D0h PSW(1)
0000 0000 PSW1(1)
0000 0000 D7h
C8h T2CON
0000 0000 T2MOD
XXXX XX00 RCAP2L
0000 0000 RCAP2H
0000 0000 TL2
0000 0000 TH2
0000 0000 CFh
C0h C7h
B8h IPL0
X000 0000 SADEN
0000 0000 SPH(1)
0000 0000 BFh
B0h P3
1111 1111 IE1
XX0X XXX0 IPL1
XX0X XXX0 IPH1
XX0X XXX0 IPH0
X000 0000 B7h
A8h IE0
0000 0000 SADDR
0000 0000 AFh
A0h P2
1111 1111 WDTRST
1111 1111 WCON
XXXX XX00 A7h
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
XXX0 0000 P1LS
0000 0000 P1IE
0000 0000 P1F
0000 0000 9Fh
90h P1
1111 1111 SSBR
0000 0000 SSCON
(2) SSCS
(3) SSDAT
0000 0000 SSADR
0000 0000 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 CKRL
0000 1000 POWM
0XXX XXXX 8Fh
80h P0
1111 1111 SP(1)
0000 0111 DPL(1)
0000 0000 DPH(1)
0000 0000 DPXL(1)
0000 0001 PCON
0000 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Reserved
14 Rev. A - May 7, 1999
TSC80251G2D
6.4 Configuration Bytes
The TSC80251G2D derivatives provide user design flexibility by configuring certain operating features at device
reset. These features fall into the following categories:
•external memory interface (Page mode, address bits, programmed wait states and the address range for RD#,
WR#, and PSEN#)
•source mode/binary mode opcodes
•selection of bytes stored on the stack by an interrupt
•mapping of the upper portion of on-chip code memory to region 00:
Two user configuration bytes UCONFIG0 (see Figure 7) and UCONFIG1 (see Figure 8) provide the information.
When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The
TSC80251G2D derivatives reserve the top eight bytes of the memory address space (FF:FFF8h-FF:FFFFh) for an
external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1
at FF:FFF9h.
For the mask ROM devices, configuration information is stored in on-chip memory (see ROM Verifying). When
EA# is tied to a high level, the configuration information is retrieved from the on-chip memory instead of the
external address space and there is no restriction in the usage of the external memory.
UCONFIG0
Configuration Byte 0
Notes:
1. UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page modes. If P2.1 is cleared during the first data fetch, a
Page mode configuration is used, otherwise the subsequent fetches are performed in Non-Page mode.
2. This selection provides compatibility with the standard 80C51 hardware which is multiplexing the address LSB and the data on Port 0.
Figure 7. Configuration Byte 0
76543210
- WSA1# WSA0# XALE# RD1 RD0 PAGE# SRC
Bit Number Bit Mnemonic Description
7-
Reserved
Set this bit when writing to UCONFIG0.
6 WSA1#
Wait State A bits
Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses
(all regions except 01:).
WSA1# WSA0# Number of Wait States
00 3
01 2
10 1
11 0
5 WSA0#
4 XALE# Extend ALE bit
Clear to extend the duration of the ALE pulse from TOSC to 3·TOSC.
Set to minimize the duration of the ALE pulse to 1·TOSC.
3 RD1 Memory Signal Select bits
Specify a 18-bit, 17-bit or 16-bit external address bus and the usage of RD#, WR# and PSEN#
signals (see Table 13).
2 RD0
1 PAGE# Page Mode Select bit(1)
Clear to select the faster Page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0.
Set to select the non-Page mode(2) with A15:8 on Port 2 and A7:0/D7:0 on Port 0.
0 SRC Source Mode/Binary Mode Select bit
Clear to select the binary mode.
Set to select the source mode.
Rev. A - May 7, 1999 15
TSC80251G2D
UCONFIG1
Configuration Byte 1
Notes:
1. The CSIZE is only available on EPROM/OTPROM products.
2. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used
with code executing outside region FF:.
3. Use only for Step A compatibility; set this bit when WSB1:0# are used.
Figure 8. Configuration Byte 1
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
Note:
1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code.
76543210
CSIZE - - INTR WSB WSB1# WSB0# EMAP#
Bit Number Bit Mnemonic Description
7
CSIZE
TSC87251G2D
On-Chip Code Memory Size bit(1)
Clear to select 16 Kbytes of on-chip code memory (TSC87251G1D product).
Set to select 32 Kbytes of on-chip code memory (TSC87251G2D product).
-
TSC80251G2D
TSC83251G2D
Reserved
Set this bit when writing to UCONFIG1.
6-
Reserved
Set this bit when writing to UCONFIG1.
5-
Reserved
Set this bit when writing to UCONFIG1.
4 INTR
Interrupt Mode bit(2)
Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register).
Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the
PSW1 register).
3 WSB Wait State B bit(3)
Clear to generate one wait state for memory region 01:.
Set for no wait states for memory region 01:.
2 WSB1#
Wait State B bits
Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses
(only region 01:).
WSB1# WSB0# Number of Wait States
00 3
01 2
10 1
11 0
1 WSB0#
0 EMAP#
On-Chip Code Memory Map bit
Clear to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space (at 00:C000h-00:FFFFh).
Set not to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space.
RD1 RD0 P1.7 P3.7/RD# PSEN# WR# External Memory
0 0 A17 A16 Read signal for all external
memory locations Write signal for all external
memory locations 256 Kbytes
0 1 I/O pin A16 Read signal for all external
memory locations Write signal for all external
memory locations 128 Kbytes
1 0 I/O pin I/O pin Read signal for all external
memory locations Write signal for all external
memory locations 64 Kbytes
1 1 I/O pin Read signal for regions 00:
and 01: Read signal for regions FE:
and FF: Write signal for all external
memory locations 2×64 Kbytes(1)
Rev. A - May 7, 1999 16
TSC80251G2D
7. Instruction Set Summary
This section contains tables that summarize the instruction set. For each instruction there is a short description, its
length in bytes, and its execution time in states (one state time is equal to two system clock cycles). There are
two concurrent processes limiting the effective instruction throughput:
●Instruction Fetch
●Instruction Execution
Table 20 to Table 34 assume code executing from on-chip memory, then the CPU is fetching 16-bit at a time and
this is never limiting the execution speed.
If the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize
the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited
depending on the average size of instructions (for the considered section of the program flow). The maximum
average instruction throughput is provided by Table 14 depending on the external memory configuration (from
Page Mode to Non-Page Mode and the maximum number of wait states). If the average size of instructions is not
an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer
values.
Table 14. Minimum Number of States per Instruction for given Average Sizes
If the average execution time of the considered instructions is larger than the number of states given by Table 14,
this larger value will prevail as the limiting factor. Otherwise, the value from Table 14 must be taken. This is
providing a fair estimation of the execution speed but only the actual code execution can provide the final value.
7.1 Notation for Instruction Operands
Table 15 to Table 19 provide notation for Instruction Operands.
Table 15. Notation for Direct Addressing
Table 16. Notation for Immediate Addressing
Average size of
Instructions
(bytes)
Page Mode
(states)
Non-Page Mode (states)
0 Wait State 1 Wait State 2 Wait States 3 Wait States 4 Wait States
1123456
224681012
3 3 6 9 12 15 18
4 4 8 12162024
5 5 10 15 20 25 30
Direct Address Description C251 C51
dir8 A direct 8-bit address. This can be a memory address (00h-7Fh) or a SFR address (80h-
FFh). It is a byte (default), word or double word depending on the other operand. ✓✓
dir16 A 16-bit memory address (00:0000h-00:FFFFh) used in direct addressing. ✓
Immediate
Address Description C251 C51
#data An 8-bit constant that is immediately addressed in an instruction ✓✓
#data16 A 16-bit constant that is immediately addressed in an instruction ✓
#0data16
#1data16 A 32-bit constant that is immediately addressed in an instruction. The upper word is filled
with zeros (#0data16) or ones (#1data16). ✓
#short A constant, equal to 1, 2, or 4, that is immediately addressed in an instruction. ✓
17 Rev. A - May 7, 1999
TSC80251G2D
Table 17. Notation for Bit Addressing
Table 18. Notation for Destination in Control Instructions
Table 19. Notation for Register Operands
Direct Address Description C251 C51
bit51 A directly addressed bit (bit number= 00h-FFh) in memory or an SFR. Bits 00h-7Fh are
the 128 bits in byte locations 20h-2Fh in the on-chip RAM. Bits 80h-FFh are the 128 bits
in the 16 SFRs with addresses that end in 0h or 8h, S:80h, S:88h, S:90h,..., S:F0h, S:F8h. ✓
bit A directly addressed bit in memory locations 00:0020h-00:007Fh or in any defined SFR. ✓
Direct Address Description C251 C51
rel A signed (two’s complement) 8-bit relative address. The destination is -128 to +127 bytes
relative to the next instruction’s first byte. ✓✓
addr11 An 11-bit target address. The target is in the same 2-Kbyte block of memory as the next
instruction’s first byte. ✓
addr16 A 16-bit target address. The target can be anywhere within the same 64-Kbyte region as
the next instruction’s first byte. ✓
addr24 A 24-bit target address. The target can be anywhere within the 16-Mbyte address space. ✓
Register Description C251 C51
@Ri A memory location (00h-FFh) addressed indirectly via byte registers R0 or R1 ✓
Rn
nByte register R0-R7 of the currently selected register bank
Byte register index: n= 0-7 ✓
Rm
Rmd
Rms
m, md, ms
Byte register R0-R15 of the currently selected register file
Destination register
Source register
Byte register index: m, md, ms= 0-15 ✓
WRj
WRjd
WRjs
@WRj
@WRj +dis16
j, jd, js
Word register WR0, WR2, ..., WR30 of the currently selected register file
Destination register
Source register
A memory location (00:0000h-00:FFFFh) addressed indirectly through word register WR0-
WR30, is the target address for jump instructions.
A memory location (00:0000h-00:FFFFh) addressed indirectly through word register (WR0-
WR30) + 16-bit signed (two’s complement) displacement value
Word register index: j, jd, js= 0-30
✓
DRk
DRkd
DRks
@DRk
@DRk +dis16
k, kd, ks
Dword register DR0, DR4, ..., DR28, DR56, DR60 of the currently selected register file
Destination register
Source register
A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register DR0-
DR28, DR56 and DR60, is the target address for jump instruction
A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register (DR0-
DR28, DR56, DR60) + 16-bit (two’s complement) signed displacement value
Dword register index: k, kd, ks= 0, 4, 8..., 28, 56, 60
✓
Rev. A - May 7, 1999 18
TSC80251G2D
7.2 Size and Execution Time for Instruction Families
Table 20. Summary of Add and Subtract Instructions
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Add ADD <dest>, <src> dest opnd ←dest opnd + src opnd
Subtract SUB <dest>, <src> dest opnd ←dest opnd - src opnd
Add with Carry ADDC <dest>, <src> (A) ←(A) + src opnd + (CY)
Subtract with Borrow SUBB <dest>, <src> (A) ←(A) - src opnd - (CY)
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
ADD
A, Rn Register to ACC 1 1 2 2
A, dir8 Direct address to ACC 2 1(2) 21
(2)
A, @Ri Indirect address to ACC 1 2 2 3
A, #data Immediate data to ACC 2 1 2 1
ADD / SUB
Rmd, Rms Byte register to/from byte register 3 2 2 1
WRjd, WRjs Word register to/from word register 3 3 2 2
DRkd, DRks Dword register to/from dword register 3 5 2 4
Rm, #data Immediate 8-bit data to/from byte register 4 3 3 2
WRj, #data16 Immediate 16-bit data to/from word register 5 4 4 3
DRk, #0data16 16-bit unsigned immediate data to/from dword register 5 6 4 5
Rm, dir8 Direct address (on-chip RAM or SFR) to/from byte register 4 3(2) 32
(2)
WRj, dir8 Direct address (on-chip RAM or SFR) to/from word register 4 4 3 3
Rm, dir16 Direct address (64K) to/from byte register 5 3(3) 42
(3)
WRj, dir16 Direct address (64K) to/from word register 5 4(4) 43
(4)
Rm, @WRj Indirect address (64K) to/from byte register 4 3(3) 32
(3)
Rm, @DRk Indirect address (16M) to/from byte register 4 4(3) 33
(3)
ADDC / SUBB
A, Rn Register to/from ACC with carry 1 1 2 2
A, dir8 Direct address (on-chip RAM or SFR) to/from ACC with
carry 21
(2) 21
(2)
A, @Ri Indirect address to/from ACC with carry 1 2 2 3
A, #data Immediate data to/from ACC with carry 2 1 2 1
19 Rev. A - May 7, 1999
TSC80251G2D
Table 21. Summary of Increment and Decrement Instructions
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 22. Summary of Compare Instructions
Notes:
1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Increment INC <dest> dest opnd ←dest opnd + 1
Increment INC <dest>, <src> dest opnd ←dest opnd + src opnd
Decrement DEC <dest> dest opnd ←dest opnd - 1
Decrement DEC <dest>, <src> dest opnd ←dest opnd - src opnd
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
INC
DEC
A ACC by 1 1 1 1 1
Rn Register by 1 1 1 2 2
dir8 Direct address (on-chip RAM or SFR) by 1 2 2(2) 22
(2)
@Ri Indirect address by 1 1 3 2 4
INC
DEC
Rm, #short Byte register by 1, 2, or 4 3 2 2 1
WRj, #short Word register by 1, 2, or 4 3 2 2 1
INC DRk, #short Double word register by 1, 2, or 4 3 4 2 3
DEC DRk, #short Double word register by 1, 2, or 4 3 5 2 4
INC DPTR Data pointer by 1 1 1 1 1
Compare CMP <dest>, <src> dest opnd - src opnd
Mnemonic <dest>, <src>(2) Comments Binary Mode Source Mode
Bytes States Bytes States
CMP
Rmd, Rms Register with register 3 2 2 1
WRjd, WRjs Word register with word register 3 3 2 2
DRkd, DRks Dword register with dword register 3 5 2 4
Rm, #data Register with immediate data 4 3 3 2
WRj, #data16 Word register with immediate 16-bit data 5 4 4 3
DRk, #0data16 Dword register with zero-extended 16-bit immediate data 5 6 4 5
DRk, #1data16 Dword register with one-extended 16-bit immediate data 5 6 4 5
Rm, dir8 Direct address (on-chip RAM or SFR) with byte register 4 3(1) 32
(1)
WRj, dir8 Direct address (on-chip RAM or SFR) with word register 4 4 3 3
Rm, dir16 Direct address (64K) with byte register 5 3(2) 42
(2)
WRj, dir16 Direct address (64K) with word register 5 4(3) 43
(3)
Rm, @WRj Indirect address (64K) with byte register 4 3(2) 32
(2)
Rm, @DRk Indirect address (16M) with byte register 4 4(2) 33
(2)
Rev. A - May 7, 1999 20
TSC80251G2D
Table 23. Summary of Logical Instructions (1/2)
Notes:
1. Logical instructions that affect a bit are in Table 29.
2. A shaded cell denotes an instruction in the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Logical AND(1) ANL <dest>, <src> dest opnd ←dest opnd Λsrc opnd
Logical OR(1) ORL <dest>, <src> dest opnd ←dest opnd ςsrc opnd
Logical Exclusive OR(1) XRL <dest>, <src> dest opnd ←dest opnd ∀src opnd
Clear(1) CLR A (A) ←0
Complement(1) CPL A (A) ←∅(A)
Rotate Left RL A (A)n+1 ←(A)n, n= 0..6
(A)0←(A)7
Rotate Left Carry RLC A (A)n+1 ←(A)n, n= 0..6
(CY) ←(A)7
(A)0←(CY)
Rotate Right RR A (A)n-1 ←(A)n, n= 7..1
(A)7←(A)0
Rotate Right Carry RRC A (A)n-1 ←(A)n, n= 7..1
(CY) ←(A)0
(A)7←(CY)
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
ANL
ORL
XRL
A, Rn register to ACC 1 1 2 2
A, dir8 Direct address (on-chip RAM or SFR) to ACC 2 1(3) 21
(3)
A, @Ri Indirect address to ACC 1 2 2 3
A, #data Immediate data to ACC 2 1 2 1
dir8, A ACC to direct address 2 2(4) 22
(4)
dir8, #data Immediate 8-bit data to direct address 3 3(4) 33
(4)
Rmd, Rms Byte register to byte register 3 2 2 1
WRjd, WRjs Word register to word register 3 3 2 2
Rm, #data Immediate 8-bit data to byte register 4 3 3 2
WRj, #data16 Immediate 16-bit data to word register 5 4 4 3
Rm, dir8 Direct address (on-chip RAM or SFR) to byte register 4 3(3) 32
(3)
WRj, dir8 Direct address (on-chip RAM or SFR) to word register 4 4 3 3
Rm, dir16 Direct address (64K) to byte register 5 3(5) 42
(5)
WRj, dir16 Direct address (64K) to word register 5 4(6) 43
(6)
Rm, @WRj Indirect address (64K) to byte register 4 3(5) 32
(5)
Rm, @DRk Indirect address (16M) to byte register 4 4(5) 33
(5)
CLR A Clear ACC 1 1 1 1
CPL A Complement ACC 1 1 1 1
RL A Rotate ACC left 1 1 1 1
RLC A Rotate ACC left through CY 1 1 1 1
RR A Rotate ACC right 1 1 1 1
RRC A Rotate ACC right through CY 1 1 1 1
21 Rev. A - May 7, 1999
TSC80251G2D
Table 24. Summary of Logical Instructions (2/2)
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
Table 25. Summary of Multiply, Divide and Decimal-adjust Instructions
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
Shift Left Logical SLL <dest> <dest>0←0
<dest>n+1 ←<dest>n, n= 0..msb-1
(CY) ←<dest>msb
Shift Right Arithmetic SRA <dest> <dest>msb ←<dest>msb
<dest>n-1 ←<dest>n, n= msb..1
(CY) ←<dest>0
Shift Right Logical SRL <dest> <dest>msb ←0
<dest>n-1 ←<dest>n, n= msb..1
(CY) ←<dest>0
Swap SWAP A A3:0 A7:4
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
SLL Rm Shift byte register left through the MSB 3 2 2 1
WRj Shift word register left through the MSB 3 2 2 1
SRA Rm Shift byte register right 3 2 2 1
WRj Shift word register right 3 2 2 1
SRL Rm Shift byte register left 3 2 2 1
WRj Shift word register left 3 2 2 1
SWAP A Swap nibbles within ACC 1 2 1 2
Multiply MUL AB (B:A) ←(A)×(B)
MUL <dest>, <src> extended dest opnd ←dest opnd ×src opnd
Divide DIV AB (A) ←Quotient ((A) ⁄(B))
(B) ←Remainder ((A) ⁄(B))
Divide DIV <dest>, <src> ext. dest opnd high ←Quotient (dest opnd ⁄src opnd)
ext. dest opnd low ←Remainder (dest opnd ⁄src opnd)
Decimal-adjust ACC DA A IF [[(A)3:0 >9]∨[(AC)= 1]]
for Addition (BCD) THEN (A)3:0 ←(A)3:0 + 6 !affects CY;
IF [[(A)7:4 >9]∨[(CY)= 1]]
THEN (A)7:4 ←(A)7:4 +6
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
MUL
AB Multiply A and B 1 5 1 5
Rmd, Rms Multiply byte register and byte register 3 6 2 5
WRjd, WRjs Multiply word register and word register 3 12 2 11
DIV
AB Divide A and B 1 10 1 10
Rmd, Rms Divide byte register and byte register 3 11 2 10
WRjd, WRjs Divide word register and word register 3 21 2 20
DA A Decimal adjust ACC 1 1 1 1
Rev. A - May 7, 1999 22
TSC80251G2D
Table 26. Summary of Move Instructions (1/3)
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. Extended memory addressed is in the region specified by DPXL (reset value= 01h).
3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
Table 27. Summary of Move Instructions (2/3)
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions from the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. Apply note 3 for each dir8 operand.
Move to High word MOVH <dest>, <src> dest opnd31:16 ←src opnd
Move with Sign extension MOVS <dest>, <src> dest opnd ←src opnd with sign extend
Move with Zero extension MOVZ <dest>, <src> dest opnd ←src opnd with zero extend
Move Code MOVC A, <src> (A) ←src opnd
Move eXtended MOVX <dest>, <src> dest opnd ←src opnd
Mnemonic <dest>, <src>(2) Comments Binary Mode Source Mode
Bytes States Bytes States
MOVH DRk, #data16 16-bit immediate data into upper word of dword register 5 3 4 2
MOVS WRj, Rm Byte register to word register with sign extension 3 2 2 1
MOVZ WRj, Rm Byte register to word register with zeros extension 3 2 2 1
MOVC A, @A +DPTR Code byte relative to DPTR to ACC 1 6(3) 16
(3)
A, @A +PC Code byte relative to PC to ACC 1 6(3) 16
(3)
MOVX
A, @Ri Extended memory (8-bit address) to ACC(2) 1415
A, @DPTR Extended memory (16-bit address) to ACC(2) 13
(4) 13
(4)
@Ri, A ACC to extended memory (8-bit address)(2) 1414
@DPTR, A ACC to extended memory (16-bit address)(2) 14
(3) 14
(3)
Move(1) MOV <dest>, <src> dest opnd ←src opnd
Mnemonic <dest>, <src>(2) Comments Binary Mode Source Mode
Bytes States Bytes States
MOV
A, Rn Register to ACC 1 1 2 2
A, dir8 Direct address (on-chip RAM or SFR) to ACC 2 1(3) 21
(3)
A, @Ri Indirect address to ACC 1 2 2 3
A, #data Immediate data to ACC 2 1 2 1
Rn, A ACC to register 1 1 2 2
Rn, dir8 Direct address (on-chip RAM or SFR) to register 2 1(3) 32
(3)
Rn, #data Immediate data to register 2 1 3 2
dir8, A ACC to direct address (on-chip RAM or SFR) 2 2(3) 22
(3)
dir8, Rn Register to direct address (on-chip RAM or SFR) 2 2(3) 33
(3)
dir8, dir8 Direct address to direct address (on-chip RAM or SFR) 3 3(4) 33
(4)
dir8, @Ri Indirect address to direct address (on-chip RAM or SFR) 2 3(3) 34
(3)
dir8, #data Immediate data to direct address (on-chip RAM or SFR) 3 3(3) 33
(3)
@Ri, A ACC to indirect address 1 3 2 4
@Ri, dir8 Direct address (on-chip RAM or SFR) to indirect address 2 3(3) 34
(3)
@Ri, #data Immediate data to indirect address 2 3 3 4
DPTR, #data16 Load Data Pointer with a 16-bit constant 3 2 3 2
23 Rev. A - May 7, 1999
TSC80251G2D
Table 28. Summary of Move Instructions (3/3)
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions unique to the C251 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states).
Move(1) MOV <dest>, <src> dest opnd ←src opnd
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
MOV
Rmd, Rms Byte register to byte register 3 2 2 1
WRjd, WRjs Word register to word register 3 2 2 1
DRkd, DRks Dword register to dword register 3 3 2 2
Rm, #data Immediate 8-bit data to byte register 4 3 3 2
WRj, #data16 Immediate 16-bit data to word register 5 3 4 2
DRk, #0data16 zero-ext 16bit immediate data to dword register 5 5 4 4
DRk, #1data16 one-ext 16bit immediate data to dword register 5 5 4 4
Rm, dir8 Direct address (on-chip RAM or SFR) to byte register 4 3(3) 32
(3)
WRj, dir8 Direct address (on-chip RAM or SFR) to word register 4 4 3 3
DRk, dir8 Direct address (on-chip RAM or SFR) to dword register 4 6 3 5
Rm, dir16 Direct address (64K) to byte register 5 3(4) 42
(4)
WRj, dir16 Direct address (64K) to word register 5 4(5) 43
(5)
DRk, dir16 Direct address (64K) to dword register 5 6(6) 45
(6)
Rm, @WRj Indirect address (64K) to byte register 4 3(4) 32
(4)
Rm, @DRk Indirect address (16M) to byte register 4 4(4) 33
(4)
WRjd, @WRjs Indirect address (64K) to word register 4 4(5) 33
(5)
WRj, @DRk Indirect address (16M) to word register 4 5(5) 34
(5)
dir8, Rm Byte register to direct address (on-chip RAM or SFR) 4 4(3) 33
(3)
dir8, WRj Word register to direct address (on-chip RAM or SFR) 4 5 3 4
dir8, DRk Dword register to direct address (on-chip RAM or SFR) 4 7 3 6
dir16, Rm Byte register to direct address (64K) 5 4(4) 43
(4)
dir16, WRj Word register to direct address (64K) 5 5(5) 44
(5)
dir16, DRk Dword register to direct address (64K) 5 7(6) 46
(6)
@WRj, Rm Byte register to indirect address (64K) 4 4(4) 33
(4)
@DRk, Rm Byte register to indirect address (16M) 4 5(4) 34
(4)
@WRjd, WRjs Word register to indirect address (64K) 4 5(5) 34
(5)
@DRk, WRj Word register to indirect address (16M) 4 6(5) 35
(5)
Rm, @WRj +dis16 Indirect with 16-bit displacement (64K) to byte register 5 6(4) 45
(4)
WRj, @WRj +dis16 Indirect with 16-bit displacement (64K) to word register 5 7(5) 46
(5)
Rm, @DRk +dis24 Indirect with 16-bit displacement (16M) to byte register 5 7(4) 46
(4)
WRj, @WRj +dis24 Indirect with 16-bit displacement (16M) to word register 5 8(5) 47
(5)
@WRj +dis16, Rm Byte register to indirect with 16-bit displacement (64K) 5 6(4) 45
(4)
@WRj +dis16, WRj Word register to indirect with 16-bit displacement (64K) 5 7(5) 46
(5)
@DRk +dis24, Rm Byte register to indirect with 16-bit displacement (16M) 5 7(4) 46
(4)
@DRk +dis24, WRj Word register to indirect with 16-bit displacement (16M) 5 8(5) 47
(5)
Rev. A - May 7, 1999 24
TSC80251G2D
Table 29. Summary of Bit Instructions
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Clear Bit CLR <dest> dest opnd ←0
Set Bit SETB <dest> dest opnd ←1
Complement Bit CPL <dest> dest opnd ←∅bit
AND Carry with Bit ANL CY, <src> (CY) ←(CY) ∧src opnd
AND Carry with Complement of Bit ANL CY, /<src> (CY) ←(CY) ∧∅src opnd
OR Carry with Bit ORL CY, <src> (CY) ←(CY) ∨src opnd
OR Carry with Complement of Bit ORL CY, /<src> (CY) ←(CY) ∨∅src opnd
Move Bit to Carry MOV CY, <src> (CY) ←src opnd
Move Bit from Carry MOV <dest>, CY dest opnd ←(CY)
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
CLR
CY Clear carry 1 1 1 1
bit51 Clear direct bit 2 2(3) 22
(3)
bit Clear direct bit 4 4(3) 33
(3)
SETB
CY Set carry 1 1 1 1
bit51 Set direct bit 2 2(3) 22
(3)
bit Set direct bit 4 4(3) 33
(3)
CPL
CY Complement carry 1 1 1 1
bit51 Complement direct bit 2 2(3) 22
(3)
bit Complement direct bit 4 4(3) 33
(3)
ANL
CY, bit51 And direct bit to carry 2 1(2) 21
(2)
CY, bit And direct bit to carry 4 3(2) 32
(2)
CY, /bit51 And complemented direct bit to carry 2 1(2) 21
(2)
CY, /bit And complemented direct bit to carry 4 3(2) 32
(2)
ORL
CY, bit51 Or direct bit to carry 2 1(2) 21
(2)
CY, bit Or direct bit to carry 4 3(2) 32
(2)
CY, /bit51 Or complemented direct bit to carry 2 1(2) 21
(2)
CY, /bit Or complemented direct bit to carry 4 3(2) 32
(2)
MOV
CY, bit51 Move direct bit to carry 2 1(2) 21
(2)
CY, bit Move direct bit to carry 4 3(2) 32
(2)
bit51, CY Move carry to direct bit 2 2(3) 22
(3)
bit, CY Move carry to direct bit 4 4(3) 33
(3)
25 Rev. A - May 7, 1999
TSC80251G2D
Table 30. Summary of Exchange, Push and Pop Instructions
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 31. Summary of Conditional Jump Instructions (1/2)
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.
Exchange bytes XCH A, <src> (A) ↔src opnd
Exchange Digit XCHD A, <src> (A)3:0 ↔src opnd3:0
Push PUSH <src> (SP) ←(SP) +1; ((SP)) ←src opnd;
(SP) ←(SP) + size (src opnd) - 1
Pop POP <dest> (SP) ←(SP) - size (dest opnd) + 1;
dest opnd ←((SP)); (SP) ←(SP) -1
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
XCH
A, Rn ACC and register 1 3 2 4
A, dir8 ACC and direct address (on-chip RAM or SFR) 2 3(3) 23
(3)
A, @Ri ACC and indirect address 1 4 2 5
XCHD A, @Ri ACC low nibble and indirect address (256 bytes) 1 4 2 5
PUSH
dir8 Push direct address onto stack 2 2(2) 22
(2)
#data Push immediate data onto stack 4 4 3 3
#data16 Push 16-bit immediate data onto stack 5 5 4 5
Rm Push byte register onto stack 3 4 2 3
WRj Push word register onto stack 3 5 2 4
DRk Push double word register onto stack 3 9 2 8
POP
dir8 Pop direct address (on-chip RAM or SFR) from stack 2 3(2) 23
(2)
Rm Pop byte register from stack 3 3 2 2
WRj Pop word register from stack 3 5 2 4
DRk Pop double word register from stack 3 9 2 8
Jump conditional on status Jcc rel (PC) ←(PC) + size (instr);
IF [cc] THEN (PC) ←(PC) + rel
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
JC rel Jump if carry 2 1/4(3) 2 1/4(3)
JNC rel Jump if not carry 2 1/4(3) 2 1/4(3)
JE rel Jump if equal 3 2/5(3) 2 1/4(3)
JNE rel Jump if not equal 3 2/5(3) 2 1/4(3)
JG rel Jump if greater than 3 2/5(3) 2 1/4(3)
JLE rel Jump if less than, or equal 3 2/5(3) 2 1/4(3)
JSL rel Jump if less than (signed) 3 2/5(3) 2 1/4(3)
JSLE rel Jump if less than, or equal (signed) 3 2/5(3) 2 1/4(3)
JSG rel Jump if greater than (signed) 3 2/5(3) 2 1/4(3)
JSGE rel Jump if greater than or equal (signed) 3 2/5(3) 2 1/4(3)
Rev. A - May 7, 1999 26
TSC80251G2D
Table 32. Summary of Conditional Jump Instructions (2/2)
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add 5 if it addresses a Peripheral SFR.
6. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.
Jump if bit JB <src>, rel (PC) ←(PC) + size (instr);
IF [src opnd= 1] THEN (PC) ←(PC) + rel
Jump if not bit JNB <src>, rel (PC) ←(PC) + size (instr);
IF [src opnd= 0] THEN (PC) ←(PC) + rel
Jump if bit and clear JBC <dest>, rel (PC) ←(PC) + size (instr);
IF [dest opnd= 1] THEN
dest opnd ←0
(PC) ←(PC) + rel
Jump if accumulator is zero JZ rel (PC) ←(PC) + size (instr);
IF [(A)= 0] THEN (PC) ←(PC) + rel
Jump if accumulator is not zero JNZ rel (PC) ←(PC) + size (instr);
IF [(A) ≠0] THEN (PC) ←(PC) + rel
Compare and jump if not equal CJNE <src1>, <src2>, rel (PC) ←(PC) + size (instr);
IF [src opnd1 < src opnd2] THEN (CY) ←1
IF [src opnd1 ≥src opnd2] THEN (CY) ←0
IF [src opnd1 ≠src opnd2] THEN (PC) ←(PC) + rel
Decrement and jump if not zero DJNZ <dest>, rel (PC) ←(PC) + size (instr); dest opnd ←dest opnd -1;
IF [ϕ(Z)] THEN (PC) ←(PC) + rel
Mnemonic <dest>, <src>(1) Comments Binary Mode(2) Source Mode(2)
Bytes States Bytes States
JB bit51, rel Jump if direct bit is set 3 2/5(3)(6) 3 2/5(3)(6)
bit, rel Jump if direct bit of 8-bit address location is set 5 4/7(3)(6) 4 3/6(3)(6)
JNB bit51, rel Jump if direct bit is not set 3 2/5(3)(6) 3 2/5(3)(6)
bit, rel Jump if direct bit of 8-bit address location is not set 5 4/7(3)(6) 4 3/6(3)
JBC bit51, rel Jump if direct bit is set & clear bit 3 4/7(5)(6) 3 4/7(5)(6)
bit, rel Jump if direct bit of 8-bit address location is set and clear 5 7/10(5)(6) 4 6/9(5)(6)
JZ rel Jump if ACC is zero 2 2/5(6) 2 2/5(6)
JNZ rel Jump if ACC is not zero 2 2/5(6) 2 2/5(6)
CJNE
A, dir8, rel Compare direct address to ACC and jump if not equal 3 2/5(3)(6) 3 2/5(3)(6)
A, #data, rel Compare immediate to ACC and jump if not equal 3 2/5(6) 3 2/5(6)
Rn, #data, rel Compare immediate to register and jump if not equal 3 2/5(6) 4 3/6(6)
@Ri, #data, rel Compare immediate to indirect and jump if not equal 3 3/6(6) 4 4/7(6)
DJNZ Rn, rel Decrement register and jump if not zero 2 2/5(6) 3 3/6(6)
dir8, rel Decrement direct address and jump if not zero 3 3/6(4)(6) 3 3/6(4)(6)
27 Rev. A - May 7, 1999
TSC80251G2D
Table 33. Summary of unconditional Jump Instructions
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 3 to the number of states if the destination address is external.
Table 34. Summary of Call and Return Instructions
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 5 to the number of states if INTR= 1.
Absolute jump AJMP <src> (PC) ←(PC) +2; (PC)10:0 ←src opnd
Extended jump EJMP <src> (PC) ←(PC) + size (instr); (PC)23:0 ←src opnd
Long jump LJMP <src> (PC) ←(PC) + size (instr); (PC)15:0 ←src opnd
Short jump SJMP rel (PC) ←(PC) +2; (PC) ←(PC) +rel
Jump indirect JMP @A +DPTR (PC)23:16 ←FFh; (PC)15:0 ←(A) + (DPTR)
No operation NOP (PC) ←(PC) +1
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
AJMP addr11 Absolute jump 2 3(2)(3) 23
(2)(3)
EJMP addr24 Extended jump 5 6(2)(4) 45
(2)(4)
@DRk Extended jump (indirect) 3 7(2)(4) 26
(2)(4)
LJMP @WRj Long jump (indirect) 3 6(2)(4) 25
(2)(4)
addr16 Long jump (direct address) 3 5(2)(4) 35
(2)(4)
SJMP rel Short jump (relative address) 2 4(2)(4) 24
(2)(4)
JMP @A +DPTR Jump indirect relative to the DPTR 1 5(2)(4) 15
(2)(4)
NOP No operation (Jump never) 1 1 1 1
Absolute call ACALL <src> (PC) ←(PC) +2; push (PC)15:0;
(PC)10:0 ←src opnd
Extended call ECALL <src> (PC) ←(PC) + size (instr); push (PC)23:0;
(PC)23:0 ←src opnd
Long call LCALL <src> (PC) ←(PC) + size (instr); push (PC)15:0;
(PC)15:0 ←src opnd
Return from subroutine RET pop (PC)15:0
Extended return from subroutine ERET pop (PC)23:0
Return from interrupt RETI IF [INTR= 0] THEN pop (PC)15:0
IF [INTR= 1] THEN pop (PC)23:0; pop (PSW1)
Trap interrupt TRAP (PC) ←(PC) + size (instr);
IF [INTR= 0] THEN push (PC)15:0
IF [INTR= 1] THEN push (PSW1); push (PC)23:0
Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode
Bytes States Bytes States
ACALL addr11 Absolute subroutine call 2 9(2)(3) 29
(2)(3)
ECALL @DRk Extended subroutine call (indirect) 3 14(2)(3) 213
(2)(3)
addr24 Extended subroutine call 5 14(2)(3) 413
(2)(3)
LCALL @WRj Long subroutine call (indirect) 3 10(2)(3) 29
(2)(3)
addr16 Long subroutine call 3 9(2)(3) 39
(2)(3)
RET Return from subroutine 1 7(2) 17
(2)
ERET Extended subroutine return 3 9(2) 28
(2)
RETI Return from interrupt 1 7(2)(4) 17
(2)(4)
TRAP Jump to the trap interrupt vector 2 12(4) 111
(4)
Rev. A - May 7, 1999 28
TSC80251G2D
8. Programming and Verifying Non-Volatile Memory
8.1 Internal Features
The internal non-volatile memory of the TSC80251G2D derivatives contains five different areas:
●Code Memory
●Configuration Bytes
●Lock Bits
●Encryption Array
●Signature Bytes
8.1.1 EPROM/OTPROM Devices
All the internal non-volatile memory but the Signature Bytes of the TSC87251G2D products is made of EPROM
cells. The Signature Bytes of the TSC87251G2D products are made of Mask ROM.
The TSC87251G2D products are programmed and verified in the same manner as TEMIC’s TSC87251G1A, using
a SINGLE-PULSE algorithm, which programs at VPP= 12.75V using only one 100 µs pulse per byte. This results
in a programming time of less than 10 seconds for the 32 Kbytes on-chip code memory.
The EPROM of the TSC87251G2D products in Window package is erasable by Ultra-Violet radiation(1) (UV).
UV erasure set all the EPROM memory cells to one and allows a reprogramming. The quartz window must be
covered with an opaque label(2) when the device is in operation. This is not so much to protect the EPROM array
from inadvertent erasure, as to protect the RAM and other on-chip logic. Allowing light to impinge on the silicon
die during device operation may cause a logical malfunction.
The TSC87251G2D products in plastic packages are One Time Programmable (OTP). Then an EPROM cell cannot
be reset by UV once programmed to zero.
Notes:
1. The recommended erasure procedure is exposure to ultra-violet light (at 2537 Å) to an integrated dose of at least 20 W-sec/cm2. Exposing
the EPROM to an ultra-violet lamp of 12000 µW/cm2rating for 30 minutes should be sufficient.
2. Erasure of the EPROM begins to occur when the chip is exposed to light wavelength shorter than 4000 Å. Since sunlight and fluorescent
light have wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room-level
fluorescent lighting) could cause inadvertent erasure.
8.1.2 Mask ROM Devices
All the internal non-volatile memory of TSC83251G2D products is made of Mask ROM cells. They can only be
verified by the user, using the same algorithm as the EPROM/OTPROM devices.
8.1.3 ROMless Devices
The TSC80251G2D products do not include on-chip Configuration Bytes, Code Memory and Encryption Array.
They only include Signature Bytes made of Mask ROM cells which can be read using the same algorithm as the
EPROM/OTPROM devices.
8.2 Security Features
In some microcontrollers applications, it is desirable that the user’s program code be secured from unauthorized
access. The TSC83251G2D and TSC87251G2D offer two kinds of protection for program code stored in the on-
chip array:
●Program code in the on-chip Code Memory is encrypted when read out for verification if the Encryption Array is
programmed.
●A three-level lock bit system restricts external access to the on-chip code memory.
29 Rev. A - May 7, 1999
TSC80251G2D
8.2.1 Lock Bit System
The TSC87251G2D products implement 3 levels of security for User’s program as described in Table 35. The
TSC83251G2D products implement only the first level of security.
Level 0 is the level of an erased part and does not enable any security features.
Level 1 locks the programming of the User’s internal Code Memory, the Configuration Bytes and the Encryption
Array.
Level 2 locks the verifying of the User’s internal Code Memory. It is always possible to verify the Configuration
Bytes and the Lock Bits. It is never possible to verify the Encryption Array.
Level 3 locks the external execution.
Table 35. Lock Bits Programming
Notes:
1. Returns encrypted data if Encryption Array is programmed.
2. Returns non encrypted data.
3. x means don’t care. Level 2 always enables level 1, and level 3 always enables levels 1 and 2.
The security level may be verified according to Table 36.
Table 36. Lock Bits Verifying
Note:
1. x means don’t care.
8.2.2 Encryption Array
The TSC83251G2D and TSC87251G2D products include a 128-byte Encryption Array located in non-volatile
memory outside the memory address space. During verification of the on-chip code memory, the seven low-order
address bits also address the Encryption Array. As the byte of the code memory is read, it is exclusive-NOR’ed
(XNOR) with the key byte from the Encryption Array. If the Encryption Array is not programmed (still all 1s),
the user program code is placed on the data bus in its original, unencrypted form. If the Encryption Array is
programmed with key bytes, the user program code is encrypted and cannot be used without knowledge of the
key byte sequence.
To preserve the secrecy of the encryption key byte sequence, the Encryption Array can not be verified.
Cautions:
1. When a MOVC instruction is executed, the content of the ROM is not encrypted. In order to fully protect the user program code, the lock
bit level 1 (see Table 35) must always be set when encryption is used.
2. If the encryption feature is implemented, the portion of the on-chip code memory that does not contain program code should be filled with
“random” byte values to prevent the encryption key sequence from being revealed.
Level Lock bits
LB[2:0] Internal
Execution External
Execution Verification Programming External
PROM read
(MOVC)
0 000 Enable Enable Enable(1) Enable Enable(2)
1 001 Enable Enable Enable(1) Disable Disable
2 01x(3) Enable Enable Disable Disable Disable
3 1xx(3) Enable Disable Disable Disable Disable
Level Lock bits Data(1)
0 xxxxx000
1 xxxxx001
2 xxxxx01x
3 xxxxx1xx
Rev. A - May 7, 1999 30
TSC80251G2D
8.3 Signature Bytes
The TSC80251G2D derivatives contain factory-programmed Signature Bytes. These bytes are located in non-volatile
memory outside the memory address space at 30h, 31h, 60h and 61h. To read the Signature Bytes, perform the
procedure described in section 8.5, using the verify signature mode (see Table 39). Signature byte values are listed
in Table 37.
Table 37. Signature Bytes (Electronic ID)
8.4 Programming Algorithm
Figure 9 shows the hardware setup needed to program the TSC87251G2D EPROM/OTPROM areas:
●The chip has to be put under reset and maintained in this state until the completion of the programming sequence.
●PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
●Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in
this state until the completion of the programming sequence (see below).
●The voltage on the EA# pin must be set to VDD.
●The programming mode is selected according to the code applied on Port 0 (see Table 38). It has to be applied
until the completion of this programming operation.
●The programming address is applied on Ports 1 and 3 which are respectively the Most Significant Byte (MSB)
and the Least Significant Byte (LSB) of the address.
●The programming data are applied on Port 2.
●The EPROM Programming is done by raising the voltage on the EA# pin to VPP, then by generating a low
level pulse on ALE/PROG# pin.
●The voltage on the EA# pin must be lowered to VDD before completing the programming operation.
●It is possible to alternate programming and verifying operation (See Paragraph 8.5). Please make sure the
voltage on the EA# pin has actually been lowered to VDD before performing the verifying operation.
●PSEN# and the other control signals have to be released to complete a sequence of programming operations
or a sequence of programming and verifying operations.
Signature Address Signature Data
Vendor TEMIC 30h 58h
Architecture C251 31h 40h
Memory 32 Kbytes EPROM or OTPROM 60h F7h
32 Kbytes MaskROM or ROMless 77h
Revision TSC80251G2D derivative 61h FDh
31 Rev. A - May 7, 1999
TSC80251G2D
Figure 9. Setup for Programming
Table 38. Programming Modes
Notes:
1. Signature Bytes are not user-programmable.
2. The ALE/PROG# pulse waveform is shown in Figure 31 page 54.
8.5 Verify Algorithm
Figure 10 shows the hardware setup needed to verify the TSC87251G2D EPROM/OTPROM or TSC83251G2D
ROM areas:
●The chip has to be put under reset and maintained in this state until the completion of the verifying sequence.
●PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
●Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in
this state until the completion of the verifying sequence (see below).
●The voltage on the EA# pin must be set to VDD and ALE must be set to a high level.
●The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion
of this verifying operation.
●The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address.
●Then device is driving the data on Port 2.
●It is possible to alternate programming and verification operation (see Paragraph 8.4). Please make sure the
voltage on the EA# pin has actually been lowered to VDD before performing the verifying operation.
●PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a
sequence of programming and verifying operations.
ROM Area(1) RST EA#/VPP PSEN# ALE/PROG#(2) P0 P2 P1(MSB) P3(LSB)
On-chip Code Memory 1 VPP 0 1 Pulse 68h Data 16-bit Address
0000h-7FFFh (32 Kbytes)
Configuration Bytes 1 VPP 0 1 Pulse 69h Data CONFIG0: FFF8h
CONFIG1: FFF9h
Lock Bits 1 VPP 0 1 Pulse 6Bh X LB0: 0001h
LB1: 0002h
LB2: 0003h
Encryption Array 1 VPP 0 1 Pulse 6Ch Data 0000h-007Fh
VDD
PSEN#
ALE/PROG#
EA#/VPP
XTAL1
VDD
4 to 12 MHz
RST
VPP
100 µs pulses
VSS/VSS1/VSS2
Mode
VDD
A[7:0]
A[14:8]
Data
P0[7:0]
P3[7:0]
P1[7:0]
P2[7:0]
TSC87251G2D
Rev. A - May 7, 1999 32
TSC80251G2D
Table 39. Verifying Modes
Note:
1. To preserve the secrecy of on-chip code memory when encrypted, the Encryption Array can not be verified.
Figure 10. Setup for Verifying
ROM Area(1) RST EA#/VPP PSEN# ALE/PROG# P0 P2 P1(MSB) P3(LSB)
On-chip code memory 1 1 0 1 28h Data 16-bit Address
0000h-7FFFh (32 Kbytes)
Configuration Bytes 1 1 0 1 29h Data CONFIG0: FFF8h
CONFIG1: FFF9h
Lock Bits 1 1 0 1 2Bh Data 0000h
Signature Bytes 1 1 0 1 29h Data 0030h, 0031h, 0060h, 0061h
VDD
PSEN#
ALE/PROG#
EA#/VPP
XTAL1
VDD
4 to 12 MHz
RST
VSS/VSS1/VSS2
Mode
VDD
A[7:0]
A[14:8]
P0[7:0]
P3[7:0]
P1[7:0]
TSC8x251G2D
P2[7:0] Data
Rev. A - May 7, 1999 33
TSC80251G2D
9. Absolute Maximum Rating and Operating Conditions
9.1 Absolute Maximum Rating
Table 40. Absolute Maximum Ratings
9.2 Operating Conditions
Table 41. Operating Conditions
Note:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond
the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
●Storage Temperature.........................
●Voltage on any other Pin to VSS....
●IOL per I/O Pin .................................
●Power Dissipation .............................
-65 to +150°C
-0.5 to +6.5 V
15 mA
1.5 W
●Ambient Temperature Under Bias
Commercial .......................................
Industrial............................................
●VDD
High Speed versions.........................
Low Voltage versions.......................
0to+70°C
-40 to +85°C
4.5 to 5.5 V
2.7 to 5.5 V
34 Rev. A - May 7, 1999
TSC80251G2D
10. DC Characteristics - Commercial & Industrial
10.1 DC Characteristics: High Speed versions - Commercial & Industrial
Table 42. DC Characteristics; VDD= 4.5 to 5.5 V, TA= -40 to +85°C
Symbol Parameter Min Typical(4) Max Units Test Conditions
VIL Input Low Voltage
(except EA#, SCL, SDA) -0.5 0.2·VDD - 0.1 V
VIL1(5) Input Low Voltage
(SCL, SDA) -0.5 0.3·VDD V
VIL2 Input Low Voltage
(EA#) 0 0.2·VDD - 0.3 V
VIH Input high Voltage
(except XTAL1, RST, SCL, SDA) 0.2·VDD + 0.9 VDD + 0.5 V
VIH1(5) Input high Voltage
(XTAL1, RST, SCL, SDA) 0.7·VDD VDD + 0.5 V
VOL Output Low Voltage
(Ports 1, 2, 3) 0.3
0.45
1.0
VI
OL= 100 µA(1)(2)
IOL= 1.6 mA(1)(2)
IOL= 3.5 mA(1)(2)
VOL1 Output Low Voltage
(Ports 0, ALE, PSEN#, Port 2 in Page
Mode during External Address)
0.3
0.45
1.0
VI
OL= 200 µA(1)(2)
IOL= 3.2 mA(1)(2)
IOL= 7.0 mA(1)(2)
VOH Output high Voltage
(Ports 1, 2, 3, ALE, PSEN#) VDD - 0.3
VDD - 0.7
VDD - 1.5
VI
OH= -10 µA(3)
IOH= -30 µA(3)
IOH= -60 µA(3)
VOH1 Output high Voltage
(Port 0, Port 2 in Page Mode during
External Address)
VDD - 0.3
VDD - 0.7
VDD - 1.5
VI
OH= -200 µA
IOH= -3.2 mA
IOH= -7.0 mA
VRET VDD data retention limit 1.8 V
IIL0 Logical 0 Input Current
(Ports 1, 2, 3) -50 µAV
IN= 0.45 V
IIL1 Logical 1 Input Current
(NMI) +50 µAV
IN=V
DD
ILI Input Leakage Current
(Port 0) ±10 µA 0.45V<V
IN <V
DD
ITL Logical 1-to-0 Transition Current
(Ports 1, 2, 3 - AWAIT#) - 650 µAV
IN= 2.0 V
RRST RST Pull-Down Resistor 40 110 225 kΩ
CIO Pin Capacitance 10 pF TA=25°C
I
DD Operating Current 20
25
35
25
30
40
mA FOSC=12MHz
F
OSC=16MHz
F
OSC=24MHz
I
DL Idle Mode Current 5
6.5
9.5
6
8
12
mA FOSC=12MHz
F
OSC=16MHz
F
OSC=24MHz
I
PD Power-Down Current 2 20 µAV
RET <V
DD < 5.5 V
VPP Programming supply voltage 12.5 13 V TA=0to+40°C
I
PP Programming supply current 75 mA TA=0to+40°C
Rev. A - May 7, 1999 35
TSC80251G2D
Notes:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:.............................................10 mA
Maximum IOL per 8-bit port: Port 0.................26 mA
Ports 1-3............15 mA
Maximum Total IOL for all: Output Pins .......71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and
3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In
applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing.
4. Typical values are obtained using VDD=5VandTA=25°C. They are not tested and there is not guarantee on these values.
5. The input threshold voltage of SCL and SDA meets the I2C specification, so an input voltage below 0.3·VDD will be recognized as a logic
0 while an input voltage above 0.7·VDD will be recognized as a logic 1.
Note:
1. The clock prescaler is not used: FOSC=F
XTAL.
Figure 11. IDD/IDL Versus Frequency; VDD= 4.5 to 5.5 V
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
40
30
20
10
0
IDD/IDL (mA)
Frequency at XTAL(1) (MHz)
2 4 6 8 10 12 14 16 18 20 22 24
36 Rev. A - May 7, 1999
TSC80251G2D
10.2 DC Characteristics: Low Voltage versions - Commercial & Industrial
Table 43. DC Characteristics; VDD= 2.7 to 5.5 V, TA= -40 to +85°C
Symbol Parameter Min Typical(4) Max Units Test Conditions
VIL Input Low Voltage
(except EA#, SCL, SDA) -0.5 0.2·VDD - 0.1 V
VIL1(5) Input Low Voltage
(SCL, SDA) -0.5 0.3·VDD V
VIL2 Input Low Voltage
(EA#) 0 0.2·VDD - 0.3 V
VIH Input high Voltage
(except XTAL1, RST, SCL, SDA) 0.2·VDD + 0.9 VDD + 0.5 V
VIH1(5) Input high Voltage
(XTAL1, RST, SCL, SDA) 0.7·VDD VDD + 0.5 V
VOL Output Low Voltage
(Ports 1, 2, 3) 0.45 V IOL= 0.8 mA(1)(2)
VOL1 Output Low Voltage
(Ports 0, ALE, PSEN#, Port 2 in Page
Mode during External Address)
0.45 V IOL= 1.6 mA(1)(2)
VOH Output high Voltage
(Ports 1, 2, 3, ALE, PSEN#) 0.9·VDD VI
OH= -10 µA(3)
VOH1 Output high Voltage
(Port 0, Port 2 in Page Mode during
External Address)
0.9·VDD VI
OH= -40 µA
VRET VDD data retention limit 1.8 V
IIL0 Logical 0 Input Current
(Ports 1, 2, 3 - AWAIT#) -50 µAV
IN= 0.45 V
IIL1 Logical 1 Input Current
(NMI) +50 µAV
IN=V
DD
ILI Input Leakage Current
(Port 0) ±10 µA 0.45 V < VIN <V
DD
ITL Logical 1-to-0 Transition Current
(Ports 1, 2, 3) - 650 µAV
IN= 2.0 V
RRST RST Pull-Down Resistor 40 110 225 kΩ
CIO Pin Capacitance 10 pF TA=25°C
I
DD Operating Current 4
8
9
11
8
11
12
14
mA 5 MHz, VDD < 3.6 V
10 MHz, VDD < 3.6 V
12 MHz, VDD < 3.6 V
16 MHz, VDD < 3.6 V
IDL Idle Mode Current 0.5
1.5
2
3
1
4
5
7
mA 5 MHz, VDD < 3.6 V
10 MHz, VDD < 3.6 V
12 MHz, VDD < 3.6 V
16 MHz, VDD < 3.6 V
IPD Power-Down Current 1 10 µAV
RET <V
DD < 3.6 V
Rev. A - May 7, 1999 37
TSC80251G2D
Notes:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:.............................................10 mA
Maximum IOL per 8-bit port: Port 0.................26 mA
Ports 1-3............15 mA
Maximum Total IOL for all: Output Pins .......71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and
3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In
applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing.
4. Typical values are obtained using VDD=3VandTA=25°C. They are not tested and there is not guarantee on these values.
5. The input threshold voltage of SCL and SDA meets the I2C specification, so an input voltage below 0.3·VDD will be recognized as a logic
0 while an input voltage above 0.7·VDD will be recognized as a logic 1.
Note:
1. The clock prescaler is not used: FOSC= FXTAL.
Figure 12. IDD/IDL Versus XTAL Frequency; VDD= 2.7 to 3.6 V
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
15
10
5
0
IDD/IDL (mA)
Frequency at XTAL(1) (MHz)
2468 1410 12 16
38 Rev. A - May 7, 1999
TSC80251G2D
10.3 DC Characteristics: IDD, IDL and IPD Test Conditions
Figure 13. IDD Test Condition, Active Mode
Figure 14. IDL Test Condition, Idle Mode
Figure 15. IPD Test Condition, Power-Down Mode
VDD
XTAL2
VDD
Clock Signal
RST
VSS
TSC80251G2D
EA#
XTAL1
VDD
P0
(NC)
IDD
VDD
All other pins are unconnected
XTAL2
VDD
Clock Signal
RST
VSS
TSC80251G2D
EA#
XTAL1
VDD
P0
(NC)
IDL
VDD
All other pins are unconnected
XTAL2
VDDRST
VSS
TSC80251G2D
EA#
XTAL1
VDD
P0
(NC)
IPD
VDD
All other pins are unconnected
Rev. A - May 7, 1999 39
TSC80251G2D
11. AC Characteristics - Commercial & Industrial
11.1 AC Characteristics - External Bus Cycles
Definition of symbols
Table 44. External Bus Cycles Timing Symbol Definitions
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 45 and Table 46 list the AC timing parameters for the TSC80251G2D derivatives with no wait states. External
wait states can be added by extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks
parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states.
Figure 16 to Figure 21 show the bus cycles with the timing parameters.
Signals Conditions
A Address H High
D Data In L Low
L ALE V Valid
Q Data Out X No Longer Valid
R RD#/PSEN# Z Floating
W WR#
40 Rev. A - May 7, 1999
TSC80251G2D
Table 45. Bus Cycles AC Timings; VDD= 4.5 to 5.5 V, TA= -40 to 85°C
Notes:
1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·TOSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N= 1..3).
Symbol Parameter 12 MHz 16 MHz 24 MHz Unit
Min Max Min Max Min Max
TOSC 1/FOSC 83 62 41 ns
TLHLL ALE Pulse Width 78 58 38 ns(2)
TAVLL Address Valid to ALE Low 78 58 37 ns(2)
TLLAX Address hold after ALE Low 19 11 3 ns
TRLRH(1) RD#/PSEN# Pulse Width 162 121 78 ns(3)
TWLWH WR# Pulse Width 165 124 81 ns(3)
TLLRL(1) ALE Low to RD#/PSEN# Low 22 14 6 ns
TLHAX ALE High to Address Hold 99 70 40 ns(2)
TRLDV(1) RD#/PSEN# Low to Valid Data 146 104 61 ns(3)
TRHDX(1) Data Hold After RD#/PSEN# High 0 0 0 ns
TRHAX(1) Address Hold After RD#/PSEN# High 0 0 0 ns
TRLAZ(1) RD#/PSEN# Low to Address Float 0 0 0 ns
TRHDZ1 Instruction Float After RD#/PSEN# High 45 40 30 ns
TRHDZ2 Data Float After RD#/PSEN# High 215 165 115 ns
TRHLH1 RD#/PSEN# high to ALE High (Instruction) 49 43 31 ns
TRHLH2 RD#/PSEN# high to ALE High (Data) 215 169 115 ns
TWHLH WR# High to ALE High 215 169 115 ns
TAVDV1 Address (P0) Valid to Valid Data In 250 175 105 ns(2)(3)
TAVDV2 Address (P2) Valid to Valid Data In 306 223 140 ns(2)(3)
TAVDV3 Address (P0) Valid to Valid Instruction In 150 109 68 ns(3)
TAXDX Data Hold after Address Hold 0 0 0 ns
TAVRL(1) Address Valid to RD# Low 100 70 40 ns(2)
TAVWL1 Address (P0) Valid to WR# Low 100 70 40 ns(2)
TAVWL2 Address (P2) Valid to WR# Low 158 115 74 ns(2)
TWHQX Data Hold after WR# High 90 69 32 ns
TQVWH Data Valid to WR# High 133 102 72 ns(3)
TWHAX WR# High to Address Hold 167 125 84 ns
Rev. A - May 7, 1999 41
TSC80251G2D
Table 46. Bus Cycles AC Timings; VDD= 2.7 to 5.5 V, TA= -40 to 85°C
Notes:
1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·TOSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N= 1..3).
Symbol Parameter 12 MHz 16 MHz Unit
Min Max Min Max
TOSC 1/FOSC 83 62 ns
TLHLL ALE Pulse Width 72 52 ns(2)
TAVLL Address Valid to ALE Low 71 51 ns(2)
TLLAX Address hold after ALE Low 14 6 ns
TRLRH(1) RD#/PSEN# Pulse Width 163 121 ns(3)
TWLWH WR# Pulse Width 165 124 ns(3)
TLLRL(1) ALE Low to RD#/PSEN# Low 17 11 ns
TLHAX ALE High to Address Hold 90 57 ns(2)
TRLDV(1) RD#/PSEN# Low to Valid Data 133 92 ns(3)
TRHDX(1) Data Hold After RD#/PSEN# High 0 0 ns
TRHAX(1) Address Hold After RD#/PSEN# High 0 0 ns
TRLAZ(1) RD#/PSEN# Low to Address Float 0 0 ns
TRHDZ1 Instruction Float After RD#/PSEN# High 59 48 ns
TRHDZ2 Data Float After RD#/PSEN# High 225 175 ns
TRHLH1 RD#/PSEN# high to ALE High (Instruction) 60 47 ns
TRHLH2 RD#/PSEN# high to ALE High (Data) 226 172 ns
TWHLH WR# High to ALE High 226 172 ns
TAVDV1 Address (P0) Valid to Valid Data In 289 160 ns(2)(3)
TAVDV2 Address (P2) Valid to Valid Data In 296 211 ns(2)(3)
TAVDV3 Address (P0) Valid to Valid Instruction In 144 98 ns(3)
TAXDX Data Hold after Address Hold 0 0 ns
TAVRL(1) Address Valid to RD# Low 111 64 ns(2)
TAVWL1 Address (P0) Valid to WR# Low 111 64 ns(2)
TAVWL2 Address (P2) Valid to WR# Low 158 116 ns(2)
TWHQX Data Hold after WR# High 82 66 ns
TQVWH Data Valid to WR# High 135 103 ns(3)
TWHAX WR# High to Address Hold 168 125 ns
42 Rev. A - May 7, 1999
TSC80251G2D
Waveforms in Non-Page Mode
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 16. External Bus Cycle: Code Fetch (Non-Page Mode)
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 17. External Bus Cycle: Data Read (Non-Page Mode)
TAVDV2(1)
TAVDV1(1)
TLLAX
TRHDZ1
TRHDX
TRHAX
TAVRL(1)
P2/A16/A17
P0
PSEN#
ALE TLHLL(1)
TRLRH(1)
Instruction In
A15:8/A16/A17
TRLAZ
TLLRL(1) TRHLH1
TRLDV(1)
TAVLL(1)
TLHAX(1)
A7:0 D7:0
TAVDV2(1)
TAVDV1(1)
TLLAX
TRHAX
TRHDX
TRHDZ2
TAVLL(1)
TAVRL(1)
P2/A16/A17
P0
RD#/PSEN#
ALE TLHLL(1)
TRLRH(1)
TLHAX(1)
Data In
A15:8/A16/A17
TRLAZ
TLLRL(1) TRHLH2
TRLDV(1)
D7:0A7:0
Rev. A - May 7, 1999 43
TSC80251G2D
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 18. External Bus Cycle: Data Write (Non-Page Mode)
Waveforms in Page Mode
Notes:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch) requires one state (2·TOSC);
a page miss requires two states (4·TOSC).
3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
Figure 19. External Bus Cycle: Code Fetch (Page Mode)
TWHLH
TAVWL2(1)
TAVWL1(1)
TLHAX(1)
TLLAX TWHQX
TWHAX
P2/A16/A17
P0
WR#
ALE TLHLL(1)
TWLWH(1)
Data Out
A15:8/A16/A17
TAVLL(1) TQVWH
A7:0 D7:0
TLLAX
TAVDV2(1)
TAVDV1(1)
TLHAX(1)
TAVRL(1)
TRHDZ1
TRLAZ
TAXDX
TAVDV3(1)
P0/A16/A17
P2
PSEN#(3)
ALE TLHLL(1)
A7:0/A16/A17
TAVLL(1)
TLLRL(1)
TRLDV(1)
Page Miss(2) Page Hit(2)
TRHAX
A7:0/A16/A17
D7:0 D7:0A15:8
Instruction In Instruction In
TRHDX
44 Rev. A - May 7, 1999
TSC80251G2D
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 20. External Bus Cycle: Data Read (Page Mode)
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 21. External Bus Cycle: Data Write (Page Mode)
TAVDV2(1)
TAVDV1(1)
TLLAX
TRHAX
TRHDX
TRHDZ2
TAVLL(1)
TAVRL(1)
P0/A16/A17
P2
RD#/PSEN#
ALE TLHLL(1)
TRLRH(1)
TLHAX(1)
Data In
A7:0/A16/A17
TRLAZ
TLLRL(1) TRHLH2
TRLDV(1)
D7:0A15:8
TWHLH
TAVWL2(1)
TAVWL1(1)
TLHAX(1)
TLLAX TWHQX
TWHAX
P0/A16/A17
P2
WR#
ALE TLHLL(1)
TWLWH(1)
Data Out
A7:0/A16/A17
TAVLL(1) TQVWH
A15:8 D7:0
Rev. A - May 7, 1999 45
TSC80251G2D
11.2 AC Characteristics - Real-Time Synchronous Wait State
Definition of symbols
Table 47. Real-Time Synchronous Wait Timing Symbol Definitions
Timings
Table 48. Real-Time Synchronous Wait AC Timings; VDD= 2.7 to 5.5 V, TA= -40 to 85°C
Waveforms
Figure 22. Real-time Synchronous Wait State: Code Fetch/Data Read
Signals Conditions
C WCLK L Low
R RD#/PSEN# V Valid
W WR# X No Longer Valid
Y WAIT#
Symbol Parameter Min Max Unit
TCLYV Wait Clock Low to Wait Set-up 0 TOSC -20 ns
T
CLYX Wait Hold after Wait Clock Low 2W·TOSC + 5 (1+2W)·TOSC -20 ns
T
RLYV PSEN#/RD# Low to Wait Set-up 0 TOSC -20 ns
T
RLYX Wait Hold after PSEN#/RD# Low 2W·TOSC + 5 (1+2W)·TOSC -20 ns
T
WLYV WR# Low to Wait Set-up 0 TOSC -20 ns
T
WLYX Wait Hold after WR# Low 2W·TOSC + 5 (1+2W)·TOSC -20 ns
State 1 State 2 State 3 State 1 (next cycle)
TRLYXmax
TRLYXmin
TRLYV
TCLYV
TCLYXmax
P2
RD#/PSEN#
ALE
WCLK
P0
WAIT#
TCLYXmin
RD#/PSEN# stretched
A15:8
A7:0 D7:0 stretched
A15:8 stretched
A7:0
46 Rev. A - May 7, 1999
TSC80251G2D
Figure 23. Real-time Synchronous Wait State: Data Write
11.3 AC Characteristics - Real-Time Asynchronous Wait State
Definition of symbols
Table 49. Real-Time Asynchronous Wait Timing Symbol Definitions
Timings
Table 50. Real-Time Asynchronous Wait AC Timings; VDD= 2.7 to 5.5 V, TA= -40 to 85°C
Note:
1. N is the number of wait states added (N≥1).
Waveforms
Figure 24. Real-time Asynchronous Wait State Timings
Signals Conditions
S PSEN#/RD#/WR# L Low
Y AWAIT# V Valid
X No Longer Valid
Symbol Parameter Min Max Unit
TSLYV PSEN#/RD#/WR# Low to Wait Set-up TOSC -10 ns
T
SLYX Wait Hold after PSEN#/RD#/WR# Low (2N-1)·TOSC +10 ns
(1)
State 1 State 2 State 3 State 1 (next cycle)
TWLYXmax
TWLYXmin
TWLYV
TCLYV
TCLYXmax
P2
RD#/PSEN#
ALE
WCLK
P0
WAIT#
TCLYXmin
WR# stretched
A7:0 D7:0 stretched
A15:8 stretched
TSLYV
TSLYX
RD#/PSEN#/WR#
AWAIT#
Rev. A - May 7, 1999 47
TSC80251G2D
11.4 AC Characteristics - Serial Port in Shift Register Mode
Definition of symbols
Table 51. Serial Port Timing Symbol Definitions
Timings
Table 52. Serial Port AC Timing -Shift Register Mode; VDD= 2.7 to 5.5 V, TA= -40 to 85°C
Note:
1. For high speed versions only.
Waveforms
Note:
1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.
Figure 25. Serial Port Waveforms - Shift Register Mode
Signals Conditions
D Data In H High
Q Data Out L Low
X Clock V Valid
X No Longer Valid
Symbol Parameter 12 MHz 16 MHz 24 MHz(1) Unit
Min Max Min Max Min Max
TXLXL Serial Port Clock Cycle Time 998 749 500 ns
TQVXH Output Data Setup to Clock Rising Edge 833 625 417 ns
TXHQX Output Data hold after Clock Rising Edge 165 124 82 ns
TXHDX Input Data Hold after Clock Rising Edge 0 0 0 ns
TXHDV Clock Rising Edge to Input Data Valid 974 732 482 ns
TXLXL
TXHDV TXHDX
TQVXH
TXHQX Set TI(1)
Set RI(1)
Valid Valid Valid Valid Valid Valid Valid ValidRXD (In)
RXD (Out)
TXD
0 1 2 3 4 5 6 7
48 Rev. A - May 7, 1999
TSC80251G2D
11.5 AC Characteristics - SSLC: I2C Interface
Timings
Table 53. I2C Interface AC Timing; VDD= 2.7 to 5.5 V, TA= -40 to 85°C
Notes:
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL= 400 pF.
4. TCLCL=T
OSC= one oscillator clock period.
Waveforms
Figure 26. I2C Waveforms
Symbol Parameter INPUT
Min Max OUTPUT
Min Max
THD; STA Start condition hold time 14·TCLCL(4) 4.0 µs(1)
TLOW SCL low time 16·TCLCL(4) 4.7 µs(1)
THIGH SCL high time 14·TCLCL(4) 4.0 µs(1)
TRC SCL rise time 1 µs-
(2)
TFC SCL fall time 0.3 µs 0.3 µs(3)
TSU; DAT1 Data set-up time 250 ns 20·TCLCL(4)-TRD
TSU; DAT2 SDA set-up time (before repeated START condition) 250 ns 1 µs(1)
TSU; DAT3 SDA set-up time (before STOP condition) 250 ns 8·TCLCL(4)
THD; DAT Data hold time 0 ns 8·TCLCL(4) -TFC
TSU; STA Repeated START set-up time 14·TCLCL(4) 4.7 µs(1)
TSU; STO STOP condition set-up time 14·TCLCL(4) 4.0 µs(1)
TBUF Bus free time 14·TCLCL(4) 4.7 µs(1)
TRD SDA rise time 1 µs-
(2)
TFD SDA fall time 0.3 µs 0.3 µs(3)
TSU;STA
TSU;DAT2THD;STA THIGHTLOW
SDA
(INPUT/OUTPUT) 0.3 VDD
0.7 VDD
TBUFTSU;STO
0.7 VDD
0.3 VDD
TRD
TFD
TRC TFC
SCL
(INPUT/OUTPUT)
TSU;DAT1 THD;DAT
TSU;DAT3
START or Repeated START condition START condition
STOP condition
Repeated START condition
Rev. A - May 7, 1999 49
TSC80251G2D
11.6 AC Characteristics - SSLC: SPI Interface
Definition of symbols
Table 54. SPI Interface Timing Symbol Definitions
Timings
Table 55. SPI Interface AC Timing; VDD= 2.7 to 5.5 V, TA= -40 to 85°C
Signals Conditions
C Clock H High
I Data In L Low
O Data Out V Valid
S SS# X No Longer Valid
Z Floating
Symbol Parameter Min Max Unit
Slave mode(1)
TCHCH Clock Period 8 TOSC
TCHCX Clock High Time 3.2 TOSC
TCLCX Clock Low Time 3.2 TOSC
TSLCH,T
SLCL SS# Low to Clock edge 200 ns
TIVCL,T
IVCH Input Data Valid to Clock Edge 100 ns
TCLIX,T
CHIX Input Data Hold after Clock Edge 100 ns
TCLOV, TCHOV Output Data Valid after Clock Edge 100 ns
TCLOX,T
CHOX Output Data Hold Time after Clock Edge 0 ns
TCLSH,T
CHSH SS# High after Clock Edge 0 ns
TIVCL,T
IVCH Input Data Valid to Clock Edge 100 ns
TCLIX,T
CHIX Input Data Hold after Clock Edge 100 ns
TSLOV SS# Low to Output Data Valid 130 ns
TSHOX Output Data Hold after SS# High 130 ns
TSHSL SS# High to SS# Low (2)
TILIH Input Rise Time 2 µs
TIHIL Input Fall Time 2 µs
TOLOH Output Rise time 100 ns
TOHOL Output Fall Time 100 ns
50 Rev. A - May 7, 1999
TSC80251G2D
Notes:
1. Capacitive load on all pins= 200 pF in slave mode.
2. The value of this parameter depends on software.
3. Capacitive load on all pins= 100 pF in master mode.
Waveforms
Note:
1. SS# handled by software. Figure 27. SPI Master Waveforms (SSCPHA= 0)
Master mode(3)
TCHCH Clock Period 4 TOSC
TCHCX Clock High Time 1.6 TOSC
TCLCX Clock Low Time 1.6 TOSC
TIVCL,T
IVCH Input Data Valid to Clock Edge 50 ns
TCLIX,T
CHIX Input Data Hold after Clock Edge 50 ns
TCLOV, TCHOV Output Data Valid after Clock Edge 65 ns
TCLOX,T
CHOX Output Data Hold Time after Clock Edge 0 ns
TILIH Input Data Rise Time 2 µs
TIHIL Input Data Fall Time 2 µs
TOLOH Output Data Rise time 50 ns
TOHOL Output Data Fall Time 50 ns
Symbol Parameter Min Max Unit
MISO
(input)
SCK
(SSCPOL= 0)
(output)
SS#(1)
(output)
SCK
(SSCPOL= 1)
(output)
MOSI
(output)
TCHCH
TCLCX
TCHCX
TIVCL TCLIX
TCHIX
TIVCH
TCHOV
TCLOV TCHOX
TCLOX
MSB IN BIT 6 LSB IN
MSB OUTPort Data LSB OUT Port DataBIT 6
TCHCL
TCLCH
Rev. A - May 7, 1999 51
TSC80251G2D
Note:
1. SS# handled by software. Figure 28. SPI Master Waveforms (SSCPHA= 1)
Note:
1. Not Defined but normally MSB of character just received.
Figure 29. SPI Slave Waveforms (SSCPHA= 0)
MISO
(input)
SCK
(SSCPOL= 0)
(output)
SS#(1)
(output)
SCK
(SSCPOL= 1)
(output)
MOSI
(output)
TCHCH
TCLCX
TCHCX
TIVCL TCLIX
TCHIX
TIVCH
TCHOV
TCLOV TCHOX
TCLOX
MSB IN BIT 6 LSB IN
MSB OUTPort Data LSB OUT Port DataBIT 6
TCHCL
TCLCH
TSLCL
TSLCH
TCHCL
TCLCH
MOSI
(input)
SCK
(SSCPOL= 0)
(input)
SS#
(input)
SCK
(SSCPOL= 1)
(input)
MISO
(output)
TCHCH
TCLCX
TCHCX
TIVCL TCLIX
TCHIX
TIVCH
TCHOV
TCLOV TCHOX
TCLOX
MSB IN BIT 6 LSB IN
SLAVE MSB OUT SLAVE LSB OUTBIT 6
TSLOV
(1)
TSHOX
TSHSL
TCHSH
TCLSH
52 Rev. A - May 7, 1999
TSC80251G2D
Note:
1. Not Defined but generally the LSB of the character which has just been received.
Figure 30. SPI Slave Waveforms (SSCPHA= 1)
TCHCL
TCLCH
MOSI
(input)
SCK
(SSCPOL= 0)
(input)
SS#
(input)
SCK
(SSCPOL= 1)
(input)
MISO
(output)
TCHCH
TCLCX
TCHCX
TIVCL TCLIX
TCHIX
TIVCH
TCLOV
TCHOV TCLOX
TCHOX
MSB IN BIT 6 LSB IN
SLAVE MSB OUT SLAVE LSB OUTBIT 6
TSLOV
(1)
TSHOX
TSHSL
TCHSH
TCLSH
TSLCL
TSLCH
Rev. A - May 7, 1999 53
TSC80251G2D
11.7 AC Characteristics - EPROM Programming and Verifying
Definition of symbols
Table 56. EPROM Programming and Verifying Timing Symbol Definitions
Timings
Table 57. EPROM Programming AC timings; VDD= 4.5 to 5.5 V, TA=0to40°C
Table 58. EPROM Verifying AC timings; VDD= 4.5 to 5.5 V, VDD= 2.7 to 5.5 V, TA=0to40°C
Signals Conditions
A Address H High
E Enable: mode set on Port 0 L Low
G Program V Valid
Q Data Out X No Longer Valid
S Supply (VPP) Z Floating
Symbol Parameter Min Max Unit
TOSC XTAL1 Period 83.5 250 ns
TAVGL Address Setup to PROG# low 48 TOSC
TGHAX Address Hold after PROG# low 48 TOSC
TDVGL Data Setup to PROG# low 48 TOSC
TGHDX Data Hold after PROG# 48 TOSC
TELSH ENABLE High to VPP 48 TOSC
TSHGL VPP Setup to PROG# low 10 µs
TGHSL VPP Hold after PROG# 10 µs
TSLEH ENABLE Hold after VPP 0ns
T
GLGH PROG# Width 90 110 µs
Symbol Parameter Min Max Unit
TOSC XTAL1 Period 83.5 250 ns
TAVQV Address to Data Valid 48 TOSC
TAXQX Address to Data Invalid 0 ns
TELQV ENABLE low to Data Valid 0 48 TOSC
TEHQZ Data Float after ENABLE 0 48 TOSC
54 Rev. A - May 7, 1999
TSC80251G2D
Waveforms
Figure 31. EPROM Programming Waveforms
Figure 32. EPROM Verifying Waveforms
TSLEH
TELSH
TDVGL
TSHGL
TAVGL TGHAX
TGHDX
TGLGH TGHSL
VPP
VDD
VSS
P1= A15:8
P3= A7:0
P2= D7:0
EA#/VPP
ALE/PROG#
P0 Mode= 68h, 69h, 6Bh or 6Ch
Data
Address
TEHQZ
TELQV
TAVQV TAXQX
P1= A15:8
P3= A7:0
P2= D7:0
P0
Address
Mode= 28h, 29h or 2Bh
Data
Rev. A - May 7, 1999 55
TSC80251G2D
11.8 AC Characteristics - External Clock Drive and Logic Level References
Definition of symbols
Table 59. External Clock Timing Symbol Definitions
Timings
Table 60. External Clock AC Timings; VDD= 4.5 to 5.5 V, TA= -40 to +85°C
Waveforms
Figure 33. External Clock Waveform
Note:
During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0.
Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 34. AC Testing Input/Output Waveforms
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV
change from the loading VOH/VOL level occurs with IOL/IOH=±20 mA.
Figure 35. Float Waveforms
Signals Conditions
C Clock H High
L Low
X No Longer Valid
Symbol Parameter Min Max Unit
FOSC Oscillator Frequency 24 MHz
TCHCX High Time 10 ns
TCLCX Low Time 10 ns
TCLCH Rise Time 3 ns
TCHCL Fall Time 3 ns
0.45 V TCLCL
VDD - 0.5 VIH1
VIL
TCHCX
TCLCH
TCHCL
TCLCX
0.45 V
VDD - 0.5 0.2 VDD + 0.9
0.2 VDD - 0.1
VIH min
VIL max
INPUTS OUTPUTS
VLOAD VOH - 0.1 V
VOL + 0.1 V
VLOAD + 0.1 V
VLOAD - 0.1 V Timing Reference Points
Rev. A - May 7, 1999 56
TSC80251G2D
12. Packages
12.1 List of Packages
●PDIL 40
●CDIL 40 with window
●PLCC 44
●CQPJ 44 with window
●VQFP 44 (10x10)
12.2 PDIL 40 - Mechanical Outline
Figure 36. Plastic Dual In Line
Table 61. PDIL Package Size
MM INCH
Min Max Min Max
A - 5.08 - .200
A1 0.38 - .015 -
A2 3.18 4.95 .125 .195
B 0.36 0.56 .014 .022
B1 0.76 1.78 .030 .070
C 0.20 0.38 .008 .015
D 50.29 53.21 1.980 2.095
E 15.24 15.87 .600 .625
E1 12.32 14.73 .485 .580
e 2.54 B.S.C. .100 B.S.C.
eA 15.24 B.S.C. .600 B.S.C.
eB - 17.78 - .700
L 2.93 3.81 .115 .150
D1 0.13 - .005 -
57 Rev. A - May 7, 1999
TSC80251G2D
12.3 CDIL 40 with Window - Mechanical Outline
Figure 37. Ceramic Dual In Line
Table 62. CDIL Package Size
MM INCH
Min Max Min Max
A - 5.71 - .225
b 0.36 0.58 .014 .023
b2 1.14 1.65 .045 .065
c 0.20 0.38 .008 .015
D - 53.47 - 2.105
E 13.06 15.37 .514 .605
e 2.54 B.S.C. .100 B.S.C.
eA 15.24 B.S.C. .600 B.S.C.
L 3.18 5.08 .125 .200
Q 0.38 1.40 .015 .055
S1 0.13 - .005 -
a 0-15 0-15
N40
Rev. A - May 7, 1999 58
TSC80251G2D
12.4 PLCC 44 - Mechanical Outline
Figure 38. Plastic Lead Chip Carrier
Table 63. PLCC Package Size
MM INCH
Min Max Min Max
A 4.20 4.57 .165 .180
A1 2.29 3.04 .090 .120
D 17.40 17.65 .685 .695
D1 16.44 16.66 .647 .656
D2 14.99 16.00 .590 .630
E 17.40 17.65 .685 .695
E1 16.44 16.66 .647 .656
E2 14.99 16.00 .590 .630
e 1.27 BSC .050 BSC
G 1.07 1.22 .042 .048
H 1.07 1.42 .042 .056
J 0.51 - .020 -
K 0.33 0.53 .013 .021
Nd 11 11
Ne 11 11
59 Rev. A - May 7, 1999
TSC80251G2D
12.5 CQPJ 44 with Window - Mechanical Outline
Figure 39. Ceramic Quad Pack J
Table 64. CQPJ Package size
MM INCH
Min Max Min Max
A - 4.90 - .193
C 0.15 0.25 .006 .010
D - E 17.40 17.55 .685 .691
D1 - E1 16.36 16.66 .644 .656
e 1.27 TYP .050 TYP
f 0.43 0.53 .017 .021
J 0.86 1.12 .034 .044
Q 15.49 16.00 .610 .630
R 0.86 TYP .034 TYP
N1 11 11
N2 11 11
Rev. A - May 7, 1999 60
TSC80251G2D
12.6 VQFP 44 (10x10) - Mechanical Outline
Figure 40. Shrink Quad Flat Pack (Plastic)
Table 65. VQFP Package Size
MM INCH
Min Max Min Max
A - 1.60 - .063
A1 0.64 REF .025 REF
A2 0.64 REF .025REF
A3 1.35 1.45 .053 .057
D 11.90 12.10 .468 .476
D1 9.90 10.10 .390 .398
E 11.90 12.10 .468 .476
E1 9.90 10.10 .390 .398
J 0.05 - .002 6
L 0.45 0.75 .018 .030
e 0.80 BSC .0315 BSC
f 0.35 BSC .014 BSC
Rev. A - May 7, 1999 61
TSC80251G2D
13. Ordering Information
13.1 TSC80251G2D ROMless
Note:
1. Dry Pack mandatory for VQFP package.
13.2 TSC83251G1D 16 Kbytes Mask ROM
Notes:
1. Dry Pack mandatory for VQFP package.
2. xxx: means ROM code, is Cxxx in case of encrypted code.
13.3 TSC83251G2D 32 Kbytes MaskROM
Notes:
1. Dry Pack mandatory for VQFP package.
2. xxx: means ROM code, is Cxxx in case of encrypted code.
TEMIC Part Number ROM Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TSC80251G2D-16CB ROMless 16 MHz, Commercial 0°to 70°C, PLCC 44
TSC80251G2D-24CB ROMless 24 MHz, Commercial 0°to 70°C, PLCC 44
TSC80251G2D-24CED ROMless 24 MHz, Commercial 0°to 70°C, VQFP 44, Dry pack(1)
TSC80251G2D-24IA ROMless 24 MHz, Industrial -40°to 85°C, PDIL 40
TSC80251G2D-24IB ROMless 24 MHz, Industrial -40°to 85°C, PLCC 44
Low Voltage Versions 2.7 to 5.5 V, Commercial
TSC80251G2D-L16CB ROMless 16 MHz, Commercial, PLCC 44
TSC80251G2D-L16CED ROMless 16 MHz, Commercial, VQFP 44, Dry pack(1)
TEMIC Part Number(2) ROM Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TSC251G1Dxxx-16CB 16K MaskROM 16 MHz, Commercial 0°to 70°C, PLCC 44
TSC251G1Dxxx-24CB 16K MaskROM 24 MHz, Commercial 0°to 70°C, PLCC 44
TSC251G1Dxxx-24CED 16K MaskROM 24 MHz, Commercial 0°to 70°C, VQFP 44, Dry pack(1)
TSC251G1Dxxx-24IA 16K MaskROM 24 MHz, Industrial -40°to 85°C, PDIL 40
TSC251G1Dxxx-24IB 16K MaskROM 24 MHz, Industrial -40°to 85°C, PLCC 44
Low Voltage Versions 2.7 to 5.5 V, Commercial
TSC251G1Dxxx-L16CB 16K MaskROM 16 MHz, Commercial 0°to 70°C, PLCC 44
TSC251G1Dxxx-L16CED 16K MaskROM 16 MHz, Commercial 0°to 70°C, VQFP 44, Dry pack(1)
TEMIC Part Number(2) ROM Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TSC251G2Dxxx-16CB 32K MaskROM 16 MHz, Commercial 0°to 70°C, PLCC 44
TSC251G2Dxxx-24CB 32K MaskROM 24 MHz, Commercial 0°to 70°C, PLCC 44
TSC251G2Dxxx-24CED 32K MaskROM 24 MHz, Commercial 0°to 70°C, VQFP 44, Dry pack(1)
TSC251G2Dxxx-24IA 32K MaskROM 24 MHz, Industrial -40°to 85°C, PDIL 40
TSC251G2Dxxx-24IB 32K MaskROM 24 MHz, Industrial -40°to 85°C, PLCC 44
Low Voltage Versions 2.7 to 5.5 V, Commercial
TSC251G2Dxxx-L16CB 32K MaskROM 16 MHz, Commercial 0°to 70°C, PLCC 44
TSC251G2Dxxx-L16CED 32K MaskROM 16 MHz, Commercial 0°to 70°C, VQFP 44, Dry pack(1)
62 Rev. A - May 7, 1999
TSC80251G2D
13.4 TSC87251G2D OTPROM
Note:
1. Dry Pack mandatory for VQFP package.
13.5 TSC87251G2D EPROM - UV Window package
13.6 Options (Please consult TEMIC sales)
•ROM code encryption
•Tape & Real or Dry Pack
•Known good dice
•Ceramic packages
•Extended temperature range: -55°C to +125°C
13.7 Starter Kit
13.8 Products Marking
Note:
1. Dry Pack letter (D) not included in the marking.
TEMIC Part Number ROM Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TSC87251G2D-16CB 32K OTPROM 16 MHz, Commercial 0°to 70°C, PLCC 44
TSC87251G2D-24CB 32K OTPROM 24 MHz, Commercial 0°to 70°C, PLCC 44
TSC87251G2D-24CED 32K OTPROM 24 MHz, Commercial 0°to 70°C, VQFP 44, Dry pack(1)
TSC87251G2D-24IA 32K OTPROM 24 MHz, Industrial -40°to 85°C, PDIL 40
TSC87251G2D-24IB 32K OTPROM 24 MHz, Industrial -40°to 85°C, PLCC 44
Low Voltage Versions 2.7 to 5.5 V, Commercial
TSC87251G2D-L16CB 32K OTPROM 16 MHz, Commercial 0°to 70°C, PLCC 44
TSC87251G2D-L16CED 32K OTPROM 16 MHz, Commercial 0°to 70°C, VQFP 44, Dry pack(1)
TEMIC Part Number ROM Description
High Speed Versions 4.5 to 5.5 V, Industrial
TSC87251G2D-24IC 32K EPROM 24 MHz, Industrial -40°to 85°C, window CQPJ 44
TSC87251G2D-24IJ 32K EPROM 24 MHz, Industrial -40°to 85°C, window CDIL 40
Low Voltage Versions 2.7 to 5.5 V, Industrial
TSC87251G2D-L16IC 32K EPROM 16 MHz, Commercial -40°to 85°C, window CQPJ 44
TEMIC Part Number Description
TSC80251-SK TSC80251 Starter Kit
ROMless versions
TEMIC
Customer Part number
Temic Part number
INTEL’97
YYWW . Lot Number
Mask ROM versions
TEMIC
Temic Part number(1)
INTEL’97
YYWW . Lot Number
OTP versions
TEMIC
Temic Part number(1)
INTEL’97
YYWW . Lot Number
MMM C C C
Sales Offices
May 1999 63
Sales Locations
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United Kingdom
TEMIC U.K. Ltd.
Easthampstead Road
Bracknell, Berkshire RG12 1LX
Tel: 44 1344 707 300
Fax: 44 1344 427 371
North America Sales Offices
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Western
TEMIC North America
c/o Atmel Corporation
2325 Orchard Parkway
San Jose
California 95131
Tel: 1 408 441 0311
Fax: 1 408 436 4200
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Eastern
TEMIC North America Inc.
180 Mount Airy Road, Ste. 100
Basking Ridge
New Jersey 07920
Tel: 1 908 630 9200
Fax: 1 908 630 9201
Asia Pacific / Japan Sales Offices
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China
TEMIC Shanghai
c/o Atmel Corp
4th floor, Block A
Shanghai Eastern Business Bldg
586 Fanyu Road, Shanghai
200052 China
Tel: 86 21 6280 9241
Fax: 86 21 6283 8816
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Hong Kong
TEMIC Hong Kong Ltd.
c/o Atmel Asia Ltd
# 1216, Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon, Hong Kong
Tel: 852 23 789 789
Fax: 852 23 755 733
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Japan
TEMIC Semiconductors
c/o Atmel Japan K.K.
Tonetsushinkawa Bldg.
1–24–8, Shinkawa, chuku
Tokyo 104–0033
Tel: 81 3 3523 3551
Fax: 81 3 3523 7581
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Rep. of Singapore
TEMIC Singapore Pte Ltd
Keppel Building, #03–00
25 Tampines Street 92
Singapore 528877
Tel: 65 260 8223
Fax: 65 787 9819
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Korea
TEMIC Korea Ltd.
Suite 605, Singsong Bldg.
25–4 Yoido–dong
Youngdeungpo–Ku
150–010 Seoul
Tel: 82 2 785 1136
Fax: 82 2 785 1137
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Taiwan, R.O.C.
TEMIC Taiwan, c/o Atmel Corp.
9F–1 NO.266
SEC.1 Wen HWA 2RD
Lin Kon Hsiang
Taipei Hsien
Tel: 886 2 2609 5581
Fax: 886 2 2600 2735
