X9401WS24I - Xicor, Inc. - Datasheet.Directory

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Low Noise/Low Power/SPI Bus

X9401

Preliminary Information

Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP

™

)

FEATURES

• Quad–4 separate pots, 64 taps/pot

• Nonvolatile storage of wiper position

• Four Nonvolatile Data Registers for Each Pot

• 16-bytes of EEPROM memory

• SPI serial interface

•R

Total

= 10k

Ω

• Wiper resistance = 150

Ω

typical

• Standby current < 1µA (total package)

• Operating current < 400µA max.

•V

= 2.7V to 5V

• Packages–24-lead TSSOP, SOIC, CSP (Chip

Scale Package)

• 100 year data retention

DESCRIPTION

The X9401 integrates 4 digitally controlled potentiome-

ters (XDCP) on a monolithic CMOS integrated

microcircuit.

The digitally controlled potentiometer is implemented

using 64 resistive elements in a series array. Between

each element are tap points connected to the wiper

terminal through switches. The position of the wiper on

the array is controlled by the user through the SPI bus

interface. Each potentiometer has associated with it a

volatile Wiper Counter Register (WCR) and 4 nonvola-

tile Data Registers (DR0:DR3) that can be directly

written to and read by the user. The contents of the

WCR controls the position of the wiper on the resistor

array through the switches. Power up recalls the con-

tents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiom-

eter or as a two-terminal variable resistor in a wide

variety of applications including control, parameter

adjustments, and signal processing.

BLOCK DIAGRAM

Interface

and

Control

Circuitry

SCK

R0 R1

R2 R3

Wiper

Counter

(WCR)

Resistor

Array

Pot 1

VH1/RH1

VL1/RL1

R0 R1

R2 R3

Wiper

Counter

(WCR)

VH0/RH0

VL0/RL0

Data

VW0/RW0

VW1/RW1

R0 R1

R2 R3

Resistor

Array

VH2/RH2

VL2/RL2

VW2/RW2

R0 R1

R2 R3

Resistor

Array

VH3/RH3

VL3/RL3

VW3/RW3

Wiper

Counter

(WCR)

Wiper

Counter

(WCR) Pot 3

Pot 2

HOLD

Pot 0

VCC

VSS

PPLICATION

OTES

AVAILABLE

AN99 • AN115 • AN120 • AN124 • AN133 • AN134

X9401 – Preliminary Information

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PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked out

by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte

addresses and data to be written to the pots and pot

registers are input on this pin. Data is latched by the

rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the

X9401.

Chip Select (CS)

When CS is HIGH, the X9401 is deselected and the

SO pin is at high impedance, and (unless an internal

write cycle is underway) the device will be in the

standby state. CS LOW enables the X9401, placing it in

the active power mode. It should be noted that after a

power-up, a HIGH to LOW transition on CS is required

prior to the start of any operation.

Hold (HOLD)

HOLD is used in conjunction with the CS pin to select the

device. Once the part is selected and a serial sequence is

underway, HOLD may be used to pause the serial com-

munication with the controller without resetting the serial

sequence. To pause, HOLD must be brought LOW while

SCK is LOW. To resume communication, HOLD is

brought HIGH, again while SCK is LOW. If the pause fea-

ture is not used, HOLD should be held HIGH at all times.

Device Address (A

–

)

The address inputs are used to set the least signiﬁcant 2 bits

of the 8-bit slave address. A match in the slave address

serial data stream must be made with the address input

in order to initiate communication with the X9401. A

maximum of 4 devices may occupy the SPI serial bus.

Potentiometer Pins

–V

), V

–V

), R

–R

)

The V

and V

inputs are equivalent to the terminal

connections on either end of a mechanical potentiometer.

–V

), R

–R

)

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when LOW prevents nonvolatile writes to

the Wiper Counter Registers.

PIN CONFIGURATION

VCC

VL0/RL0

VH0/RH0

VL3/RL3

VH3/RH3

VW3/RW3

HOLD

SCK

VL2/RL2

VH2/RH2

SOIC

X9401

VSS

VW0/RW0

VL1/RL1

VH1/RH1

VW1/RW1 VW2/RW2

VH2/RH2

VW0/RW0

VCC

VL3/RL3

VH3/RH3

VW3/RW3

TSSOP

X9401

VW2/RW2

HOLD

VL1/RL1

VH1/RH1

VW1/RW1

VH0/RH0

SCK

VL2/RL2

VL0/RL0

VSS

2 3 4

Top View–Bumps Down

VW0/RW0

VL0/RL0

HOLD

VL1/RL1

VCC

VL3/RL3

VW3/RW3

SI VW1/RW1

SCK VL2/RL2

VH0/RH0 VH1/RH1

VH3/RH3 VH2/RH2

VSS

VW2/RW2

CS A1

CSP

X9401 – Preliminary Information

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PIN NAMES

DEVICE DESCRIPTION

The X9401 is a highly integrated microcircuit incorpo-

rating four resistor arrays and their associated regis-

ters and counters and the serial interface logic

providing direct communication between the host and

the XDCP potentiometers.

Serial Interface

The X9401 supports the SPI interface hardware con-

ventions. The device is accessed via the SI input with

data clocked in on the rising SCK. CS must be LOW

and the HOLD and WP pins must be HIGH during the

entire operation.

The SO and SI pins can be connected together, since

they have three state outputs. This can help to reduce

system pin count.

Array Description

The X9401 is comprised of four resistor arrays. Each

array contains 63 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the ﬁxed terminals of a mechanical

potentiometer (VH/RH and VL/RL inputs).

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper

(VW/RW) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter

to select, and enable, one of sixty-four switches.

Wiper Counter Register (WCR)

The X9401 contains four Wiper Counter Registers,

one for each XDCP potentiometer. The WCR is equiv-

alent to a serial-in, parallel-out register/counter with its

outputs decoded to select one of sixty-four switches

along its resistor array. The contents of the WCR can

be altered in four ways: it may be written directly by the

host via the Write Wiper Counter Register instruction

(serial load); it may be written indirectly by transferring

the contents of one of four associated data registers

via the XFR Data Register or Global XFR Data Regis-

ter instructions (parallel load); it can be modiﬁed one

step at a time by the Increment/Decrement instruction.

Finally, it is loaded with the contents of its data register

zero (R0) upon power-up.

The Wiper Counter Register is a volatile register; that

is, its contents are lost when the X9401 is powered-

down. Although the register is automatically loaded

with the value in R0 upon power-up, this may be differ-

ent from the value present at power-down. The wiper

position must be stored in R0 to insure restoring the

wiper position after power-up.

Data Registers

Each potentiometer has four 6-bit nonvolatile data reg-

isters. These can be read or written directly by the

host. Data can also be transferred between any of the

four data registers and the associated Wiper Counter

data registers is a nonvolatile operation and will take a

maximum of 10ms.

If the application does not require storage of multiple

settings for the potentiometer, the data registers can

be used as memory locations for system parameters

or user preference data.

Data Register Detail

Symbol Description

SCK Serial Clock

SI, SO Serial Data

A0-A1Device Address

VH0/RH0–VH3/RH3,

VL0/RL0–VL3/RL3

Potentiometers (terminal

equivalent)

VW0/RW0–VW1/RW1 Potentiometers (wiper

equivalent)

WP Hardware Write Protection

VCC System Supply Voltage

VSS System Ground

NC No Connection

(MSB) (LSB)

D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV

X9401 – Preliminary Information

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Write in Process

The contents of the Data Registers are saved to non-

volatile memory when the CS pin goes from LOW to

HIGH after a complete write sequence is received by

the device. The progress of this internal write opera-

tion can be monitored by a Write In Process bit (WIP).

The WIP bit is read with a Read Status command.

INSTRUCTIONS

Identification (ID) Byte

The ﬁrst byte sent to the X9401 from the host, follow-

ing a CS going HIGH to LOW, is called the Identiﬁca-

tion byte. The most signiﬁcant four bits of the slave

address are a device type identiﬁer, for the X9401 this

is ﬁxed as 0101[B] (refer to Figure 1).

The two least signiﬁcant bits in the ID byte select one

of four devices on the bus. The physical device

address is deﬁned by the state of the A0-A1 input pins.

The X9401 compares the serial data stream with the

address input state; a successful compare of both

address bits is required for the X9401 to successfully

continue the command sequence. The A0–A1 inputs

can be actively driven by CMOS input signals or tied to

VCC or VSS.

The remaining two bits in the slave byte must be set to 0.

Figure 1. Identiﬁcation Byte Format

Instruction Byte

The next byte sent to the X9401 contains the instruc-

tion and register pointer information. The four most

signiﬁcant bits are the instruction. The next four bits

point to one of the four pots and, when applicable, they

point to one of four associated registers. The format is

shown below in Figure 2.

100

0 0 A1 A0

Device Type

Identifier

Device Address

Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

Serial

Bus

Input

Parallel

Bus

Input

Wiper

Counter

INC/DEC

Logic

UP/DN

CLK

Modified SCL

UP/DN

VH/RH

VL/RL

VW/RW

If WCR = 00[H] then VW/RW = VL/RL

If WCR = 3F[H] then VW/RW = VH/RH

8 6

(WCR)

(One of Four Arrays)

X9401 – Preliminary Information

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Figure 2. Instruction Byte Format

The four high order bits of the instruction byte specify

the operation. The next two bits (R1 and R0) select one

of the four registers that is to be acted upon when a

(P1 and P0) selects which one of the four potentiome-

ters is to be affected by the instruction.

Four of the ten instructions are two bytes in length and

end with the transmission of the instruction byte. These

instructions are:

– XFR Data Register to Wiper Counter Register—This

transfers the contents of one speciﬁed Data Register

to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register—This

transfers the contents of the speciﬁed Wiper Counter

– Global XFR Data Register to Wiper Counter Register —

This transfers the contents of all speciﬁed Data Reg-

isters to the associated Wiper Counter Registers.

– Global XFR Wiper Counter Register to Data Register—

This transfers the contents of all Wiper Counter Reg-

isters to the speciﬁed associated Data Registers.

The basic sequence of the two byte instructions is illus-

trated in Figure 3. These two-byte instructions exchange

data between the WCR and one of the data registers. A

transfer from a data register to a WCR is essentially a

write to a static RAM, with the static RAM controlling the

wiper position. The response of the wiper to this action

will be delayed by tWRL. A transfer from the WCR (cur-

rent wiper position), to a data register is a write to nonvol-

atile memory and takes a minimum of tWR to complete.

The transfer can occur between one of the four potenti-

ometers and one of its associated registers; or it may

occur globally, where the transfer occurs between all

potentiometers and one associated register.

Five instructions require a three-byte sequence to com-

plete. These instructions transfer data between the host

and the X9401; either between the host and one of the

data registers or directly between the host and the

Wiper Counter Register. These instructions are:

– Read Wiper Counter Register— read the current

wiper position of the selected pot,

–Write Wiper Counter Register—change current wiper

position of the selected pot,

– Read Data Register—read the contents of the

selected data register;

–Write Data Register—write a new value to the

selected data register.

– Read Status—This command returns the contents of

the WIP bit which indicates if the internal write cycle

is in progress.

The sequence of these operations is shown in Figure 4

and Figure 5.

The ﬁnal command is Increment/Decrement. It is differ-

ent from the other commands, because it’s length is

indeterminate. Once the command is issued, the mas-

ter can clock the selected wiper up and/or down in one

resistor segment steps; thereby, providing a ﬁne tuning

capability to the host. For each SCK clock pulse (tHIGH)

while SI is HIGH, the selected wiper will move one

resistor segment towards the VH/RH terminal. Similarly,

for each SCK clock pulse while SI is LOW, the selected

wiper will move one resistor segment towards the VL/RL

terminal. A detailed illustration of the sequence and tim-

ing for this operation are shown in Figure 6 and Figure 7.

I1I2I3 I0 R1 R0 P1 P0

Pot Select

Select

Instructions

X9401 – Preliminary Information

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Figure 3. Two-Byte Command Sequence

Figure 4. Three-Byte Command Sequence (Write)

Figure 5. Three-Byte Command Sequence (Read)

Figure 6. Increment/Decrement Command Sequence

010100A1A0 I3 I2 I1 I0 R1 R0 P1 P0

SCK

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0

SCL

0 0 D5 D4 D3 D2 D1 D0

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0

SCL

0 0 D5 D4 D3 D2 D1 D0

Don’t Care

010100A1A0 I3 I2 I1 I0 0 P1 P0

SCK

X9401 – Preliminary Information

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Figure 7. Increment/Decrement Timing Limits

Table 1. Instruction Set

Instruction

Instruction Set

OperationI3I2I1I0R1R0P1P0

Read Wiper Counter Register 1 0 0 1 0 0 P1P0Read the contents of the Wiper Counter Register

pointed to by P1-P0

Write Wiper Counter Register 1 0 1 0 0 0 P1P0Write new value to the Wiper Counter Register

pointed to by P1-P0

Read Data Register 1 0 1 1 R1R0P1P0Read the contents of the Data Register pointed to

by P1-P0 and R1–R0

Write Data Register 1 1 0 0 R1R0P1P0Write new value to the Data Register pointed to by

P1-P0 and R1–R0

XFR Data Register to Wiper

Counter Register

1101R

1R0P1P0Transfer the contents of the Data Register pointed

to by R1–R0 to the Wiper Counter Register pointed

to by P1-P0

XFR Wiper Counter Register

to Data Register

1110R

1R0P1P0Transfer the contents of the Wiper Counter Register

pointed to by P1-P0 to the Register pointed to by

R1–R0

Global XFR Data Register to

Wiper Counter Register

0001R

1R00 0 Transfer the contents of the Data Registers pointed

to by R1–R0 of all four pots to their respective Wiper

Counter Register

Global XFR Wiper Counter

1000R

1R00 0 Transfer the contents of all Wiper Counter Regis-

ters to their respective data Registers pointed to by

R1–R0 of all four pots

Increment/Decrement Wiper

Counter Register

00100 0P

1P0Enable Increment/decrement of the Wiper Counter

Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by

checking the WIP bit.

SCK

VW/RW

INC/DEC CMD Issued

tWRID

Voltage Out

X9401 – Preliminary Information

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Instruction Format

Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Counter Register

(3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).

(4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

wiper position

(sent by X9401 on SO) CS

Rising

Edge

010100A

0100100P

000

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

Data Byte

(sent by Host on SI) CS

Rising

Edge

010100A

0101000P

000

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Data Byte

(sent by X9401 on SO) CS

Rising

Edge

010100A

01011R

000

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Data Byte

(sent by host on SI) CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

010100A

01100R

000

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses CS

Rising

Edge

010100A

01101R

X9401 – Preliminary Information

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Transfer Wiper Counter Register (WCR) to Data Register (DR)

Increment/Decrement Wiper Counter Register (WCR)

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

Read Status

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

010100A

01110R

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

increment/decrement

(sent by master on SDA) CS

Rising

Edge

010100A

00010XXP

D....

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses CS

Rising

Edge

010100A

00001R

000

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

010100A

01000R

000

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

wiper

addresses

Data Byte

(sent by X9401 on SO) CS

Rising

Edge

010100A

0010100010000000

X9401 – Preliminary Information

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias.................... –65°C to +135°C

Storage temperature......................... –65°C to +150°C

Voltage on SCK, SCL or any address

input with respect to VSS ........................ –1V to +7V

∆V = |(VH–VL)| ......................................................5.5V

Lead temperature (soldering, 10 seconds) ........ 300°C

COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; the functional operation of

the device (at these or any other conditions above

those listed in the operational sections of this speciﬁca-

tion) is not implied. Exposure to absolute maximum rat-

ing conditions for extended periods may affect device

reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature Min. Max.

Commercial 0°C +70°C

Industrial –40°C +85°C

Device Supply Voltage (VCC) Limits

X9401 5V ±10%

X9401-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

POWER UP AND DOWN REQUIREMENTS

The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the poten-

tiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW.

The VCC power-up spec is always in effect.

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used

as a potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (VH–VL)/63, single pot

Symbol Parameter

Limits

Test ConditionMin. Typ. Max. Unit

RTOTAL End to end resistance –20 +20 %

Power rating 50 mW 25°C, each pot

IW Wiper current –6 +6 mA

RWWiper resistance 150 500 ΩWiper Current = ± 3mA

VTERM Voltage on any VH or VL Pin VSS VCC VV

SS = 0V

Noise -120 dBV Ref: 1kHz

Resolution 1.6 %

Absolute linearity (1) –1 +1 MI(3) Vw(n)(actual)—Vw(n)(expected)

Relative linearity (2) –0.2 +0.2 MI(3) Vw(n + 1)—[Vw(n) + MI]

Temperature coefficient of RTOTAL ±300 ppm/°C

Ratiometric temp. coefficient ±20 ppm/°C

CH/CL/CWPotentiometer capacitances 10/10/25 pF See Macro model

IAL RH, RL, RW leakage current 0.1 10 µA VIN = VSS to VCC. Device is in

stand-by mode.

X9401 – Preliminary Information

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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

Symbol Parameter

Limits

Test ConditionsMin. Typ. Max. Unit

ICC1 VCC supply current (active) 400 µA fSCK = 2MHz, SO = Open,

Other Inputs = VSS

ICC2 VCC supply current (nonvola-

tile write)

1mAf

SCK = 2MHz, SO = Open,

Other Inputs = VSS

ISB VCC current (standby) 1 µA SCK = SI = VSS, Addr. = VSS,

CS = VCC

ILI Input leakage current 10 µA VIN = VSS to VCC

ILO Output leakage current 10 µA VOUT = VSS to VCC

VIH Input HIGH voltage VCC x 0.7 VCC + 0.5 V

VIL Input LOW voltage –0.5 VCC x 0.1 V

VOL Output LOW voltage 0.4 V IOL = 3mA

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

Symbol Test Max. Unit Test Condition

COUT(4) Output capacitance (SO) 8 pF VOUT = 0V

CIN(4) Input capacitance (A0, A1, SI, and SCK) 6 pF VIN = 0V

Symbol Parameter Min. Max. Unit

tr VCC(6) VCC Power-up rate 0.2 50 V/ms

tPUR(5) Power-up to initiation of read operation 1 ms

tPUW(5) Power-up to initiation of write operation 5 ms

A.C. TEST CONDITIONS

Notes: (4) This parameter is periodically sampled and not 100%

tested

(5) tPUR and tPUW are the delays required from the time the

(last) power supply (VCC-) is stable until the speciﬁc

instruction can be issued. These parameters are periodi-

cally sampled and not 100% tested.

(6) This is not a tested or guaranteed parameter and should

be used only as a guideline.

EQUIVALENT A.C. LOAD CIRCUIT

Input pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Input and output timing level VCC x 0.5

1533Ω

100pF

SDA

Output

10pF

CLCL

RTOTAL

25pF

10pF

SPICE Macro Model

X9401 – Preliminary Information

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AC TIMING

HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

Symbol Parameter Min. Max. Unit

fSCK SSI/SPI clock frequency 2.0 MHz

tCYC SSI/SPI clock cycle rime 500 ns

tWH SSI/SPI clock high rime 200 ns

tWL SSI/SPI clock low time 200 ns

tLEAD Lead time 250 ns

tLAG Lag time 250 ns

tSU SI, SCK, HOLD and CS input setup time 50 ns

tHSI, SCK, HOLD and CS input hold time 50 ns

tRI SI, SCK, HOLD and CS input rise time 2 µs

tFI SI, SCK, HOLD and CS input fall time 2 µs

tDIS SO output disable time 0 500 ns

tVSO output valid time 100 ns

tHO SO output hold time 0 ns

tRO SO output rise time 50 ns

tFO SO output fall time 50 ns

tHOLD HOLD time 400 ns

tHSU HOLD setup time 100 ns

tHH HOLD hold time 100 ns

tHZ HOLD low to output in high Z 100 ns

tLZ HOLD high to output in low Z 100 ns

TINoise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns

tCS CS deselect time 2 µs

tWPASU WP, A0 and A1 setup time 0 ns

tWPAH WP, A0 and A1 hold time 0 ns

Symbol Parameter Typ. Max. Unit

tWR High-voltage write cycle time (store instructions) 5 10 ms

Symbol Parameter Min. Max. Unit

tWRPO Wiper response time after the third (last) power supply is stable 10 µs

tWRL Wiper response time after instruction issued (all load instructions) 10 µs

tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns

X9401 – Preliminary Information

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SYMBOL TABLE

TIMING DIAGRAMS

Input Timing

Output Timing

WAVEFORM INPUTS OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A Center Line

is High

Impedance

...

SCK

MSB LSB

High Impedance

tLEAD

tSU tFI

tCS

tLAG

tCYC

tWL

...

tRI

tWH

...

SCK

SI ADDR

MSB LSB

tDIS

tHO

...

X9401 – Preliminary Information

Characteristics subject to change without notice. 14 of 21

REV 1.9 4/13/04 www.xicor.com

Hold Timing

XDCP Timing (for All Load Instructions)

XDCP Timing (for Increment/Decrement Instruction)

...

SCK

HOLD

tHSU tHH

tLZ

tHZ

tHOLD

tRO tFO

...

SCK

SI MSB LSB

VW/RW

tWRL

...

SO High Impedance

...

SCK

SI ADDR

tWRID

High Impedance

VW/RW

...

Inc/Dec Inc/Dec

...

X9401 – Preliminary Information

Characteristics subject to change without notice. 15 of 21

REV 1.9 4/13/04 www.xicor.com

Write Protect and Device Address Pins Timing

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

tWPASU tWPAH

(Any Instruction)

VW/RW

+VR

Three terminal Potentiometer;

Variable voltage divider Two terminal Variable Resistor;

Variable current

X9401 – Preliminary Information

Characteristics subject to change without notice. 16 of 21

REV 1.9 4/13/04 www.xicor.com

Application Circuits

Noninverting Amplifier Voltage Regulator

Offset Voltage Adjustment Comparator with Hysteresis

–

VO = (1+R2/R1)VS

Iadj

VO (REG) = 1.25V (1+R2/R1)+Iadj R2

VO (REG)VIN 317

–

VUL = {R1/(R1+R2)} VO(max)

VLL = {R1/(R1+R2)} VO(min)

100KΩ

10KΩ

+5V

TL072

–

VSVO

}

Attenuator Filter

–

VO = G VS

-1/2 ≤ G ≤ +1/2

GO = 1 + R2/R1

fc = 1/(2pRC)

R4All RS = 10kΩ

–

X9401 – Preliminary Information

Characteristics subject to change without notice. 17 of 21

REV 1.9 4/13/04 www.xicor.com

Application Circuits (continued)

Inverting Amplifier Equivalent L-R Circuit

–

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq

(R1 + R3) >> R2

–

Function Generator

}

VO = G VS

G = - R2/R1

ZIN

–R2

–

}

frequency ∝ R1, R2, C

amplitude ∝ RA, RB

X9401 – Preliminary Information

Characteristics subject to change without notice. 18 of 21

REV 1.9 4/13/04 www.xicor.com

PACKAGING INFORMATION

0.290 (7.37)

0.299 (7.60)

0.393 (10.00)

0.420 (10.65)

0.014 (0.35)

0.020 (0.50)

Pin 1

Pin 1 Index

0.050 (1.27)

0.598 (15.20)

0.610 (15.49)

0.003 (0.10)

0.012 (0.30)

0.092 (2.35)

0.105 (2.65)

(4X) 7°

24-Lead Plastic Small Outline Gull Wing Package Type S

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.420"

0.050" Typical

0.050"

Typical

0.030" Typical

24 Places

FOOTPRINT

0.010 (0.25)

0.020 (0.50)

0.015 (0.40)

0.050 (1.27)

0.009 (0.22)

0.013 (0.33)

0° – 8°

X 45°

X9401 – Preliminary Information

Characteristics subject to change without notice. 19 of 21

REV 1.9 4/13/04 www.xicor.com

PACKAGING INFORMATION

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

24-Lead Plastic, TSSOP Package Type V

.169 (4.3)

.177 (4.5).252 (6.4) BSC

.026 (.65) BSC

.303 (7.70)

.311 (7.90)

.002 (.06)

.005 (.15)

.047 (1.20)

.0075 (.19)

.0118 (.30)

See Detail “A”

.031 (.80)

.041 (1.05)

.010 (.25)

.020 (.50)

.030 (.75)

Gage Plane

Seating Plane

Detail A (20X)

(4.16) (7.72)

(1.78)

(0.42)

(0.65)

ALL MEASUREMENTS ARE TYPICAL

0°–8°

X9401 – Preliminary Information

Characteristics subject to change without notice. 20 of 21

REV 1.9 4/13/04 www.xicor.com

PACKAGING INFORMATION

Ball Matrix:

X9401W/X9401Y

4321

A RL1 A1 CS RW0

B RW1 SI WP RL0

C VSS RH1 RH0 VCC

D NC RH2 RH3 NC

E RW2 HOLD SO RL3

F RL2 SCK A0 RW3

Package Dimensions

Symbol

Min Nominal Max

Millimeters

Package Width a 2.595 2.625 2.655

Package Length b 3.814 3.844 3.874

Package Height c 0.644 0.677 0.710

Body Thickness d 0.444 0.457 0.470

Ball Height e 0.220 0.240 0.260

Ball Diameter f 0.310 0.330 0.350

Ball Pitch – Width j 0.5

Ball Pitch – Length k 0.5

Ball to Edge Spacing – Width l 0.538 0.563 0.588

Ball to Edge Spacing – Length m 0.647 0.672 0.697

9401WRR

YWW I2.7

LOT #

24-Bump Chip Scale Package (CSP B24)

Package Outline Drawing

Top View (Sample Marking) Bottom View (Bumped Side) Side View

A4 A3 A2 A1

B4 B3 B2 B1

C4 C3 C2 C1

D4 D3 D2 D1

E4 E3 E2 E1

F4 F3 F2 F1

Side View

X9401 – Preliminary Information

Characteristics subject to change without notice. 21 of 21

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,

express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.

Xicor, Inc. makes no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices

at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All

others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;

4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;

5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection

and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

REV 1.9 4/13/04 www.xicor.com

ORDERING INFORMATION

Device VCC Limits

Blank = 5V ±10%

–2.7 = 2.7 to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C

I = Industrial = –40°C to +85°C

Package

S24 = 24-Lead SOIC

V24 = 24-Lead TSSOP

B24 = 24 Lead CSP

Potentiometer Organization

Pot 0 Pot 1 Pot 2 Pot 3

W = 10KW 10KW 10KW 10KW

Y = 2.5KΩ2.5KΩ2.5KΩ2.5KΩ

X9401 P T VY