HY5PS12421CFLP-S5 - SK Hynix - Datasheet.Directory

This document is a general product description an d is subject to change without notice. Hynix Semicond uctor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.8 / Oct. 2007 1

HY5PS12421C(L)FP

HY5PS12821C(L)FP

HY5PS121621C(L)FP

512Mb DDR2 SDRAM

HY5PS12421C(L)FP

HY5PS12821C(L)FP

HY5PS121621C(L)FP

Rev. 0.8 / Oct. 2007 2

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

Revision History

Rev. History Draft Date

0.1 Preliminary May 2006

0.2 IDD Spec. Changed July 2006

0.3 Removed improper note in ODT spec. July 2006

0.4 Updated IDD3P-S value/OCD Default Characteristics Aug. 2006

0.5 Updated IDD spec for x8 org. on page 16 Feb. 2007

0.6 Removed Y4 Speed bin July 2007

0.7 Updated Timing Patterns (DDR2-800 5/5/5 and 6/6/6) Sep. 2007

0.8 Corrected Typo Oct. 2007

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Contents

1. Description

1.1 Device Features and Ordering Information

1.1.1 Key Features

1.1.2 Ordering Information

1.1.3 Ordering Frequency

1.2 Pin configuration

1.3 Pin Description

2. Maximum DC ratings

2.1 Absolute Maximum DC Ratings

2.2 Operating Temperature Condition

3. AC & DC Operating Conditions

3.1 DC Operating Conditions

5.1.1 Recommended DC Operating Conditions(SSTL_1.8)

5.1.2 ODT DC Electrical Characteristics

3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

3.2.2 Input AC Logic Level

3.2.3 AC Input Test Conditions

3.2.4 Differential Input AC Logic Level

3.2.5 Differential AC output parameters

3.3 Output Buffer Levels

3.3.1 Output AC Test Conditions

3.3.2 Output DC Current Drive

3.3.3 OCD default characteristics

3.4 IDD Specifications & Measurement Conditions

3.5 Input/Output Capacitance

4. AC Timing Specifications

5. Package Dimensions

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1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

• VDD ,VDDQ =1.8 +/- 0.1V

• All inputs and outputs are compatible with SSTL_18 interface

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)

• Differential Data Strobe (DQS, DQS)

• Data outputs on DQS, DQS edges when read (edged DQ)

• Data inputs on DQS centers when write(centered DQ)

• On chip DLL align DQ, DQS and DQS transition with CK transition

• DM mask write data-in at the both rising and falling edges of the data strobe

• All addresses and contr ol inputs ex cept data, da ta strobe s and data masks latched on the rising edges of the clock

• Programmable CAS latency 3, 4, 5 and 6 supported

• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported

• Programmable burst length 4 / 8 with both nibble sequential and interleave mode

• Internal four bank operations with single pulsed RAS

• Auto refresh and self refresh supported

• tRAS lockout supported

• 8K refresh cycles /64ms

• JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)

• Full strength driver option controlled by EMRS

• On Die Termination supported

• Off Chip Driver Impedance Adjustment supported

• Read Data Strobe supported (x8 only)

• Self-Refresh High Temperature Entry

• Partial Array Self Refresh support

Ordering Information

Part No. Organization Package

HY5PS12421C(L)FP-X* 128Mx4

Lead free**HY5PS12821C(L)FP-X* 64Mx8

HY5PS121621C(L)FP-X* 32Mx16

Note:

1. -X* is the speed bin, refer to the Operation Frequency table for

complete Part No.

2. Hynix Lead-free products are compliant to RoHS.

Operating Frequency

Speed Bin tCK(ns) CL tRCD tRP Unit

E3 5333

Clk

C4 3.75 4 4 4 Clk

Y5 3555

Clk

S5 2.5 5 5 5 Clk

S6 2.5 6 6 6 Clk

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1.2 Pin Configuration & Address Table

128Mx4 DDR2 Pin Configuration(Top view: see balls through package)

3

VSS

DM

VDDQ

DQ3

VSS

WE

BA1

A1

A5

A9

NC

2

NC

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A3

A7

A12

1

VDD

NC

VDDQ

NC

VDDL

NC

VSS

VDD

A

B

C

D

E

F

G

H

J

K

L

7

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

CAS

A2

A6

A11

NC

8

DQS

VSSQ

DQ0

VSSQ

CK

CS

A0

A4

A8

A13

9

VDDQ

NC

VDDQ

NC

VDD

ODT

VDD

VSS

ROW AND COLUMN ADDRESS TABLE

ITEMS 128Mx4

# of Bank 4

Bank Address BA0, BA1

Auto Precharge Flag A10/AP

Row Address A0 - A13

Column Address A0-A9, A11

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64Mx8 DDR2 PIN CONFIGURATION(Top view: see balls through package)

3

VSS

DM, RDQS

VDDQ

DQ3

VSS

WE

BA1

A1

A5

A9

NC

2

NU, RDQS

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A3

A7

A12

1

VDD

DQ6

VDDQ

DQ4

VDDL

NC

VSS

VDD

A

B

C

D

E

F

G

H

J

K

L

7

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

CAS

A2

A6

A11

NC

8

DQS

VSSQ

DQ0

VSSQ

CK

CS

A0

A4

A8

A13

9

VDDQ

DQ7

VDDQ

DQ5

VDD

ODT

VDD

VSS

ROW AND COLUMN ADDRESS TABLE

ITEMS 64Mx8

# of Bank 4

Bank Address BA0, BA1

Auto Precharge Flag A10/AP

Row Address A0 - A13

Column Address A0-A9

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32Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)

3

VSS

UDM

VDDQ

DQ11

VSS

WE

BA1

A1

A5

A9

NC

2

NC

VSSQ

DQ9

VSSQ

VREF

CKE

BA0

A10

A3

A7

A12

1

VDD

DQ14

VDDQ

DQ12

VDDL

NC

VSS

VDD

A

B

C

D

J

K

L

M

N

P

R

7

VSSQ

UDQS

VDDQ

DQ10

VSSDL

RAS

CAS

A2

A6

A11

NC

8

UDQS

VSSQ

DQ8

VSSQ

CK

CS

A0

A4

A8

NC

9

VDDQ

DQ15

VDDQ

DQ13

VDD

ODT

VDD

VSS

LDM

VDDQ

DQ3

NC

VSSQ

DQ1

VSSQ

VDD

DQ6

VDDQ

DQ4

E

F

G

H

VSSQ

LDQS

VDDQ

DQ2

LDQS

VSSQ

DQ0

VSSQ

VDDQ

DQ7

VDDQ

DQ5

ROW AND COLUMN ADDRESS TABLE

ITEMS 32Mx16

# of Bank 4

Bank Address BA0, BA1

Auto Precharge Flag A10/AP

Row Address A0 - A12

Column Address A0-A9

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1.3 PIN DESCRIPTION

PIN TYPE DESCRIPTION

CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK. Output

(read) data is referenced to the crossings of CK and CK (both directions of crossing).

CKE Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for

SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. After VREF has

become stable during the power on and initialization sequence, it must be maintained

for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF

must be maintained to this input. CKE must be maintained high throughout READ and

WRITE accesses. Input buf fers, excluding CK, CK and CKE ar e disabled during POWER

DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.

CS Input Chip Select : All commands are masked when CS is registered HIGH. CS provides for

external bank selection on systems with multiple banks. CS is considered part of the

command code.

ODT Input

On Die Termination Control : ODT(registered HIGH) enables on die termination resis-

tance internal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS,

DQS, RDQS, RDQS, and DM signal f or x4 ,x8 con figur ations. For x16 configu r ation OD T

is applied to each DQ, UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin

will be ignored if the Extended Mode R egister(EMRS(1)) is pr ogrammed to disable OD T.

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being

entered.

DM

(LDM, UDM) Input

Input Data Mask : DM is an input mask signal for write data. Input Data is masked

when DM is sampled High coincident with that input data during a WRITE access. DM

is sampled on both edges of DQS, Although DM pins are input only, the DM loading

matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/ RDQS is

enabled by EMRS command.

BA0 - BA2 Input

Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied(For 256Mb and 512Mb, BA2 is not applied). Bank

address also determines if the mode register or extended mode register is to be

accessed during a MRS or EMRS cycle.

A0 -A15 Input

Address Inputs: Provide the row address for ACTIVE commands, and the column

address and AUTO PRECHARGE bit for READ/WRITE commands to select one location

out of the memory array in the respective bank. A10 is sampled during a precharge

command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all

banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0-

BA2. The address inputs also provide the op code during MODE REGISTER SET com-

mands.

DQ Input/

Output Data input / output : Bi-directional data bus

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PIN TYPE DESCRIPTION

DQS, (DQS)

(UDQS),(UDQS)

(LDQS),(LDQS)

(RDQS),(RDQS)

Input/

Output

Data Strobe : Output with read data, input with write data. Edge aligned with read data,

centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS

corresponds to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can

be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS,

UDQS, and RDQS may be used in single ended mode or paired with optional comple-

mentary signals DQS, LDQS,UDQS and RDQS to provide diff erential pair signaling to the

system during both reads and wirtes. An EMRS(1) control bit enables or disables all

complementary data strobe signals.

In this data sheet, "diff erential DQS signals" ref ers to an y of the following with A10 = 0

of EMRS(1)

x4 DQS/DQS

x8 DQS/DQS if EMRS(1)[A11] = 0

x8 DQS/DQS, RDQS/RDQS, if EMRS(1)[A11] = 1

x16 LDQS/LDQS and UDQS/UDQS

"single-ended DQS signals" refers to any of the f ollowing with A10 = 1

of EMRS(1)

x4 DQS

x8 DQS if EMRS(1)[A11] = 0

x8 DQS, RDQS, if EMRS(1)[A11] = 1

x16 LDQS and UDQS

NC No Connect : No internal electrical connection is present.

VDDQ Supply DQ Power Supply: 1.8V +/- 0.1V

VSSQ Supply DQ Ground

VDDL Supply DLL Power Supply : 1.8V +/- 0.1V

VSSDL Supply DLL Ground

VDD Supply Power Supply : 1.8V +/- 0.1V

VSS Supply Ground

VREF Supply Reference voltage for inputs for SSTL interface.

-Continue-

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2. Maximum DC Ratings

2.1 Absolute Maximum DC Ratings

2.2 Operating Temperature Condition

Symbol Parameter Rating Units Notes

VDD Voltage on VDD pin relative to Vss - 1.0 V ~ 2.3 V V 1

VDDQ Voltage on VDDQ pin relative to Vss - 0.5 V ~ 2.3 V V 1

VDDL Voltage on VDDL pin relative to Vss - 0.5 V ~ 2.3 V V 1

VIN, VOUT Voltage on any pin relative to Vss - 0.5 V ~ 2.3 V V 1

TSTG Storage Temperature -55 to +100 ℃1, 2

IIInput leakage current; any input 0V VIN VDD;

all other balls not under test = 0V) -2 uA ~ 2 uA uA

IOZ Output leakage current; 0V VOUT VDDQ; DQ

and ODT disabled -5 uA ~ 5 uA uA

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions for extended period s may affect reliability.

2. Storage Temperature is the ca se surface temp eratur e on the center/top s ide of the DRAM. F or the measur ement

conditions. Please refer to JESD51-2 standard.

Symbol Parameter Rating Units Notes

tOPER Operating Temperat ure 0 to 95 °C 1,2

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the mea-

surement conditions, please refer to JESD51-2 standard.

2. At tOPER 85~95℃, Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this

temperature range it must be required an EMRS command to change itself refresh rate.

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3. AC & DC Operating Conditons

3.1 DC Operating Conditions

3.1.1 Recommended DC Operating Conditions (SSTL_1.8)

3.1.2 ODT DC electrical characteristics

Symbol Parameter Rating Units Notes

Min. Typ. Max.

VDD Supply Voltage 1.7 1.8 1.9 V 1

VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 1,2

VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1,2

VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 3,4

VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 5

1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.

2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.

3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the

value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track vari-

ations in VDDQ

4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).

5. VTT of transmitting device must track VREF of receiving device.

PARAMETER/CONDITION SYMBOL MIN NOM MAX UNITS NOTES

Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt1(eff) 60 75 90 ohm 1

Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt2(eff) 120 150 180 ohm 1

Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Rtt3(eff) 40 50 60 ohm 1

Deviation of VM with respect to VDDQ/2 delta VM -6 +6 % 1

Note:

1. Test condition for Rtt measurements

Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH

(ac)) and I(VIL(ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18

Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.

Rtt(eff) = VIH (ac) - VIL (ac)

I(VIH (ac)) - I(VIL (ac))

delta VM = 2 x Vm

VDDQ x 100%- 1

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3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

3.2.2 Input AC Logic Level

3.2.3 AC Input Test Conditions

Note:

1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device

under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising

edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions

and VIH(ac) to VIL(ac) on the negative transitions.

Symbol Parameter Min. Max. Units Notes

VIH(dc) dc input logic high VREF + 0.125 VDDQ + 0.3 V

VIL(dc) dc input logic low - 0.3 VREF - 0.125 V

Symbol Parameter DDR2 400,533 DDR2 667,800 Units Notes

Min. Max. Min. Max.

VIH (ac) ac input logic high VREF +

0.250 -VREF +

0.200 -V

VIL (ac) ac input logic low - VREF - 0.250 - VREF - 0.200 V

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V1

VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1

SLEW Input signa l mini mu m sl ew r at e 1.0 V/ns 2, 3

VDDQ

VIH(ac) min

VREF

VSWING(MAX)

delta TRdelta TF

VIH(dc) min

VIL(dc) max

VIL(ac) max

VSS

Rising Slew = delta TR

VIH(ac) min - VREF

VREF - VIL(ac) max

delta TF

Falling Slew =

< Figure : AC Input Test Signal Waveform>

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3.2.4 Differential Input AC logic Level

3.2.5 Differential AC output parameters

Symbol Parameter Min. Max. Units Notes

VID (ac) ac differential input voltage 0.5 VDDQ + 0.6 V 1

VIX (ac) ac differential cross po i nt volta g e 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS,

LDQS, LDQS, UDQS and UDQS.

2. VID(DC) specifies the input diff er ential voltage |VTR -VCP | required for switching, where VTR is the true input

(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS

or UDQS) level. The minimum value is equal to VIH(DC) - V IL(DC).

Note:

1. VID(AC) specifies the input differential voltage |VT R -VCP | r equir ed f o r swit chin g, whe re VTR is the true in put

signal (such as CK, DQS, LDQS or UDQS ) and VCP is the complementary input signal (such as CK, DQS, LDQS

or UDQS). The minimum value is equal to V IH(AC) - V IL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is

expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must

cross.

Symbol Parameter Min. Max. Units Notes

VOX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1

Note:

1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmi tting device and VOX(AC) is

expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals

must cross.

VDDQ

Crossing point

VSSQ

VTR

VCP

VID VIX or VOX

< Differential signal le vels >

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3.3 Output Buffer Characteristics

3.3.1 Output AC Test Conditions

3.3.2 Output DC Current Drive

Symbol Parameter SSTL_18 Class II Units Notes

VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1

1. The VDDQ of the device under test is referenced.

Symbol Parameter SSTl_18 Units Notes

IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4

IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4

1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ

and VDDQ - 280 mV.

2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280

mV.

3. The dc value of VREF applied to the receiving device is set to VTT

4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test

device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are

delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating

point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement.

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3.3.3 OCD default characteristics

Description Parameter Min Nom Max Unit Notes

Output impedance See full strength default

driver characteristics ohms 1

Output impedance step size for OCD calibration 0 1.5 ohms 6

Pull-up and pull-down mismatch 0 4 ohms 1,2,3

Output slew rate Sout 1.5 - 5 V/ns 1,4,5,6,7,8

Note

1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for

timing,voltage, and

slew rate are no longer applicable if OCD is changed from default settings. Please refer to the Device Operation &

Timing Diagram

of DDR2 for the Full Strength Default Driver Characteristics.

2. Impedance measur ement condition for output source dc current: VDDQ=1. 7V ; VOUT=1420mV ; (VOUT -VD DQ)/Ioh

must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement

conditio n for output sink

dc current: VDDQ = 1. 7V; VOUT = 280mV; VOUT/I ol must be less than 23.4 ohms f or v alues of VOUT b etween 0V

and 280mV.

3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.

4. Slew rate measured from vil(ac) to vih(ac).

5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as

measured from AC to AC. This is guaranteed by design and characterization.

6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/

variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the

OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.

Output Slew rate load:

7. DRAM output slew rate specification applies to 400 , 533 and 667 MT/s speed bins.

8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in

tDQSQ and tQHS specification.

VTT

25 ohms

Output

(Vout) Reference

point

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3.4 IDD Specifications & Test Conditions

IDD Specifications(max)

Note:

1. Low power parts have an extra suffix ‘L’ in part number ; ex) HY5PS1216CLFP-C4

Symbol DDR2 80 0 DDR2 667 DDR2 533 DDR2 400

Units

x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8 x16

IDD0 100 120 90 110 80 100 80 100 mA

IDD1 100 130 90 120 90 110 80 110 mA

IDD2P 88888 8 8 8 mA

IDD2Q 40 40 40 40 30 30 30 30 mA

IDD2N 50 50 40 40 40 40 30 30 mA

IDD3P

F35 35 30 30 30 30 30 30 mA

S12 12 12 12 12 12 12 12 mA

IDD3N 60 60 50 50 50 50 40 40 mA

IDD4W 160 240 140 200 120 170 90 130 mA

IDD4R 140 200 120 170 100 150 80 110 mA

IDD5B 160 165 160 160 150 150 150 150 mA

IDD6

Normal

Power 8888 8 8 8 8 mA

Low Power* 44444 4 4 4 mA

IDD7 230 340 220 320 210 320 210 320 mA

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IDD Test Conditions

(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)

Symbol Conditions Units

IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS =

tRAS min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are

SWITCHING;Data bus inputs are SWITCHING mA

IDD1

Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL

= 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH,

CS is HIGH between valid commands ; Addre ss bus inputs are SWITCHING ; Data pattern is same

as IDD4W

mA

IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING mA

IDD2Q Precharge quiet standby current ; All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH;

Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA

IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other

control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD3P Active power-down current; All banks open; tCK = tCK(IDD);

CKE is LOW; Other control and address bus inputs are STABLE;

Data bus in puts are FLOATING

Fast PDN Exit MRS(12) = 0 mA

Slow PDN Exit MRS(12) = 1 mA

IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP

=tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus

inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),

AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH

between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD4R

Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4,

CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS

is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as

IDD4W

mA

IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is

HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-

ING; Data bus inputs are SWITCHING mA

IDD6 Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING mA

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IDD7

Operating bank interleave read current; All bank interleaving reads, IOUT = 0m A; BL = 4, CL

= CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD),

tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are

STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for

detailed timing conditions

mA

Note:

1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V

(exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade)

2. IDD specifications are tested after the device is properly initialized

3. Input slew rate is specified by AC Parametric Test Condition

4. IDD parameters are specified with ODT disabled.

5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met

with all combinations of EMRS bits 10 and 11.

6. Definitions for IDD

LOW is defined as Vin £ VILAC(max)

HIGH is defined as Vin Š VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)

for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per

clock) for DQ signals not including masks or strobes.

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For purposes of IDD testing, the following parameters are to be utilized

Detailed IDD7

The detailed timings are shown below for IDD7. Changes will be required if timing par ameter changes are made to the

specification.

Legend: A = Active; RA = Read with Autoprecharge; D = Deselect

IDD7: Operating Current: All Bank Interleave Read operation

All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Cont rol

and address bus inputs are STABLE during DESELECTs. IOUT = 0mA

Timing Patterns for 4 bank devices x4/ x8/ x16

-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)

-DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)

-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)

-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)

-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)

-DDR2-800 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D (23 clocks)

-DDR2-800 6/6/6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D (24 clocks)

Speed Bin

(CL-tRCD-tRP)

DDR2-800 DDR2-667 DDR2-533 DDR2-400 Units

5-5-5 6-6-6 5-5-5 4-4-4 3-3-3

CL(IDD) 5 6 5 4 3 tCK

tRCD(IDD) 12.5 15 15 15 15 ns

tRC(IDD) 57.25 60 60 60 55 ns

tRRD(IDD)-x4/x8 7.5 7.5 7.5 7.5 7.5 ns

tRRD(IDD)-x16 10 10 10 10 10 ns

tCK(IDD) 2.5 2.5 3 3.75 5 ns

tRASmin(IDD) 45 45 45 45 40 ns

tRASmax(IDD) 70000 70000 70000 70000 70000 ns

tRP(IDD) 12.5 15 15 15 15 ns

tRFC(IDD)-256Mb 75 75 75 75 75 ns

tRFC(IDD)-512Mb 105 105 105 105 105 ns

tRFC(IDD)-1Gb 127.5 127.5 127.5 127.5 127.5 ns

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3.5. Input/Output Capacitance

4. Electrical Characteristics & AC Timing Specification

( 0 ℃ ≤ TCASE ≤ 95℃; VDDQ = 1.8 V +/- 0.1V; VDD = 1.8V +/- 0.1V)

Refresh Parameters by Device Density

DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin

Parameter Symbol

DDR2- 400

DDR2- 533 DDR2 667 DDR2 800 Units

Min Max Min Max Min Max

Input capacitance, CK and CK CCK 1.0 2.0 1.0 2.0 1.0 2.0 pF

Input capacitance delta , CK and CK CDCK x0.25 x0.25 x0.25 pF

Input capacitance, all other input-only pins CI 1.0 2.0 1.0 2.0 1.0 1.75 pF

Input capacitance delta , all other input-only pins CDI x0.25 x0.25 x0.25 pF

Input/output capacitance, DQ, DM, DQS, DQS CIO 2.5 4.0 2.5 3.5 2.5 3.5 pF

Input/output capacitance d elta, DQ, DM, DQS, DQS CDIO x0.5 x0.5 x0.5 pF

Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units

Refresh to Active

/Refresh command time tRFC 75 105 127.5 195 327.5 ns

Average periodic refresh interval tREFI 0 ℃≤ TCASE ≤85℃ 7.8 7.8 7.8 7.8 7.8 us

85℃ < TCASE ≤95℃ 3.9 3.9 3.9 3.9 3.9 us

Speed DDR2-800D DDR2-800E DDR2-667D DDR2-533C DDR2-400B Units

Bin(CL-tRCD-tRP) 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3

Parameter min min min min min

CAS Latency 56545tCK

tRCD 12.5 15 15 15 15 ns

tRP 12.5 15 15 15 15 ns

tRAS 45 45 45 45 40 ns

tRC 57.25 60 60 60 55 ns

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Timing Parameters by Speed Grade

(Refer to notes for information related to this table at the following pages of this table)

Parameter Symbol DDR2-400 DDR2-533 Unit Note

min max min max

DQ output access time from CK/CK tAC -600 +600 -500 +500 ps

DQS output access time from CK/CK tDQSCK -500 +500 -450 +450 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP min

(tCL,tCH) -min

(tCL,tCH) -ps 11,12

Clock cycle time, CL=x tCK 5000 8000 3750 8000 ps 15

DQ and DM input setup time

(differential strobe) tDS

(base) 150 - 100 -ps 6,7,8,

20

DQ and DM input hold time

(differential strobe) tDH

(base) 275 - 225 -ps 6,7,8,

21

DQ and DM input setup time

(single ended strobe) tDS 25 --25-ps 6,7,8,

20

DQ and DM input hold time

(single ended strobe) tDH 25 --25-ps 6,7,8,

21

Control & Address input pulse width for

each input tIPW 0.6 -0.6-tCK

DQ and DM input pulse width for each

input tDIPW 0.35 -0.35-tCK

Data-out high-impedance time from CK/CK tHZ - tAC max - tAC max ps 18

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps 18

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps 18

DQS-DQ skew for DQS and associated DQ

signals tDQSQ -350-300ps 13

DQ hold skew factor tQHS -450-400ps 12

DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps

First DQS latching transition to associated

clock edge tDQSS -0.25 + 0.25 -0.25 + 0.25 tCK

DQS input high pulse width tDQSH 0.35 -0.35 -tCK

DQS input low pulse width tDQSL 0.35 -0.35;; -tCK

DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK

Mode register set command cycle time tMRD 2 - 2 - tCK

Write pos tamble tWPST 0.4 0.6 0.4 0.6 tCK 10

Write pr eamble tWPRE 0.35 -0.35 -tCK

Address and control input setup time tIS(base) 350 - 250 -ps 5,7,9,

23

Address and control input hold time tIH(base) 475 - 375 -ps 5,7,9,

23

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-Continue-

(Refer to notes for information related to this table at the following pages of this table)

Parameter Symbol DDR2-400 DDR2-533 Unit Note

min max min max

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Active to active command period for 1KB

page size products tRRD 7.5 -7.5-ns 4

Active to active command period for 2KB

page size products tRRD 10 -10-ns 4

Four Active Window for 1KB page size

products tFAW 37.5 -37.5-ns

Four Active Window for 2KB page size

products tFAW 50 -50-ns

CAS to CAS command delay tCCD 2 2tCK

Write recovery time tWR 15 -15-ns

Auto precharge write r ecovery + precharge

time tDAL WR+tRP -WR+tRP -tCK 14

Internal write to read command delay tWTR 10 -7.5-ns 24

Internal read to precharge command delay tRTP 7.5 7.5 ns 3

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 -200 -tCK

Exit precharge power down to any non-

read command tXP 2 - 2 - tCK

Exit active power down to read command tXARD 2 2 tCK 1

Exit active power down to read command

(Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK 1, 2

CKE minimum pulse width

(high and low pulse width) tCKE 33 tCK 27

ODT turn-on delay tAOND 2222tCK

ODT turn-on tAON tAC(min) tAC(max)

+1 tAC(min) tAC(max)

+1 ns 16

ODT turn-on(Power-Down mode) tAONPD tAC(min)+

2

2tCK+

tAC(max)

+1

tAC(min)+

2

2tCK+

tAC(max)

+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max)

+ 0.6 tAC(min) tAC(max)

+ 0.6 ns 17

ODT turn-off (Power-Down mode) tAOFPD tAC(min)+

2

2.5tCK+

tAC(max)

+1

tAC(min)+

2

2.5tCK+

tAC(max)

+1 ns

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after CKE

asynchronously drops LOW tDelay tIS+tCK+t

IH tIS+tCK+t

IH ns 15

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Parameter Symbol DDR2-667 DDR2-800 Unit Note

min max min max

DQ output access time from CK/CK tAC -450 +450 -400 +400 ps

DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP min(tCL,

tCH) -min(tCL,

tCH) -ps 11,12

Clock cycle time, CL=x tCK 3000 8000 2500 ps 15

DQ and DM input setup time tDS(base) 100 - 50 -ps 6,7,8,2

0

DQ and DM input hold time tDH

(base) 175 - 125 -ps 6,7,8,2

1

Control & Address input pulse width for

each input tIPW 0.6 - 0.6 -tCK

DQ and DM input pulse width for each

input tDIPW 0.35 - 0.35 -tCK

Data-out high-impedance time from CK/

CK tHZ - tAC max - tAC max ps 18

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps 18

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps 18

DQS-DQ skew for DQS and associated

DQ signals tDQSQ - 240 -200ps 13

DQ hold skew factor tQHS - 340 -300ps 12

DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps

First DQS latching transition to

associated clock edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK

DQS input high pulse width tDQSH 0.35 -0.35 -tCK

DQS input low pulse width tDQSL 0.35 -0.35 -tCK

DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK

Mode register set command cycle time tMRD 2 - 2 - tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 10

Write preamble tWPRE 0.35 -0.35 -tCK

Address and control input setup time tIS(base) 200 - 175 -ps 5,7,9,2

2

Address and control input hold time tIH(base) 275 - 250 -ps 5,7,9,2

3

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 19

Read posta mble tRPST 0.4 0.6 0.4 0.6 tCK 19

Activate to precharge command tRAS 45 70000 45 70000 ns 3

Active to active command period f or 1KB

page size pr oducts tRRD 7.5 -7.5-ns 4

Active to active command period f or 2KB

page size pr oducts tRRD 10 -10-ns 4

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Parameter Symbol DDR2-667 DDR2-800 Unit Note

min max min max

Four Active Window for 1KB page size

products tFAW 37.5 -37.5 -ns

Four Active Window for 2KB page size

products tFAW 50 -50 -ns

CAS to CAS command delay tCCD 2 2 tCK

Write recovery time tWR 15 -15-ns

Auto precharge write recovery +

precharge time tDAL WR+tRP -WR+tRP -tCK 14

Internal write to read command delay tWTR 7.5 -7.5-ns

Internal read to precharge command

delay tRTP 7.5 7.5 ns 3

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC +

10 ns

Exit self refresh to a read command tXSRD 200 -200 -tCK

Exit precharge power down to any non-

read command tXP 2 - 2 - tCK

Exit active power down to r ead command tXARD 2 2 tCK 1

Exit active power down to r ead command

(Slow exit, Lower power) tXARDS 7 - AL 8 - AL tCK 1, 2

CKE minimum pulse width

(high and low pulse width) tCKE 33tCK

ODT turn-on delay tAOND 2222tCK

ODT turn-on tAON tAC(min) tAC(max)

+0.7 tAC(min) tAC(max)

+0.7 ns 6,16

ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+

tAC(max)+1 tAC(min)

+2 2tCK+

tAC(max)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max)+

0.6 tAC(min) tAC(max)

+0.6 ns 17

ODT turn-off (Power-Down mode) tAOFPD tAC(min)

+2 2.5tCK+

tAC(max)+1 tAC(min)

+2 2.5tCK+

tAC(max)+1 ns

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after

CKE asynchronously drops LOW tDelay tIS+tCK+tI

HtIS+tCK

+tIH ns 15

-Continue-

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General notes, which may apply for all AC parameters

1. Slew Rate Measurement Levels

a. Output slew ra te for fallin g and rising edges is meas ured between VT T - 250 mV and VTT + 250 mV for single ended

signals.

For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS

- DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.

b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for

rising edges and from

VIH(dc) and VIL(ac) for falling edges.

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK =

+500 mV(250mV to -500 mV for falling egdes).

c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between

DQS and DQS for differential strobe.

2. DDR2 SDRAM AC timing reference load

The following figure represents the timing reference load used in defining the relevant timing parameters of the part.

It is not intended to be either a precise repr esentation of the typical sys tem en vironment nor a depiction of the actual

load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing

reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a

coaxial transmission line terminated at the tester electronics).

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing refer-

ence voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS)

signal.

3. DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown below.

4. Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of

the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method

by which the DDR2 SDRAM pin timings are measured is mode dependent. In single

VDDQ

DUT

DQ

DQS

RDQS

Output VTT = VDDQ/2

25Ω

Timing

reference

point

AC Timing Reference Load

VDDQ

DUT DQ

DQS, DQS

RDQS, RDQS

Output VTT = VDDQ/2

25Ω

Test point

Slew Rate Test Load

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VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its comple-

ment, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differen-

tial data strobe mode is disabled via th e EMRS, the complementary pin, DQS, must be tied e xternally to VSS thr ough a

20 ohm to 10 K ohm resistor to insure proper operation.

5. AC timings are for linear signal transitions. See System Derating for other signal transitions.

6. These parameters guarantee device behavior, but they are not necessarily tested on each device.

They may be guaranteed by device design or tester correlation.

7. All voltages referenced to VSS.

8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/

supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage

range specified.

tDS tDS tDH

tWPRE tWPST

tDQSH tDQSL

DQS

D

DMin

DQS/

DQ

DM

tDH

Figure -- Data input (write) timing

DMin DMin DMin

DDD

DQS

VIH(ac)

VIL(ac)

VIH(ac)

VIL(ac)

VIH(dc)

VIL(dc)

VIH(dc)

VIL(dc)

tCH tCL

CK

CK/CK

DQS/DQS

DQ

DQS

tRPST

Q

tRPRE

tDQSQmax

tQH tQH

tDQSQmax

Figure -- Data output (read) timing

QQQ

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Specific Notes for dedicate d AC parameters

1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast

active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower

power value is defined by each vendor data sheet.

2. AL = Additive Latency

3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min)

have been satisfied.

4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency

5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate

values.

6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns.

See System Derating for other slew rate values.

7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a

differen tial slew rate of 2.0 V/ns in differential strobe mode and a slew r ate of 1V/ns in single ended mode. See Syst em

Derating for other slew rate values.

8. tDS and tDH derating table (for DDR2- 400 / 533)

1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value

to the derating value listed in above Table.

Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate b etween the last crossing of VREF(dc) and the

first crossing of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate

line between shaded ‘ VREF(dc) to ac region’, use nominal slew rate for derating value(see Fig a.) If the actual signal is

later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew ra te of a tangent line to

the actual signal from the ac level to dc level is used for derating value(see Fig b.)

Hold(tDH) no minal slew rate for a rising sign al is defined as the slew rate rate between the last crossing of Vil(dc) max and

the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of Vih(dc) min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line

anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to

VREF(dc) level is used for derating value(see Fig d.)

△tD

S

△tD

H

△tD

S

△tD

H

△tD

S

△tD

H

△tD

S

△tD

H

△tD

S

△tD

H

△tD

S

△tD

H

△tD

S

△tD

H

△tD

S

△tD

H

△tD

S

△tD

H

2.0 125 45 125 45 +125 +45 - - - - - - - - - - - -

1.5 83218321+83+219533----------

1.0 00000012122424--------

0.9 - - -11-14-11-141 -213102522 - - - - - -

0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - -

0.7 -------31-42-42-19-7-85-6176--

0.6 ---------43-59-31-47-19-35-7-235-11

0.5 -----------74-89-62-77-50-65-38-53

0.4 - - - - - - - - - - - - -127 -140 -115 -128 -103 -116

t DS, tDH Derating V alu es( AL L u nits in 'ps', No t e 1 app lies to en t ire Table)

1.6 V/n s 1.4 V/n s 1.2 V/n s 1.0 V/ns4.0 V/ns 3.0 V/ns 0.8 V/n s

DQ

Slew

rate

V/ns

DQS, DQS Differential Slew Rat e

2.0 V/ns 1.8 V/ns

Rev. 0.8 / Oct. 2007 28

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/

IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach

VIH/IL(ac).

For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max

and the first crossing of VREF(dc). Hold (tDH) nominal sle w rate for a falling signal is defined as the slew rate between

the last crossing of Vih(dc) min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew

rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the

dc level to VREF(dc) level is used for derating value(see Fig d.)

Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/

IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach

VIH/IL(ac).

For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

Rev. 0.8 / Oct. 2007 29

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

Fig. a Illustration of nominal slew rate for tIS,tDS

CK,DQS

VDDQ

VIH(ac)min

VIH(dc)min

VREF(dc)

VIL(dc)max

VIL(ac)max

Vss

Delta TF Delta TR

VREF to a c

region

nominal

slew rate

nominal

slew rate

tIS,

tDS

VREF(dc)-VIL(ac)max

Setup Slew Rate

Falling Signal =Delta TF VIH(ac)min-VREF(dc)

Setup Slew Rate

Rising Signal =Delta TR

tIH,

tDH tIS,

tDS

tIH,

tDH

CK, DQS

Rev. 0.8 / Oct. 2007 30

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

Fig. -b Illustration of tangent line for tIS,tDS

CK, DQS

VDDQ

VIH(ac)min

VIH(dc)min

VREF(dc)

VIL(dc)max

VIL(ac)max

Vss

Delta TF

Delta TR

VREF to ac

region

tangent

line

Tangent

line

tIS,

tDS

CK, DQS

Nomial

line

nominal

line

Delta TR

Tangent line[VIH(ac)min-VREF(dc)]

Setup Slew Rate

Rising Signal =

Tangent line[VREF(dc)-VIL(ac)max]

Setup Slew Rate

Falling Signal =Delta TF

tIH,

tDH tIS,

tDS

tIH,

tDH

Rev. 0.8 / Oct. 2007 31

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

Fig. -c Illustration of nominal line for tIH, tDH

CK, DQS

VDDQ

VIH(ac)min

VIH(dc)min

VREF(dc)

VIL(dc)max

VIL(ac)max

Vss

Delta TR

nominal

slew rate

nominal

slew rate

tIS,

tDS

VREF(dc)-VIL(dc)max

Hold Slew Rate

Rising Signal =Delta TR VIH(d c)min - V REF(dc)

Hold Slew Rate

Falling Signal =Delta TF

dc to VREF

region

Delta TF

CK, DQS

tIH,

tDH tIS,

tDS

tIH,

tDH

Rev. 0.8 / Oct. 2007 32

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

Fig. -d Illustration of tangent line for tIH , tDH

CK, DQS

VDDQ

VIH(ac)min

VIH(dc)min

VREF(dc)

VIL(dc)max

VIL(ac)max

Vss

Delta TF

tangent

line

Tangent

line

tIS,

tDS

CK, DQS

nominal

line

dc to VREF

region nominal

line

Delta T R

Tangent line[VIH(ac)min-VREF(dc)]

Hold Slew Rate

Falling Signal =Delta TF

Tangent line[VREF(dc)-VIL(ac)max]

Hold Slew Rate

Rising Signal =Delta T R

tIH,

tDH

tIS,

tDS

tIH,

tDH

Rev. 0.8 / Oct. 2007 33

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

9. tIS and tIH (input setup and hold) derating

△tIS △tIH △tIS △tIH △tIS △tIH Units Notes

4.0 +187 +94 +217 +124 +247 +124 ps 1

3.5 +179 +89 +209 +119 +239 +149 ps 1

3.0 +167 +83 +197 +113 +227 +143 ps 1

2.5 +150 +75 +180 +105 +210 +135 ps 1

2.0 +125 +45 +155 +75 +185 +105 ps 1

1.5 +83 +21 +113 +51 +143 +81 ps 1

1.0 +0 0 +30 +30 +60 60 ps 1

0.9 -11 -14 +19 +16 +49 +46 ps 1

0.8 -25 -31 +5 -1 +35 +29 ps 1

0.7 -43 -54 -37 -53 -7 +6 ps 1

0.6 -67 -83 -37 -53 -7 -23 ps 1

0.5 -100 -125 -80 -95 -50 -65 ps 1

0.4 -150 -188 -145 -158 -115 -128 ps 1

0.3 -223 -292 -255 -262 -225 -232 ps 1

0.25 -250 -375 -320 -345 -290 -315 ps 1

0.2 -500 -500 -495 -470 -465 -440 ps 1

0.15 -750 -708 -770 -678 -740 -648 ps 1

0.1 -1250 -1125 -1420 -1095 -1065 TBD ps 1

△tIS △tIH △tIS △tIH △tIS △tIH Units Notes

4.0 +150 +94 +180 +124 +210 +154 ps 1

3.5 +143 +89 +173 +119 +203 +149 ps 1

3.0 +133 +83 +163 +113 +193 +143 ps 1

2.5 +120 +75 +150 +105 +180 +135 ps 1

2.0 +100 +45 +130 +75 +160 +105 ps 1

1.5 +67 +21 +97 +51 +127 +81 ps 1

1.0 0 0 +30 +30 +60 60 ps 1

0.9 -5 -14 +25 +16 +55 +46 ps 1

0.8 -13 -31 +17 -1 +47 +29 ps 1

0.7 -22 -54 +8 -24 +38 +6 ps 1

0.6 -34 -83 -4 -53 -26 -23 ps 1

0.5 -60 -125 -30 -95 0 -65 ps 1

0.4 -100 -188 -70 -158 -40 -128 ps 1

0.3 -168 -292 -138 -262 -108 -232 ps 1

0.25 -200 -375 -170 -345 -140 -315 ps 1

0.2 -325 -500 -295 -470 -265 -440 ps 1

0.15 -517 -708 -487 -678 -457 -648 ps 1

0.1 -1000 -1125 -970 -1095 -940 -1065 ps 1

tIS, tIH Derating Values for DDR2 400, DDR2 533

Command /

Address Slew

rate(V/ns)

2.0 V/nsCK, CK

Differential Slew R ate

1.5 V/ns 1.0 V/ns

Command /

Address Slew

rate(V/ns)

tIS, tIH Derating Values for DDR2 667, DDR2 800

CK, CK Differential Slew Rate

2.0 V/ns 1.5 V/ns 1.0 V/ns

Rev. 0.8 / Oct. 2007 34

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value to

the derating value listed in above Table.

Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first

crossing of VIH(ac)min. Setup(tIS) nominal slew r ate for a falling signal is de fined as the slew rate betwee n the last crossing

of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate for line

between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value(see fig a.) If the actual signal is later than

the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual

signal from the ac level to dc level is used for derating value(see Fig b.)

Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the

first crossing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last cross-

ing of VREF(dc). If the actual signal signal is always later than the nominal slew rate line between shaded ‘dc to VREF(dc)

region’, use nominal slew rate for derating value(see Fig.c) If the actual signal is earlier than the nominal slew rate line any-

where between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to

VREF(dc) level is used for derating value(see Fig d.)

Although for slow rates the total setup time might be negative(i.e. a v alid input signal will not ha ve reached V IH/IL(ac) at the

time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).

For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the

device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). F or example, t CL and t CH

are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due to

crosstalk (tJIT(crosstalk)) into the clock traces.

12. t QH = t HP – t QHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock

low ( tCH, tCL).

tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition,

both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel

variation of the output drivers.

13. tDQSQ: Consists of data pin sk ew and output patt ern eff ects, and p-channel to n- channel va riation of the ou tput drivers

as well as output slew rate mismatch between DQS/ DQS and associated DQ in a ny given cycle.

14. DAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up. WR ref e rs to the tWR parameter stored in the MRS.

For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the

application clock period.

Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.

tDAL = 4 + (15ns/3.75ns) clocks = 4+(4) clocks = 8 clocks.

15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock

frequency change during precharge power-down, a specific procedure is required as described in section 2.9.

16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

Rev. 0.8 / Oct. 2007 35

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

17. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters ar e re fer enced

to a specific vo ltage le ve l which sp ecifies when the device output is no longer driving(tHZ), or begins driving (tLZ).

Below figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ)

by measuring the signal at two diffe rent voltages. The actual voltage measurement points a re not critical as long as

the calculation is consistenet.

19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device

output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to calculate these

points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows a method to

calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the

signal at two different v oltages. The actual voltage meas urement points are not critical as long as the calculation is

consistent.

20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input signal

crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal

crossing at the VIL(ac) level to the diff erential data strobe cr osspoint for a f alling signal applied to the device under

test.

21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal

crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to the

differential data strobe crosspoint for a falling signal applied to the device under test.

22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling

signal applied to the device under test.

23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling

signal applied to the device under test.

tHZ , tRPST end point = 2*T1-T2 tLZ , tRPRE begin point = 2*T1-T2

VOH + xmV

VOH + 2xmV

VOL + 1xmV

VOL + 2xmV

tHZ

tRPST end po int

VTT + 2xmV

VTT + xmV

VTT -xmV

VTT - 2xmV

tHZ

tRPRE begin point

DQS

VDDQ

VIH(ac)min

VIH(dc)min

tDHtDS

DQS

VREF(dc)

VSS

VIL(dc)max

VIL(ac)max

tDHtDS

Differential Input waveform timing

Rev. 0.8 / Oct. 2007 36

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

24. tWTR is at least two clocks (2*tCK) independent of operation frequency.

25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal

crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a

rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing

VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be

monotonic between VIL(dc)max and VIH(dc) min.

26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal

crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a

rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing

VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be

monotonic between VIL(dc) max and VIH(dc) min.

27 . tCKE min of 3 clocks means CKE must be registered on three consecutive positiv e clock edges. CKE must remain at

the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition,

CKE may not transition from its valid level during the time period of tIS + 2*tCK + tIH.

DQS

VDDQ

VIH(ac)min

VIH(dc)min

tIHtIS

DQS

VREF(dc)

VSS

VIL(dc)ma

x

VIL(ac)max

tIHtIS

Rev. 0.8 / Oct. 2007 37

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

5. Package Dimensions

Package Dimension(x4,x8)

60Ball Fine Pitch Ball Grid Array O utl ine

A1 Ball Mark

10.00 +/- 0.10

10.50 +/- 0.10

0.8 x 10 = 8.0

A B C D E F G H J K L

1 2 3

7 8 9

0.34 +/- 0.0 5

1.20 Max.

0.80

0.80 x 8 = 6.40

A1 Ball Mark

<Bottom View> note: all dimension units are Millimeters.

60 - φ0.45 ±0.05

Rev. 0.8 / Oct. 2007 38

1HY5PS12421C(L)FP

1HY5PS12821C(L)FP

1HY5PS121621C(L)FP

Package Dimension(x16)

84Ball Fine Pitch Ball Grid Array O utl ine

A1 Ball Mark

13.00 +/- 0.10

10.50 +/- 0.10

0.8 x 14 = 11.2

A B C D E F G H J K L M N P R

1 2 3

7 8 9

0.34 +/- 0.05

1.20 Max.

0.80

0.80 x 8 = 6.40

A1 Ball Mark 84 - φ0.45 ±0.05

note: all dimension units are Millimeters.