1. General description
The TEA1753T is the third generation of green Switched Mode Power Supply (SMPS)
controller ICs. The TEA1753T combines a controller for Power Factor Correction (PFC)
and a flyback controller. Its high level of integration allows the design of a cost-effective
power supply with a very low number of external components.
The special built-in green functions provide high efficiency at all power levels. This
efficiency applies to quasi-resonant operation at high-power levels, quasi-resonant
operation with valley skipping, as well as reduced frequency operation at lower power
levels. At low-power levels, the PFC switches off to maintain high efficiency.
During low-power conditions, the flyback controller sw itches to freque ncy re duction mode
and limits the peak current to an adjustable minimum value. This mode ensures high
efficiency at low-power and good standby power performance while minimizing audible
noise from the transformer.
The controller is switched to the power-down mode for no-load operation. In this mode,
the controller is shut down for very low standby power applications.
The TEA1753T is a Multi-Chip Module, (MCM), containing two chips. The proprietary
high-voltage BCD800 process which makes direct start-up possible from the rectified
universal mains voltage in an effective and green way. The second low voltage
Silicon On Insulator (SOI) is used for accurate, high-speed protection functions and
control.
The TEA1753T enables the design of highly efficient and reliable supplies with power
requirements of up to 250 W using the minimum number of external components.
Remark: All values provided throughout this data sheet ar e typical values unless
otherwise stated.
TEA1753T
HV start-up DCM/QR flyback controller with integrated
DCM/QR PFC controller
Rev. 3 — 24 August 2012 Product data sheet
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 2 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
2. Features and benefits
2.1 Distinctive features
Integrated PFC and flyback controller
Universal mains supply operation (70 V (AC) to 276 V (AC))
Dual-boost PFC with accurate maximum output voltage (NXP patented)
High level of integration, resulting in a very low external component count and a
cost-effective design
Adjustable PFC switch off delay
2.2 Green features
On-chip start-up current source
Power down functionality for very low standby power
2.3 PFC green features
Valley/Zero Voltage Switching (ZVS) for minimum switching losses (NXP patented)
Frequency limitation to reduce switching losses
PFC is switched off when a low load is detected at the flyback output
2.4 Flyback green features
Valley switching for minimum switching losses (NXP patented)
Frequency reduction with adjustable minimum peak current at low-power operation to
maintain high efficiency at low output power levels
2.5 Protection features
Safe restart mode for system fault conditions
Continuous mode protection with demagnetization dete ctio n for both converter s (NXP
patented)
UnderVoltage Protection (UVP) (foldback during overload)
Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback
converter)
Mains voltage independent OverPower Protection (OPP)
Open control loop protection for both converters. The open-loop protection on the
flyback converter is safe restart
OverTemperature Protection (OTP)
Low and adjustable OverCurrent Protection (OCP) trip level for both converters
General-purpose latched protection input for system OverTemperature Protection
(OTP) for example
3. Applications
The device is used in all applications requiring an efficient and cost-effective power
supply solutions up to 250 W. Notebook adapters in particular benefit from the high
level of integration
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 3 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
TEA1753T SO16 plastic small outl ine package; 16 leads; body width 3.9 mm SOT109-1
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 4 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
5. Block diagram
Fig 1. Block diagram
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TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 5 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration: TEA1753T (SOT109-1)
TEA1753T
V
CC
HV
GND HVS
FBCTRL PFCTIMER
FBAUX FBDRIVER
LATCH PFCDRIVER
PFCCOMP PFCSENSE
VINSENSE FBSENSE
PFCAUX VOSENSE
001aan780
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
VCC 1 supply voltage
GND 2 ground
FBCTRL 3 flyback control input
FBAUX 4 auxiliary winding input for demagnetization timing and flyback OVP
LATCH 5 general-purpose protection input
PFCCOMP 6 frequency compensation pin for PFC
VINSENSE 7 mains voltage sense input
PFCAUX 8 auxiliary winding input for demagnetization timing for PFC
VOSENSE 9 sense input for PFC output voltage
FBSENSE 10 flyback current sense input
PFCSENSE 11 PFC current sense input
PFCDRIVER 12 PFC gate-driver output
FBDRIVER 13 flyback gate-driver output
PFCTIMER 14 delay timer pin for PFC on/off control
HVS 15 high-voltage safety spacer, not connected
HV 16 high-voltage start-up / flyback valley sensing
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 6 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
7. Functional description
7.1 General control
The TEA1753T contains a controller for a power factor correction circuit as well as a
controller for a flyback circuit. The typical configuration is shown in Figure 3.
7.1.1 Start-up and UnderVoltage LockOut (UVLO)
Initially, the cap acitor on the VCC pin is charged from the high-voltage mains using the HV
pin.
When VCC is less than Vtrip, the charge current is low. This low current protects the IC if
the VCC pin is shorted to grou nd. To ensure a s hort start-up time, the charge current above
Vtrip is increased until VCC reaches Vth(UVLO). When VCC is between Vth(UVLO) and Vstartup,
the charge current goes low again to ensure a low safe restart duty cycle during fault
conditions.
The control logic activates the internal circuitry and switches off the HV charge current
when the voltage on the VCC pin passes the Vstartup level. First, the LATCH pin current
source is activated and the soft-start capacitors on the PFCSENSE and FBSENSE pins
are charged. Also the clamp circuit on the PFCCOMP pin is activated.
The PFC circuit is activated when the following conditions are met:
•the LATCH pin voltage exceeds the Ven(LATCH) voltage
•the PFCCOMP pin voltage reaches the Ven(PFCCOMP) voltage
•the soft-start capacitor on the PFCSENSE pin is charged
Fig 3. TEA1753T typical configuration
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TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 7 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
If the soft-start capacitor on the FBSENSE pin is charged, the flyback converter is also
activated. The flyback converter output voltage is then regulated to its nominal output
voltage. The auxiliary winding of the flyback converter takes over the IC supply. See
Figure 4.
If during start-up the LATCH pin does not reach the Ven(LATCH) level before VCC reaches
Vth(UVLO), it is deactivated. The charge current is then switched on again.
When the flyback converter starts, VFBCTRL is monitored. If this output voltage does not
reach its intended regulation level within a specified time, the voltage on the FBCTRL pin
reaches the Vto(FBCTRL) level. An error is then assumed and a safe restart is initiated.
When one of the protection functions is activated, both converters stop switching and the
VCC voltage drops to Vth(UVLO). A latched protection recharges capacitor CVCC using the
HV pin, but does not restart the converters. To provide safe restart protection, the
capacitor is recharged using the HV pin and the device restarts (see block diagram,
Figure 1).
If OVP of the PFC circuit (VVOSENSE >V
OVP(VOSENSE)) occurs, the PFC controller stops
switching until the VOSENSE pin voltage drops to less than VOVP(VOSENSE). If a mains
undervoltage is detected, VVINSENSE <V
stop(VINSENSE), the PFC controller stops switching
until VVINSENSE >V
start(VINSENSE) again.
When the voltage on the VCC pin drops below the undervoltage lockout level, both
controllers stop switching and re-ente r the safe rest art mode. In the safe rest art mode, the
driver outputs are disabled and the VCC pin voltage is recharged using the HV pin.
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 8 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
7.1.2 Power down
The power-down mode is activated for very low st andby power applications by pulling the
VINSENSE pin below the Vth(pd) level. The TEA1753T stops switching an d the safe rest art
protection is activated. The high-voltage start-up current source is also disabled during
power-down, so the TEA1753T does not restart until the VINSENSE pin voltage is raised
again. During power down all internal circuitry is disabled except for a voltage detection
circuit on the VINSENSE pin. This circuit is supplied by the HV pin and draws 16 A from
the HV pin for biasing.
If the VINSENSE pin is pulled low, a latched protection is also reset (see Section 7.1.5).
Fig 4. Start-up sequence, normal operation and restart sequence
V
CC
LATCH
PROTECTION
PFCSENSE
PFCDRIVER
FBSENSE
FBDRIVER
FBCTRL
VOSENSE
V
O
charging VCC
capacitor starting
converters normal
operation protection restart
soft start
soft start
I
HV
V
start(VINSENSE)
V
to(FBCTRL)
V
startup
V
th(UVLO)
V
trip
V
en(LATCH)
V
start(fb)
VINSENSE
014aaa744
PFCCOMP V
en(PFCCOMP)
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 9 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
7.1.3 Supply management
All internal refere nce voltages are d eri ved fro m a temp eratur e comp en sate d an d trim med
on-chip band gap circuit. Internal reference currents are derived from a temperature
compensated and trimmed on-chip current reference circuit.
7.1.4 Latch input
The LATCH pin is a general-p urpose input pin, which is used to switch of f both converters.
The pin sources a current IO(LATCH) of 80 A. Switching is stopped as soon as the voltage
on the latch drops below 1.25 V.
At initial start-up, switching is prevented until the capacitor on the LATCH pin is charged
above 1.35 V. No internal filtering is done on this pin. An internal Zener clamp of 2.9 V
protects this pin from excessive voltages.
7.1.5 Fast latch reset
In a typical application, the mains is interrupted briefly to reset the latched protection . The
PFC bus capacitor, Cbus, does not have to discharge for this latched protection to re set.
When the VINSENSE voltage drops below 750 mV and is then raised to 870 mV, the
latched protection is reset.
The latched protection is also reset by removing the voltage from the VCC and HV pins.
7.1.6 Overtemperature protection
An accurate internal temperature protection is provided in the circuit. When the junction
temperature exceeds the thermal shut-down temperature, the IC stops switching. While
OTP is active, the capacitor CVCC is not recharged from the HV mains. If the VCC supply
voltage is not sufficient, the OTP circuit is supplied from the HV pin.
OTP is a latched protection. It is reset by removing the voltage from the VCC and HV pins
or by the fast latch reset function (see Section 7.1.5).
7.2 Power factor correction circuit
The power factor correction circuit operates in quasi-resonant or Discontinuous
Conduction Mode (DCM) with valley switching. The next primary stroke is only started
when the previous secondary str oke has ended and the volt age across the PFC MOSFET
has reached a minim u m va lu e . VPFCAUX is used to detect transformer demagnetization
and the minimum voltage across the external PFC MOSFET switch.
7.2.1 ton control
The power factor correcti on circuit is operate d in ton control. The resulting mains harmonic
reduction is well within the class-D requirements.
7.2.2 Valley switching and demagnetization (PFCAUX pin)
The PFC MOSFET is switched on af ter the tr ansformer is dem agnetized. Internal circuitr y
connected to the PFCAUX pin detect s the en d of the secondary stroke. It also detect s the
voltage across the PFC MOSFET. To reduce switching losses and electromagnetic
Interference (EMI) (valley switching), the next stroke is started if the voltage across the
PFC MOSFET is at its minimum.
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 10 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
If a demagnetization signal is not detected on the PFCAUX pin, the contro ller genera tes a
Zero-current Signal (ZCS), 50 s after the last PFCGATE signal.
If a valley signal is not detected on the PFCAUX pin, the controller generates a valley
signal 4 s after demagnetization is detected.
To protect the internal circuitry during lightning events, for example, add a 5 k series
resistor to PFCAUX. To prevent incorrect switching due to external disturbance, place the
resistor close to the IC on the printed-circuit board.
7.2.3 Frequency limitation
To optimize the transformer and minimize switching losses, the switching frequency is
limited to fsw(PFC)max. If the frequency for quasi -resonant op eration is above the fsw(PFC)max
limit, the system switches over to DCM. The PFC MOSFET is only switched on at a
minimum voltage acro ss th e s witch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)
The equation for the transfer function of a power factor corrector contains the square of
the mains input voltage. In a typical application, this results in a low bandwidth for low
mains input voltages and a high bandwidth for high mains input voltages.
To compensate for the mains input volt age influence, the TEA1753T co nt ains a corre ction
circuit. The average input voltage is measured using the VINSENSE pin and the
information is fed to an internal compensation circuit. Using this compensation, it is
possible to keep the regulation loop bandwidth constant over the mains input range. This
feature yields a fast transient response on load steps, while still complying with class-D
MHR requirements.
In a typical application, a resistor and two capacitors connected to the PFCCOMP pin set
the bandwidth of the regulation loop.
7.2.5 Soft-start-up (PFCSENSE pin)
To prevent audible transformer noise at start-up or during hiccup, the soft-start function
slowly increases the transformer p eak current. This increase is achieved by inserting RSS1
and CSS1 between the PFCSENSE pin and the current sense resistor RSENSE1.
An internal current source charges the capacitor to:
(1)
The voltage is limited to Vstart(soft)PFC.
The start level and the time constant of the increasing primary current level is adjusted
externally by changing the values of RSS1 and- CSS1.
(2)
The charging current I start(soft)PFC flows as long as VPFCSENSE is below 0.5 V. If VPFCSENSE
exceeds 0.5 V, the soft-start current source starts limiting current Istart(soft)PFC. When the
PFC starts switching, the Istart(soft)PFC current source is switched off; see Figure 5.
VPFCSENSE Istart softPFC RSS1
=
soft s–tart 3 RSS1 CSS1
=
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 11 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
7.2.6 Low-power mode
When the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches over to frequency reduction mode. When the maximum switching
frequency of the flyback drops below 48 kHz, the power factor correction circuit is
switched off to maint ain high efficiency. Connect a capacitor to the PFCTIMER pin to delay
switching off (see Section 7.2.7).
During low-power mod e operation, the PFCCOMP pin is clampe d to a minimum voltage o f
3.5 V or 2.5 V and a maximum voltage of 3.9 V. The lower clamp voltage depends on the
voltage on VINSENSE pin. This voltage limits the maximum power that is delivered when
the PFC is switched on again . The upper clamp volt age ensures that the PFC retur ns from
low-power mode to its normal regulation point in a limited time.
When the flyback converter frequency exceeds 86 kHz, the power factor correction circuit
restores normal operation.
7.2.7 PFC off delay (PFCTIMER pin)
When the flyback converter maximum frequency drops below 48 kHz, the PFC is
switched off. The IC then outputs a 5 A current to the PFCTIMER pin. When the voltage
on the PFCTIMER pin reaches 3.6 V, the PFC is switched off by performing a soft-stop.
When the flyback converter frequency exceeds 86 kHz, a switch discharges the
PFCTIMER pin capa citor. When the volt age on the PCTIMER pin dr op s below 1.27 V, the
PFC is switched on (see Figure 6).
Fig 5. Soft-start-up of PFC
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TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 12 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
7.2.8 Dual-boost PFC
The mains input voltage modulates the PFC output voltage. The mains input voltage is
measured using the VINSENSE pin. If the voltage on the VINSENSE pin drops below
2.2 V, the current is sourced from the VOSENSE pin. To ensure the stable switch-over, a
200 mV transition region is inserted around the 2.2 V, see Figure 7.
At low VINSENSE input voltages, the output current is 8 A. This output current, in
combination with the re sist or s on the VOSENSE pin, sets the lower PFC output voltage
level at low mains voltages. At high mains input voltages, the current is switched to zero.
The PFC output voltage is then at its maximum. As this current is zero in this situation, it
does not affect the accuracy of the PFC output voltage.
To ensure proper switch-of f, the VOSENSE current switches to its maximum value of 8 A
when the voltage on the VOSENSE pin drops below 2.1 V.
7.2.9 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor, RSENSE1, on the source of the exte rnal MOSFET. The voltage is
measured using the PFCSENSE pin.
7.2.10 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, the voltage on the
VINSENSE pin is continuously sensed. When the voltage on this pin drops below the
Vstop(VINSENSE) level, switching of the PFC is stopped.
7.2.11 Overvoltage protection (VOSENSE pin)
To prevent output overvoltage during load steps and mains transients, an overvoltage
protection circuit is built in.
When the volt age on the VOSENSE pin exceeds the VOVP(VOSENSE) level, switching of the
power factor correction circui t is prevented. Switching of the PFC recommences when the
VOSENSE pin voltage drops below the VOVP(VOSENSE) level again.
When the resistor between the VOSENSE pin and ground is open, the overvoltage
protection is also triggered.
Fig 7. Voltage to current transfer function for dual boost PFC
V
VINSENSE
I
I(VOSENSE) 014aaa097
−8 μA
2.2 V
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 13 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
7.2.12 PFC open-loop protection (VOSENSE pin)
The power factor correction circuit does not start switching until the voltage on the
VOSENSE pin is above the Vth(ol)(VOSENSE) level. This feature protects the circuit from
open-loop and VOSENSE short-circuit.
7.2.13 Driver (PFCDRIVER pin)
The driver circuit to the gate of the power MOSFET has a current sourcing capability of
500 mA and a current sink capability of 1.2 A. These capabilities permit fast turn-on and
turn-off of the power MOSFET for efficient operation.
7.3 Flyback controller
The TEA1753T includes a controller for a flyback converter. The flyback converter
operates in quasi-resonant or DCM with valley switching. The auxiliary winding of the
flyback transformer provides demagnetization detection and powers the IC after start-up.
7.3.1 Multimode operation
The TEA1753T flyback controller operates in several modes; see Figure 8.
At high output power, the converter switches to quasi-resonant mode. The next converter
stroke starts after demagnet iza tio n of th e tra n sfo rm e r an d de te ctio n of the valle y. In
quasi-resonant mode switching losses are minimized. This minimization is ach iev ed by
the converter only switching on when the voltage across the external MOSFET is at its
minimum (see also Section 7.3.2).
To prevent high frequency operation at low loads, the maximum switching frequency is
limited to 125 kHz. When the frequency limit is reached, the quasi-resonant operation
changes to DCM with valley skipping. The frequency limit reduces the MOSFET switch-on
losses and conducted EMI.
Fig 8. Multimode operation flyback
discontinuous
with valley
switching quasi-resonant
PFC off
frequency
reduction
output power
flyback
switching
frequency
014aaa745
PFC on
86 kHz
48 kHz
125 kHz
Ipmin
adjust
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Product data sheet Rev. 3. — 24 August 2012 14 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
A Voltage Controlled Oscillator (VCO) controls the frequency at very low power and
standby levels. The minimum frequency is reduced to zero. During frequency reduction
mode, the primary peak current is kept at an adjustable minimal level to maintain a high
efficiency. As the primary peak current is low in frequency red uction oper ation, no audible
noise is noticeable at switching frequencies in the audible range. Valley switching is also
active in this mode.
In frequency reduction mode, the PFC controller is switched off. The flyback maximum
frequency changes linearly with the control voltage on the FBCTRL pin (see Figure 9).
Hysteresis has been added for stable on and off switching of the PFC. At no-load
operation, the switching frequency is reduced to (almost) zero.
The input voltage of the flyback converter and the capacitance on the drain node of the
flyback power switch affect the frequency reduction slope. By choosing the proper
compensation, the frequency reduction slope for high input voltages are chosen as the
same as for low input voltages. This compensation yields an input voltage independent
PFC switch-on and switch-off power level (see the application information in Section 11).
7.3.2 Valley switching (HV pin)
A new cycle starts when the external MOSFET is switched on. VFBSENSE and VFBCTRL
determine the on-time . The MOSFET is then switched of f and the secondary stroke st arts.
After the secondary stroke, the drain voltage shows an oscillation with a frequency of
approximately:
(3)
Where Lp is the primary self-inductance of the flyback transformer and Cd is the
capacitance on the drain node.
When the internal oscillator voltage is high and the secondary stroke ended, the circuit
waits for the lowest drain voltage before starting a new primary stroke.
Fig 9. Frequency control of flyback
V
FBCTRL
1.5 V
discontinuous
with valley
switching quasi-resonant
frequency
reduction
PFC off
flyback
switching
frequency
014aaa746
PFC on
f
sw(fb)max
f1
2 LpCd

---------------------------------------------------
=
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Product data sheet Rev. 3. — 24 August 2012 15 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
Figure 10 shows the drain voltage, valley signal, secondary stroke signal and the internal
oscillator signal.
Valley switching allows high frequency operation as capacitive switching losses are
reduced, see Equation 4. High frequency operation makes small and cost-effective
magnetic components possible.
(4)
7.3.3 Current mode control (FBSENSE pin)
Current mode control is used for the flyback converter because of its good line regulation.
The FBSENSE pin senses the primary current across an external resistor and comp ares it
with an internal control volt age. The inte rnal control volt age is proportional to the FBCT RL
pin voltage, see Figure 11.
The FBSENSE pin outputs a current of 3 A. This current runs thro ugh the resistors from
the FBSENSE pin to the sense resistor and creates an offset voltage. The minimum peak
current of the flyback is adjusted using this offset voltage. Adjusting the minimum peak
current level changes the frequency reduction slope (see Figure 8).
(1) Start of new cycle at lowest drain voltage.
(2) Start of new cycle in a classical Pulse Width Modulation (PWM) system without valley detection.
Fig 10. Signals for valley switching
P1
2
---CdV2
f=
drain
secondary
stroke
014aaa027
secondary
ringing
primary
stroke
valley
(2) (1)
secondary
stroke
oscillator
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Product data sheet Rev. 3. — 24 August 2012 16 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
7.3.4 Demagnetization (FBAUX pin)
The system is always in QR or DCM mode. The internal oscillator does not start a new
primary stroke until the previous secondary stroke has ended.
Demagnetization features a cycle-by-cycle output short-circuit protection by immediately
lowering the frequency (longer off-time), thus reducing the power level.
Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time of 2 s. This
suppression is necessary at low output voltages and at start-up. It is also required in
applications where the transformer has a large leakage inductance.
If the FBAUX pin is open-circuit or not connected, a fault condition is assumed and the
converter immediately stop s. Oper ation restart s as soon as the fault condition is removed.
7.3.5 Flyback control/time-out (FBCTRL pin)
The FBCTRL pin is connected to an internal voltage source of 3.5 V using an internal
resistor of 3 k. When the voltage on this pin exceeds 2.5 V, the connection is disabled
and the pin is biased with a small curre nt. If the voltage on this pin exceeds 4.5 V, a fault is
assumed, switching is stopped and a restart is made.
If a capacitor and a resistor are connected in series to this pin, a time-out function is
created to protect against an open control loop. See Figure 12 and Figure 13. The
time-out function is disabled by connecting a resistor (100 k) to ground on the FBCTRL
pin.
If the pin is short-circuited to ground, switching of the flyback controller is prevented.
Under normal operating conditions, the converter regulates the output voltage. The
voltage on the FBCTRL pin then varies between 1.3 V for the minimum output power and
2 V for the maximum output power.
Fig 11. Peak current control of flyback
V
FBCTRL
1.5 V 2.0 V
0.65 V
flyback
frequency
reduction
PFC off
FBSENSE
peak voltage
014aaa747
PFC on
flyback
discontinuous
or QR
flyback
cycle skip
mode
SENSE resistor
peak voltage
FBSENSE
offset voltage
V
sense(fb)max
0.325 V
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Product data sheet Rev. 3. — 24 August 2012 17 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
7.3.6 Soft-start (FBSENSE pin)
To prevent audible transformer noise during start-up, the soft-start function slowly
increases the transformer peak current. This increase is achieved by ins ertin g a re sisto r
and a capacitor between th e FBS E NSE pin and the curr e nt se ns e re sisto r.
An internal current source charges the capacitor to:
(5)
with a maximum of approximately 0.63 V.
The start level and the time constant of the increasing primary current level is adjusted
externally by changing the values of RSS2 and CSS2.
(6)
The soft-start current Istart(soft)fb is switched on as soon as VCC reaches Vstartup. When
VFBSENSE reaches 0.63 V, the flyback converter starts switching.
Fig 12. Time-out protection circuit
Fig 13. Time-out protection (signals), safe restart in the TEA1753T
014aaa049
FBCTRL
2.5 V
4.5 V
30 μA
3 kΩ
3.5 V
time-out
014aaa050
4.5 V
2.5 V
V
FBCTRL
output
voltage intended output
voltage not
reached within
time-out time.
intended output voltage
reached within time-out
time.
restart
VI
start softfb RSS2
=
soft s–tart 3 RSS1 CSS1
=
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Product data sheet Rev. 3. — 24 August 2012 18 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
The charging current Istart(soft)(FB) flows as long as VFBSENSE is less than approximately
0.63 V. If VFBSENSE exceeds 0.63 V, the soft-st art current source st art s limiting the current.
After the flyback converter has started, the soft-start current source is switched off.
7.3.7 Maximum on-time
The flyback controller limits the on-time of the external MOSFET to 40 s. When the
on-time is longer than 40 s, the IC stops switching and enters the safe restart mode.
7.3.8 Overvoltage protection (FBAUX pin)
An output overvoltage protection is implemented i n the GreenChip III series. In the
TEA1753T, the auxiliary voltage is sensed using the current flowing into the FBAUX pin
during the secondary stroke. The auxiliary winding voltage is a well-defined replica of the
output voltage. An internal filter averages voltage spikes.
An internal up-down counter prevents any false OVP detection that occurs during ESD or
lightning events. The internal counter counts up by one when the output volt age exceeds
the OVP trip level within one switching cycle. The internal counter counts down by two
when the output voltage has not exceeded the OVP trip level within one switching cycle.
When the counter has reached eight, the IC assumes a true OVP, sets the latched
protection and switches off both converters.
The converter only restarts after the OVP latch is reset. In a typical application, the
internal latch is reset when the VINSENSE voltage drops below 750 mV a nd is then raised
to 870 mV.
The latched protection is a l so re se t b y rem oving b oth the vo ltage on th e VCC and HV pins.
The demagnetization resistor, RFBAUX sets the output voltage Vo(OVP) at which the OVP
function trips:
(7)
where Ns is the number of secondary turn s and Naux is the number of auxiliary turns of the
transformer. Current Iovp(FBAUX) is internally trimmed.
Fig 14. Soft-start up of flyback.
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Product data sheet Rev. 3. — 24 August 2012 19 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
Accurate OVP detection is made possible by adjusting the value of R FBAUX to the turns
ratio of the transformer.
7.3.9 Overcurrent protection (FBSENSE pin)
The primary peak current in the transformer is measured accurately cycle-by-cycle using
the external sense resistor Rsense2. The OCP circuit limits VFBSENSE to a level set by Vfbctrl
(see Section 7.3.3). The OCP detection is suppressed during the leading-edge blanking
period, tleb, to prevent false triggering due to switch-on spikes.
7.3.10 Overpower protection
During the primary stroke of the flyback converter, the input voltage is measured by
sensing the current drawn from the FBAUX pin.
The current information is used to limit the maximum peak current of the flyback
converter, measured from the FBSENSE pin. The internal compensation is such, that a
maximum output power is realized which is almost independent of the input voltage.
The OPP curve is given in Figure 16.
7.3.11 Driver (FBDRIVER pin)
The driver circuit to the power MOSFET gate has a current sourcing capability of 500 mA
and a current sink capability of 1.2 A. These capabilities permit fast switching of the power
MOSFET, thus ensuring efficient operation.
Fig 15. OCP leading-edge blanking
t
leb
OCP level
V
FBSENSE
t
014aaa022
Fig 16. Overpower protection curve
−360 0−100
014aaa749
0.65
0.46
I
FBAUX
(μA)
V
FBSENSE
(V)
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Product data sheet Rev. 3. — 24 August 2012 20 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
8. Limiting values
Table 3. Limiting va lues
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Voltages
VCC supply voltage 0.4 +38 V
VLATCH voltage on the LATCH pin current limited 0.4 +5 V
VFBCTRL voltage on the FBCTRL pin 0.4 +5 V
VPFCCOMP voltage on the PFCCOMP
pin 0.4 +5 V
VVINSENSE voltage on the VINSENSE
pin 0.4 +5 V
VVOSENSE voltage on the VOSENSE
pin 0.4 +5 V
VPFCAUX voltage on the PFCAUX pin 25 +25 V
VFBSENSE voltage on the FBSENSE pin current limited 0.4 +5 V
VPFCSENSE voltage on the PFCSENSE
pin current limited 0.4 +5 V
VPFCTIMER voltage on the PFCTIMER
pin 0.4 +5.5 V
VHV voltage on the HV pin 0.4 +650 V
Currents
IFBCTRL current on the FBCTR L pi n 30 mA
IFBAUX current on the FBAUX pin 1+1mA
IPFCSENSE current on the PFCSENSE
pin 1+10mA
IFBSENSE current on the FBSENSE pin 1+10mA
IFBDRIVER current on the FBDRIVER
pin duty cycle < 10 0.8 +2 A
IPFCDRIVER current on the PFCDRIVER
pin duty cycle < 10 0.8 +2 A
IHV current on the HV pin - 8 mA
General
Ptot total power dissipation Tamb <75C-0.6W
Tstg storage temperature 55 +150 C
Tjjunction temperature 40 +150 C
ESD
VESD electrostatic discharge
voltage class 1
human body
model
pins 1 to 13 [1] -2000V
pin 16 (HV) [1] -1500V
machine mode l [2] -200V
charged device
model -500V
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Product data sheet Rev. 3. — 24 August 2012 21 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
[1] Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[2] Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10 resistor.
9. Thermal characteristics
10. Characteristics
Table 4. Ther mal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from
junction to ambient in free air; JEDEC test board 124 K/W
Rth(j-c) thermal resistance from
junction to case in free air; JEDEC test board 37 K/W
Table 5. Chara cteristics
Tamb =25
C; VCC = 20 V; all voltages are measured with respect to ground; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Start-up current source (HV pin)
IHV current on the HV pin VHV >80V
VCC <V
trip;
Vth(UVLO) <V
CC <V
startup
-1.0-mA
Vtrip <V
CC <V
th(UVLO) -5.4-mA
with auxiliary supply 8 20 40 A
in Power-down mode 5 16 20 A
VBR breakdown voltage 650 - - V
Supply voltage management (VCC pin)
Vtrip trip voltage 0.55 0.65 0.75 V
Vstartup start-up voltage 212223V
Vth(UVLO) undervoltage lockout threshold
voltage 14 15 16 V
Vstart(hys) hysteresis of start voltage during start-up phase - 300 - mV
Vhys hysteresis voltage Vstartup Vth(UVLO) 6.3 7 7.7 V
Ich(low) low charging current VHV >80V; V
CC <V
trip or
Vth(UVLO) <V
CC <V
startup
1.2 1.0 0.8 mA
Ich(high) high charging current VHV >80V; V
trip <V
CC < Vth(UVLO) 4.6 5.4 6.3 mA
ICC(oper) operating supply current no-load on the FBDRIVER and
PFCDRIVER pins 2.25 3 3.75 mA
Input Voltage Sensing PFC (VINSENSE pin)
Vstop(VINSENSE) stop voltage on the VINSENSE
pin 0.85 0.88 0.91 V
Vstart(VINSENSE) st art voltage on the VINSENSE
pin 1.11 1.15 1.19 V
Vmvc(VINSENSE)max maximum mains voltage
compensation voltage on the
VINSENSE pin
4--V
Vflr fast latch reset voltage active after Vth(UVLO) is detected - 0.75 - V
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Product data sheet Rev. 3. — 24 August 2012 22 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
Vflr(hys) hysteresis of fast latch reset
voltage -0.12-V
II(VINSENSE) input current on the VINSENSE
pin VVINSENSE >V
stop(VINSENSE) af te r
Vstart(VINSENSE) is detected 533100nA
Vbst(dual) dual boo st voltage current switch-over point - 2.2 - V
switch-over region - 200 - mV
Vth(pd) power-down threshold voltage 305 355 405 mV
Vhys(pd) power-down hysteresis voltage 55 85 120 mV
Loop compensation PFC (P FCCOM P pi n)
gmtransconductance VVOSENSE to IO(PFCCOMP) 60 80 100 A/V
IO(PFCCOMP) output current on the
PFCCOMP pin VVOSENSE = 2 V 333945A
VVOSENSE = 3.3 V 45 39 33 A
Ven(PFCCOMP) enable voltage on the
PFCCOMP pin VINSENSE Vbst(dual) -3.5-V
VINSENSE < Vbst(dual) -2.5-V
Vclamp(PFCCOMP) clamp voltage on the
PFCCOMP pin Low-power mode; PFC off; lower
clamp voltage. [1]
VINSENSE Vbst(dual) -3.5-V
VINSENSE < Vbst(dual) -2.5-V
Upper clamp voltage - 3.9 - V
Vton(PFCCOMP)zero zero on-time voltage on the
PFCCOMP pin 3.4 3.5 3.6 V
Vton(PFCCOMP)max maximum on-time voltage on
the PFCCOMP pin 1.20 1.25 1.30 V
Pulse-width modulator PFC
ton(PFC) PFC on-time VVINSENSE =3.3V;
VPFCCOMP =V
ton(PFCCOMP)max
3.6 4.5 5 s
VVINSENSE =0.9V;
VPFCCOMP =V
ton(PFCCOMP)max
30 40 53 s
Output voltage sensing PFC (VOSENSE pin)
Vth(ol)(VOSENSE) open-loop threshold voltage on
the VOSENSE pin -1.15-V
Vreg(VOSENSE) regulation voltage on the
VOSENSE pin for IO(PFCCOMP) = 0 2.475 2.500 2.525 V
Vovp(VOSENSE) overvoltage protection voltage
on the VOSENSE pin 2.60 2.63 2.67 V
Ibst(dual) dual boost current VVINSENSE <V
bst(dual) or
VVOSENSE <2.1V -8- A
VVINSENSE >V
bst(dual) -30 - nA
Over current protecti on PFC (PFCSENSE pin)
Vsense(PFC)max maximum PFC sense voltage V/t = 50 mV/s 0.49 0.52 0.55 V
V/t = 200 mV/s 0.51 0.54 0.57 V
tleb(PFC) PFC leading-edge blanking
time 250 310 370 ns
Table 5. Chara cteristics …continued
Tamb =25
C; VCC = 20 V; all voltages are measured with respect to ground; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 3. — 24 August 2012 23 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
Iprot(PFCSENSE) protection current on the
PFCSENSE pin 50 - 5nA
Soft -start PFC (pin PFCSENSE)
Istart(soft)PFC PFC soft-start current 75 60 45 A
Vstart(soft)PFC PFC soft-start voltage enabling voltage 0.46 0.50 0.54 V
Vstop(soft)PFC PFC soft-stop voltage disabling voltage 0.42 0.45 0.48 V
Oscillator PFC
fsw(PFC)max maximum PFC switching
frequency -250-kHz
toff(PFC)min minimum PFC off-time 0.8 1.1 1.4 s
Valley switching PFC (PFCAUX pin)
(V/t)vrec(PFC) PFC valley recognition voltage
change with time --1.7V/s
tvrec(PFC) PFC valley recognition time VPFCAUX = 1 V peak-to-peak [2] --300ns
demagnetization to V/t=0 [3] --50ns
tto(vrec)PFC PFC valley recognition time-out
time 346s
Demagnetization management PFC (PFCAUX pin)
Vth(comp)PFCAUX comparator threshold voltage
on the PFCAUX pin 150 100 50 mV
tto(demag)PFC PFC demagnetization time-out
time 40 50 60 s
Iprot(PFCAUX) protection current on the
PFCAUX pin VPFCAUX =50mV 75 - 5nA
PFC off delay (PFCTIMER pin)
Isource(PFCTIMER) source current on the
PFCTIMER pin -5- A
Isink(PFCTIMER) sink current on the PFCTIMER
pin VPFCTIMER = 5 V - 3.5 - mA
Vstart(PFCTIMER) st art voltage on the PFCTIMER
pin -1.27-V
Vstop(PFCTIMER) stop voltage on the PFCTIMER
pin -3.6-V
Driver (PFCDRIVER pin)
Isrc(PFCDRIVER) source current on the
PFCDRIVER pin VPFCDRIVER =2V - 0.5 - A
Isink(PFCDRIVER) sink current on the
PFCDRIVER pin VPFCDRIVER =2V - 0.7 - A
VPFCDRIVER =10V -1.2-A
VO(PFCDRIVER)max maximum output voltage on the
PFCDRIVER pin 9.5 10.8 12 V
OverVoltage Protection flyback (FBAUX pin)
Iovp(FBAUX) overvoltage protection current
on the FBAUX pin 279 300 321 A
Table 5. Chara cteristics …continued
Tamb =25
C; VCC = 20 V; all voltages are measured with respect to ground; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 3. — 24 August 2012 24 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
Ncy(ovp) number of overvoltage
protection cycles 6812
Demagnetization man agement flyback (FBAUX pin)
Vth(comp)FBAUX comparator threshold voltage
on the FBAUX pin 60 80 110 mV
Iprot(FBAUX) protection current on the
FBAUX pin VFBAUX =50mV 75 - 5nA
Vclamp(FBAUX) clamp voltage on the FBAUX
pin IFBAUX =100 A0.85 0.7 0.55 V
IFBAUX =300A 0.79 0.94 1.09 V
tsup(xfmr_ring) transformer ringing
suppression time 1.5 2 2.5 s
Pulse-width modulator flyback
ton(fb)min minimum flyback on-time - tleb -ns
ton(fb)max maximum flyback on-time 32 40 48 s
Oscillator flyback
fsw(fb)max maximum flyback switching
frequency 100 125 150 kHz
Vstart(VCO)FBCTRL VCO start voltage on the
FBCTRL pin 1.3 1.5 1.7 V
fsw(fb)swon(PFC) PFC switch-on flyback
switching frequency - 86 - kHz
fsw(fb)swoff(PFC) PFC switch-off flyback
switching frequency - 48 - kHz
VVCO(FBCTRL) VCO voltage difference on the
FBCTRL pin -0.12 - V
Peak current control flyback (FBCTRL pin)
VFBCTRL voltage on the FBCTRL pin for maximum flyback peak current 1.85 2 2.15 V
Vto(FBCTRL) time-out voltage on the
FBCTRL pin enable voltage - 2.5 - V
trip voltage 4.2 4.5 4.8 V
Rint(FBCTRL) internal resistance on the
FBCTRL pin -3-k
IO(FBCTRL) output current on the FBCTRL
pin VFBCTRL =0V 1.4 1.19 0.93 mA
VFBCTRL =2V 0.6 0.5 0.4 mA
Ito(FBCTRL) time-out current on the
FBCTRL pin VFBCTRL =2.6V 36 30 24 A
VFBCTRL =4.1V 34.5 28.5 22.5 A
Valley switching flyback (HV pin)
(V/t)vrec(fb) flyback valley recognition
voltage change with time 75 - +75 V/s
td(vrec-swon) valley recognition to switch on
delay time [4] -150-ns
Soft -start flyback (FBSENSE pin)
Istart(soft)fb flyback soft-st art current 75 60 45 A
Vstart(soft)fb flyback sof t-start voltage enable voltage 0.55 0.63 0.70 V
Table 5. Chara cteristics …continued
Tamb =25
C; VCC = 20 V; all voltages are measured with respect to ground; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 3. — 24 August 2012 25 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
[1] Applies to a typical application with a compensation network on the PFCCOMP pin, like the example in Figure 3.
[2] Minimum required voltage change time for valley recognition on the PFCAUX pin.
[3] Minimum time required between demagnetization detection and V/t = 0 on the PFCAUX pin.
[4] Guaranteed by design.
Overcurrent protection flyb ack (FBSENSE pin)
Vsense(fb)max maximum flyback sense
voltage V/t=50mV/s 0.61 0.65 0.69 V
V/t=200mV/s 0.64 0.68 0.72
Vsense(fb)min minimum flyback sense voltage V/t=50mV/s 0.305 0.325 0.345 V
tleb(fb) flyback leading-edge blanking
time 255 305 355 ns
Iadj(FBSENSE) adjust current on the
FBSENSE pin 3.2 32.8 A
Overpower protection flyback (FBSENSE pin)
Vsense(fb)max maximum flyback sense
voltage V/t=50mV/s
IFBAUX =80A 0.61 0.65 0.69 V
IFBAUX =120A 0.57 0.62 0.67 V
IFBAUX =240A 0.47 0.52 0.57 V
IFBAUX =360A 0.41 0.46 0.51 V
Driver (FBDRIVER pin)
Isrc(FBDRIVER) source current on the
FBDRIVER pin VFBDRIVER =2V - 0.5 - A
Isink(FBDRIVER) sink current on the FBDRIVER
pin VFBDRIVER =2V - 0.7 - A
VFBDRIVER =10V -1.2-A
VO(FBDRIVER)(max) maximum output voltage on the
FBDRIVER pin 9.5 10.8 12 V
LATCH input (LATCH pin)
Vprot(LATCH) protection voltage on the
LATCH pin 1.23 1.25 1.27 V
IO(LATCH) output current on the LATCH
pin Vprot(LATCH) <V
LATCH <V
oc(LATCH) 85 80 75 A
Ven(LATCH) enable voltage on the LATCH
pin at start-up 1.30 1.35 1.40 V
Vhys(LATCH) hysteresis voltage on the
LATCH pin Ven(LATCH) Vprot(LATCH) 80 100 140 mV
Voc(LATCH) open-circuit voltage on the
LATCH pin 2.65 2.9 3.15 V
Temperature protection
Tpl(IC) IC protection leve l te mperature 130 140 150 C
Tpl(IC)hys hysteresis of IC protection level
temperature -10-C
Table 5. Chara cteristics …continued
Tamb =25
C; VCC = 20 V; all voltages are measured with respect to ground; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 26 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
11. Application information
A power supply with the TEA1753T consists of a power factor correction circuit and a
flyback converter. See Figure 17.
Capacitor CVCC buffers the IC supply voltage. The IC is powered from the high voltage
rectified mains during start-up and the auxiliary winding of the flyback converter during
operation. Sense resistors RSENSE1 and RSENSE2 convert the curren t through the
MOSFETs S1 and S2 into a voltage at the PFCSENSE and FBSENSE pins. The values of
RSENSE1 and RSENSE2 defin e th e ma xim um pr im ar y pea k cu rr en t in MO SFETs S1 and S2.
In the example given, the LATCH pin is connected to a Negative Temperatur e Coe fficient
(NTC) resistor. The protection is activated when the resistance drops below a value
calculated as follows:
(8)
A capacitor CTIMEOUT is connected to the FBCTRL pin. With a 120 nF capacitor, the
time-out protection is activated after 10 ms. RLOOP is added so that the time-out capacitor
does not interfere with the normal regulation loop.
RS1 and RS2 are added to prevent the soft-start capacitors from being charged during
normal operation due to negative voltage spikes across the sense resistors.
Resistor RAUX1 is added to protect the IC from damage during lightning events.
RS3 and RCOMP are added to compensate for input voltage variations. The (stray)
capacitance on the drain node of MOSFET S3 affects the frequency reduction slope and
therefore the PFC switch-on and switch-off levels. Choosing the proper values for RS3
and RCOMP results in an input voltage independent PFC switch-on and switch-off power
level.
Vprot LATCH
IOLATCH
------------------------------- 15.6 k=
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 27 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
Fig 17. Typical application diag ra m for the TEA1 75 3 T IC
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TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 28 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
12. Package outline
Fig 18. Package outline SOT109-1 (SO16)
X
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θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
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(1) E(1) (1)
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REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 29 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
13. Revision history
Table 6. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TEA1753T v.3 20120824 Product data sheet TEA1753T v.2
Modifications: •Multiple text changes
•Multiple graphic updates
•Updates to several characteristics
TEA1753T v.2 20110408 Product data sheet - TEA1753T v.1
TEA1753T v.1 20110304 Objective data sheet - -
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 30 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby exp ressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
TEA1753T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3. — 24 August 2012 31 of 32
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
GreenChip — is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors TEA1753T
HV start-up flyback controller with integrated PFC controller
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 August 2012
Document identifier: TEA1753T
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2
2.1 Distinctive features. . . . . . . . . . . . . . . . . . . . . . 2
2.2 Green features . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.3 PFC green features . . . . . . . . . . . . . . . . . . . . . 2
2.4 Flyback green features. . . . . . . . . . . . . . . . . . . 2
2.5 Protection features . . . . . . . . . . . . . . . . . . . . . . 2
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 General control. . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.1 Start-up and UnderVoltage LockOut (UVLO) . . 6
7.1.2 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.1.3 Supply management. . . . . . . . . . . . . . . . . . . . . 9
7.1.4 Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.1.5 Fast latch reset. . . . . . . . . . . . . . . . . . . . . . . . . 9
7.1.6 Overtemperature protection . . . . . . . . . . . . . . . 9
7.2 Power factor correction circuit . . . . . . . . . . . . . 9
7.2.1 ton control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2.2 Valley switching and demagnetization
(PFCAUX pin). . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2.3 Frequency limitation . . . . . . . . . . . . . . . . . . . . 10
7.2.4 Mains voltage compensation
(VINSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 10
7.2.5 Soft-start-up (PFCSENSE pin) . . . . . . . . . . . . 10
7.2.6 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 11
7.2.7 PFC off delay (PFCTIMER pin) . . . . . . . . . . . 11
7.2.8 Dual-boost PFC . . . . . . . . . . . . . . . . . . . . . . . 12
7.2.9 Overcurrent protection (PFCSENSE pin) . . . . 12
7.2.10 Mains undervoltage lockout/brownout
protection (VINSENSE pin) . . . . . . . . . . . . . . 12
7.2.11 Overvoltage protection (VOSENSE pin). . . . . 12
7.2.12 PFC open-loop protection (VOSENSE pin) . . 13
7.2.13 Driver (PFCDRIVER pin) . . . . . . . . . . . . . . . . 13
7.3 Flyback controller . . . . . . . . . . . . . . . . . . . . . . 13
7.3.1 Multimode operation. . . . . . . . . . . . . . . . . . . . 13
7.3.2 Valley switching (HV pin) . . . . . . . . . . . . . . . . 14
7.3.3 Current mode control (FBSENSE pin) . . . . . . 15
7.3.4 Demagnetization (FBAUX pin) . . . . . . . . . . . . 16
7.3.5 Flyback control/time-out (FBCTRL pin) . . . . . 16
7.3.6 Soft-start (FBSENSE pin). . . . . . . . . . . . . . . . 17
7.3.7 Maximum on-time. . . . . . . . . . . . . . . . . . . . . . 18
7.3.8 Overvoltage protection (FBAUX pin) . . . . . . . 18
7.3.9 Overcurrent protection (FBSENSE pin) . . . . . 19
7.3.10 Overpower protection. . . . . . . . . . . . . . . . . . . 19
7.3.11 Driver (FBDRIVER pin) . . . . . . . . . . . . . . . . . 19
8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 20
9 Thermal characteristics . . . . . . . . . . . . . . . . . 21
10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21
11 Application information . . . . . . . . . . . . . . . . . 26
12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 28
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 29
14 Legal information . . . . . . . . . . . . . . . . . . . . . . 30
14.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 30
14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15 Contact information . . . . . . . . . . . . . . . . . . . . 31
16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32