SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009
1
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FEATURES
DProgrammable Slope Compensation
DInternal Soft-Start on the UCC38083/4
DCycle-by-Cycle Current Limiting
DLow Start-Up Current of 120 µA and 1.5 mA
Typical Run Current
DSingle External Component Oscillator
Programmable from 50 kHz to 1 MHz
DHigh-Current Totem-Pole Dual Output Stage
Drives Push-Pull Configuration with 1-A Sink
and 0.5-A Source Capability
DCurrent Sense Discharge Transistor to
Improve Dynamic Response
DInternally Trimmed Bandgap Reference
DUndervoltage Lockout with Hysteresis
APPLICATIONS
DHigh-Efficiency Switch-Mode Power Supplies
DTelecom dc-to-dc Converters
DPoint-of-Load or Point-of-Use Power Modules
DLow-Cost Push-Pull and Half-Bridge
Applications
DESCRIPTION
The UCC38083/4/5/6 is a family of BiCMOS pulse width
modulation (PWM) controllers for dc-to-dc or off-line
fixed-frequency current-mode switching power
supplies. The dual output stages are configured for the
push-pull topology. Both outputs switch at half the
oscillator frequency using a toggle flip-flop. The dead
time between the two outputs is typically 110 ns, limiting
each output’s duty cycle to less than 50%.
The new UCC3808x family is based on the UCC3808A
architecture. The major dif ferences include the addition
of a programmable slope compensation ramp to the CS
signal and the removal of the error amplifier. The current
flowing out of the ISET pin through an external resistor
is monitored internally to set the magnitude of the slope
compensation function. This device also includes an
internal discharge transistor from the CS pin to ground,
which is activated at each clock cycle after the pulse is
terminated. This discharges any filter capacitance on
the CS pin during each cycle and helps minimize filter
capacitor values and current sense delay.
The UCC38083 and the UCC38084 devices have a
typical soft-start interval time of 3.5 ms while the
UCC38085 a n d t h e U C C 3 8 0 8 6 has less than 100 µs for
applications where internal soft-start is not desired.
The UCC38083 and the UCC38085 devices have the
turn-on/off thresholds of 12.5 V / 8.3 V, while the
UCC38084 and the UCC38086 has the turn-on/off
thresholds o f 4.3 V / 4.1 V. Each device is offered in 8-pin
TSSOP (PW), 8-pin SOIC (D) and 8-pin PDIP (P)
packages.
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Copyright 2002−2009, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
UDG−01080
BASIC APPLICATION
OUTA
OUTB
CS
CTRL
RT
ISET
GND
VDD
RSET
RT
POWER
TRANSFORMER
CF
RF
RS
VIN
UCC3808x
FEEDBACK
VOUT
SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009
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ORDERING INFORMATION
THERMAL RESISTANCE TABLE
PACKAGE θjc(°C/W) θja(°C/W)
SOIC−8 (D) 42 84 to 160(1)
PDIP−8 (P) 50 110(1)
TSSOP−8 (PW) 32(2) 232 to 257(2)
NOTES: (1) Specified θja (junction to ambient) is for devices mounted to 5-inch2 FR4 PC board
with one ounce copper where noted. When resistance range is given, lower values
are for 5 inch2 aluminum PC board. Test PWB was 0.062 inch thick and typically
used 0.635-mm trace widths for power packages and 1.3-mm trace widths for
non-power packages with a 100-mil x 100-mil probe land area at the end of each
trace.
(2). Modeled data. If value range given for θja, lower value is for 3x3 inch. 1 oz internal
copper ground plane, higher value is for 1x1-inch. ground plane. All model data
assumes only one trace for each non-fused lead.
AVAILABLE OPTIONS
TA
INTERNAL
SOFT START
UVLO PACKAGES
T
A
INTERNAL
SOFT START ON OFF SOIC-8 (D) PDIP-8 (P) TSSOP-8 (PW)
3.5 ms
12.5 V 8.3 V UCC28083D UCC28083P UCC28083PW
−40°C to 85°C
3.5 ms
4.3 V 4.1 V UCC28084D UCC28084P UCC28084PW
−40
°
C to 85
°
C
75 µs
12.5 V 8.3 V UCC28085D UCC28085P UCC28085PW
75
µ
s
4.3 V 4.1 V UCC28086D UCC28086P UCC28086PW
3.5 ms
12.5 V 8.3 V UCC38083D UCC38083P UCC38083PW
0°C to 70°C
3.5 ms
4.3 V 4.1 V UCC38084D UCC38084P UCC38084PW
0
°
C to 70
°
C
75 µs
12.5 V 8.3 V UCC38085D UCC38085P UCC38085PW
75
µ
s
4.3 V 4.1 V UCC38086D UCC38086P UCC38086PW
†The D and PW packages are available taped and reeled. Add R suffix to device type, e.g. UCC28083DR (2500 devices
per reel) or UCC38083PWR (2000 devices per reel).
1
2
3
4
8
7
6
5
CTRL
ISET
CS
RT
VDD
OUTA
OUTB
GND
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
PW PACKAGE
(TOP VIEW)
OUTB
GND
RT
CS
OUTA
VDD
CTRL
ISET
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (IDD < 10 mA) 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply current, IDD 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sink current (peak): OUTA 1.0 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTB 1.0 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source current (peak): OUTA −0.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTB −0.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog inputs: CTRL −0.3 V to VDD +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CS −0.3 V to VDD +0.3 V, not to exceed 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RSET (minimum) >5 kΩ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RT (−100 µA < IRT < 100 µA) −0.3 V to 2.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation at TA = 25°C (P package) 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation at TA = 25°C (D package) 650 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation at TA = 25°C (PW package) 400 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction operating temperature, TJ−55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (soldering 10 seconds) 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND.
Currents are positive into, and negative out of the specified terminal.
electrical characteristics over recommended operating virtual junction temperature range,
VDD = 10 V (See Note 1),1-µF capacitor from VDD to GND, RT = 165 kΩ, RF = 1 kΩ, CF = 220 pF,
RSET = 50 kΩ, TA = −40°C to 85°C for UCC2808x, TA = 0°C to 70°C for UCC3808x, TA = TJ
(unless otherwise noted)
overall
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Start-up current VDD < UVLO start threshold voltage 120 200 µA
Supply current CTRL = 0 V, CS = 0 V,
See Note 1 1.5 2.5 mA
undervoltage lockout
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Start threshold voltage
UCC38083/5 See Note 1 11.5 12.5 13.5
Start threshold voltage UCC38084/6 4.1 4.3 4.5
Minimum operating voltage
UCC38083/5 7.6 8.3 9.0
V
Minimum operating voltage
after start UCC38084/6 3.9 4.1 4.3 V
Hysteresis voltage
UCC38083/5 3.5 4.2 5.1
Hysteresis voltage UCC38084/6 0.1 0.2 0.3
oscillator
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Frequency 2 x f(OUTA) 180 200 220 kHz
Voltage amplitude See Note 2 1.4 1.5 1.6 V
Oscillator fall time (dead time) 110 220 ns
RT pin voltage 1.2 1.5 1.6 V
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electrical characteristics over recommended operating virtual junction temperature range,
VDD = 10 V (See Note 1),1-µF capacitor from VDD to GND, RT = 165 kΩ, RF = 1 kΩ, CF = 220 pF,
RSET = 50 kΩ, TA = −40°C to 85°C for UCC2808x, TA = 0°C to 70°C for UCC3808x, TA = TJ
(unless otherwise noted)
current sense
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Gain See Note 3 1.9 2.2 2.5 V/V
Maximum input signal voltage CTRL = 5 V, See Note 4 0.47 0.52 0.57 V
CS to output delay time CTRL = 3.5 V, 0 mV ≤ CS ≤ 600 mV 100 200 ns
Source current −200 nA
Sink current CS = 0.5 V, RT = 2.0 V,
See Note 5 3 7 12 mA
Overcurrent threshold voltage 0.70 0.75 0.80 V
CTRL to CS offset voltage
CS = 0 V, 25°C 0.55 0.70 0.90 V
CTRL to CS offset voltage CS = 0 V 0.37 0.70 1.10 V
pulse width modulation
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Maximum duty cycle Measured at OUTA or OUTB, See Note 7 48% 49% 50%
Minimum duty cycle CTRL = 0 V 0%
output
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Low-level output voltage (OUTA or OUTB) IOUT = 100 mA 0.5 1.0
V
High-level output voltage (OUTA or OUTB) IOUT = −50 mA, (VDD − VOUT), See Note 6 0.5 1.0 V
Rise time CLOAD = 1 nF 25 60
ns
Fall time CLOAD = 1 nF 25 60 ns
soft-start
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
OUTA/OUTB soft-start interval time,
UCC38083/4 CTRL = 1.8 V, CS = 0 V,
Duty cycle from 0 to full, See Note 8 1.3 3.5 8.5 ms
OUTA/OUTB soft-start interval time,
UCC38085/6 CTRL = 1.8 V, CS = 0 V,
Duty cycle from 0 to full, See Note 8 30 75 110 µs
slope compensation
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
IRAMP, peak ISET, peak = 30 µA,Full duty cycle 125 150 175 µA
NOTE 1: For UCCx8083/5, set VDD above the start threshold before setting to 10 V.
NOTE 2: Measured at ISET pin.
NOTE 3: Gain is defined by A +
DVCTRL
DVCS , 0 ≤VCS ≤ 0.4 V.
NOTE 4: Measured at trip point of latch with CS ramped from 0.4 V to 0.6 V.
NOTE 5: This internal current sink on the CS pin is designed to discharge and external filter capacitor. It is not intended to be a dc sink path.
NOTE 6: Not 100% production tested. Ensured by design and also by the rise time test.
NOTE 7: For devices in PW package, parameter tested at wafer probe.
NOTE 8: Ensured by design.
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functional block diagram
UDG−01081
Q
Q
T
+
8
2
3
4
7
6
5
1CTRL
VDD
CS
ISET
GND
RT
OUTA
OUTB
0.75V
0.5V
1.5V
0.2V
SQ
R
SQ
R
0.5V
Vdd−1
VREF
SQ
R
ISLOPE
Css
Iss
SQ
R
Soft Start and Fault Latch
PWM Comparator/Latch Output Driver
Oscillator
CS Circuitry
Slope Circuit
Bias/UVLO
ISLOPE =
5 x I SET
ICT
CT
1.5V
CT
80 kΩ
60 kΩ
0.3 V
Terminal Functions
TERMINAL
NAME PACKAGE I/O DESCRIPTION
NAME
D OR P
I/O
DESCRIPTION
CS 3 I The current-sense input to the PWM comparator, the cycle-by-cycle peak current comparator, and the
overcurrent comparator. The overcurrent comparator is only intended for fault sensing. Exceeding the
overcurrent threshold causes a soft-start cycle. An internal MOSFET discharges the current-sense filter
capacitor to improve dynamic performance of the power converter.
CTRL 1 I Error voltage input to PWM comparator.
GND 5 − Reference ground and power ground for all functions. Due to high currents, and high-frequency operation
of the IC, a low-impedance circuit board ground plane is highly recommended.
ISET 2 I Current selection for slope compensation.
OUTA 7 O
Alternating high-current output stages.
OUTB 6 O Alternating high-current output stages.
RT 4 I Programs the oscillator.
VDD 8 I Power input connection.
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detailed pin descriptions
CTRL: The error voltage is typically generated by a secondary-side error amplifier and transmitted to the
primary-side referenced UCC3808x by means of an opto-coupler. CTRL has an internal divider ratio of 0.45 to
maintain a usable range with the minimum VDD of 4.1 V. The UCC38083/UCC38084 family features a built-in
full-cycle soft start while the UCC38085/6 does not.
For the UCC38083/4, soft-start is implemented as a clamp at the input to the PWM comparator. This causes
the output pulses to start near 0% duty cycle and increase until the clamp exceeds the CTRL voltage.
ISET: Program the slope compensation current ramp by connecting a resistor, RSET, from ISET to ground. The
voltage of the ISET pin tracks the 1.5-V internal oscillator ramp, as shown in Figure 1.
ISET
IRAMP
OUTA
OUTB
IRAMP, peak = 5 x ISET, peak
1
2
3
4
UCC38083
8
7
6
5
1F
VDD
RT
165 k
220F
10 k
RF
1 k
IRAMP
VCS
CTRL VDD
ISET
CS
RT
OUTA
OUTB
GND
Figure 1. Full Duty Cycle Output
The compensating current source, ISLOPE, at the CS pin is proportional to the ISET current, according to the
relation:
ISLOPE +5 ISET
The ramping current due to ISLOPE develops a voltage across the effective filter impedance that is normally
connected from the current sense resistor to the CS input. In order to program a desired compensating slope
with a specific peak compensating ramp voltage at the CS pin, use the RSET value in the following equation:
RSET +VOSC(peak) ǒ5 RF
RAMP VOLTAGE HEIGHTǓ
Where VOSC(peak) +1.5 V
Notice that the PWM Latch drives an internal MOSFET that will discharge an external filtering capacitor on the
CS pin. Thus, ISLOPE will appear to terminate when the PWM comparator or the cycle-by-cycle current limit
comparator sets the PWM latch. The actual compensating slope is not af fected by premature termination of the
switching cycle.
(1)
(2)
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detailed pin descriptions (continued)
OUT A and OUTB: Alternating high-current output stages. Both stages are capable of driving the gate of a power
MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A peak-sink current.
The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the
internal oscillator capacitor is rising, one of the two outputs is high, but during fall time, both outputs are of f. This
dead time between the two outputs, along with a slower output rise time than fall time, ensures that the two
outputs cannot be on at the same time. This dead time is typically 110 ns.
The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output
stage also provides a very low impedance to overshoot and undershoot. This means that in many cases,
external Schottky clamp diodes are not required.
RT: The oscillator programming pin. The oscillator features an internal timing capacitor. An external resistor,
RT, sets a current from the R T pin to ground. Due to variations in the internal CT, nominal VRT of 1.5 V can vary
from 1.2 V to 1.6 V
Selecting RT as shown programs the oscillator frequency:
RT +1
28.7 10−12 ǒ1
fOSC *2.0 10−7Ǔ
where fOSC is in Hz, resistance in Ω. The recommended range of timing resistors is between 25 kΩ and 698 kΩ.
For best performance, keep the timing resistor lead from the RT pin to GND (pin 5) as short as possible.
UDG−01083
Approximate Frequency +1
28.7 10−12 RT)ǒ2.0 10−7Ǔ
4
1.5 V
0.2 V
SQ
R
IRT ICT
CT
1.5 V
OSCILLATOR
OUTPUT
RT
Figure 2. Block Diagram for Oscillator
VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply
current may be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total
VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating
frequency and the MOSFET gate charge (QG), average OUT current can be calculated from:
IOUT +QG fOSC
where f is the oscillator frequency.
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. A 1-µF decoupling capacitor is recommended.
(3)
(4)
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APPLICATION INFORMATION
The following application circuit shows an isolated 12-VIN to 2.5 VOUT push-pull converter with scalable output
power (20 W to 200 W). Note that the pinout shown is for SOIC-8 and PDIP-8 packages.
typical application
UDG−01084
UCC3808x
7 OUTA
6 OUTB
3CS 1CTRL
4RT
2
ISET
5
GND
8
VDD
CF
220 pF
RS
6
3
1
42
5
165
kΩ
TL431
4.7Ω
4.7Ω
1 µF
SR
DRIVE
VO
= 2.2 V TO 3.3 V
ADJUSTABLE
VIN = 12 V
+/−20%V
RF 1 kΩ
RSET
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APPLICATION INFORMATION
operational waveforms
Figure 3 illustrates how the voltage ramp is effectively added to the voltage across the current sense element
VCS, to implement slope compensation.
UDG−01085
OUTA
OUTB
VRS
ADDED
RAMP
VOLTAGE
VCS, Pin 3
Figure 3. Typical Slope Compensation Waveforms at 80% Duty Cycle
In Figure 3, OUTA and OUTB are shown at a duty cycle of 80%, with the associated voltage VRS across the
current sense resistor of the primary push-pull power MOSFETs. The current flowing out of CS generates the
ramp voltage across the filter resistor RF that is positioned between the power current sense resistor and the
CS pin. This voltage is effectively added to VRS to provide slope compensation at VCS, pin 3. A capacitor CF
is also recommended to filter the waveform at CS.
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layout considerations
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. A 1-µF decoupling capacitor is recommended.
Use a local ground plane near the small signal pins (CTRL, ISET, CS and RT) of the IC for shielding. Connect
the local ground plane to the GND pin with a single trace. Do not extend the local ground plane under the power
pins (VDD, OUTA, OUTB and GND). Instead, use signal return traces to the GND pin for ground returns on the
side of the integrated circuit with the power pins.
For best performance, keep the timing resistor lead from RT pin (pin 4) to GND (pin 5) as short as possible.
special layout considerations for the TSSOP package
Due to the different pinout and smaller lead pitch of the TSSOP package, special attention must be paid to
minimize noise problems. The pinout is dif ferent because the device had to be rotated 90° to fit into the smaller
TSSOP package.
For example, the two output pins are now on opposite sides of the package. The traces should not run under
the package together as they will couple switching noise into analog pins.
Another common problem is when RT and OUTB (pins 6 and 8) are routed together for some distance even
though they are not immediate side by side pins. Because of this, when OUTB rises, a voltage spike of upto
400 mV can couple into the RT. This spike causes the internal charge current into CT to be turned off
momentarily resulting in lower duty cycle. It is also important that note that the RT pin voltage cannot be
stabilized with a capacitor. The RT pin is just a dc voltage to program the internal CT. Instead, keep the OUTB
and RT runs short and far from each other and follow the printed wiring board layout suggestions above to fix
the problem.
reference design
A reference design is discussed in 50-W Push-Pull Converter Reference Design Using the UCC38083, TI
Literature Number SLUU135. This design controls a push-pull synchronous rectified topology with input range
of 18 V to 35 V (24 nominal) and 3.3-V output at 15 A. The schematic is shown in Figure 5 and the board layout
for the reference design is shown in Figure 4. Refer to the document for further details.
Figure 4. Reference Design Layout
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APPLICATION INFORMATION
Note 1. C28, R25, and D12 accelerate the control to the secondary side feedback at start-up and prevent output voltage overshoot.
Note 2. Components used for the UCC38085 only.
+
3
GND
1
REG_IN
2
1IN 4
2IN
8REG_OUT
6VCC
52OUT
71OUT
+ +
See Note 2
Figure 5. Reference Design Schematic
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TYPICAL CHARACTERISTICS
Figure 6
10 100 1000
1200
1000
800
600
400
200
0
Frequency − kH z
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
VDD = 15 V
VDD = 6 V
VDD = 10 V
T = 25°C
T = 85°C
T = 40°C
RT − Timing Resistance − kΩ
Figure 7
−50 50 12
5
Temperature −
220
215
205
200
195
185
180
−25 0 25 75 100
210
190
OSCILLATOR FREQUENCY
vs
TEMPERATURE
Frequency − kH z
°C
RT = 165 kΩ″
RF= 1 kΩ
CF = 220 kΩ
RSET = 50 kΩ
Figure 8
10 100
0
Frequency − kHz
12
10
8
6
4
2
0
100
IDD
vs
OSCILLATOR FREQUENCY, (NO LOAD)
IDD − mA
VDD = 14 V
VDD = 10 V
VDD = 6 V
Figure 9
10 1000
Frequency − kHz
25
20
15
10
5
0
100
IDD
vs
OSCILLATOR FREQUENCY, 1 nF LOAD
IDD − mA
VDD = 14 V
VDD = 10 V
VDD = 6 V
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TYPICAL CHARACTERISTICS
10 100
0
200
160
120
80
40
0
100
20
60
100
140
180
Figure 10
DEAD TIME
vs
TIMING RESISTANCE OVER VDD
Dead Time − ns
VDD = 14 V
T = −40°C
T = 25°C
VDD = 6 V* VDD = 10 V
VDD = 6 V*
T = 85°C
VDD = 14 V
RT − Timing Resistance − kΩ
* UCCx8084/6, only
Figure 11
−50 125
Temperature −
160
100
60
40
0
50
20
80
120
140
−25 0 25 75 100
DEAD TIME
vs
TEMPERATURE
Dead Time − ns
°C
RT = 165 kΩ″
RF= 1 kΩ
CF = 220 kΩ
RSET = 50 kΩ
Figure 12
−50 125
Temperature −
2.0
1.6
1.2
0.8
0.4
0.0
50
0.2
0.6
1.0
1.4
1.8
−25 0 25 75 100
CONTROL TO CS OFFSET
vs
TEMPERATURE
VCTRL − Control Voltage − V
°C
VCS = 0.40 V
VCS = 0 V
Figure 13
015
VDD − Volts
0.6
0.5
0
10
0.1
0.2
0.3
0.4
(OC Clamped)
5
RAMP HEIGHT
vs
VDD
VPK(cs) − V
RSET = 18 kΩ
TA = 25°C
RSET = 10 kΩ
RSET = 50 kΩ
RSET = 100 kΩ
SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009
14 www.ti.com
TYPICAL CHARACTERISTICS
Figure 14
10 1000
RT − kΩ
0.7
0.6
0.4
0.3
0.1
0
100
0.2
0.5
(OC Clamped)
RAMP HEIGHT
vs
RT
VPK(cs) − V
RSET = 18 kΩ
TA = 25°C
RSET = 10 kΩ
RSET = 50 kΩ
RSET = 100 kΩ
Figure 15
−50 125
Temperature −
0.6
0.5
0.1
0.0
25
0.2
0.3
0.4
(OC Clamped)
−25 0 50 75 100
RAMP HEIGHT
vs
TEMPERATURE
°C
VPK(cs) − V
RSET = 18 kΩ
RSET = 10 kΩ
RSET = 50 kΩ
RSET = 100 kΩ
Figure 16
−50 12
5
Temperature −
6
5
2
1
0
25
3
4
0−25 50 75 100
SOFT START
vs
TEMPERATURE
Soft Start Internal − ms
°C
UCCx8083 AND UCCx8084
Figure 17
−50 125
Temperature −
100
90
80
70
60
50
25
55
65
75
85
95
50 75 1000−25
SOFT START
vs
TEMPERATURE
Soft Start Internal − µs
°C
UCCx8085 AND UCCx8086
SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009
15
www.ti.com
TYPICAL CHARACTERISTICS
Figure 18
−50 125
Temperature −
150
130
110
90
70
50
25
60
80
100
120
140
50 75 1000−25
°C
CS TO OUTX DELAY TIME
vs
TEMPERATURE
CS Prop Delay − ns
RELATED PRODUCTS
UCC3808, 8-Pin Low Power Current Mode Push-Pull PWM, (SLUS168)
UCC3808A, 8-Pin Low-Power Current-Mode Push-Pull PWM, (SLUS456)
UCC3806, Low Power, Dual Output, Current Mode PWM Controller, (SLUS272)
Table 1. 8-Pin Push-Pull PWM Controller Family Feature Comparison
Part Number UVLO On UVLO Off CS
Discharge FET Error
Amplifier
Programmable
Slope
Compensation
Internal
Softstart
UCC38083 12.5 V 8.3 V Yes No Yes Yes
UCC38084 4.3 V 4.1 V Yes No Yes Yes
UCC38085 12.5 V 8.3 V Yes No Yes No
UCC38086 4.3 V 4.1 V Yes No Yes No
UCC3808A−1 12.5 V 8.3 V Yes Yes No Yes
UCC3808A−2 4.3 V 4.1 V Yes Yes No Yes
UCC3808−1 12.5 V 8.3 V No Yes No Yes
UCC3808−2 4.3 V 4.1 V No Yes No Yes
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC28083D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28083DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28083DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28083DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28083P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC28083PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC28083PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC28083PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC28084D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28084DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28084DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28084DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28084P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC28084PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC28084PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC28084PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC28084PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC28084PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC28085D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28085DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28085DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28085DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28085P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC28085PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC28085PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC28085PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC28086D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28086DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28086DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28086DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28086P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC28086PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC28086PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC28086PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC28086PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC28086PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC38083D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38083DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38083DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38083DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38083P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC38083PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC38084D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38084DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38084DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38084DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38084P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC38084PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC38084PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC38084PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC38084PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC38084PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC38085D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC38085DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38085P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC38085PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC38086D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38086DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38086DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38086DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC38086P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC38086PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 5
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC28083DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC28084DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC28084PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
UCC28085DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC28086DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC28086PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
UCC38083DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC38084DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC38084PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
UCC38086DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC28083DR SOIC D 8 2500 340.5 338.1 20.6
UCC28084DR SOIC D 8 2500 340.5 338.1 20.6
UCC28084PWR TSSOP PW 8 2000 367.0 367.0 35.0
UCC28085DR SOIC D 8 2500 340.5 338.1 20.6
UCC28086DR SOIC D 8 2500 340.5 338.1 20.6
UCC28086PWR TSSOP PW 8 2000 367.0 367.0 35.0
UCC38083DR SOIC D 8 2500 340.5 338.1 20.6
UCC38084DR SOIC D 8 2500 340.5 338.1 20.6
UCC38084PWR TSSOP PW 8 2000 367.0 367.0 35.0
UCC38086DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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