CS5250-80 TM High Performance AES Decryption Cores Virtual Components for the Converging World The CS5250-80 series of decryption cores1 are designed to achieve data privacy and authenticity in digital broadband, wireless, and multimedia systems. These high performance application specific silicon cores support the AES (Rijndael) algorithm as described in the NIST Federal Information Processing Standard. They can be used in conjunction with the CS5210-40 series of Amphion AES encryption cores to rapidly construct complete security solutions. The CS5200 family of cores are available in both ASIC and programmable logic versions that have been hand crafted by Amphion to deliver high performance while minimizing power consumption and silicon area. Satellite Downlink Ultra High Speed AES Ground Station Uplink Ultra High Speed AES Ground Station Uplink Metropolitan Link Metropolitan Link Ultra High Speed AES High Speed AES High Speed AES Long Distance Location Location #1 Location #2 Figure 1: Example of a Satellite and Point-to-Point Secure Communication Scheme Using AES 1. Patent pending DECRYPTION CORE FEATURES Table 1: CS5250-80 Features at a Glance CS5250 Standard CS5260 Compact CS5270 High Speed CS5280 Ultra High Speed Fully compliant with AES NIST FIPS * * * * 128-bit data block * * * * 128-, 192-, 256-bit keys on-line selectable * * * * * * 128-bit keys only * 32-bit I/O * 128-bit I/O Electronic Codebook mode (ECB) * * * * Output Feedback mode (OFB) * * * * Cipher Block Chaining mode (CBC) * * * Cipher Feedback mode (CFB) * * * Optimized for Amphion continues to expand its family of application-specific cores See http://www.amphion.com for a current list of products 1 CS5250-80 High Performance AES Decryption Cores APPLICATIONS Electronic financial transactions - eCommerce - Banking - Securities exchange - Point-of-Sale Secure corporate communications - Storage Area Networks (SAN) - Virtual private networks (VPN) - Video conferencing - Voice services Personal mobile communications - Video phones - PDA - Point-to-Point Wireless - Wearable computers Secure environments - Satellite communications - Surveillance systems - Network appliances CS5250-80 SYMBOL AND PIN DESCRIPTION Table 2 gives the descriptions of the input and output ports (shown graphically in Figure 2) of the CS5250-80 series of AES decryption cores. Unless otherwise stated, all signals are active high and bit(0) is the least significant bit. D KSTAT DAADR LDKY DSTAT IKEY KADDR NKS (CS5250 only) CS5250-80 QSTRB QADDR Q LOAD CLK RST Figure 2: CS5250-80 Symbol 2 Optimized for TM Table 2: CS5250-80 Standard Rijndael Decryption Interface Signal Definitions Signal I/O Width (Bits) Description D I 32 (128) Cipher text data (128-bit width for CS5280) DADDR I 2 Cipher text data address, 0: the lowest 32-bit word LDKEY I 1 Load inverse cipher key IKEY I 32 (128) KADDR I 3a Inverse cipher key address, 0: the lowest 32-bit word NKS I 2 Inverse cipher key size select (CS5250 only) When 00: Selects a 128-bit Key When 01: Selects a 192-bit Key When 1X: Selects a 256-bit Key LOAD I 1 Load ciphertext enable CLK I 1 System clock, rising edge active RST I 1 Asynchronous reset KSTAT O 1 Key port status, when Asserted, loading of cipher keys is not allowed DSTAT O 1 Input port status The next cycle after text D[3] (the highest word of 128-bit clock) is loaded, DSTAT will be De-asserted to indicate decryption is in progress. It will be Asserted when the core is ready for loading the highest word of the next 128-bit text. The lower three words can be loaded at anytime in the period when DSTAT is LOW depending on the key-size selection. QSTRB O 1 Output strobe indicating the Plaintext word Q is valid QADDR O 2 Plaintext data address, 0: the lowest 32-bit word Q O 32 (128) Inverse cipher key (128-bit width for CS5280) Plaintext data (128-bit width for CS5280) a. 3 bits wide for the standard; 2 bits wide for compact/high speed cores; not applicable for ultra high speed core Optimized for 3 CS5250-80 High Performance AES Decryption Cores FUNCTIONAL DESCRIPTION The Rijndael algorithm is an iterated block cipher that encrypts and decrypts data in 128-bit data blocks using a 128-bit, 192-bit, or 256-bit key. The algorithm consists of: * An initial data/key addition * Nine, eleven or thirteen rounds when the length is 128-bits, 192-bits, or 256-bits respectively * A final round which is a variation of the typical round Figure 3 represents a block diagram of the Rijndael decryption algorithm. A Rijndael round transforms the data using permutations, non-linear substitutions, additions and Galois field multiplications. The Rijndael key schedule consists of two parts: 1. Key Expansion - expands the cipher key into a linear array of 4-byte words 2. Round Key Selection - selection of the required number of Round Keys from the expanded key array All four versions of the Amphion AES decryption cores follow the block diagram shown in Figure 3. The CS5200 AES decryption cores are outstanding matches with other Amphion cores. For instance they can be combined with the CS6650 MPEG2 Decoder to easily provide a secure high definition closed-circuit TV system, and they can be combined with the CS3252 FEC Codec as part of a secure wireless access point. The Amphion encryption/decryption cores are also an excellent choice for VPN security ICs incorporated into broadband switches, routers, firewalls and remote access concentrators. Likewise, the cores are an ideal fit for the Secure Socket Layer (SSL) channel ICs used in Web servers, WAP gateways and other access applications requiring a high number of parallel SSL channels to carry out eCommerce. Control Logic Ciphertext Inverse Key Input Buffer Round Transformations Key Buffer Key Scheduler Output Buffer Plaintext Figure 3: Block Diagram of CS5250-80 Series of Decryption Cores 4 Optimized for TM AVAILABILITY AND IMPLEMENTATION INFORMATION Hardware accelerated AES technology is governed internationally by export regulations. The Amphion AES cores listed in this datasheet have been officially reviewed and classified by the UK Department of Trade and Industry and US Bureau of Export Administration. These cores are licensed for immediate export to the following countries: Austria Australia Belgium Canada Czech Republic Denmark Finland France Germany Greece Hungary Ireland Italy Japan Luxembourg New Zealand Spain The Netherlands Sweden Norway Switzerland Poland United Kingdom Portugal United States For delivery to other destinations, please contact Amphion. Approval is subject to applicable export regulations. Licensees of the Amphion AES cores are responsible for complying with applicable requirements for the re-export of electronics containing AES technology. Optimized for 5 CS5250-80 High Performance AES Decryption Cores PROGRAMMABLE LOGIC CORES For ASIC prototyping or for projects requiring the fast time-to-market of a programmable logic solution, Amphion delivers programmable logic core solutions that offer the silicon-aware performance tuning found in all Amphion products, combined with the rapid design times offered by today's leading programmable logic solutions. Table 3: CS5250-80 Family of Programmable Logic Cores using Actel Axcelerator PRODUCT ID SILICON VENDOR DEVICE MAX. FREQUENCY (MHz) DATA RATE (MBits/Sec) CS5250RR Actel AX500 68.63 199a 2997 UTILIZATION DEVICE UTIL AVAILABILITY R-CELLS C-CELLS 1063 3570 57.2 Now b 399c CS5260RR Actel AX500 76.78 233a 920 3028 49.0 Now CS5270RR Actel AX1000 37.09 107 750 7162 43.6 Now CS5280RR N/A N/A N/A N/A N/A N/A N/A N/A a. Implementation of 128-bit key length b. Implementation of 192-bit key length c. Implementation of 256-bit key length Table 4: CS5250-80 Family of Programmable Logic Cores using Actel ProASICPlus PRODUCT ID CS5250RQ SILICON VENDOR Actel DEVICE APA750 MAX. FREQUENCY (MHz) DATA RATE (MBits/Sec) 26.95 78a 117 UTILIZATION (Tiles) DEVICE UTIL AVAILABILITY Combinatorial Sequential 7314 977 25.3 Now b 157c CS5260RQ Actel APA1000 25.93 75a 6521 728 12.9 Now CS5270RQ Actel APA1000 18 52a 14107 736 26.4 Now CS5280RQ N/A N/A N/A N/A N/A N/A N/A N/A a. Implementation of 128-bit key length b. Implementation of 192-bit key length c. Implementation of 256-bit key length 6 Optimized for TM Software Deliverables Supplied by AMPHION Typical ASIC or FPGA Design Flow (Conceptual) System-Level "C" Code simulation Hardware Deliverables Supplied by AMPHION Bit Accurate C Model Software Development Hardware RTL Development Instruction Set Simulation RTL Simulation Software RTL Simulation Models Hardware/Software Co-Simulation Testbench (VHDL & Verilog) Logic Synthesis Gate-level analysis (timing & functional) Netlists (Verilog, VHDL, EDIF, .bd) Physical Design FPGA Programming Files Figure 4: Design Data Formats Supplied by Amphion Optimized for 7 CS5250-80 High Performance AES Decryption Cores ABOUT AMPHION Amphion (formerly Integrated Silicon Systems) is the leading supplier of speech coding, video/ image processing and channel coding application specific silicon cores for system-on-a-chip (SoC) solutions in the broadband, wireless, and mulitmedia markets Web: www.amphion.com Email: info@amphion.com TM Virtual Components for the Converging World CORPORATE HEADQUARTERS Amphion Semiconductor Ltd 50 Malone Road Belfast BT9 5BS Northern Ireland, UK WORLDWIDE SALES & MARKETING Amphion Semiconductor, Inc 2001 Gateway Place, Suite 130W San Jose, CA 95110 Tel: Fax: Tel: Fax: +44.28.9050.4000 +44.28.9050.4001 (408) 441 1248 (408) 441 1239 EUROPEAN SALES Amphion Semiconductor Ltd CBXII, West Wing 382-390 Midsummer Boulevard Central Milton Keynes MK9 2RG England, UK CANADA & EAST COAST US SALES Amphion Semiconductor, Inc Montreal Quebec Canada Tel: Fax: Tel: Fax: +44 1908 847109 +44 1908 847580 (450) 455 5544 (450) 455 5543 SALES AGENTS Voyageur Technical Sales Inc 6205 Airport Road Building A, Suite 300 Toronto, Ontario Canada L4V1E1 Phoenix T echnologies Ltd 3 Gavish Street Kfar-Saba, 44424 Israel SPINNAKER SYSTEMS INC Shin-Yokohama Square Bldg. 11F, 2-3-12 Shin-Yokohama, Kouhoku-Ku Yokohama 222-0033 Japan Tel: Fax: T el: Fax: Tel: Fax: (905) 672 0361 (905) 677 4986 +972 9 7644 800 +972 9 7644 801 JASONTECH, INC Hansang Building, Suite 300 Bangyidong 181-3, Songpaku Seoul Korea 138-050 SPS-DA PTE LTD 21 Science Park Rd #03-19 The Aquarius Singapore Science Park II Singapore 117628 Tel: Fax: T el: Fax: +82 2 420 6700 +82 2 420 8600 +81 45 478 3803 +81 45 478 3809 +65 774 9070 +65 774 9071 (c) 2001-02 Amphion Semiconductor Ltd. All rights reserved. Amphion, the Amphion logo and "Virtual Components for the Converging World" are trademarks of Amphion Semiconductor Ltd. All others are the property of their respective owners. Optimized for 8 11/02 Publication #: DS5210/40ACT v1.1