1www.semtech.com
PROTECTION PRODUCTS
LCDA15C-6
Low Capacitance TVS Diode Array
For Multi-mode Tranciever Protection
Description Features
Circuit Diagram Schematic & PIN Configuration
Revision 01/15/03
The LCDA15C-6 has been specifically designed to
protect sensitive components which are connected to
data and transmission lines from over voltages caused
by electrostatic discharge (ESD), electrical fast tran-
sients (EFT), and lightning.
The low capacitance array configuration of the
LCDA15C-6 allows the user to protect six high-speed
data or I/O lines. They may be used on systems
operating from 5 to 15 Volts. The high surge capability
(500W, tp=8/20µs) makes the LCDA15C-6 suitable for
telecommunications systems operating in harsh tran-
sient environments. The low inductance construction
minimizes voltage overshoot during high current
surges.
The features of the LCDA15C-6 are ideal for protecting
multi-protocol transceivers in WAN applications such as
Frame Relay systems, routers, and switches. Applications
Mechanical Characteristics
Multi-Mode Transceiver Protection
WAN Equipment:
CSU/DSU
Multiplexers
Routers
ISP Equipment
Customer Premise Equipment
Protection for any of the following interfaces:
RS-232 (V.28)
RS-422 (V.11, X.21)
RS-449 (V.11/V.10)
RS-485
Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 0.5kV, 12A (8/20µs)
Protects six I/O lines
Low capacitance for high-speed interfaces
High surge capability
Low clamping voltage
Solid-state silicon avalanche technology
JEDEC SO-8 package
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tape and Reel per EIA 481
SO-8 (Top View)
Pin 1
Pin 4 and 5
22003 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
LCDA15C-6
Absolute Maximum Rating
Electrical Characteristics
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3
2003 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
LCDA15C-6
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve
Pulse Waveform Clamping Voltage vs. Peak Pulse Current
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30
Time (µs)
Percent of IPP
e-t
td = IPP/2
Waveform
Parameters:
tr = 8µs
td = 20µs
0
10
20
30
40
50
60
70
80
90
100
110
0 25 50 75 100 125 150 175
Ambient Temperature - TA (oC)
% of Rated Power or IPP
0.01
0.1
1
10
0.1 1 10 100 1000
Pulse Durat ion - tp (µs)
Peak Pulse P o wer - Ppk (kW)
10
12
14
16
18
20
22
24
26
28
0246810121416
Peak Pul se Current - IPP (A)
Clamping Voltage - VC (V)
Waveform
Parameters:
tr = 8µs
td = 20µs
Capacitance vs. Reverse Voltage
7
7.5
8
8.5
9
0123456789101112
Rever se Vol tag e - VR (V)
Capacitance - Cj (pF)
f=1MHz
Line-to-Ground
42003 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
LCDA15C-6
Device Connection
Multi-Mode T ranceiver Protection Example
Device Connection Options for Protection of Six High-
Speed Data Lines
The LCDA16C-6 may be configured to protect up to six
I/O lines operating between 5 and 15V. It may be used
to protect the most popular serial data interface
standard lines making it ideal for use in equipment
utilizing multi-mode transceivers. Data lines are
connected at pins 1, 2, 3, 6, 7, and 8. Pins 4 and 5
are connected to ground. For best results, these pins
should be connected directly to a ground plane on the
board. The path length should be kept as short as
possible to minimize parasitic inductance.
Multi-Mode Transceiver Protection
A typical multi-mode transceiver protection circuit is
shown. The LCDA15C-6 is used to protect I/O lines
with external connections. The LCDA15C-6 adds a
maximum loading capacitance of 15pF with a working
voltage of 15V. This allows the transceiver to safely
operate in all modes without clipping or degradation of
the signal.
With proper design and layout, the transceiver port can
be protected to >15kV (HBM per IEC 61000-4-2).
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of fast rise-time transients such as ESD. The following
guidelines are recommended:
zPlace the LCDA15C-6 near the input terminals or
connectors to restrict transient coupling.
zMinimize the path length between the LCDA15C-6
and the protected line.
zMinimize all conductive loops including power and
ground loops.
zThe ESD transient return path to ground should be
kept as short as possible.
zNever run critical signals near board edges.
zUse ground planes whenever possible.
Applications Information
5
2003 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
LCDA15C-6
Land Pattern - SO-8
Outline Drawing - SO-8
62003 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
LCDA15C-6
Contact Information
Semtech Corporation
Protection Products Division
200 Flynn Rd., Camarillo, CA 930 12
Phone: (805)498-211 1 FAX (805)498-3804
Ordering Information
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BT.6-C51ADCLV51005hcnI7
ET.6-C51ADCLV51005,2hcnI31
Note:
(1) No suffix indicates tube pack.