Differential/Single-Ended Input, Dual
1 MSPS, 12-Bit, 3-Channel SAR ADC
AD7265
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES FUNCTIONAL BLOCK DIAGRAM
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
D
OUT
A
OUTPUT
DRIVERS
CONTROL
LOGIC
T/H
BUF
V
A1
V
A2
V
A3
V
A4
V
A5
V
A6
MUX
REF
AD7265
V
DRIVE
REF SELECT D
CAP
A AV
DD
DV
DD
BUF
D
OUT
B
OUTPUT
DRIVERS
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
MUX
AGND AGND AGND D
CAP
B DGND DGND
CS
SCLK
RANGE
SGL/DIFF
A0
A1
A2
04674-001
Dual 12-bit, 3-channel ADC
Throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Power consumption
7 mW at 1 MSPS with 3 V supplies
17 mW at 1 MSPS with 5 V supplies
Pin-configurable analog inputs
12-channel single-ended inputs
6-channel fully differential inputs
6-channel pseudo differential inputs
70 dB SINAD at 50 kHz input frequency
Accurate on-chip reference: 2.5 V
±0.2% maximum @ 25°C, 20 ppm/°C maximum
Dual conversion with read 875 ns, 16 MHz SCLK
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
−40°C to +125°C operation
Shutdown mode: 1 μA maximum
32-lead LFCSP and 32-lead TQFP
2 MSPS version, AD7266
GENERAL DESCRIPTION
Figure 1.
The AD72651 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates of up to 1 MSPS. The
device contains two ADCs, each preceded by a 3-channel
multiplexer, and a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 30 MHz.
PRODUCT HIGHLIGHTS
1. Two Complete ADC Functions Allow Simultaneous
Sampling and Conversion of Two Channels.
Each ADC has three fully/pseudo differential pairs, or six
single-ended channels, as programmed. The conversion
result of both channels is simultaneously available on
separate data lines, or in succession on one data line if only
one serial port is available.
The conversion process and data acquisition use standard
control inputs allowing easy interfacing to microprocessors or
DSPs. The input signal is sampled on the falling edge of CS;
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. The AD7265 uses advanced
design techniques to achieve very low power dissipation at high
throughput rates. With 5 V supplies and a 1 MSPS throughput rate,
the part consumes 4 mA maximum. The part also offers flexible
power/throughput rate management when operating in normal
mode, because the quiescent current consumption is so low.
2. High Throughput with Low Power Consumption.
The AD7265 offers a 1 MSPS throughput rate with 9 mW
maximum power dissipation when operating at 3 V.
3. The AD7265 offers both a standard 0 V to VREF input range
and a 2 × V input range.
REF
4. No Pipeline Delay.
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a
The analog input range for the part can be selected to be a 0 V
to V CS
input and once off conversion control.
(or 2 × V
REF REF) range, with either straight binary or twos
complement output coding. The AD7265 has an on-chip 2.5 V
reference that can be overdriven when an external reference is
preferred. This external reference range is 100 mV to V
1 Protected by U.S. Patent No. 6,681,332.
DD. The
AD7265 is available in 32-lead LFCSP and 32-lead TQFP.
AD7265
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Ter mi no lo g y .................................................................................... 11
Theory of Operation ...................................................................... 13
Circuit Information.................................................................... 13
Converter Operation.................................................................. 13
Analog Input Structure.............................................................. 13
Analog Inputs.............................................................................. 14
Analog Input Selection .............................................................. 17
Output Coding............................................................................ 17
Transfer Functions...................................................................... 18
Digital Inputs .............................................................................. 18
VDRIVE ............................................................................................ 18
Modes of Operation ....................................................................... 19
Normal Mode.............................................................................. 19
Partial Power-Down Mode ....................................................... 19
Full Power-Down Mode ............................................................ 20
Power-Up Times......................................................................... 21
Power vs. Throughput Rate....................................................... 21
Serial Interface ................................................................................ 22
Microprocessor Interfacing........................................................... 23
AD7265 to ADSP218x............................................................... 23
AD7265 to ADSP-BF53x ........................................................... 24
AD7265 to TMS320C541.......................................................... 24
AD7265 to DSP563xx................................................................ 25
Application Hints ........................................................................... 26
Grounding and Layout .............................................................. 26
PCB Design Guidelines for LFCSP .......................................... 26
Evaluating the AD7265 Performance...................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
11/06—Rev. 0 to Rev. A
Changes to Format .............................................................Universal
Changes to Reference Input/Output Section ................................ 4
Changes to Table 4............................................................................ 7
Changes to Terminology Section.................................................. 11
Changes to Figure 24 and Differential Mode Section................ 15
Changes to Figure 29...................................................................... 16
Changes to AD7265 to ADSP-BF53x Section............................. 24
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide .......................................................... 27
4/05—Revision 0: Initial Version
AD7265
Rev. A | Page 3 of 28
SPECIFICATIONS
TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, fSCLK = 16 MHz, fS = 1 MSPS, VDRIVE = 2.7 V to 5.25 V; specifications apply using internal
reference or external reference = 2.5 V ± 1%, unless otherwise noted.1
Table 1.
Parameter Specification Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)271 dB min fIN = 50 kHz sine wave; differential mode
69 dB min
fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
Signal-to-Noise + Distortion Ratio (SINAD)270 dB min fIN = 50 kHz sine wave; differential mode
68 dB min
fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
Total Harmonic Distortion (THD)2 –77 dB max fIN = 50 kHz sine wave; differential mode
–73 dB max
fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
Spurious-Free Dynamic Range (SFDR)2–75 dB max fIN = 50 kHz sine wave
Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz
Second-Order Terms –88 dB typ
Third-Order Terms –88 dB typ
Channel-to-Channel Isolation –88 dB typ
SAMPLE AND HOLD
Aperture Delay311 ns max
Aperture Jitter350 ps typ
Aperture Delay Matching3200 ps max
Full Power Bandwidth 33/26 MHz typ @ 3 dB, VDD = 5 V/VDD = 3 V
3.5/3 MHz typ @ 0.1 dB, VDD = 5 V/VDD = 3 V
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity2±1 LSB max ±0.5 LSB typ; differential mode
±1.5 LSB max
±0.5 LSB typ; single-ended and pseudo
differential modes
Differential Nonlinearity2,4 ±0.99 LSB max Differential mode
−0.99/+1.5 LSB max Single-ended and pseudo differential modes
Straight Binary Output Coding
Offset Error ±6 LSB max
Offset Error Match ±2 LSB typ
Gain Error ±2.5 LSB max
Gain Error Match ±0.5 LSB typ
Twos Complement Output Coding
Positive Gain Error ±2 LSB max
Positive Gain Error Match ±0.5 LSB typ
Zero Code Error ±5 LSB max
Zero Code Error Match ±1 LSB typ
Negative Gain Error ±2 LSB max
Negative Gain Error Match ±0.5 LSB typ
ANALOG INPUTT
5
Single-Ended Input Range 0 V to VREF V RANGE pin low
0 V to 2 × VREF RANGE pin high
Pseudo Differential Input Range: VIN+ − VIN−60 to VREF V RANGE pin low
2 × VREF V RANGE pin high
Fully Differential Input Range: VIN+ and VIN− VCM ± VREF/2 V VCM = common-mode voltage7 = VREF/2
VIN+ and VIN− VCM ± VREF V VCM = VREF
AD7265
Rev. A | Page 4 of 28
Parameter Specification Unit Test Conditions/Comments
DC Leakage Current ±1 μA max
Input Capacitance 45 pF typ When in track
10 pF typ When in hold
REFERENCE INPUT/OUTPUT
Reference Output Voltage82.5 V min/V max ±0.2% max @ 25°C
Long-Term Stability 150 ppm typ For 1000 hours
Output Voltage Hysteresis250 ppm typ
Reference Input Voltage Range 0.1/VDD V min/V max See Typical Performance Characteristics section
DC Leakage Current ±2 μA max External reference applied to Pin DCAPA/Pin DCAPB
Input Capacitance 25 pF typ
DCAPA, DCAPB Output Impedance 10 Ω typ
Reference Temperature Coefficient 20 ppm/°C max
10 ppm/°C typ
VREF Noise 20 μV rms typ
LOGIC INPUTS
Input High Voltage, VINH 2.8 V min
Input Low Voltage, VINL 0.4 V max
Input Current, IIN ±15 nA typ VIN = 0 V or VDRIVE
Input Capacitance, CIN35 pF typ
LOGIC OUTPUTS
Output High Voltage, VOH VDRIVE − 0.2 V min
Output Low Voltage, VOL 0.4 V max
Floating State Leakage Current ±1 μA max
Floating State Output Capacitance37 pF typ
Output Coding Straight (natural) binary SGL/DIFF = 1 with 0 V to VREF range selected
Twos complement
SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × VREF range
CONVERSION RATE
Conversion Time 14 SCLK cycles 875 ns with SCLK = 16 MHz
Track-and-Hold Acquisition Time390 ns max Full-scale step input; VDD = 5 V
110 ns max Full-scale step input; VDD = 3 V
Throughput Rate 1 MSPS max
POWER REQUIREMENTS
VDD 2.7/5.25 V min/V max
VDRIVE 2.7/5.25 V min/V max
IDD Digital I/Ps = 0 V or VDRIVE
Normal Mode (Static) 2.3 mA max VDD = 5.25 V
Operational, fS = 1 MSPS 4 mA max VDD = 5.25 V; 3.5 mA typ
fS = 1 MSPS 3.2 mA max VDD = 3.6 V; 2.7 mA typ
Partial Power-Down Mode 500 μA max Static
Full Power-Down Mode (VDD) 1 μA max TA = −40°C to +85°C
2.8 μA max TA > 85°C to 125°C
Power Dissipation
Normal Mode (Operational) 21 mW max VDD = 5.25 V
Partial Power-Down (Static) 2.625 mW max VDD = 5.25 V
Full Power-Down (Static) 5.25 μW max VDD = 5.25 V, TA = −40°C to +85°C
1 Temperature range is −40°C to +125°C.
2 See Terminology section.
3 Sample tested during initial release to ensure compliance.
4 Guaranteed no missed codes to 12 bits.
5 VIN− or VIN+ must remain within GND/VDD.
6 VIN− = 0 V for specified performance. For full input range on VIN− pin, see Figure 28 and Figure 29.
7 For full common-mode range, see Figure 24 and Figure 25.
8 Relates to Pin DCAPA or Pin DCAPB.
AD7265
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = TMAX to TMIN, unless otherwise noted1.
Table 2.
Parameter Limit at TMIN, TMAX Unit Description
fSCLK21 MHz min TA = −40°C to +85°C
4 MHz min TA > 85°C to 125°C
16 MHz max
tCONVERT 14 × tSCLK ns max tSCLK = 1/fSCLK
875 ns max fSCLK = 16 MHz
tQUIET 30 ns min
Minimum time between end of serial read and next falling edge of CS
t215/20 ns min
VDD = 5 V/3 V, CS to SCLK setup time, TA = −40°C to +85°C
20/30 ns min
VDD = 5 V/3 V, CS to SCLK setup time, TA > 85°C to 125°C
t315 ns max
Delay from CS until DOUTA and DOUTB are three-state disabled
t4336 ns max Data access time after SCLK falling edge, VDD = 3 V
27 ns max Data access time after SCLK falling edge, VDD = 5 V
t50.45 tSCLK ns min SCLK low pulse width
t60.45 tSCLK ns min SCLK high pulse width
t710 ns min SCLK to data valid hold time, VDD = 3 V
5 ns min SCLK to data valid hold time, VDD = 5 V
t815 ns max
CS rising edge to DOUTA, DOUTB, high impedance
t930 ns min
CS rising edge to falling edge pulse width
t10 5 ns min SCLK falling edge to DOUTA, DOUTB, high impedance
50 ns max SCLK falling edge to DOUTA, DOUTB, high impedance
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Serial
Interface section and Figure 41 and Figure 42.
2 Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
AD7265
Rev. A | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD to AGND −0.3 V to +7 V
DVDD to DGND −0.3 V to +7 V
VDRIVE to DGND −0.3 V to DVDD
VDRIVE to AGND −0.3 V to AVDD
AVDD to DVDD −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V
VREF to AGND −0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except
Supplies1±10 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
LFCSP/TQFP
θJA Thermal Impedance 108.2°C/W (LFCSP)
55°C/W (TQFP)
θJC Thermal Impedance 32.71°C/W (LFCSP)
Lead Temperature, Soldering
Reflow Temperature (10 sec to 30 sec) 255°C
ESD 1.5 kV
1 Transient currents of up to 100 mA will not cause SCR latch up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7265
Rev. A | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04674-041
CS
SGL/DIFF
1
2
3
4
5
6
7
8
REF SELECT
AV
DD
D
CAP
A
V
A1
AGND
AGND
DGND
V
A2
23
A2
22
21
RANGE
18
V
B1
19
AGND
20
D
CAP
B
24
A1
17
V
B2
PIN 1
9
V
A3
10
V
A4
11
V
A5
12
V
A6
13
V
B6
14
V
B5
15
V
B4
16
V
B3
32
DV
DD
31
V
DRIVE
30
D
OUT
A
29
DGND
28
D
OUT
B
27
SCLK
26 25
A0
AD7265
TOP VIEW
(Not to Scale)
04674-002
24
23
22
21
1
2
3
32
DV
DD
A0
CS
SCLK
D
OUT
B
DGND
D
OUT
A
V
DRIVE
20
19
18
17
V
B2
V
B1
AGND
D
CAP
B
RANGE
SGL/DIFF
A2
A1
9
10
11
12
13
V
B5
V
B4
V
B3
V
B6
V
A6
V
A5
V
A4
V
A3
14
15
16
4
5
6
7
8
V
A2
V
A1
AGND
AGND
D
CAP
A
AV
DD
REF SELECT
DGND
31
30
29
28
27
26
25
AD7265
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 3. 32-Lead SU-32-2
Figure 2. 32-Lead CP-32-2
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 29 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
2 REF SELECT
Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used
as the reference source for both ADC A and ADC B. In addition, Pin D A and Pin D
CAP CAPB must be tied to
decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the
AD7265 through the D A pin and/or the D B pin.
CAP CAP
3 AVDD Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The
AV and DV
DD DD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis. This supply should be decoupled to AGND.
4, 20 D A, D B
CAP CAP Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to
decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference
can be taken from these pins and applied externally to the rest of a system. The range of the external reference is
dependent on the analog input range selected.
5, 6, 19 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect
to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
7 to 12 V to V
A1 A6 Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential
analog input channel pairs. See Table 6.
13 to 18 VB6 to VB1 Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential
analog input channel pairs. See Table 6.
21 RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog
input channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is tied to a logic
high when CS goes low, the analog input range is 2 × V . See the Analog Input Selection section for details.
REF
22 SGL/DIFF Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A
logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input
Selection section for details.
23 to 25 A2 to A0 Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously
converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair
of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins
need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the
multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for
multiplexer address decoding.
26 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265
and framing the serial data transfer.
27 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7265. This
clock is also used as the clock source for the conversion process.
AD7265
Rev. A | Page 8 of 28
Pin No. Mnemonic Description
28, 30 DOUTB, DOUTA Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input and 14 SCLKs are required to access the data. The data simultaneously appears
on both pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros
followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles
rather than 14, then two trailing zeros appear after the 12 bits of data. If CS is held low for a further 16 SCLK
cycles on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data from a
simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one
serial port. See the Serial Interface section.
31 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage at this pin may be different than that at AVDD and DVDD but
should never exceed either by more than 0.3 V.
32 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7265. The DVDD
and AVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a
transient basis. This supply should be decoupled to DGND.
AD7265
Rev. A | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, unless otherwise noted.
A
04674-003
SUPPLY RIPPLE FREQUENCY (kHz)
20000 200 400 600 800 1000 1200 1400 1600 1800
PSRR (dB)
–60
–70
–80
–90
–100
–110
–120
100mV p-p SINE WAVE ON AV
DD
NO DECOUPLING
SINGLE-ENDED MODE
EXTERNAL REFERENCE
INTERNAL REFERENCE
04674-006
FREQUENCY (kHz)
5000 50 100 150 200 250 300 350 400 450
(dB)
–10
–30
–50
–70
–90
–110
4096 POINT FFT
V
DD
= 5V, V
DRIVE
= 3V
F
SAMPLE
= 1MSPS
F
IN
= 26kHz
SINAD = 71.4dB
THD = –84.42dB
DIFFERENTIAL MODE
Figure 7. FFT
Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
04674-007
CODE
40000 1000 2000 3000 3500500 1500 2500
DNL ERROR (LSB)
1.0
0.6
0.8
0.2
0.4
–0.2
0
–0.6
–0.8
–0.4
–1.0
V
DD
= 5V, V
DRIVE
= 3V
DIFFERENTIAL MODE
04674-004
NOISE FREQUENCY (kHz)
10000 100 200 300 400 500 600 800700 900
ISOLATION (dB)
–50
–55
–60
–65
–70
–75
–90
–95
–80
–85
–100
V
DD
= 5V
Figure 8. Typical DNL
Figure 5. Channel-to-Channel Isolation
04674-008
CODE
40000 500 1000 1500 2000 2500 3000 3500
INL ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
DD
= 5V, V
DRIVE
= 3V
DIFFERENTIAL MODE
04674-005
INPUT FREQUENCY (kHz)
10000 500
SINAD (dB)
74
72
68
70
66
V
DD
= 5V
DIFFERENTIAL MODE
V
DD
= 3V
DIFFERENTIAL MODE
RANGE = 0 TO V
REF
Figure 6. SINAD vs. Analog Input Frequency for Various Supply Voltages Figure 9. Typical INL
AD7265
Rev. A | Page 10 of 28
04674-012
CODE
2046 2047 20492048 2050
NO. OF OCCURRENCES
10000
8000
9000
6000
7000
4000
5000
2000
1000
3000
0
10000
CODES
DIFFERENTIAL
MODE
INTERNAL
REFERENCE
04674-009
VREF (V)
2.50 0.5 1.0 1.5 2.0
LINEARITY ERROR (LSB)
1.0
0.6
0.8
0.2
0.4
–0.2
0
–0.6
–0.4
–1.0
–0.8
VDD = 3V/5V
DIFFERENTIAL MODE
POSITIVE INL
POSITIVE DNL
NEGATIVE DNL
NEGATIVE INL
Figure 10. Linearity Error vs. V Figure 13. Histogram of Codes for 10k Samples in Differential Mode
REF
04674-010
V
REF
(V)
5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
EFFECTIVE NUMBER OF BITS
12.0
11.0
11.5
10.0
10.5
9.0
9.5
8.0
7.5
8.5
7.0
V
DD
= 5V
DIFFERENTIAL MODE
V
DD
= 3V
DIFFERENTIAL MODE
V
DD
= 3V
SINGLE-ENDED MODE
V
DD
= 5V
SINGLE-ENDED MODE
04674-042
CODE
2046 2047 2048 2049 2050
NO. OF OCCURRENCES
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
9984
CODES
SINGLE-ENDED
MODE
INTERNAL
REFERENCE
5 CODES 11 CODES
Figure 11. Effective Number of Bits vs. VREF Figure 14. Histogram of Codes for 10k Samples in Single-Ended Mode
04674-011
CURRENT LOAD (μA)
2000 20 40 60 80 100 120 140 160 180
V
REF
(V)
2.5010
2.5000
2.5005
2.4995
2.4990
2.4985
2.4980
04674-040
RIPPLE FREQUENCY (kHz)
12000 200 400 600 800 1000
CMRR (dB)
–60
–65
–70
–75
–80
–85
–95
–90
–100
DIFFERENTIAL MODE
V
DD
= 3V/5V
vs. Reference Output Current Drive
Figure 12. VREF
Figure 15. CMRR vs. Common-Mode Ripple Frequency
AD7265
Rev. A | Page 11 of 28
TERMINOLOGY
Differential Nonlinearity (DNL) Signal-to-(Noise + Distortion) Ratio (SINAD)
Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes in
the ADC.
SINAD is the measured ratio of signal-to-(noise + distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all non-fundamental signals
up to half the sampling frequency (f
Integral Nonlinearity (INL) S/2), excluding dc. The ratio
is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale with a
single (1) LSB point below the first code transition, and full scale
with a 1 LSB point above the last code transition. Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, this is 74 dB.
Offset Error
Offset error applies to straight binary output coding. It is the
deviation of the first code transition (00 . . . 000) to (00 . . . 001)
from the ideal (AGND + 1 LSB).
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. For the AD7265, it is defined as
Offset Error Match
1
2
6
2
5
2
4
2
3
2
2
log20)( V
VVVVV
dBTHD ++++
=
Offset error match is the difference in offset error across all
12 channels.
where:
Gain Error
Gain error applies to straight binary output coding. It is the
deviation of the last code transition (111 . . . 110) to (111 . . .
111) from the ideal (VREF − 1 LSB) after the offset error is
adjusted out. Gain error does not include reference error.
V is the rms amplitude of the fundamental.
1
V, V, V, V
Gain Error Match
Gain error match is the difference in gain error across all
12 channels.
Zero Code Error
Zero code error applies when using twos complement output
coding with, for example, the 2 × VREF input range as −VREF
to +VREF biased about the VREF point. It is the deviation of
the midscale transition (all 1s to all 0s) from the ideal VIN
voltage (VREF).
Zero Code Error Match
Zero code error match refers to the difference in zero code error
across all 12 channels.
Positive Gain Error
This applies when using twos complement output coding with,
for example, the 2 × VREF input range as −VREF to +VREF biased
about the VREF point. It is the deviation of the last code transition
(011…110) to (011…111) from the ideal (+VREF − 1 LSB) after
the zero code error is adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
2 3 4 5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic, or spurious noise, is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale (2 × V when V = 5 V , and V when V
REF DD REF DD = 3 V),
10 kHz sine wave signal to all unselected input channels and
determining how much that signal is attenuated in the selected
channel with a 50 kHz signal (0 V to VREF). The result obtained
is the worst-case across all 12 channels for the AD7265.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum, and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa − fb),
(fa + 2fb), and (fa − 2fb).
AD7265
Rev. A | Page 12 of 28
The AD7265 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second-order and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Thermal Hysteresis
Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either
T_HYS+ = +25°C to TMAX to +25°C
or
T_HYS− = +25°C to TMIN to +25°C
It is expressed in ppm by
6
10
)C25(
)_()C25(
)( ×
°
−°
=
REF
REFREF
HYS V
HYSTVV
ppmV
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of V
where:
V
and V
IN+ IN− of
frequency f
REF (25°C) is VREF at 25°C.
V
S as REF (T_HYS) is the maximum change of VREF at T_HYS+ or
T_HYS−.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
f
PS is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value (see Figure 4).
AD7265
Rev. A | Page 13 of 28
THEORY OF OPERATION
When the ADC starts a conversion (see Figure 17), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the V
CIRCUIT INFORMATION
The AD7265 is a fast, micropower, dual, 12-bit, single-supply,
ADC that operates from a 2.7 V to a 5.25 V supply. When
operated from either a 3 V or a 5 V supply, the AD7265 is
capable of throughput rates of 1 MSPS when provided with a
16 MHz clock.
The AD7265 contains two on-chip, differential track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins. It is housed in a
32-lead LFCSP or a 32-lead TQFP, offering the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part, but also
provides the clock source for each successive approximation
ADC. The analog input range for the part can be selected to be
a 0 V to V
and V
IN+ IN− pins must be matched;
otherwise, the two inputs will have different settling times,
resulting in errors.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
IN+
V
IN–
V
REF
04674-014
input or a 2 × V
REF REF input, configured with either
single-ended or differential analog inputs. The AD7265 has an
on-chip 2.5 V reference that can be overdriven when an external
reference is preferred. If the internal reference is to be used
elsewhere in a system, then the output needs to be buffered first.
The AD7265 also features power-down options to allow power
saving between conversions. The power-down feature is
implemented via the standard serial interface, as described in
the
Figure 17. ADC Conversion Phase
ANALOG INPUT STRUCTURE
Modes of Operation section.
Figure 18 shows the equivalent circuit of the analog input
structure of the AD7265 in differential/pseudo differential
modes. In single-ended mode, V
CONVERTER OPERATION
The AD7265 has two successive approximation ADCs, each
based around two capacitive DACs. IN− is internally tied to AGND.
The four diodes provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. This causes these
diodes to become forward-biased and starts conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
Figure 16 and Figure 17
show simplified schematics of one of these ADCs in acquisition
and conversion phase, respectively. The ADC is comprised of
control logic, a SAR, and two capacitive DACs. In Figure 16 (the
acquisition phase), SW3 is closed, SW1 and SW2 are in Position A,
the comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
The C1 capacitors in Figure 18 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC’s sampling capacitors with a
capacitance of 45 pF typically.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
IN+
V
IN–
V
REF
04674-013
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins with optimum
values of 47 Ω and 10 pF. In applications where harmonic
distortion and signal-to-noise ratio are critical, the analog input
should be driven from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC
and may necessitate the use of an input buffer amplifier. The
choice of the op amp is a function of the particular application.
Figure 16. ADC Acquisition Phase
AD7265
Rev. A | Page 14 of 28
V
DD
C1
D
D
V
IN+
R1 C2
V
DD
C1
D
D
V
IN–
R1 C2
04674-015
Figure 21 shows a graph of the THD vs. the analog input
frequency for various supplies while sampling at 1 MSPS. In this
case, the source impedance is 47 Ω.
04674-018
INPUT FREQUENCY (kHz)
6000 200100 400300 500
THD (dB)
–50
–60
–55
–65
–70
–75
–80
–85
–90
V
DD
= 3V
SINGLE-ENDED MODE
V
DD
= 5V
SINGLE-ENDED MODE
V
DD
= 3V
DIFFERENTIAL MODE
V
DD
= 5V
DIFFERENTIAL MODE
F
SAMPLE
= 1MSPS
V
DD
= 3V/5V
RANGE = 0 TO V
REF
Figure 18. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be toler-
ated. The THD increases as the source impedance increases and
performance degrades.
Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
Figure 19 shows a graph of the THD vs.
the analog input signal frequency for different source impedances
in single-ended mode, while
ANALOG INPUTS
Figure 20 shows the THD vs. the
analog input signal frequency for different source impedances
in differential mode.
The AD7265 has a total of 12 analog inputs. Each on-board
ADC has six analog inputs that can be configured as six single-
ended channels, three pseudo differential channels, or three
fully differential channels. These can be selected as described in
the
04674-016
INPUT FREQUENCY (kHz)
6000200100 400300 500
THD (dB)
–50
–60
–55
–65
–70
–75
–80
–85
–90
F
SAMPLE
= 1MSPS
V
DD
= 3V
RANGE = 0V TO V
REF
R
SOURCE
= 0Ω
R
SOURCE
= 10Ω
R
SOURCE
= 47Ω
R
SOURCE
= 100Ω
R
SOURCE
= 300Ω
Analog Input Selection section.
Single-Ended Mode
The AD7265 can have a total of 12 single-ended analog input
channels. In applications where the signal source has high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. The analog input range can be pro-
grammed to be either 0 to V or 0 to 2 × V .
REF REF
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it correctly formatted for the ADC. Figure 22
shows a typical connection diagram when operating the ADC
in single-ended mode.
Figure 19. THD vs. Analog Input Frequency for
Various Source Impedances, Single-Ended Mode
V
IN
0V
+1.25V
–1.25V
D
CAP
A/D
CAP
B
V
A1
V
B6
R
R
3R
R
0V
+2.5
V
0.47µF
1
ADDITIONAL PINS OMITTED FOR CLARITY.
04674-019
AD7265
1
04674-017
INPUT FREQUENCY (kHz)
6000200100 400300 500
THD (dB)
–
60
–65
–70
–75
–80
–85
–90
F
SAMPLE
= 1MSPS
V
DD
= 3V
RANGE = 0V TO V
REF
R
SOURCE
= 300Ω
R
SOURCE
= 0Ω
R
SOURCE
= 10Ω
R
SOURCE
= 47Ω
R
SOURCE
= 100Ω
Figure 22. Single-Ended Mode Connection Diagram
Figure 20. THD vs. Analog Input Frequency for
Various Source Impedances, Differential Mode
AD7265
Rev. A | Page 15 of 28
04674-021
V
REF
(V)
5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
COMMON-MODE RANGE (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
A
= 25°C
Differential Mode
The AD7265 can have a total of six differential analog
input pairs.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 23 defines the fully differential analog
input of the AD7265.
V
IN+
V
IN–
V
REF
p-p
V
REF
p-p
COMMON
MODE
VOLTAGE
1
ADDITIONAL PINS OMITTED FOR CLARITY.
04674-020
AD7265
1
Figure 24. Input Common-Mode Range vs. V (0 to V Range, V
Figure 23. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN− pins in each
differential pair (VIN+ − VIN−). VIN+ and VIN− should be
simultaneously driven by two signals each of amplitude VREF (or
2 × VREF, depending on the range chosen) that are 180° out of
phase. The amplitude of the differential signal is therefore
(assuming the 0 to VREF range is selected) −VREF to +VREF peak-
to-peak (2 × VREF), regardless of the common mode (CM).
The common mode is the average of the two signals
(VIN+ + VIN−)/2
and is therefore the voltage on which the two inputs are
centered.
This results in the span of each input being CM ± VREF/2. This
voltage has to be set up externally, and its range varies with the
reference value, VREF. As the value of VREF increases, the common-
mode range decreases. When driving the inputs with an amplifier,
the actual common-mode range is determined by the amplifier’s
output voltage swing.
Figure 24 and Figure 25 show how the common-mode range
typically varies with VREF for a 5 V power supply using the 0 to
VREF range or 2 × VREF range, respectively. The common mode
must be in this range to guarantee the functionality of the AD7265.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude −VREF to
+VREF corresponding to the digital codes of 0 to 4096. If the
2 × VREF range is used, then the input signal amplitude extends
from −2 VREF to +2 VREF after conversion.
REF REF DD = 5 V)
04674-022
VREF (V)
2.50 0.5 1.0 1.5 2.0
COMMON-MODE RANGE (V)
5.0
4.0
4.5
3.0
3.5
2.0
2.5
0.5
1.0
1.5
0
TA = 25°C
Figure 25. Input Common-Mode Range vs. V (2 × V Range, V
REF REF DD = 5 V)
Driving Differential Inputs
Differential operation requires that V and V
IN+ IN− be
simultaneously driven with two equal signals that are 180° out
of phase. The common mode must be set up externally. The
common-mode range is determined by VREF, the power supply,
and the particular amplifier used to drive the analog inputs.
Differential modes of operation with either an ac or dc input
provide the best THD performance over a wide frequency
range. Because not all applications have a signal preconditioned
for differential operation, there is often a need to perform
single-ended-to-differential conversion.
AD7265
Rev. A | Page 16 of 28
Using an Op Amp Pair Pseudo Differential Mode
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7265. The
circuit configurations illustrated in
The AD7265 can have a total of six pseudo differential pairs. In
this mode, VIN+ is connected to the signal source that must have
an amplitude of V
Figure 26 and Figure 27
show how a dual op amp can be used to convert a single-ended
signal into a differential signal for both a bipolar and unipolar
input signal, respectively.
(or 2 × V
REF REF, depending on the range
chosen) to make use of the full dynamic range of the part. A dc
input is applied to the VIN− pin. The voltage applied to this input
provides an offset from ground or a pseudo ground for the VIN+
input. The benefit of pseudo differential inputs is that they
separate the analog input signal ground from the ADC’s ground
allowing dc common-mode voltages to be cancelled. The typical
voltage range for the V
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a
suitable dual op amp that can be used in this configuration to
provide differential drive to the AD7265.
IN− pin, while in pseudo differential
mode, is shown in Figure 28 and Figure 29. Figure 30 shows a
connection diagram for pseudo differential mode.
04674-043
V
REF
(V)
3.00 0.5 1.0 1.5 2.0 2.5
V
IN–
(V)
1.0
0.8
0.4
0.6
0.2
–0.2
0
–0.4
T
A
= 25°C
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 26 and Figure 27 are optimized for
dc coupling applications requiring best distortion performance.
The circuit configuration shown in Figure 26 converts a
unipolar, single-ended signal into a differential signal.
The differential op amp driver circuit shown in Figure 27 is
configured to convert and level shift a single-ended, ground-
referenced (bipolar) signal to a differential signal centered at the
V level of the ADC.
REF
GND
2 × V
REF
p-p
27Ω
27Ω
V+
V–
V+
V–
V
REF
2.5V
3.75V
1.25V
2.5V
3.75V
1.25V
D
CAP
A/D
CAP
B
V
IN+
V
IN–
440Ω
220Ω
0.47µF
1
ADDITIONAL PINS OMITTED FOR CLARITY.
220Ω
220Ω
10kΩ
A
04674-023
AD7265
1
Figure 28. VIN− Input Voltage Range vs. VREF in
Pseudo Differential Mode with VDD = 3 V
04674-044
V
REF
(V)
5.00 0.51.01.52.02.53.03.54.04.5
V
IN–
(V)
2.5
2.0
1.5
1.0
0.5
0
–0.5
T
A
= 25°C
Figure 26. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
into a Differential Signal
20kΩ
220kΩ
2 × V
REF
p-p
27Ω
27Ω
V+
V–
V+
V–
GND
2.5V
3.75V
1.25V
2.5V
3.75V
1.25V
D
CAP
A/D
CAP
B
V
IN+
V
IN–
440Ω
220Ω
0.47µF
1
ADDITIONAL PINS OMITTED FOR CLARITY.
220Ω
220Ω
10kΩ
A
04674-024
AD7265
1
Figure 29. VIN− Input Voltage Range vs. VREF in
Pseudo Differential Mode with VDD = 5 V
DC INPUT
VOLTAGE
V
REF
p–p
V
REF
V
IN+
V
IN–
0.47µF
1
ADDITIONAL PINS OMITTED FOR CLARITY.
04674-025
AD7265
1
Figure 27. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
Figure 30. Pseudo Differential Mode Connection Diagram
AD7265
Rev. A | Page 17 of 28
The channels used for simultaneous conversions are selected via
the multiplexer address input pins, A0 to A2. The logic states of
these pins also need to be established prior to the acquisition
time; however, they may change during the conversion time,
provided that the mode is not changed. If the mode is changed
from fully differential to pseudo-differential, for example, then
the acquisition time would start again from this point. The
selected input channels are decoded as shown in
ANALOG INPUT SELECTION
The analog inputs of the AD7265 can be configured as single-
ended or true differential via the SGL/DIFF logic pin, as shown
in Figure 31. If this pin is tied to a logic low, the analog input
channels to each on-chip ADC are set up as three true differen-
tial pairs. If this pin is at logic high, the analog input channels to
each on-chip ADC are set up as six single-ended analog inputs.
The required logic level on this pin needs to be established prior
to the acquisition time and remain unchanged during the con-
version time until the track-and-hold has returned to track. The
track-and-hold returns to track on the 13
Tabl e 6.
The analog input range of the AD7265 can be selected as 0 V to
V or 0 V to 2 × V
REF REF via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/DIFF pin by setting
the logic state of the RANGE pin a time t
th rising edge of SCLK
after the CS falling edge (see Figure 41). If the level on this pin
is changed, it is recognized by the AD7265; therefore, it is
necessary to keep the same logic level during acquisition and
conversion to avoid corrupting the conversion in progress.
acq prior to the falling
edge of CS. Subsequent to this, the logic level on this pin can be
altered after the third falling edge of SCLK. If this pin is tied to a
logic low, the analog input range selected is 0 V to VREF. If this
pin is tied to a logic high, the analog input range selected is 0 V
to 2 × V
DIFF
For example, in Figure 31, the SGL/ pin is set at logic high
for the duration of both the acquisition and conversion times
so the analog inputs are configured as single ended for that
conversion (Sampling Point A). The logic level of the SGL/
REF.
OUTPUT CODING
DIFF
changed to low after the track-and-hold returned to track and
prior to the required acquisition time for the next sampling
instant at Point B; therefore, the analog inputs are configured as
differential for that conversion.
The AD7265 output coding is set to either twos complement or
straight binary, depending on which analog input configuration
is selected for a conversion. Table 5 shows which output coding
scheme is used for each possible analog input configuration.
Table 5. AD7265 Output Coding
SCLK
CS
114 141
A
SGL/DIFF
B
tACQ
04674-026
Figure 31. Selecting Differential or Single-Ended Configuration
SGL/DIFF Range Output Coding
DIFF 0 V to V Twos complement
REF
DIFF 0 V to 2 × VREF Twos complement
SGL 0 V to VREF Straight binary
SGL 0 V to 2 × VREF Twos complement
PSEUDO DIFF 0 V to VREF Straight binary
PSEUDO DIFF 0 V to 2 × V Twos complement
REF
Table 6. Analog Input Type and Channel Selection
ADC A ADC B
SGL/DIFF V V V
A2 A1 A0 VIN+ IN− IN+ IN− Comment
1 0 0 0 V AGND V AGND Single ended
A1 B1
1 0 0 1 V AGND V AGND
A2 B2 Single ended
1 0 1 0 V AGND V AGND
A3 B3 Single ended
1 0 1 1 V AGND V AGND
A4 B4 Single ended
1 1 0 0 V AGND V AGND
A5 B5 Single ended
1 1 0 1 V AGND V AGND
A6 B6 Single ended
0 0 0 0 V V V
A1 A2 B1 VB2 Fully differential
0 0 0 1 V V V V
A1 A2 B1 B2 Pseudo differential
0 0 1 0 V V V
A3 A4 B3 VB4 Fully differential
0 0 1 1 V V V V
A3 A4 B3 B4 Pseudo differential
0 1 0 0 V V V
A5 A6 B5 VB6 Fully differential
0 1 0 1 V VVVPseudo differential
A5 A6 B5 B6
AD7265
Rev. A | Page 18 of 28
TRANSFER FUNCTIONS DIGITAL INPUTS
The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB
size is V
The digital inputs applied to the AD7265 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs can be applied up to 7 V and are not restricted by
the V
/4096 when the 0 V to V
REF REF range is used, and the LSB
size is 2 × V /4096 when the 0 V to 2 × V
REF REF range is used. In
differential mode, the LSB size is 2 × V
+ 0.3 V limit, as are the analog inputs. See the
DD Absolute
Maximum Ratings
REF/4096 when the 0 V to
V
section for more information. Another
advantage of the SCLK, RANGE, A0 to A2, and
REF range is used, and the LSB size is 4 × VREF/4096 when the
0 V to 2 × V
CS pins not
being restricted by the V
REF range is used. The ideal transfer characteristic
for the AD7265 when straight binary coding is output is shown
in
DD + 0.3 V limit is that power supply
sequencing issues are avoided. If one of these digital inputs is
applied before V
Figure 32, and the ideal transfer characteristic for the AD7265
when twos complement coding is output is shown (with the 2 ×
V
DD, there is no risk of latch-up, as there would
be on the analog inputs if a signal greater than 0.3 V were
applied prior to V
range) in Figure 33.
REF DD.
04674-027
000...000
111...111
1LSB = VREF/4096
1LSB VREF – 1LSB
ANALOG INPUT
ADC CODE
0V
000...001
000...010
111...110
111...000
011...111
NOTE
1. VREF IS EITHER VREF OR 2 × VREF.
VDRIVE
The AD7265 also has a VDRIVE feature to control the voltage at
which the serial interface operates. VDRIVE allows the ADC to
easily interface to both 3 V and 5 V processors. For example, if
the AD7265 was operated with a V of 5 V, the V
DD DRIVE pin
could be powered from a 3 V supply, allowing a large dynamic
range with low voltage digital processors. Therefore, the
AD7265 could be used with the 2 × V input range, with a V
REF DD
of 5 V while still being able to interface to 3 V digital parts.
Figure 32. Straight Binary Transfer Characteristic
04674-028
100...000
011...111
1LSB = 2
×
V
REF
/4096
+V
REF
– 1 LSB–V
REF
+ 1LSB V
REF
– 1LSB
ANALOG INPUT
ADC CODE
100...001
100...010
011...110
000...001
000...000
111...111
Figure 33. Twos Complement Transfer Characteristic with
V ± V Input Range
REF REF
AD7265
Rev. A | Page 19 of 28
MODES OF OPERATION
Once 32 SCLK cycles have elapsed, the D
The mode of operation of the AD7265 is selected by controlling
the (logic) state of the
OUT line returns to
three-state on the 32
CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. After a conversion is
initiated, the point at which
CS
SCLK falling edge. If
nd is brought high
prior to this, the DOUT line returns to three-state at that point.
Therefore, CS may idle low after 32 SCLK cycles until it is
brought high again sometime prior to the next conversion
(effectively idling
CS is pulled high determines which
power-down mode, if any, the device enters. Similarly, if already
in a power-down mode,
CS low), if so desired, because the bus still
returns to three-state upon completion of the dual result read.
CS can control whether the device
returns to normal operation or remains in power-down. These
modes of operation are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for differing
application requirements.
Once a data transfer is complete and D A and D
OUT OUTB have
returned to three-state, another conversion can be initiated after
the quiet time, t CS
NORMAL MODE
This mode is intended for applications that need the fastest
throughput rates because the user does not have to worry about
any power-up times with the AD7265 remaining fully powered
at all times. Figure 34 shows the general diagram of the
operation of the AD7265 in this mode.
SCLK
LEADING ZEROS + CONVERSION RESULT
CS
D
OUT
A
D
OUT
B
110 14
04674-029
Figure 34. Normal Mode Operation
The conversion is initiated on the falling edge of CS, as
described in the Serial Interface section. To ensure that the part
remains fully powered up at all times, CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS. If CS is brought high any time after the 10th SCLK falling
edge but before the 14th SCLK falling edge, the part remains
powered up, but the conversion is terminated and DOUTA and
DOUTB go back into three-state. Fourteen serial clock cycles are
required to complete the conversion and access the conversion
result. The DOUT line does not return to three-state after 14
SCLK cycles have elapsed, but instead does so when CS is
brought high again. If CS is left low for another 2 SCLK cycles
(for example, if only a 16 SCLK burst is available), two trailing
zeros are clocked out after the data. If CS is left low for a further
14 (or 16) SCLK cycles, the result from the other ADC on board
is also accessed on the same DOUT line, as shown in Figure 42
(see the Serial Interface section).
QUIET, has elapsed by bringing low again
(assuming the required acquisition time is allowed).
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate, and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7265 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffer.
To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high anywhere after the
second falling edge of SCLK and before the 10th falling edge of
SCLK, as shown in CS
Figure 35. Once is brought high in this
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of CS is
terminated, and DOUTA and D B go back into three-state. If
OUT
CS is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the CS line.
SCLK
THREE-STATE
CS
D
OUT
A
D
OUT
B
1110 42
04674-030
Figure 35. Entering Partial Power-Down Mode
AD7265
Rev. A | Page 20 of 28
To exit this mode of operation and power up the AD7265 again,
a dummy conversion is performed. On the falling edge of CS,
the device begins to power up and continues to power up as
long as CS is held low until after the falling edge of the 10th
SCLK. The device is fully powered up after approximately 1 μs
has elapsed, and valid data results from the next conversion, as
shown in Figure 36. If CS is brought high before the second
falling edge of SCLK, the AD7265 again goes into partial
power-down. This avoids accidental power-up due to glitches
on the CS line. Although the device may begin to power up on
the falling edge of CS, it powers down again on the rising edge
of CS. If the AD7265 is already in partial power-down mode
and CS is brought high between the second and 10th falling
edges of SCLK, the device enters full power-down mode.
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes
substantially longer than that from partial power-down. This
mode is more suited to applications where a series of
conversions performed at a relatively high throughput rate are
followed by a long period of inactivity and thus power-down.
When the AD7265 is in full power-down, all analog circuitry is
powered down. Full power-down is entered in a similar way as
partial power-down, except the timing sequence shown in
Figure 35 must be executed twice. The conversion process must
be interrupted in a similar fashion by bringing CS high anywhere
after the second falling edge of SCLK and before the 10th falling
edge of SCLK. The device enters partial power-down at this
point. To reach full power-down, the next conversion cycle
must be interrupted in the same way, as shown in Figure 37.
Once CS is brought high in this window of SCLKs, the part
completely powers down.
CS
Note that it is not necessary to complete the 14 SCLKs once
is brought high to enter a power-down mode.
To exit full power-down and power up the AD7265, a dummy
conversion is performed, as when powering up from partial
power-down. On the falling edge of CS, the device begins to
power up and continues to power up, as long as CS is held low
until after the falling edge of the 10th SCLK. The required
power-up time must elapse before a conversion can be initiated,
as shown in Figure 38. See the Power-Up Times section for the
power-up times associated with the AD7265.
SCLK
CS
D
OUT
A
D
OUT
BINVALID DATA VALID DATA
11014 141
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.
t
POWER-UP1
04674-031
Figure 36. Exiting Partial Power-Down Mode
THREE-STATE
110142
SCLK
CS
D
OUT
A
D
OUT
B
THREE-STATE
1102
INVALID DATAINVALID DATA
THE PART BEGINS
TO POWER UP.
THE PART ENTERS
PARTIAL POWER DOWN.
THE PART ENTERS
FULL POWER DOWN.
04674-032
14
Figure 37. Entering Full Power-Down Mode
AD7265
Rev. A | Page 21 of 28
SCLK
D
OUT
A
D
OUT
BINVALID DATA VALID DATA
110 14 14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
t
POWER-UP2
CS
04674-033
Figure 38. Exiting Full Power-Down Mode
POWER-UP TIMES
As described in detail, the AD7265 has two power-down
modes, partial power-down and full power-down. This section
deals with the power-up time required when coming out of
either of these modes. It should be noted that the power-up
times, as explained in this section, apply with the recommended
capacitors in place on the DCAPA and DCAPB pins.
To power up from full power-down (whether using an internal
or external reference), approximately 1.5 ms should be allowed
from the falling edge of CS, shown as tPOWER-UP2 in Figure 38.
Powering up from partial power-down requires much less time.
The power-up time from partial power-down is typically 1 μs;
however, if using the internal reference, then the AD7265 must
be in partial power-down for at least 67 μs in order for this
power-up time to apply.
When power supplies are first applied to the AD7265, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure the part is fully powered up before attempting a
valid conversion. Likewise, if it is intended to keep the part in
the partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th SCLK falling
edge (see Figure 34); in the second cycle, CS must be brought
high before the 10th SCLK edge but after the second SCLK
falling edge (see Figure 35). Alternatively, if it is intended to
place the part in full power-down mode when the supplies are
applied, then three dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th SCLK falling
edge (see Figure 34); the second and third dummy cycles place
the part in full power-down (see Figure 37).
Once supplies are applied to the AD7265, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final values.
POWER vs. THROUGHPUT RATE
The power consumption of the AD7265 varies with throughput
rate. When using very slow throughput rates and as fast an
SCLK frequency as possible, the various power-down options
can be used to make significant power savings. However, the
AD7265 quiescent current is low enough that even without
using the power-down options, there is a noticeable variation in
power consumption with sampling rate. This is true whether a
fixed SCLK value is used or if it is scaled with the sampling rate.
Figure 39 and Figure 40 show plots of power vs. the throughput
rate when operating in normal mode for a fixed maximum
SCLK frequency, and an SCLK frequency that scales with the
sampling rate with VDD = 3 V and VDD = 5 V, respectively. In all
cases, the internal reference was used.
04674-045
THROUGHPUT (kSPS)
10000 100 200 300 500400 700 800 900600
POWER (mW)
10.0
9.0
8.5
9.5
8.0
7.0
6.5
7.5
6.0
5.5
5.0
16MHz SCLK
VARIABLE SCLK
T
A
= 25°C
Figure 39. Power vs. Throughput in Normal Mode with VDD = 3 V
04674-046
THROUGHPUT (kSPS)
10000 200 300 400100 500 600 700 800 900
POWER (mW)
25
21
19
23
17
13
15
9
7
11
5
VARIABLE SCLK
T
A
= 25°C
16MHz SCLK
Figure 40. Power vs. Throughput in Normal Mode with VDD = 5 V
AD7265
Rev. A | Page 22 of 28
SERIAL INTERFACE
A minimum of 14 serial clock cycles are required to perform
the conversion process and to access data from one conversion
on either data line of the AD7265.
Figure 41 shows the detailed timing diagram for serial inter-
facing to the AD7265. The serial clock provides the conversion
clock and controls the transfer of information from the AD7265
during conversion.
CS going low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Therefore, the first
falling clock edge on the serial clock has the leading zero pro-
vided and also clocks out the second leading zero. The 12-bit
result then follows with the final bit in the data transfer valid on
the 14
CS
The signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once 13
SCLK falling edges have elapsed, the track-and-hold goes back
into track on the next SCLK rising edge, as shown in
th falling edge, having being clocked out on the previous
(13th) falling edge. It may also be possible to read in data on
each SCLK rising edge depending on the SCLK frequency or
the supply voltage. The first rising edge of SCLK after the
Figure 41
at Point B. If a 16-SCLK transfer is used, then two trailing zeros
will appear after the final LSB. On the rising edge of CS
falling edge would have the second leading zero provided, and
the 13
CS, the
conversion is terminated and DOUTA and DOUTB go back into
three-state. If
th rising SCLK edge would have DB0 provided.
CS is not brought high but is instead held low for
a further 14 (or 16) SCLK cycles on D Note that with fast SCLK values, and thus short SCLK periods,
in order to allow adequately for t
OUTA, the data from Con-
version B is output on DOUTA (followed by 2 trailing zeros). 2, an SCLK rising edge may
occur before the first SCLK falling edge. This rising edge of
SCLK can be ignored for the purposes of the timing descriptions in
this section. If a falling edge of SCLK is coincident with the
falling edge of
CS
Likewise, if is held low for a further 14 (or 16) SCLK cycles
on D B, the data from Conversion A is output on D
OUT OUTB. This
is illustrated in Figure 42 where the case for DOUTA is shown. In
this case, the D CS, then this falling edge of SCLK is not
acknowledged by the AD7265, and the next falling edge of
SCLK will be the first registered after the falling edge of
OUT line in use goes back into three-state on the
32nd SCLK falling edge or the rising edge of CS, whichever
occurs first. CS.
CS
SCLK
1513
D
OUT
A
D
OUT
B
2 LEADING ZEROS
THREE-
STATE
t
4
234
t
5
t
3
t
QUIET
t
2
THREE-STATE
DB11 DB10 DB2 DB0
t
6
t
7
t
8
0
0DB1
B
DB9 DB8
t
9
04674-034
Figure 41. Serial Interface Timing Diagram
CS
SCLK
1515
D
OUT
ATHREE-
STATE
t
4
234 16
t
5
t
3
t
2
THREE-
STATE
t
6
t
7
14
ZERO0 ZERO DB11
B
17
2 LEADING ZEROS
t
10
32
DB11
A
2 LEADING
ZEROS
DB10
A
DB9
A
ZEROZERO ZERO
2 TRAILING ZEROS
ZERO ZERO
2 TRAILING ZEROS
04674-035
Figure 42. Reading Data from Both ADCs on One D Line with 32 SCLKs
OUT
AD7265
Rev. A | Page 23 of 28
MICROPROCESSOR INTERFACING
The connection diagram is shown in
The serial interface on the AD7265 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7265 with some of the
more common microcontroller and DSP serial interface
protocols.
Figure 43. The ADSP-218x
has the TFS0 and RFS0 of the SPORT0 and the RFS1 of
SPORT1 tied together. TFS0 is set as an output, and both RFS0
and RFS1 are set as inputs. The DSP operates in alternate
framing mode, and the SPORT control register is set up as
described. The frame synchronization signal generated on the
TFS is tied to
AD7265 TO ADSP-218x CS, and, as with all signal processing applications,
equidistant sampling is necessary. However, in this example, the
timer interrupt is used to control the sampling rate of the ADC
and, under certain conditions, equidistant sampling may not be
achieved.
The ADSP-218x family of DSPs interface directly to the
AD7265 without any glue logic required. The VDRIVE pin of the
AD7265 takes the same supply voltage as that of the ADSP-218x.
This allows the ADC to operate at a higher supply voltage than
its serial interface and, therefore, the ADSP-218x, if necessary.
This example shows both D AD72651
SCLK
CS
ADSP-218x
1
1ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK0
DR0
RFS0
TFS0
DOUTA
VDRIVE
VDD
DOUTB DR1
RFS1
SCLK1
04674-036
A and D
OUT OUTB of the AD7265
connected to both serial ports of the ADSP-218x. The SPORT0
and SPORT1 control registers should be set up as shown in
Table 7 and Table 8.
Table 7. SPORT0 Control Register Setup
Setting Description
TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right justify data
SLEN = 1111 16-bit data-word (or may be set to
1101 for 14-bit data-word)
ISCLK = 1 Internal serial clock
TFSR = RFSR = 1 Frame every word
Figure 43. Interfacing the AD7265 to the ADSP-218x
IRFS = 0
ITFS = 1 The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS, and hence, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (AX0 = TX0), the state of the SCLK is checked. The
DSP waits until the SCLK has gone high, low, and high again
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
Table 8. SPORT1 Control Register Setup
Setting Description
TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right justify data
SLEN = 1111 16-bit data-word (or may be set to
1101 for 14-bit data-word)
ISCLK = 0 External serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0
ITFS = 1 For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
then an SCLK of 2 MHz is obtained, and eight master clock
periods will elapse for every one SCLK period. If the timer
registers are loaded with the value 803, then 100.5 SCLKs will
occur between interrupts and, subsequently, between transmit
instructions. This situation yields sampling that is not equidistant,
as the transmit instruction is occurring on a SCLK edge. If the
number of SCLKs between interrupts is a whole integer figure
of N, then equidistant sampling will be implemented by the DSP.
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
AD7265
Rev. A | Page 24 of 28
AD7265 to ADSP-BF53x AD7265 TO TMS320C541
The ADSP-BF53x family of DSPs interface directly to the
AD7265 without any glue logic required. The availability of
secondary receive registers on the serial ports of the Blackfin®
DSPs means only one serial port is necessary to read from both
D
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7265. The CS input allows easy interfacing between the
TMS320C541 and the AD7265 without any glue logic required.
The serial ports of the TMS320C541 are set up to operate in
burst mode with internal CLKX0 (TX serial clock on Serial
Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial
port control registers (SPC) must have the following setup.
OUT pins simultaneously. Figure 44 shows both DOUTA and
DOUTB of the AD7265 connected to Serial Port 0 of the
ADSP-BF53x. The SPORT0 Receive Configuration 1 register
and SPORT0 Receive Configuration 2 register should be set up
as outlined in Table 9 and Table 10.
SERIAL
DEVICE A
(PRIMARY)
SERIAL
DEVICE B
(SECONDARY)
D
OUT
A
CS
SCLK
ADSP-BF53x
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
DR0PRI
DR0SEC
RFS0
V
DRIVE
V
DD
D
OUT
B
RCLK0
04674-037
SPORT0
AD7265
1
Table 11. Serial Port Control Register Setup
SPC FO FSM MCM TXM
SPC0 0 1 1 1
SPC1 0 1 0 0
The format bit, FO, may be set to 1 to set the word length to
8 bits to implement the power-down modes on the AD7265.
The connection diagram is shown in Figure 45. For signal
processing applications, it is imperative that the frame
synchronization signal from the TMS320C541 provide
equidistant sampling. The V
DRIVE pin of the AD7265 takes the
same supply voltage as that of the TMS320C541. This allows the
ADC to operate at a higher voltage than its serial interface, and
therefore, the TMS320C541, if necessary.
Figure 44. Interfacing the AD7265 to the ADSP-BF53x
Table 9. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
Setting Description
FSR1
FSR0
SCLK
TMS320C541
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
CLKX0
DR1
CLKR1
CLKX1
D
OUT
B
D
OUT
A
V
DRIVE
V
DD
CS FSX0
DR0
CLKR0
04674-038
AD7265
1
RCKFE = 1 Sample data with falling edge of RSCLK
LRFS = 1 Active low frame signal
RFSR = 1 Frame every word
IRFS = 1 Internal RFS used
RLSBIT = 0 Receive MSB first
RDTYPE = 00 Zero fill
IRCLK = 1 Internal receive clock
RSPEN = 1 Receive enabled
16-bit data-word (or may be set to 1101
for 14-bit data-word)
SLEN = 1111
TFSR = RFSR = 1
Table 10. The SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2)
Figure 45. Interfacing the AD7265 to the TMS320C541
Setting Description
RXSE = 1 Secondary side enabled
SLEN = 1111 16-bit data-word (or may be set to 1101
for 14-bit data-word)
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst. A Blackfin driver for the
AD7265 is available to download at
www.analog.com.
AD7265
Rev. A | Page 25 of 28
In the example shown in Figure 46, the serial clock is taken
from the ESSI0 so the SCK0 pin must be set as an output,
SCKD = 1, while the SCK1 pin is set as an input, SCKD = 0. The
frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1,
while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an
input. The V
AD7265 TO DSP563xx
The connection diagram in Figure 46 shows how the AD7265
can be connected to the ESSI (synchronous serial interface) of
the DSP563xx family of DSPs from Motorola. There are two
on-board ESSIs, and each operates in synchronous mode
(Bit SYN = 1 in CRB register) with internally generated word
length frame sync for both TX and RX (Bit FSL1 = 0 and
Bit FSL0 = 0 in CRB).
DRIVE pin of the AD7265 takes the same supply
voltage as that of the DSP563xx. This allows the ADC to operate
at a higher voltage than its serial interface and therefore the
DSP563xx, if necessary.
Normal operation of the ESSI is selected by making MOD = 0
in the CRB. Set the word length to 16 by setting Bit WL1 = 1
and Bit WL0 = 0 in CRA.
SCLK
DSP563xx1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
SCK0
SC12
SRD1
SRD0
CS
D
OUT
A
D
OUT
B
V
DRIVE
V
DD
SC02
SCK1
04674-039
AD7265
1
To implement the power-down modes on the AD7265, the
word length can be changed to 8 bits by setting Bit WL1 = 0 and
Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1
so the frame sync is negative. It is imperative for signal
processing applications that the frame synchronization signal
from the DSP563xx provides equidistant sampling.
Figure 46. Interfacing the AD7265 to the DSP563xx
AD7265
Rev. A | Page 26 of 28
APPLICATION HINTS
GROUNDING AND LAYOUT
The analog and digital supplies to the AD7265 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The printed circuit
board (PCB) that houses the AD7265 should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. This design facilitates the use of
ground planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All three AGND pins of the
AD7265 should be sunk in the AGND plane. Digital and analog
ground planes should be joined in only one place. If the AD7265
is in a system where multiple devices require an AGND to DGND
connection, the connection should still be made at one point
only, a star ground point that should be established as close as
possible to the ground pins on the AD7265.
Avoid running digital lines under the device as this couples
noise onto the die. However, the analog ground plane should be
allowed to run under the AD7265 to avoid noise coupling. The
power supply lines to the AD7265 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line.
To avoid radiating noise to other sections of the board, fast
switching signals, such as clocks, should be shielded with digital
ground, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. To reduce
the effects of feedthrough within the board, traces on opposite
sides of the board should run at right angles to each other. A
microstrip technique is the best method but is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground planes,
while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to GND. To achieve the best results from these
decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 μF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types. These low ESR
and ESI capacitors provide a low impedance path to ground at
high frequencies to handle transient currents due to internal
logic switching.
PCB DESIGN GUIDELINES FOR LFCSP
The lands on the chip scale package (CP-32-3) are rectangular.
The PCB pad for these should be 0.1 mm longer than the
package land length, and 0.05 mm wider than the package land
width, thereby having a portion of the pad exposed. To ensure
that the solder joint size is maximized, the land should be
centered on the pad.
The bottom of the chip scale package has a thermal pad. The
thermal pad on the PCB should be at least as large as the
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern to ensure that shorting is avoided.
To improve thermal performance of the package, use thermal
vias on the PCB incorporating them in the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via. The user should connect the PCB
thermal pad to AGND.
EVALUATING THE AD7265 PERFORMANCE
The recommended layout for the AD7265 is outlined in the
evaluation board documentation. The evaluation board package
includes a fully assembled and tested evaluation board, docu-
mentation, and software for controlling the board from the PC
via the evaluation board controller. The evaluation board con-
troller can be used in conjunction with the AD7265 evaluation
board, as well as many other Analog Devices, Inc. evaluation
boards ending in the CB designator, to demonstrate/evaluate
the ac and dc performance of the AD7265.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7265.
The software and documentation are on a CD shipped with the
evaluation board.
AD7265
Rev. A | Page 27 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80 SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ
3.25
3.10 SQ
2.95
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad (CP-32-2)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MS-026ABA
0.45
0.37
0.30
0.80
BSC
LEAD PITCH
7.00
BSC SQ
9.00 BSC SQ
124
25
32
8
9
17
16
1.20
MAX
0.75
0.60
0.45
1.05
1.00
0.95
0.20
0.09
0.08 MAX
COPLANARITY
SEATING
PLANE
0° MIN
7°
3.5°
0°
0.15
0.05
VIEW A
ROTATED 90° CCW
VIEW A
PIN 1
TOP VIEW
(PINS DOWN)
Figure 48. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7265BCP –40°C to +125°C 32-Lead LFCSP_VQ CP-32-2
AD7265BCPZ –40°C to +125°C 32-Lead LFCSP_VQ CP-32-2
1
AD7265BCPZ-REEL7 –40°C to +125°C 32-Lead LFCSP_VQ CP-32-2
1
AD7265BCPZ-REEL –40°C to +125°C 32-Lead LFCSP_VQ CP-32-2
1
AD7265BSUZ –40°C to +125°C 32-Lead TQFP SU-32-2
1
AD7265BSUZ-REEL7 –40°C to +125°C 32-Lead TQFP SU-32-2
1
AD7265BSUZ-REEL –40°C to +125°C 32-Lead TQFP SU-32-2
1
EVAL-AD7265CB Evaluation Board
2
EVAL-CONTROL BRD2 Control Board
3
1 Z = Pb-free part.
2 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.
3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. To order a
complete evaluation kit, the particular ADC evaluation board (such as, EVAL-AD7265CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the
relevant evaluation board technical note for more information.
AD7265
Rev. A | Page 28 of 28
T
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04674-0-11/06(A)
TTT
