Revised June 2005 74VCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold General Description The VCXH16244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The VCXH16244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74VCXH16244 is designed for low voltage (1.2V to 3.6V) VCC applications with output capability up to 3.6V. The 74VCXH16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features 1.2V to 3.6V VCC supply operation 3.6V tolerant control inputs and outputs Bushold on data inputs eliminating the need for external pull-up/pull-down resistors tPD 2.5 ns max for 3.0V to 3.6V VCC Static Drive (IOH/IOL) r24 mA @ 3.0V VCC Uses patented noise/EMI reduction circuitry Latch-up performance exceeds 300 mA ESD performance: Human body model ! 2000V Machine model ! 200V Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number 74VCXH16244G (Note 1)(Note 2) Package Number BGA54A (Preliminary) 74VCXH16244MTD (Note 2) MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: Ordering Code "G" indicates Tray. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbol (c) 2005 Fairchild Semiconductor Corporation DS500230 www.fairchildsemi.com 74VCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold November 1999 74VCXH16244 Connection Diagrams Pin Descriptions Pin Assignment for TSSOP Pin Names Description OEn Output Enable Input (Active LOW) I0-I15 Bushold Inputs O0-O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 OE2 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE4 OE3 NC I15 Truth Tables Inputs I0-I3 OE1 Pin Assignment for FBGA Outputs L L L L H H H X Z Inputs Outputs I4-I7 OE2 L L L H H H X Z Outputs I8-I11 OE3 L L L H H H X Z Inputs Outputs I12-I15 O12-O15 L L L L H H H X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial (HIGH or LOW, inputs may not float) Z High Impedance 2 O8-O11 L OE4 www.fairchildsemi.com O4-O7 L Inputs (Top Thru View) O0-O3 puts are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. The 74VCXH16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE out- Logic Diagram 3 www.fairchildsemi.com 74VCXH16244 Functional Description 74VCXH16244 Absolute Maximum Ratings(Note 3) Recommended Operating Conditions (Note 5) 0.5V to 4.6V 0.5V to 4.6V Supply Voltage (VCC) DC Input Voltage (VI) Power Supply Output Voltage (VO) Operating Outputs 3-STATED Outputs Active (Note 4) DC Input Diode Current (IIK) VI 0V 0.5V to 4.6V 0.5V to VCC 0.5V 50 mA Output Voltage (VO) DC Output Diode Current (IOK) VO 0V 50 mA 50 mA VO ! VCC r50 mA DC VCC or GND Current per Supply Pin (I CC or GND) Storage Temperature Range (TSTG) Output in Active States 0.0V to VCC Output in 3-STATE 0.0V to 3.6V Output Current in IOH/IOL DC Output Source/Sink Current (IOH/IOL) 1.2V to 3.6V 0.3V to 3.6V Input Voltage r100 mA 65qC to 150qC VCC 3.0V to 3.6V VCC 2.3V to 2.7V VCC 1.65V to 2.3V VCC 1.4V to 1.6V VCC 1.2V Free Air Operating Temperature (TA) r24 mA r18 mA r6 mA r2 mA r100 PA 40qC to 85qC Minimum Input Edge Rate ('t/'V) VIN 0.8V to 2.0V, VCC 3.0V 10 ns/V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused control inputs must be held HIGH or LOW. DC Electrical Characteristics Symbol Parameter Conditions VCC Min Max Units (V) VIH VIL HIGH Level Input Voltage LOW Level Input Voltage 2.7 - 3.6 2.0 2.3 - 2.7 1.6 1.65 - 2.3 0.65 x VCC 1.4 - 1.6 0.65 x VCC 1.2 0.65 x VCC 2.7 - 3.6 0.8 2.3 - 2.7 0.7 1.65 - 2.3 0.35 x VCC 1.4 - 1.6 0.35 x VCC 1.2 VOH HIGH Level Output Voltage www.fairchildsemi.com V 0.05 x VCC IOH 100 PA 2.7 - 3.6 VCC - 0.2 IOH 12 mA 2.7 2.2 IOH 18 mA 3.0 2.4 IOH 24 mA 3.0 2.2 IOH 100 PA 2.3 - 2.7 VCC - 0.2 IOH 6 mA 2.3 2.0 IOH 12 mA 2.3 1.8 IOH 18 mA 2.3 1.7 IOH 100 PA 1.65 - 2.3 VCC - 0.2 IOH 6 mA IOH 100 PA IOH 2 mA 1.4 1.05 IOH 100 PA 1.2 VCC - 0.2 4 V 1.65 1.25 1.4 - 1.6 VCC - 0.2 V Symbol (Continued) Parameter Conditions VCC Min Max Units (V) VOL II II(HOLD) LOW Level Output Voltage Input Leakage Current Bushold Input Minimum Drive Hold Current II(OD) IOL 100 PA 2.7 - 3.6 0.2 IOL 12 mA 2.7 0.4 IOL 18 mA 3.0 0.4 IOL 24 mA 3.0 0.55 IOL 100 PA 2.3 - 2.7 0.2 IOL 12 mA 2.3 0.4 IOL 18 mA 2.3 0.6 IOL 100 PA 1.65 - 2.3 0.2 IOL 6 mA 1.65 0.3 IOL 100 PA IOL 2 mA IOL 100 PA 0.2 1.4 0.35 1.2 0.05 Control Pins 0 d VI d 3.6V 1.2 - 3.6 r5.0 PA Data Pins VI 1.2 - 3.6 r5.0 PA V CC or GND VIN 0.8V 3.0 75.0 75.0 VIN 2.0V 3.0 VIN 0.7V 2.3 45.0 VIN 1.6V 2.3 45.0 VIN 0.57V 1.65 25.0 VIN 1.07V 1.65 25.0 Bushold Input Over-Drive (Note 6) 3.6 450 Current to Change State (Note 7) 3.6 450 (Note 6) 2.7 300 (Note 7) 2.7 300 (Note 6) 1.95 200 (Note 7) 1.95 200 IOZ 3-STATE Output Leakage 0 d VO d 3.6V IOFF Power-OFF Leakage Current 0 d (VO) d 3.6V ICC Quiescent Supply Current VI VI V IH or VIL V CC or GND VCC d (VO) d 3.6V (Note 8) 'ICC 1.4 - 1.6 Increase in ICC per Input V VIH VCC 0.6V PA PA 2.7 - 3.6 r10.0 PA 0 10.0 PA 1.2 - 3.6 20.0 PA 1.2 - 3.6 r20.0 PA 2.7 - 3.6 750 PA Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: Outputs disabled or 3-STATE only. 5 www.fairchildsemi.com 74VCXH16244 DC Electrical Characteristics 74VCXH16244 AC Electrical Characteristics Symbol tPHL (Note 9) Parameter Propagation Delay CL 30 pF, RL (V) 500: tPLH CL tPZL Output Enable Time CL 15 pF, RL 30 pF, RL 2 k: 500: tPZH CL tPLZ Output Disable Time CL 15 pF, RL 30 pF, RL 2 k: 500: tPHZ CL tOSHL Output to Output Skew tOSLH (Note 10) CL CL Note 9: For CL 15 pF, RL 30 pF, RL 15 pF, RL TA VCC Conditions 2 k: 500: 2 k: 40qC to 85qC Min Units Max 3.3 r 0.3 0.8 2.5 2.5 r 0.2 1.0 3.0 1.8 r 0.15 1.5 6.0 1.5 r 0.1 1.0 12.0 1.2 1.5 30.0 3.3 r 0.3 0.8 3.5 2.5 r 0.2 1.0 4.1 1.8 r 0.15 1.5 8.2 1.5 r 0.1 1.0 16.4 1.2 1.5 41.0 3.3 r 0.3 0.8 3.5 2.5 r 0.2 1.0 3.8 1.8 r 0.15 1.5 6.8 1.5 r 0.1 1.0 13.6 1.2 1.5 34.0 3.3 r 0.3 0.5 2.5 r 0.2 0.5 1.8 r 0.15 0.75 1.5 r 0.1 1.5 1.2 1.5 Figure Number Figures 1, 2 ns Figures 5, 6 Figures 1, 3, 4 ns Figures 5, 7, 8 Figures 1, 3, 4 ns Figures 5, 7, 8 ns 50PF, add approximately 300 ps to the AC maximum specification. Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP VOLV VOHV Parameter VCC Conditions Quiet Output Dynamic Peak VOL CL Quiet Output Dynamic Valley VOL CL Quiet Output Dynamic Valley VOH CL 30 pF, VIH VCC, VIL 30 pF, VIH VCC, VIL 30 pF, VIH VCC, VIL 0V 0V 0V TA 25qC (V) Typical 1.8 0.25 2.5 0.6 3.3 0.8 1.8 0.25 2.5 0.6 3.3 0.8 1.8 1.5 2.5 1.9 3.3 2.2 Units V V V Capacitance Symbol Parameter Conditions CIN Input Capacitance VCC COUT Output Capacitance VI 0V or VCC, VCC CPD Power Dissipation Capacitance VI 0V or VCC, f www.fairchildsemi.com 1.8, 2.5V or 3.3V, VI 6 0V or VCC 1.8V, 2.5V or 3.3V 10 MHz, VCC 1.8V, 2.5V or 3.3V TA 25qC Typical Units 6.0 pF 7.0 pF 20.0 pF 74VCXH16244 AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V) TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC 3.3 r 0.3V; VCC x 2 at VCC 2.5 r 0.2V; 1.8V r 0.15V tPZH, tPHZ GND FIGURE 1. AC Test Circuit FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic Symbol VCC 3.3V r 0.3V 2.5V r 0.2V 1.8V r 0.15V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VX VOL 0.3V VOL 0.15V VOL 0.15V VY VOH 0.3V VOH 0.15V VOH 0.15V 7 www.fairchildsemi.com 74VCXH16244 AC Loading and Waveforms (VCC 1.5 r 0.1V to 1.2V) TEST SWITCH tPLH, tPHL tPZL, tPLZ Open 1.5 r 0.1V VCC x 2 at VCC tPZH , tPHZ GND FIGURE 5. AC Test Circuit FIGURE 6. Waveform for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic VCC Symbol 1.5V r 0.1V Vmi www.fairchildsemi.com VCC/2 Vmo VCC/2 VX VOL 0.1V VY VOH 0.1V 8 74VCXH16244 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com 74VCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10