June 1996 Revision 1.0 DATA SHEET FSA2UN3641-(60/70)J(G/S)-S 8MByte (2M x 36) CMOS DRAM Module - ECC General Description The FSA2UN3641-(60/70)J(G/S)-S is a high performance, 8-megabyte dynamic RAM module organized as 2M words by 36 bits, in a 72-pin, JEDEC ECC configuration, leadless, single-in-line memory module (SIMM) package. The module utilizes eighteen, Fujitsu MB814400C-(60/70)PJ CMOS 1Mx4 dynamic RAMs in a surface mount package on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity. Control lines provided are such that Dword control is possible. Features * JEDEC ECC standard * High Density: 8MByte * Fast Access Time of 60/70 ns (max.) * Low Power: 3.82/3.32W (max.) -Active (60/70 ns) 198mW (max.) - Standby (TTL) 99mW (max.) - Standby (CMOS) * TTL-compatible inputs and outputs * Separate power and ground planes to improve noise immunity * Single power supply of 5V10% * PCB footprint of less than 1.49 sq. in. (Height: 0.91 inch) ABSOLUTE MAXIMUM RATINGS Symbol Ratings Unit Voltage on any pin relative to VSS Item VT -1 to +7.0 V Power Dissipation PT 18 W Operating Temperature Topr 0 to +70 C Storage Temperate Tstg -55 to +125 C Short Circuit Output Current IOS -50 to +50 mA RECOMMENDED DC OPERATING CONDITIONS (TA = 0 to +70 C) Symbol Parameter Min Typ Max Unit 4.5 5.0 5.5 V 0 0 0 V VCC Supply Voltage VSS Ground VIH Input High voltage 2.4 - VCC+1 V VIL Input Low voltage -1 - 0.8 V Fujitsu Microelectronics, Inc. 1 June 1996 Revision 1.0 FSA2UN3641-(60/70)J(G/S)-S Functional Diagram RAS0* CAS0* RAS1* CAS1* 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM 1M x 4 DRAM DQ0~DQ35 (All specifications of the device are subject to change without notice.) VCC VSS Decoupling capacitors to all devices Notes: 2 1. 2. 3. "*" signifies active low signal. A0 ~ A9: To all devices. WE* and OE*: To all devices. Fujitsu Microelectronics, Inc. June 1996 Revision 1.0 FSA2UN3641-(60/70)J(G/S)-S Pin Name A0~A9 DQ0~DQ35 CAS0*~CAS1* RAS0*, RAS1* WE* OE* PD1~PD5 VCC VSS NC Addresses Data Inputs/Outputs Column Address Strobe Row Address Strobe Write Enable Output Enable Presence Detects Power Supply Ground No Connection Presence Detect Pins Pin 60 ns 70 ns PD1 NC NC PD2 NC NC PD3 NC VSS PD4 NC NC PD5 NC NC Note: PD5 is grounded through a 2.6 K resistor. Pin No. 1 Pin Designation VSS 2 3 Pin No. Pin Designation Pin No. Pin Designation Pin No. Pin Designation 19 OE* 37 DQ19 55 DQ28 DQ0 20 DQ8 38 DQ29 21 DQ9 39 DQ20 VSS 56 DQ1 57 DQ30 4 DQ2 22 DQ10 40 CAS0* 58 5 DQ3 23 DQ11 41 NC 59 DQ31 VCC 6 7 8 9 24 25 26 27 DQ12 DQ13 DQ14 DQ15 42 43 44 45 NC CAS1* RAS0* RAS1* 60 61 62 63 DQ32 DQ33 DQ34 DQ35 10 DQ4 DQ5 DQ6 DQ7 VCC 28 A7 46 DQ21 64 NC 11 PD5 29 47 NC A0 30 48 WE* VSS 65 12 DQ16 VCC 66 NC 13 14 15 16 17 A1 A2 A3 A4 A5 31 32 33 34 35 A8 A9 NC NC DQ17 49 50 51 52 53 DQ22 DQ23 DQ24 DQ25 DQ26 67 68 69 70 71 18 A6 36 DQ18 54 DQ27 72 PD1 PD2 PD3 PD4 NC VSS Fujitsu Microelectronics, Inc. 3 June 1996 Revision 1.0 FSA2UN3641-(60/70)J(G/S)-S DC CHARACTERISTICS (VCC = 5.0V10%, VSS = 0V, TA = 0 to +70 C) 60 Parameter Symbol ICC1 Operating Current ICC2 Standby current 70 Test Condition Unit Note 603 mA 1, 2 - 36 mA 18 - 18 mA Min. Max. Min. Max. RAS*, CAS* cycling; tRC = min. - 693 - TTL Interface RAS*, CAS* = V IH Dout = High-Z - 36 CMOS Interface RAS*, CAS* Vcc - 0.2V Dout = High-Z - RAS* -only Refresh Current ICC3 CAS* = V IH; RAS*, Address cycling tRC = Min - 693 - 603 mA CAS*-before-RAS* Refresh Current ICC4 RAS* and CAS* cycling tRC = Min. - 693 - 603 mA Fast Page Mode Current ICC5 RAS*= VIL; CAS*, Address cycling tPC = Min - 513 - 423 mA Input Leakage Current ILI 0V Vin VCC+0.5V -180 180 -180 180 A Output Leakage Current ILO 0V Vout VCC Dout = Disable -20 20 -20 20 A Output High Voltage VOH High Iout = -5mA 2.4 - 2.4 - V Output Low Voltage VOL Low Iout = 4.5 mA - 0.4 - 0.4 V Notes: 2 1, 3 1. 2. Values depend on output load condition when the device is selected. Maximum Values are specified at the output open condition. Address can be changed once or less while RAS* = VIL. 3. Address can be changed once or less while CAS* = VIH. CAPACITANCE (TA =+25C, VCC = 5V10%) Parameter Symbol Max. Unit Note Input Capacitance (Address) CI1 95 pF 1 Input Capacitance (RAS*, CAS*) CI2 68 pF 1 Input Capacitance (WE*, OE*) CI3 131 pF 1 Input/Output Capacitance (DQ0~DQ31) CI/O 19 pF 1, 2 Notes: 4 1. 2. Capacitance is measured with Boonton Meter or effective capacitance method. CAS* = VIH to disable Dout. Fujitsu Microelectronics, Inc. June 1996 Revision 1.0 FSA2UN3641-(60/70)J(G/S)-S AC CHARACTERISTICS (TA = 0 to +70C, VCC = 5V10%, VSS = 0V) 60 Parameter 70 Symbol Unit Min Max Min Notes Max Random read/write cycle time tRC 110 - 130 - ns Access time from RAS* tRAC - 60 - 70 ns 3, 4 Access time from CAS* tCAC - 15 - 20 ns 3, 4, 5 Access time from column address tAA - 30 - 35 ns 3, 10 Output buffer turn-off time tOFF 0 15 0 15 ns 6 Transition time (rise and fall) tT 3 50 3 50 ns 2 RAS* precharge time tRP 40 - 50 - ns RAS* pulse width tRAS 60 100000 70 100000 ns RAS* hold time tRSH 15 - 20 - ns CAS* hold time tCSH 60 - 70 - ns CAS* pulse width tCAS 15 10000 20 10000 ns RAS* to CAS* delay time tRCD 20 45 20 50 ns 4 RAS* to column address delay time tRAD 15 30 15 35 ns 10 CAS* to RAS* precharge time tCRP 5 - 5 - ns Row address set-up time tASR 0 - 0 - ns Row address hold time tRAH 10 - 10 - ns Column address set-up time tASC 0 - 0 - ns Column address hold time tCAH 12 - 15 - ns Column address to RAS* lead time tRAL 30 - 35 - ns Read command set-up time tRCS 0 - 0 - ns Read command hold time to CAS* tRCH 0 - 0 - ns Read command hold time to RAS* tRRH 0 - 0 - ns Write command hold time tWCH 10 - 15 - ns Write command pulse width tWP 10 - 15 - ns Write command to RAS* lead time tRWL 15 - 20 - ns Write command to CAS* lead time tCWL 15 - 20 - ns Data-in set-up time tDS 0 - 0 - ns 9 10 9 Data-in hold time tDH Refresh period (1024 cycles) tREF Write command set-up time tWCS 8 - 15 - ns 16 - 16 ms 0 - 0 - ns 7 CAS* set-up time (CBR refresh) tCSR 10 - 10 - ns 1 CAS* hold time (CBR refresh) tCHR 10 - 15 - ns 1 RAS* precharge to CAS* hold time tRPC 5 - 5 - ns Access time from CAS* precharge tCPA - 35 - 40 ns Fast Page mode cycle time tPC 40 - 45 - ns CAS* precharge time (Fast Page) tCP 10 - 10 - ns RAS* pulse width (Fast Page) tRASC 60 100000 70 100000 ns 12 Column address hold time to RAS* tAR 45 - 55 - ns 13 OE* access time tOEA - 15 - 20 ns Fujitsu Microelectronics, Inc. 3, 11 5 June 1996 Revision 1.0 FSA2UN3641-(60/70)J(G/S)-S AC CHARACTERISTICS (continued) (TA = 0 to +70C, VCC = 5V10%, VSS = 0V) 60 Parameter 70 Symbol Unit Min Max Min Max Notes Output buffer turn off delay time from OE* tOEZ 0 15 0 15 ns CAS* to output in Low-Z tCLZ 0 - 0 - ns 3 Write command hold time to RAS* tWCR 45 - 55 - ns 13 Data-in-time to RAS* tDHR 45 - 55 - ns 13 RAS* hold time from CAS* precharge tRHCP 35 - 40 - ns WE* to RAS* precharge time (CBR refresh) tWRP 10 - 10 - ns WE* to RAS* hold time (CBR refresh) tWRH 10 - 10 - ns Notes: 1. 2. 3. 4. An initial pulse of at least 200s is required after power-up followed by a minimum of eight RAS* cycles before device operation is achieved. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH (min.) and VIL (max.) and are assumed to be 5 ns for all inputs. Measure with a load equivalent of 2 TTL loads and 100pF. Operation within the tRCD (max.) limit ensures that tRAC (max.) limit can be met; tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD tRCD (max.). 6. This parameter defines the time at which the output achieves open circuit condition and is not referenced to VOH or VOL. 7. tWCS is non restrictive operating parameter. It is included in the data sheet as an electrical characteristic only. If tWCS tWCS(min.) the cycle is an early write cycle and the data-out pin will remain at high impedance for the duration of the cycle. Either tRCH or tRRH must be satisfied for a read cycle. 8. 9. These parameters are referenced to the CAS* leading edge in early write cycles. 10. Operation within the tRAD(max.) limit ensures that tRAC(max.) limit can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 11. Access time is determined by the longer of tAA, tCAC, or tACP. 12. tRASC defines RAS* pulse width in fast page mode cycles. 13. tAR, tWCR, tDHR are referenced to tRAD (max.) Physical Dimensions 72-pin SIMM 0.350 max. 4.250 3.984 1 0.080 0.250 72 0.250 0.400 0.91 Max. 0.25 0.125 Dia. 0.050 3.750 0.002 0.050 +0.004/-0.003 (All dimensions are in inches with 0.005" tolerance unless otherwise specified) 6 Fujitsu Microelectronics, Inc. June 1996 Revision 1.0 FSA2UN3641-(60/70)J(G/S)-S All Rights Reserved. Circuit diagrams using fujitsu products are included to illustrate typical semiconductor applications. Information sufficient for construction purpose may not be shown. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies. The information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc. Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice. No part of the publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu Microelectronics, Inc. Fujitsu Microelectronics, Inc. 7 June 1996 Revision 1.0 FSA2UN3641-(60/70)J(G/S)-S Visit our web site for the latest information: http://www.fujitsumicro.com Customer Response Center: For semiconductor products, flat panel displays, and PC cards in the U.S., Canada and Mexico, please contact the Fujitsu Microelectronics Customer Response Center (CRC). The CRC provides a single point of contact for resolving customer issues and answering technical questions. Web: Click on Tech Support in the FMI home page, then submit our form Tel: Telephone: 1-800-866-8608 Monday through Friday, 7 to 5 PST Outside U.S., Canada & Mexico call: 010-1-408-922-9000 and ask for the Customer Response Center. (Note: Country Code may vary) Fax: (408) 922-9179 E-Mail: fmicrc@fmi.fujitsu.com MP-DRAMM-DS-20316-6/96 8 Fujitsu Microelectronics, Inc.