FSA2UN3641-70JS-S - Fujitsu Quantum Devices Limited

Fujitsu Microelectronics, Inc.

DATA SHEET

June 1996

Revision 1.0

FSA2UN3641-(60/70)J(G/S)-S

8MByte (2M x 36) CMOS DRAM Module - ECC

General Description

The FSA2UN3641-(60/70)J(G/S)-S is a high perf ormance, 8-megab yte dynamic RAM module organized as 2M words b y 36 bits,

in a 72-pin, JEDEC ECC conﬁguration, leadless, single-in-line memory module (SIMM) package.

The module utilizes eighteen, Fujitsu MB814400C-(60/70)PJ CMOS 1Mx4 dynamic RAMs in a surface mount package on an

epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity.

Control lines provided are such that Dword control is possible.

Features

• JEDEC ECC standard

• High Density: 8MByte

• Fast Access Time of 60/70 ns (max.)

• Low Power: 3.82/3.32W (max.) -Active (60/70 ns)

198mW (max.) - Standby (TTL)

99mW (max.) - Standby (CMOS)

• TTL-compatible inputs and outputs

• Separate power and ground planes to improve noise immunity

• Single power supply of 5V±10%

• PCB footprint of less than 1.49 sq. in. (Height: 0.91 inch)

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to +70 °C)

Item Symbol Ratings Unit

Voltage on any pin relative to VSS VT-1 to +7.0 V

Power Dissipation PT18 W

Operating Temperature Topr 0 to +70 °C

Storage Temperate Tstg -55 to +125 °C

Short Circuit Output Current IOS -50 to +50 mA

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 4.5 5.0 5.5 V

VSS Ground 0 0 0 V

VIH Input High voltage 2.4 - VCC+1 V

VIL Input Low voltage -1 - 0.8 V

2Fujitsu Microelectronics, Inc.

FSA2UN3641-(60/70)J(G/S)-S

June 1996

Revision 1.0

Functional Diagram

Notes: 1. “*” signiﬁes active low signal.

2. A0 ~ A9: To all devices.

3. WE* and OE*: To all devices.

RAS0*

CAS0*

VCC VSS

Decoupling capacitors

to all devices

(All speciﬁcations of the device are subject to change without notice.)

1M x 4

DRAM

RAS1*

CAS1*

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

1M x 4

DRAM

DQ0~DQ35

Fujitsu Microelectronics, Inc.

FSA2UN3641-(60/70)J(G/S)-S

June 1996

Revision 1.0

Pin Name

A0~A9 Addresses

DQ0~DQ35 Data Inputs/Outputs

CAS0*~CAS1* Column Address Strobe

RAS0*, RAS1* Row Address Strobe

WE* Write Enable

OE* Output Enable

PD1~PD5 Presence Detects

VCC Power Supply

VSS Ground

NC No Connection

Presence Detect Pins

Note: PD5 is grounded through a 2.6 KΩ resistor.

Pin 60 ns 70 ns

PD1 NC NC

PD2 NC NC

PD3 NC VSS

PD4 NC NC

PD5 NC NC

Pin No. Pin Designation Pin No. Pin Designation Pin No. Pin Designation Pin No. Pin Designation

1VSS 19 OE* 37 DQ19 55 DQ28

2 DQ0 20 DQ8 38 DQ20 56 DQ29

3 DQ1 21 DQ9 39 VSS 57 DQ30

4 DQ2 22 DQ10 40 CAS0* 58 DQ31

5 DQ3 23 DQ11 41 NC 59 VCC

6 DQ4 24 DQ12 42 NC 60 DQ32

7 DQ5 25 DQ13 43 CAS1* 61 DQ33

8 DQ6 26 DQ14 44 RAS0* 62 DQ34

9 DQ7 27 DQ15 45 RAS1* 63 DQ35

10 VCC 28 A7 46 DQ21 64 NC

11 PD5 29 DQ16 47 WE* 65 NC

12 A0 30 VCC 48 VSS 66 NC

13 A1 31 A8 49 DQ22 67 PD1

14 A2 32 A9 50 DQ23 68 PD2

15 A3 33 NC 51 DQ24 69 PD3

16 A4 34 NC 52 DQ25 70 PD4

17 A5 35 DQ17 53 DQ26 71 NC

18 A6 36 DQ18 54 DQ27 72 VSS

4Fujitsu Microelectronics, Inc.

FSA2UN3641-(60/70)J(G/S)-S

June 1996

Revision 1.0

DC CHARACTERISTICS

(VCC = 5.0V±10%, VSS = 0V, TA = 0 to +70 °C)

Notes: 1. V alues depend on output load condition when the device is selected. Maximum V alues are speciﬁed at the output open condition.

2. Address can be changed once or less while RAS* = VIL.

3. Address can be changed once or less while CAS* = VIH.

CAPACITANCE

(TA =+25°C, VCC = 5V±10%)

Notes: 1. Capacitance is measured with Boonton Meter or effective capacitance method.

2. CAS* = VIH to disable Dout.

Parameter Symbol Test Condition 60 70 Unit Note

Min. Max. Min. Max.

Operating Current ICC1 RAS*, CAS* cycling; tRC = min. - 693 - 603 mA 1, 2

Standby current ICC2

TTL Interface

RAS*, CAS* = V IH

Dout = High-Z -36-36mA

CMOS Interface

RAS*, CAS* ≥ Vcc - 0.2V

Dout = High-Z -18-18mA

RAS* -only Refresh

Current ICC3 CAS* = V IH; RAS*, Address

cycling tRC = Min - 693 - 603 mA 2

CAS*-before-RAS*

Refresh Current ICC4 RAS* and CAS* cycling

tRC = Min. - 693 - 603 mA

Fast Page Mode

Current ICC5 RAS*= VIL; CAS*, Address

cycling tPC = Min - 513 - 423 mA 1, 3

Input Leakage Current ILI 0V ≤ Vin ≤ VCC+0.5V -180 180 -180 180 µA

Output Leakage Current ILO 0V ≤ Vout ≤ VCC

Dout = Disable -20 20 -20 20 µA

Output High Voltage VOH High Iout = -5mA 2.4 - 2.4 - V

Output Low Voltage VOL Low Iout = 4.5 mA - 0.4 - 0.4 V

Parameter Symbol Max. Unit Note

Input Capacitance (Address) CI1 95 pF 1

Input Capacitance (RAS*, CAS*) CI2 68 pF 1

Input Capacitance (WE*, OE*) CI3 131 pF 1

Input/Output Capacitance (DQ0~DQ31) CI/O 19 pF 1, 2

Fujitsu Microelectronics, Inc.

FSA2UN3641-(60/70)J(G/S)-S

June 1996

Revision 1.0

AC CHARACTERISTICS

(TA = 0 to +70°C, VCC = 5V±10%, VSS = 0V)

Parameter Symbol 60 70 Unit Notes

Min Max Min Max

Random read/write cycle time tRC 110 - 130 - ns

Access time from RAS* tRAC - 60 - 70 ns 3, 4

Access time from CAS* tCAC - 15 - 20 ns 3, 4, 5

Access time from column address tAA - 30 - 35 ns 3, 10

Output buffer turn-off time tOFF 0 15 0 15 ns 6

Transition time (rise and fall) tT3 50 3 50 ns 2

RAS* precharge time tRP 40-50-ns

RAS* pulse width tRAS 60 100000 70 100000 ns

RAS* hold time tRSH 15-20-ns

CAS* hold time tCSH 60-70-ns

CAS* pulse width tCAS 15 10000 20 10000 ns

RAS* to CAS* delay time tRCD 20 45 20 50 ns 4

RAS* to column address delay time tRAD 15 30 15 35 ns 10

CAS* to RAS* precharge time tCRP 5-5-ns

Row address set-up time tASR 0-0-ns

Row address hold time tRAH 10-10-ns

Column address set-up time tASC 0-0-ns

Column address hold time tCAH 12-15-ns

Column address to RAS* lead time tRAL 30-35-ns

Read command set-up time tRCS 0-0-ns

Read command hold time to CAS* tRCH 0-0-ns8

Read command hold time to RAS* tRRH 0-0-ns

Write command hold time tWCH 10-15-ns

Write command pulse width tWP 10-15-ns

Write command to RAS* lead time tRWL 15-20-ns

Write command to CAS* lead time tCWL 15-20-ns

Data-in set-up time tDS 0-0-ns9

Data-in hold time tDH 10 - 15 - ns 9

Refresh period (1024 cycles) tREF 16 - 16 ms

Write command set-up time tWCS 0-0-ns7

CAS* set-up time (CBR refresh) tCSR 10 - 10 - ns 1

CAS* hold time (CBR refresh) tCHR 10 - 15 - ns 1

RAS* precharge to CAS* hold time tRPC 5-5-ns

Access time from CAS* precharge tCPA - 35 - 40 ns 3, 11

Fast Page mode cycle time tPC 40-45-ns

CAS* precharge time (Fast Page) tCP 10-10-ns

RAS* pulse width (Fast Page) tRASC 60 100000 70 100000 ns 12

Column address hold time to RAS* tAR 45 - 55 - ns 13

OE* access time tOEA -15-20ns

6Fujitsu Microelectronics, Inc.

FSA2UN3641-(60/70)J(G/S)-S

June 1996

Revision 1.0

AC CHARACTERISTICS (continued)

(TA = 0 to +70°C, VCC = 5V±10%, VSS = 0V)

Notes: 1. An initial pulse of at least 200µs is required after pow er-up follo wed b y a minimum of eight RAS* cycles bef ore device oper ation

is achieved.

2. VIH (min.) and VIL (max.) are ref erence le vels f or measuring timing of input signals. Transition times are measured between VIH

(min.) and VIL (max.) and are assumed to be 5 ns for all inputs.

3. Measure with a load equivalent of 2 TTL loads and 100pF.

4. Operation within the tRCD (max.) limit ensures that tRAC (max.) limit can be met; tRCD (max.) is speciﬁed as a reference point

only. If tRCD is greater than the speciﬁed tRCD (max) limit, then access time is controlled exclusively by tCAC.

5. Assumes that tRCD ≥tRCD (max.).

6. This parameter deﬁnes the time at which the output achieves open circuit condition and is not referenced to VOH or VOL.

7. tWCS is non restrictive operating parameter . It is included in the data sheet as an electrical characteristic only . If t WCS ≥ tWCS(min.)

the cycle is an early write cycle and the data-out pin will remain at high impedance for the duration of the cycle.

8. Either tRCH or tRRH must be satisﬁed for a read cycle.

9. These parameters are referenced to the CAS* leading edge in early write cycles.

10. Operation within the tRAD(max.) limit ensures that tRAC(max.) limit can be met. tRAD(max.) is speciﬁed as a ref erence point only.

If tRAD is greater than the speciﬁed tRAD(max.) limit, then access time is controlled by tAA.

11. Access time is determined by the longer of tAA, tCAC, or tACP.

12. tRASC deﬁnes RAS* pulse width in fast page mode cycles.

13. tAR, tWCR, tDHR are referenced to tRAD (max.)

Physical Dimensions

72-pin SIMM

Parameter Symbol 60 70 Unit Notes

Min Max Min Max

Output buffer turn off delay time from OE* tOEZ 015015ns

CAS* to output in Low-Z tCLZ 0-0-ns3

Write command hold time to RAS* tWCR 45 - 55 - ns 13

Data-in-time to RAS* tDHR 45 - 55 - ns 13

RAS* hold time from CAS* precharge tRHCP 35-40-ns

WE* to RAS* precharge time (CBR refresh) tWRP 10-10-ns

WE* to RAS* hold time (CBR refresh) tWRH 10-10-ns

4.250

0.91

Max.

0.125

Dia.

3.984

0.400

0.25

0.250

0.350

max.

0.050

+0.004/-0.003

1 72

0.250

0.080

(All dimensions are in inches with ±0.005" tolerance unless otherwise speciﬁed)

3.750±0.002

0.050

Fujitsu Microelectronics, Inc.

FSA2UN3641-(60/70)J(G/S)-S

June 1996

Revision 1.0

Circuit diagrams using fujitsu products are included to illustrate typical semiconductor applications.

Information sufficient for construction purpose may not be shown.

The information contained in this document has been carefully checked and is believed to be reliable.

However, Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies.

The information conveyed in this document does not convey any license under the copyrights, patent

rights or trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu

Microelectronics, Inc.

Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.

No part of the publication may be copied or reproduced in any form or by any means, or transferred

to any third party without prior written consent of Fujitsu Microelectronics, Inc.

8Fujitsu Microelectronics, Inc.

FSA2UN3641-(60/70)J(G/S)-S

June 1996

Revision 1.0

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