SST39LF402C-55-4C-B3KE - MICROCHIP TECHNOLOGY

Data Sheet

www.microchip.com

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Features

• Organized as 256K x16

• Single Voltage Read and Write Operations

– 2.7-3.6V for SST39VF401C/402C

– 3.0-3.6V for SST39LF401C/402C

• Superior Reliability

– Endurance: 100,000 Cycles (Typical)

– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 5 mA (typical)

– Standby Current: 3 µA (typical)

– Auto Low Power Mode: 3 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 8 KWord)

– Bottom Block-Protection (bottom 8 KWord)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Flexible block architecture; one 8-, two 4-, one 16-, and

seven 32-KWord blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Latched Address and Data

• Security-ID Feature

– 128 bits; User: 128 words

• Fast Read Access Time:

– 70 ns for SST39VF401C/402C

– 55 ns for SST39LF401C/402C

• Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Word-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bits

– Data# Polling

– Ready/Busy# Pin

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-lead TSOP (12mm x 20mm)

– 48-ball TFBGA (6mm x 8mm)

– 48-ball WFBGA (4mm x 6mm)

• All devices are RoHS compliant

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C are 256K x16

CMOS Multi-Purpose Flash Plus (MPF+) manufactured with proprietary, high per-

formance CMOS SuperFlash® technology. The split-gate cell design and thick-

oxide tunneling injector attain better reliability and manufacturability compared

with alternate approaches. SST39LF401C/402C write (Program or Erase) with a

3.0-3.6V power supply. SST39VF401C/402C write with a 2.7-3.6V power supply.

These devices conforms to JEDEC standard pinouts for x16 memories.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Product Description

The SST39VF401C/402C and SST39LF401C/402C devices are 256K x16 CMOS Multi-Purpose Flash

Plus (MPF+) manufactured with proprietary, high performance CMOS SuperFlash technology. The

split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability

compared with alternate approaches. SST39LF401C/402C write (Program or Erase) with a 3.0-3.6V

power supply. SST39VF401C/402C write with a 2.7-3.6V power supply. These devices conform to

JEDEC standard pinouts for x16 memories.

Featuring high performance Word-Program, the SST39VF401C/402C and SST39LF401C/402C

devices provide a typical Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling,

or the RY/BY# pin to indicate the completion of Program operation. To protect against inadvertent

write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured,

and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical

endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39VF401C/402C and SST39LF401C/402C devices are suited for applications that require

convenient and economical updating of program, configuration, or data memory. For all system appli-

cations, they significantly improve performance and reliability, while lowering power consumption. They

inherently use less energy during Erase and Program than alternative flash technologies. The total

energy consumed is a function of the applied voltage, current, and time of application. Since for any

given voltage range, the SuperFlash technology uses less current to program and has a shorter erase

time, the total energy consumed during any Erase or Program operation is less than alternative flash

technologies. These devices also improve flexibility while lowering the cost for program, data, and con-

figuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of

Erase/Program cycles that have occurred. Therefore the system software or hardware does not have

to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-

gram times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39VF401C/402C and SST39LF401C/402C

are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4

for pin assignments.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Block Diagrams

Figure 1: Functional Block Diagram

Y-Decoder

I/O Buffers and Data Latches

25053 B1.0

Address Buffer Latches

X-Decoder

DQ15 -DQ

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

WP#

RESET#

RY/BY#

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Pin Assignment

Figure 2: Pin Assignments for 48-Lead TSOP

Figure 3: Pin Assignments for 48-Ball TFBGA

A16

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

1434 48-tsop EK P1.0

Standard Pinout

Top View

Die Up

A15

A14

A13

A12

A11

A10

WE#

RST#

WP#

RY/BY#

A17

A13

WE#

RY/BY#

A12

RST#

WP#

A17

A14

A10

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

25053 48-tfbga B3K P2.0

TOP VIEW (balls facing down)

ABCDEFGH

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 4: Pin Assignments for 48-Ball WFBGA

Table 1: Pin Description

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS =A

Address Inputs To provide memory addresses.

During Sector-Erase AMS-A11 address lines will select the sector.

During Block-Erase AMS-A15 address lines will select the block.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when

grounded.

RST# Reset To reset and return the device to Read mode.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 2.7-3.6V for SST39VF401C/402C or 3.0-3.6V

for SST39LF401C/402C

VSS Ground

NC No Connection Unconnected pins.

RY/BY# Ready/Busy# To output the status of a Program or Erase operation

RY/BY# is a open drain output, so a 10K- 100Kpull-up resistor is required

to allow RY/BY# to transition high indicating the device is ready to read.

T1.2 25053

CE#

VSS

DQ8

OE#

DQ0

DQ10

DQ9

DQ1

A17

WP#

DQ2

DQ3

VDD

WE#

DQ12

RST#

RY/BY#

DQ13

A10

DQ4

DQ5

DQ14

A11

A13

A12

DQ11

DQ6

DQ15

A14

A15

A16

DQ7

VSS

TOP VIEW (balls facing down)

AB CD E F GH J K L

25053 48-wfbga MAQ P3.0

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Table 2: Top / Bottom Boot Block Address

Top Boot Block Address

SST39VF402C/SST39LF402C

Bottom Boot Block Address

SST39VF401C/SST39LF401C

#Size

(KWord) Address Range # Size

(KWord) Address Range

18 8 3E000H-3FFFFH 10 32 38000H-3FFFFH

17 4 3D000H-3DFFFH 9 32 30000H-37FFFH

16 4 3C000H-3CFFFH 8 32 28000H-2FFFFH

15 16 38000H-3BFFFH 7 32 20000H-27FFFH

14 32 30000H-37FFFH 6 32 18000H-1FFFFH

13 32 28000H-2FFFFH 5 32 10000H-17FFFH

12 32 20000H-27FFFH 4 32 08000H-0FFFFH

11 32 18000H-1FFFFH 3 16 04000H-07FFFH

10 32 10000H-17FFFH 2 4 03000H-03FFFH

9 32 08000H-0FFFFH 1 4 02000H-02FFFH

8 32 00000H-07FFFH 0 8 00000H-01FFFH

T2.25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written

to the device using standard microprocessor write sequences. A command is written by asserting WE#

low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever

occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39VF401C/402C and SST39LF401C/402C also have the Auto Low Power mode which puts

the device in a near standby mode after data has been accessed with a valid Read operation. This

reduces the IDD active read current from typically 5 mA to typically 3 µA. The Auto Low Power mode

reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device

exits the Auto Low Power mode with any address transition or control signal transition used to initiate

another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power

mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.

Read

The Read operation of the SST39VF401C/402C and SST39LF401C/402C is controlled by CE# and OE#,

both have to be low for the system to obtain data from the outputs. CE# is used for device selection.

When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output con-

trol and is used to gate data from the output pins. The data bus is in high impedance state when either

CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).

Word-Program Operation

The SST39VF401C/402C and SST39LF401C/402C are programmed on a word-by-word basis. Before

programming, the sector where the word exists must be fully erased. The Program operation is accom-

plished in three steps. The first step is the three-byte load sequence for Software Data Protection. The

second step is to load word address and word data. During the Word-Program operation, the

addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is

latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal

Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs

first. The Program operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for

WE# and CE# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the

Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program

operation, the host is free to perform additional tasks. Any commands issued during the internal Pro-

gram operation are ignored. During the command sequence, WP# should be statically held high or low.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or

block-by-block) basis. The SST39VF401C/402C and SST39LF401C/402C offer both Sector-Erase and

Block-Erase mode.

The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based

on non-uniform block sizes—seven 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks.

See Figure 2 for top and bottom boot device block addresses. The Sector-Erase operation is initiated

by executing a six-byte command sequence with Sector-Erase command (50H) and sector address

(SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command

sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector

or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or

50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle

Bit methods. See Figures 12 and 13 for timing waveforms and Figure 26 for the flowchart. Any com-

mands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt

to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP#

should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing

data to be read from any memory location, or program data into any sector/block that is not suspended

for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-

Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the

Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address location within erase-suspended sectors/

blocks will output DQ2toggling and DQ6at ‘1’. While in Erase-Suspend mode, a Word-Program opera-

tion is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue

Erase Resume command. The operation is executed by issuing one byte command sequence with

Erase Resume command (30H) at any address in the last Byte sequence.

Chip-Erase Operation

The SST39VF401C/402C and SST39LF401C/402C provide a Chip-Erase operation, which allows the

user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase

command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising

edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is

Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and

Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When

WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should

be statically held high or low.

Write Operation Status Detection

The SST39VF401C/402C and SST39LF401C/402C provide two software means to detect the comple-

tion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software

detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detec-

tion mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase opera-

tion.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with

either DQ7or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software

routine should include a loop to read the accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Ready/Busy# (RY/BY#)

The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that

indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-

put, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising

edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.

When RY/BY# is high (Ready), the devices may be read or left in standby mode.

Data# Polling (DQ7)

When the SST39VF401C/402C and SST39LF401C/402C are in the internal Program operation, any

attempt to read DQ7will produce the complement of the true data. Once the Program operation is

completed, DQ7will produce true data. Note that even though DQ7may have valid data immediately follow-

ing the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on

the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal

Erase operation, any attempt to read DQ7will produce a ‘0’. Once the internal Erase operation is com-

pleted, DQ7will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#)

pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the ris-

ing edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for

a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce

alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation

is completed, the DQ6bit will stop toggling. The device is then ready for the next operation. For Sector-

, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.

DQ6will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-

gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6will toggle.

An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6to check

whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status

bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of

Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart.

Note: DQ7and DQ2require a valid address when reading status information.

Table 3: Write Operation Status

Status DQ7DQ6DQ2RY/BY#

Normal Operation Standard Program DQ7# Toggle No Toggle 0

Standard Erase 0 Toggle Toggle 0

Erase-Suspend

Mode

Read from Erase-Sus-

pended Sector/Block

1 1 Toggle 1

Read from Non-Erase-

Suspended Sector/Block

Data Data Data 1

Program DQ7# Toggle N/A 0

T3.0 25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Data Protection

The SST39VF401C/402C and SST39LF401C/402C provide both hardware and software features to pro-

tect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-

vents inadvertent writes during power-up or power-down.

Hardware Block Protection

The SST39VF402C/SST39LF402C support top hardware block protection, which protects the top 8

KWord block of the device. The SST39VF401C/SST39LF401C support bottom hardware block protec-

tion, which protects the bottom 8KWord block of the device. The Boot Block address ranges are

described in Table 4. Program and Erase operations are prevented on the 8 KWord when WP# is low.

If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected,

enabling Program and Erase operations on that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST#

pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When

no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#

is driven high before a valid Read can take place (see Figure 18).

The Erase or Program operation that has been interrupted needs to be re-initiated after the device

resumes normal operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST39VF401C/402C and SST39LF401C/402C provide the JEDEC approved Software Data Pro-

tection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation

requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the

Program operation, providing optimal protection from inadvertent Write operations, e.g., during the

system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence.

These devices are shipped with the Software Data Protection permanently enabled. See Table 7 for

Table 4: Boot Block Address Ranges

Product Address Range

Bottom Boot Block

SST39VF401C/SST39LF401C 00000H - 01FFFH

Top Boot Block

SST39VF402C/SST39LF402C 3E000H - 3FFFFH

T4.0 25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

the specific software command codes. During SDP command sequence, invalid commands will abort

the device to read mode within TRC. The contents of DQ15-DQ8can be VIL or VIH, but no other value,

during any SDP command sequence.

Common Flash Memory Interface (CFI)

The SST39VF401C/402C and SST39LF401C/402C also contain the CFI information to describe the

characteristics of the device. In order to enter the CFI Query mode, the system writes a three-byte

sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in

the last byte sequence. Additionally, the system can use the one-byte sequence with 55H on the

Address and 89H on the Data Bus to enter the CFI Query mode. Once the device enters the CFI

Query mode, the system can read CFI data at the addresses given in Tables 8 through 10. The system

must write the CFI Exit command to return to Read mode from the CFI Query mode.

Product Identification

The Product Identification mode identifies the devices as the SST39VF401C / SST39VF402C /

SST39LF401C / SST39LF402C, and manufacturer as Microchip. This mode may be accessed soft-

ware operations. Users may use the Software Product Identification operation to identify the part (i.e.,

using the device ID) when using multiple manufacturers in the same socket. For details, see Table 7 for

software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 24 for the

Software ID Entry command sequence flowchart.

Product Identification Mode Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited.

Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to

the Read mode. This command may also be used to reset the device to the Read mode after any inad-

vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor-

rectly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program

or Erase operation. See Table 7 for software command codes, Figure 16 for timing waveform, and Fig-

ure 25 for flowcharts.

Table 5: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39VF401C/SST39LF401C 0001H 2321H

SST39VF402C/SST39LF402C 0001H 2322H

T5.2 25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Security ID

The SST39VF401C/402C and SST39LF401C/402C devices offer a 136 Word Security ID space. The

Secure ID space is divided into two segments—one factory programmed segment and one user pro-

grammed segment. The first segment is programmed and locked at the factory with a random 128-bit

number. The user segment, with a 128 word space, is left un-programmed for the customer to program

as desired.

To program the user segment of the Security ID, the user must use the Security ID Word-Program

command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once

this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables

any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither

Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID

command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID com-

mand should be executed. Refer to Table 7 for more details.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Operations

Table 6: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector or block address, XXH for Chip-

Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 7

T6.0 25053

Table 7: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr

1. Address format A10-A0(Hex). Addresses A11-A17 can be VIL or VIH, but no other value, for Command sequence.

Data

2. DQ15-DQ8can be VIL or VIH, but no other value, for Command sequence

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Word-Program 555H AAH 2AAH 55H 555H A0H WA3

3. WA = Program Word address

Data

Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX4

4. SAXfor Sector-Erase; uses AMS-A11 address lines

BAX, for Block-Erase; uses AMS-A15 address lines

AMS = Most significant address; AMS =A

50H

Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX430H

Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Erase-Suspend XXXH B0H

Erase-Resume XXXH 30H

Query Sec ID5555H AAH 2AAH 55H 555H 88H

User Security ID

Word-Program

555H AAH 2AAH 55H 555H A5H WA6Data

User Security ID

Program Lock-

Out

555H AAH 2AAH 55H 555H 85H XXH60000

Software ID

Entry7,8 555H AAH 2AAH 55H 555H 90H

CFI Query Entry 555H AAH 2AAH 55H 555H 98H

CFI Query Entry 55H 98H

Software ID Exit9,10

/CFI Exit/Sec ID

Exit

555H AAH 2AAH 55H 555H F0H

Software ID Exit9,10

/CFI Exit/Sec ID

Exit

XXH F0H

T7.6 25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

5. With AMS-A4= 0; Sec ID is read with A3-A0,

Microchip ID is read with A3= 0 (Address range = 000000H to 000007H),

User ID is read with A3= 1 (Address range = 000008H to 000087H).

Lock Status is read with A7-A0= 0000FFH. Unlocked: DQ3= 1 / Locked: DQ3=0.

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H.

7. The device does not remain in Software Product ID Mode if powered down.

8. With AMS-A1=0; Microchip Manufacturer ID = 00BFH, is read with A0=0,

SST39VF401C/SST39LF401C Device ID = 233BH, is read with A0= 1, SST39VF402C/SST39LF402C Device ID =

233AH, is read with A0=1,

AMS = Most significant address; AMS =A

9. Both Software ID Exit operations are equivalent

10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)

using the Sec ID mode again (the programmed ‘0’ bits cannot be reversed to ‘1’). Valid Word-Addresses for Sec ID are

from 000000H-000007H and 000008H-000087H.

Table 8: CFI Query Identification String1

Address Data Data

10H 0051H Query Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0002H Primary OEM command set

14H 0000H

15H 0000H Address for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H

T8.1 25053

1. Refer to CFI publication 100 for more details.

Table 9: System Interface Information

Address Data Data

1BH 0027H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 0036H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 0000H VPP min. (00H = no VPP pin)

1EH 0000H VPP max. (00H = no VPP pin)

1FH 0003H Typical time out for Word-Program 2Nµs (23= 8 µs)

20H 0000H Typical time out for min. size buffer program 2Nµs (00H = not supported)

21H 0004H Typical time out for individual Sector/Block-Erase 2Nms (24=16ms)

22H 0005H Typical time out for Chip-Erase 2Nms (25=32ms)

23H 0001H Maximum time out for Word-Program 2Ntimes typical (21x2

3=16µs)

24H 0000H Maximum time out for buffer program 2Ntimes typical

25H 0001H Maximum time out for individual Sector/Block-Erase 2Ntimes typical (21x2

4=32ms)

26H 0001H Maximum time out for Chip-Erase 2Ntimes typical (21x2

5=64ms)

T9.3 25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Table 10: Device Geometry Information

Address Data Data

27H 0013H Device size = 2NBytes

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of byte in multi-byte write = 2N(00H = not supported)

2BH 0000H

2CH 0005H Number of Erase Sector/Block sizes supported by device

2DH 0000H Erase Block Region 1 Information (Refer to the CFI specification or CFI publication

100)

2EH 0000H

2FH 0040H

30H 0000H

31H 0001H Erase Block Region 2 Information

32H 0000H

33H 0020H

34H 0000H

35H 0000H Erase Block Region 3 Information

36H 0000H

37H 0080H

38H 0000H

39H 0007H Erase Block Region 4 Information

3AH 0000H

3BH 0000H

3CH 0001H

T10.0 25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Electrical Specifications

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-

ditions may affect device reliability.)

Temperature Under Bias .............................................. -55°C to +125°C

Storage Temperature ................................................ -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential .............................-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential ..................-2.0V to VDD+2.0V

Voltage on A9Pin to Ground Potential .....................................-0.5V to 13.2V

Package Power Dissipation Capability (TA= 25°C) ................................... 1.0W

Surface Mount Solder Reflow ...................................... 260°C for 10 seconds

Output Short Circuit Current1.................................................. 50mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

Table 11: Operating Range

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V for SST39VF401C/402C or

3.0-3.6V for SST39LF401C/402C

Industrial -40°C to +85°C 2.7-3.6V for SST39VF401C/402C or

3.0-3.6V for SST39LF401C/402C

T11.0 25053

Table 12: AC Conditions of Test1

1. See Figures 20 and 21

Input Rise/Fall Time Output Load

5ns CL=30pF

T12.1 25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Power Up Specifications

All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100

ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware

reset is required. The recommended VDD power-up to RESET# high time should be greater than 100

µs to ensure a proper reset.

Figure 5: Power-Up Diagram

Table 13: DC Operating Characteristics VDD = 3.0-3.6V for SST39LF401C/402C and 2.7-

3.6V for SST39VF401C/402C1

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and VDD = 3V. Not 100% tested.

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT2, at f=5 MHz,

VDD=VDD Max

2. See Figure 20

3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.

18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 30 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 20 µA CE#=VIHC,V

DD=VDD Max

RST#=VDD±0.3, WP#=VDD±0.3,

WE#=VDD±0.3

IALP Auto Low Power 20 µA CE#=VILC,V

DD=VDD Max

All inputs=VSS or VDD, WE#=VIHC

ILI Input Leakage Current 1 µA VIN=GND to VDD,V

DD=VDD Max

ILIW Input Leakage Current

on WP# pin and RST#

10 µA WP#=GND to VDD or RST#=GND to VDD

ILO Output Leakage Current 10 µA VOUT=GND to VDD,V

DD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7VDD VDD+0.3 V VDD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 VDD+0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T13.8 25053

25053 F24.0

VDD

RESET#

CE#

TPU-READ 100µs

VDD min

VIH

TRHR 5 0ns

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Table 14: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T14.0 25053

Table 15: Capacitance (TA= 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

I/O Pin Capacitance VI/O =0V 12pF

CIN1Input Capacitance VIN =0V 6pF

T15.0 25053

Table 16: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would

result in a higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T16.2 25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

AC Characteristics

Table 17: Read Cycle Timing Parameters - VDD = 3.0-3.6V for SST39LF401C/402C and

2.7-3.6V for SST39VF401C/402C

Symbol Parameter

SST39VF401C/402C SST39LF401C/402C

UnitsMin Max Min Max

TRC Read Cycle Time 70 55 ns

TCE Chip Enable Access Time 70 55 ns

TAA Address Access Time 70 55 ns

TOE Output Enable Access Time 35 30 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 20 15 ns

TOHZ1OE# High to High-Z Output 20 15 ns

TOH1Output Hold from Address Change 0 0 ns

TRP1RST# Pulse Width 500 500 ns

TRHR1RST# High before Read 50 50 ns

TRY1,2

2. This parameter applies to Sector-Erase, Block-Erase and Program operations.

This parameter does not apply to Chip-Erase operations.

RST# Pin Low to Read Mode 20 20 µs

T17.3 25053

Table 18: Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Word-Program Time 10 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

TBY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

RY/BY# Delay Time 90 ns

TBR1Bus Recovery Time 0 µs

T18.1 25053

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 6: Read Cycle Timing Diagram

Figure 7: WE# Controlled Program Cycle Timing Diagram

25053 F03.0

ADDRESS AMS-0

DQ15-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ TOH

TCHZ

HIGH-Z

DATA VA L I DDATA VA L I D

TOHZ

Note: AMS = Most significant address

AMS =A

25053 F25.0

ADDRESSES

DQ15-0

CE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

RY/BY#

VALID

TDH

TWPH

TAS

TCH

TCS

TAH

TWP

TDS

TBY TBR

TBP

Note: WP# must be held in proper logic state (VIL

or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 8: CE# Controlled Program Cycle Timing Diagram

Figure 9: Data# Polling Timing Diagram

25053 F26.0

ADDRESSES

DQ15-0

WE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

CE#

RY/BY#

VALID

TDH

TCPH

TAS

TCH

TCS

TAH

TCP

TDS

TBY TBR

TBP

Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after

the command sequence.

X can be VIL or VIH, but no other value.

25053 F27.0

ADDRESS A17-0

DQ7DATA

WE#

OE#

CE#

RY/BY#

DATA# DATA # DATA

TOES

TOEH

TBY

TCE

TOE

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 10:Toggle Bits Timing Diagram

Figure 11:WE# Controlled Chip-Erase Timing Diagram

25053 F07.0

ADDRESS AMS-0

DQ6and DQ2

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most significant address

AMS =A

25053 F31.0

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX10

XX55XXAA XX80 XXAA

555

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR CHIP-ERASE

TOEH

TSCE

TBY TBR

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are inter-

changeable as long as minimum timings are met. (See Table 18).

WP# must be held in proper logic state (VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 12:WE# Controlled Block-Erase Timing Diagram

Figure 13:WE# Controlled Sector-Erase Timing Diagram

25053 F32.0

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX30

XX55XXAA XX80 XXAA

BAX

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR BLOCK-ERASE

TWP

TBE

TBY TBR

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are inter-

changeable as long as minimum timings are met. (See Table 18).

BAX= Block Address

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

25053 F28.0

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX50

XX55XXAA XX80 XXAA

SAX

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR SECTOR-ERASE

TWP

TSE

TBY TBR

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are inter-

changeable as long as minimum timings are met. (See Table 18).

SAX= Block Address

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 14:Software ID Entry and Read

Figure 15:CFI Query Entry and Read

25053 F11.0

ADDRESS

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555 0000 0001

OE#

CE#

Three-Byte Sequence for Software ID Entry

TWP

TWPH TAA

00BF Device IDXX55XXAA XX90

Note: Device ID = 233BH for SST39VF401C/SST39LF401C and 233AH for SST39VF401C/SST39LF401C

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

25053 F12.0

ADDRESS

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555

OE#

CE#

Three-Byte Sequence for CFI Query Entry

TWP

TWPH TAA

XX55XXAA XX98

Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 16:Software ID Exit/CFI Exit

Figure 17:Sec ID Entry

25053 F13.0

ADDRESS

DQ15-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

555 2AA 555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA XX55 XXF0

Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

25053 F20.0

ADDRESS A

MS-0

IDA

15-0

WE#

SW0 SW1 SW2

555 2AA 555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

WPH

XX55XXAA XX88

Note: AMS = Most significant address

AMS =A

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 18:RST# Timing Diagram (When no internal operation is in progress)

Figure 19:RST# Timing Diagram (During Program or Erase operation)

Figure 20:AC Input/Output Reference Waveforms

25053 F29.0

RY/BY#

RST#

CE#/OE#

TRP

TRHR

25053 F30.0

RY/BY#

CE#

OE#

TRP

TRY

TBR

RST#

25053 F14.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic ‘1’ and VILT (0.1 VDD) for a logic ‘0’. Measure-

ment reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and

fall times (10% 90%) are <5 ns.

Note: VIT -V

INPUT Test

VOT -V

OUTPUT Test

VIHT -V

INPUT HIGH Test

VILT -V

INPUT LOW Test

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 21:A Test Load Example

25053 F15.0

TO TESTER

TO DUT

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 22:Word-Program Algorithm

25053 F16.0

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Note: X can VIL or VIH, but no other value.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 23:Wait Options

25053 F17.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7=

true data

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

Ye s

RY/BY#

RY/BY# = 1

Read RY/BY#

Program/Erase

Initiated

Program/Erase

Completed

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 24:Software ID/CFI Entry Command Flowcharts

25053 F21.0

Load data: XXAAH

Address: 555H

Software Product ID

Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX98H

Address: 55H

Wait TIDA

Read CFI data

Load data: XXAAH

Address: 555H

Sec ID Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX88H

Address: 555H

Wait TIDA

Read Sec ID

Load data: XX98H

Address: 55H

Wait TIDA

Read CFI data

Note: X can VIL or VIH, but no other value.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 25:Software ID/CFI Exit Command Flowcharts

25053 F18.0

Load data: XXAAH

Address: 555H

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Load data: XXF0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

Note: X can be VIL or VIH, but no other value.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 26:Erase Command Sequence

25053 F19.0

Load data: XXAAH

Address: 555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XXAAH

Address: 555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX50H

Address: SAX

Load data: XXAAH

Address: 555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX30H

Address: BAX

Load data: XXAAH

Address: 555H

Wait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Product Ordering Information

SST 39 VF 401C - 70 - 4C - EKE

XX XX XXXX - XX - XX -XXX

Environmental Attribute

E1= non-Pb

Package Modifier

K = 48 balls or leads

Q = 48 balls (66 possible positions)

Package Type

E = TSOP (type1, die up, 12mm x 20mm)

B3 = TFBGA (6mm x 8mm, 0.8mm pitch)

MA = WFBGA (4mm x 6mm, 0.5mm pitch)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

55 = 55 ns

Hardware Block Protection

1 = Bottom Boot-Block

2 = Top Boot-Block

Device Density

40 = 4 Mbit

Voltage

V = 2.7-3.6V

L = 3.0-3.6V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder.

non-Pb solder devices are “RoHS Compliant”.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Valid Combinations for SST39VF401C

SST39VF401C-70-4C-EKE SST39VF401C-70-4C-B3KE SST39VF401C-70-4C-MAQE

SST39VF401C-70-4I-EKE SST39VF401C-70-4I-B3KE SST39VF401C-70-4I-MAQE

Valid Combinations for SST39VF402C

SST39VF402C-70-4C-EKE SST39VF402C-70-4C-B3KE SST39VF402C-70-4C-MAQE

SST39VF402C-70-4I-EKE SST39VF402C-70-4I-B3KE SST39VF402C-70-4I-MAQE

Valid Combinations for SST39LF401C

SST39LF401C-55-4C-EKE SST39LF401C-55-4C-B3KE SST39LF401C-55-4C-MAQE

Valid Combinations for SST39LF402C

SST39LF402C-55-4C-EKE SST39LF402C-55-4C-B3KE SST39LF402C-55-4C-MAQE

Note:Valid combinations are those products in mass production or will be in mass production. Consult your Micro-

chip sales representative to confirm availability of valid combinations and to determine availability of new

combinations.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Packaging Diagrams

Figure 27:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm

Package Code: EK

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Microchip Technology Drawing C04-14036A Sheet 1 of 1

48-Lead Thin Small Outline Package (EKE/F) - [TSOP]

48-tsop-EK-8

Note:

1. Complies with JE

DEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 28:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm

Package Code: B3K

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Microchip Technology Drawing C04-14035A Sheet 1 of 1

48-Lead Thin Fine-Pitch Ball Grid Array (B3KE/F) - 6x8 mm Body [TFBGA]

48-tfbga-B3K-6x8-450mic-5

Note:

1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Figure 29:48-ball Very, Very Thin-profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm

Package Code: MAQ

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Microchip Technology Drawing C04-14039A Sheet 1 of 1

48-Lead Very, Very Thin Find-Pitch Ball Grid Array (MAQE/F) - 4x6 mm Body [WFBGA]

48-wfbga-MAQ-4x6-32mic-2.

Note:

1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger

and bottom side A1 indicator is triangle at corner.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm

4. Ball opening size is 0.29 mm (± 0.05 mm)

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Table 19: Revision History

Number Description Date

A•Initial release Oct 2011

B•Updated product description on page 1 and 2 to correct a typo

•Clarified the voltage information on page 1.

•Updated package drawing to the new format in “Packaging Diagrams” on

page 35

Apr 2014

2014 Microchip Technology Inc.

SST, Silicon Storage Technology, the SST logo, SuperFlash, and MTP are registered trademarks of Microchip Technology, Inc.

MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Microchip Technology, Inc. All other trademarks and registered trade-

marks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current

package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

Microchip makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions

of Sale.

For sales office locations and information, please see www.microchip.com.

www.microchip.com

ISBN:978-1-63276-111-8