HIGH-PERFORMANCE PRODUCTS
1www.semtech.com
Revision 1/February 13, 2001
SK10/100E151
6-Bit D Register
Description Features
Functional Block Diagram
PIN Description
The SK10/100E151 offers 6 edge-triggered, high-speed,
master-slave D-type flip-flops with differential outputs,
designed for use in new high-performance ECL systems.
This device is fully compatible with MC10E151 and
MC100E151. The two external clock signals (CLK1, CLK2)
are gated through a logical OR operation before use as
clocking control for the flip-flops. Data is clocked into
the flip-flops on the rising edge of either CLK1 or CLK2
(or both). When both CLK1 and CLK2 are at a logic
LOW, data enters the master and is transferred to the
slave when either CLK or CLK2 (or both) go HIGH.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
• 1100 MHz Toggle Frequency
• Extended 100E VEE Range of –4.2V to –5.46V
• Differential Outputs
• Asynchronous Master Reset
• Dual Clocks
• Internal 75KΩ Input Pull-Down Resistors
• ESD Protection of >4000V
• Fully Compatible with MC10E/100E151
• Specified Over Industrial Temperature Range:
–40oC to +85oC
• Available in 28-Pin PLCC Package
niPnoitcnuF
5D0DstupnIataD
2KLC,1KLCstupnIkcolC
RMteseRretsaM
5Q0QstuptuOeurT
*5Q*0QstuptuOgnitrevnI
0CCVtuptuOotCCV
DQ0
D0
Q0*
R
DQ1
D1
Q1*
R
DQ2
D2
Q2*
R
DQ3
D3
Q3*
R
DQ4
D4
Q4*
R
DQ5
D5
CLK1
CLK2
MR
Q5*
R
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25
24
23
22
21
20
19
MR
CLK2
CLK1
NC
VCC0
Q5*
Q5
Q4*
Q4
VCC
Q3*
Q3
Q2*
Q2
D5
D4
D3
VEE
D2
D1
D0
NC
VCC0
Q0
Q0*
Q1
Q1*
VCC0
5
6
7
8
9
10
11
PLCC
T OP VIEW
2Revision 1/February 13, 2001 www.semtech.com
HIGH-PERFORMANCE PRODUCTS
SK10/100E151
PIN Description (continued)
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nD1KLC2KLCRM)1+t(nQ
XXXHL
stupnItuptuO
nD1KLC2KLCRM)1+t(nQ
LuLLL
HuLLH
LLuLL
HLuLH
XHuL )t(nQ
XuHL )t(nQ
XLLL )t(nQ
Truth Tables
Asynchronous Operation
Synchronous Operation
1. H = HIGH Voltage Level
2. L = LOW Voltage Level
3. X = Don’t Care
4. t = Time Before Positive CLK Transition
5. t+1 = Time After Positive CLK Transition
6. u = LOW-to-HIGH Transition
NOTES:
3
Revision 1/February 13, 2001 www.semtech.com
HIGH-PERFORMANCE PRODUCTS
SK10/100E151
Package Information
PIN Descriptions
28-Pin PLCC Package
–L–
–M–
–N–
28 1 V
W
Y BRK
D
D
Z
0.007 (0.180) T L – M N
SS
0.007 (0.180) T L – M N
MSS
J
A
R
EE
C
G1
G0.004 (0.100)
–T–
SEATING PLANE
VIEW S
0.010 (0.250) T L – M N
SS
M
++
+
S
+
+
Z
X
U
B
G1
0.007 (0.180) T L - M N
SS
0.007 (0.180) T L - M N
M SS
0.010 (0.250) T L - M N
S
SS
M
K
K1
H
F
0.007 (0.180) T L – M N
MS
0.007(0.180) T L – M N
MS
S
S
MIDNIMXAMNIMXAM
A584.0594.023.2175.21
B584.0594.023.2175.21
C561.0081.002.475.4
E090.0011.092.297.2
F310.0910.033.084.0
G050.0CSB72.1CSB
H620.0230.066.018.0
J020.0--15.0--
K520.0--46.0--
R054.0654.034.1185.11
U054.0654.034.1185.11
V240.0840.070.112.1
W240.0840.070.112.1
X240.0650.070.124.1
Y--020.0--05.0
Z2
o
01
o
2
o
01
o
1G014.0034.024.0129.01
1K040.0--20.1--
MILLIMETERS
INCHES
NOTES:
1. Datums -L-, -M-, and -N - determined where top of
lead shoulder exits plastic body at mold parting line.
2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.
3. DIM R and U do not include mold flash. Allowable
mold flash is 0.010 (0.250) per side.
4. Dimensioning and tolerancing per ANSI Y14.5M,
1982.
5. Controlling Dimension: Inch.
6. The package top may be smaller than the package
bottom by up to 0.012 (0.300). Dimensions R and
U are determined at the outermost extremes of the
plastic body exclusive of mold flash, tie bar burrs,
gate burrs and interlead flash, but including any
mismatch between the top and bottom of the plastic
body.
7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause
the H dimension to be greater than 0.037 (0.940).
The Dambar intrusion(s) shall not cause the H
dimension to be smaller than 0.025 (0.635).
4Revision 1/February 13, 2001 www.semtech.com
HIGH-PERFORMANCE PRODUCTS
SK10/100E151
AC Characteristics
SK10/100E151 AC Electrical Characteristics
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fXAM ycneuqerFelggoTmumixaM00110041001100410011004100110041zHM
tHLP
tLHP
tuptuOotyaleDnoitagaporP KLC RM 634 974 435 685 174 215 575 326 494 435 206 946 355 195 076 517 spsp
tSD,emiTputeS0571057105710571sp
tHD,emiTdloH053571053571053571053571sp
tRR emiTyrevoceRteseR057055057055057055057055sp
tWP htdiWesluPmuminiM RM,KLC 004004004004sp
wekstwekSeciveD-nihtiW56565656sp
trt, fsemiTllaF/esiRtuptuO )%08ot%02( 781165391135791494902714sp
TA = –40oC TA = 0oC TA = +25oC TA = +85oC
Notes:
1. 10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained. Outputs are terminated through a 50Ω resistor to VCC –2.0V.
2. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow
greater than 500 lfpm is maintained.
3. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specification Data
Sheet.
4. For part ordering description, see HPP Part Ordering Information Data Sheet.
(VCC – VEE = 4.2V to 5.46V ; VOUT loaded 50Ω to VCC – 2.0V)
DC Characteristics
(VCC – VEE = 4.2V to 5.46V; VOUT loaded 50Ω to VCC– 2.0V)
SK10/100E151 DC Electrical Characteristics (Notes 1, 2)
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I
HI
tnerruChgiHtupnI051051051051Aµ
I
EE
tnerruCylppuSrewoP LE01 LE001 4434 8787 4434 8787 4434 8787 4434 8758 AmAm
V
CC
V
EE
egatloVylppuSrewoP2.464.52.464.52.464.52.464.5V
TA = –40oC TA = 0oC TA = +25oC TA = +85oC
5
Revision 1/February 13, 2001 www.semtech.com
HIGH-PERFORMANCE PRODUCTS
SK10/100E151
Ordering Information
edoCgniredrODIegakcaPegnaRerutarepmeT
JP151E01KSCCLP-82lairtsudnI
TJP151E01KSCCLP-82lairtsudnI
JP151E001KSCCLP-82lairtsudnI
TJP151E001KSCCLP-82lairtsudnI
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Phone: (858) 695-1808
FAX: (858) 695-2633
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1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
FAX: (408) 727-8994
Semtech Corporation
High-Performance Products Division
Contact Information