PRELIMINARY PRODUCT SPECIFICATION 1 Z86E33/733/E34 Z86E43/743/E44 1 CMOS Z8 OTP MICROCONTROLLERS FEATURES Device ROM (KB) RAM* (Bytes) I/O Lines Speed (MHz) Z86E33 Z86733 Z86E34 Z86E43 Z86743 Z86E44 4 8 16 4 8 16 237 237 237 236 236 236 24 24 24 32 32 32 12 12 12 12 12 12 Note: *General-Purpose Standard Temperature (VCC = 3.5V to 5.5V) Extended Temperature (VCC = 4.5V to 5.5V) Available Packages: 28-Pin DIP/SOIC/PLCC OTP (E33/733/E34) 40-Pin DIP OTP (E43/743/E44) 44-Pin PLCC/QFP OTP (E43/743/E44) Software Enabled Watch-Dog Timer (WDT) Push-Pull/Open-Drain Programmable on Port 0, Port 1, and Port 2 24/32 Input/Output Lines Clock-Free WDT Reset Auto Power-On Reset (POR) Programmable OTP Options: RC Oscillator EPROM Protect Auto Latch Disable Permanently Enabled WDT Crystal Oscillator Feedback Resistor Disable RAM Protect Low-Power Consumption: 60 mW Fast Instruction Pointer: 0.75 s Two Standby Modes: STOP and HALT Digital Inputs CMOS Levels, Schmitt-Triggered Software Programmable Low EMI Mode Two Programmable 8-Bit Counter/Timers Each with a 6-Bit Programmable Prescaler Six Vectored, Priority Interrupts from Six Different Sources Two Comparators On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive GENERAL DESCRIPTION The Z86E33/733/E34/E43/743/E44 8-Bit One-Time Programmable (OTP) Microcontrollers are members of Zilog's single-chip Z8 (R) MCU family featuring enhanced wake-up circuitry, programmable Watch-Dog Timers, Low Noise EMI options, and easy hardware/software system expansion capability. Four basic address spaces support a wide range of memory configurations. The designer has access to three addi- DS97Z8X1500 tional control registers that allow easy access to register mapped peripheral and I/O circuits. For applications demanding powerful I/O capabilities, the Z86E33/733/E34 have 24 pins, and the Z86E43/743/E44 have 32 pins of dedicated input and output. These lines are grouped into four ports, eight lines per port, and are configurable under software control to provide timing, status sig- PRELIMINARY 1 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog GENERAL DESCRIPTION (Continued) nals, and parallel I/O with or without handshake, and address/data bus for interfacing external memory. Power connections follow conventional descriptions below: Notes: All signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Connection Circuit Device Power VCC VDD Ground GND VSS (E43/743/E44 Only) Output Input VCC GND XTAL /AS /DS R//W /RESET Machine Timing & Instruction Control Port 3 Counter/ Timers (2) RESET WDT, POR ALU FLAGS Interrupt Control Two Analog Comparators OTP Register Pointer Register File Program Counter Port 0 Port 1 Port 2 4 I/O (Bit Programmable) 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) (E43/743/E44 Only) Figure 1. Functional Block Diagram 2 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog D7 - 0 1 AD 11- 0 Z8 MCU AD 11- 0 Address MUX D7 - 0 AD 13- 0 Address Counter EPROM TEST ROM Data MUX D7 - 0 Z8 Port 2 OTP Options PGM + Test Mode Logic VPP P33 CLR CLK (P00) (P01) EPM P32 /OE P31 /PGM P02 /CE XT1 Figure 2. EPROM Programming Block Diagram DS97Z8X1500 PRELIMINARY 3 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PIN IDENTIFICATION Table 1. 40-Pin DIP Pin Identification Standard Mode R//w P25 P26 P27 P04 P05 P06 P14 P15 P07 VCC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 /AS 1 40 DIP 40 - Pin 20 21 /DS P24 P23 P22 P21 P20 P03 P13 P12 GND P02 P11 P10 P01 P00 P30 P36 P37 P35 /RESET Figure 3. 40-Pin DIP Pin Configuration Standard Mode 4 Pin # Symbol Function Direction 1 2-4 5-7 8-9 10 11 R//W P25-P27 P04-P06 P14-P15 P07 VCC Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Output In/Output In/Output In/Output In/Output 12-13 14 15 16-18 19 20 21 22 23 24 25 26-27 28-29 30 31 32-33 34 35-39 40 P16-P17 XTAL2 XTAL1 P31-P33 P34 /AS /RESET P35 P37 P36 P30 P00-P01 P10-P11 P02 GND P12-P13 P03 P20-P24 /DS Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe In/Output Output Input Input Output Output Input Output Output Output Input In/Output In/Output In/Output PRELIMINARY In/Output In/Output In/Output Output DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog 1 6 P21 P22 P23 P24 /DS NC R//W P25 P26 P27 P04 1 40 39 7 44-Pin PLCC 17 29 28 18 P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31 Figure 4. 44-Pin PLCC Pin Configuration Standard Mode Table 2. 44-Pin PLCC Pin Identification Pin # Symbol Function 1-2 3-4 5 6-10 11 12 13 14-16 17-19 20-21 22 23-24 25-26 27 GND P12-P13 P03 P20-P24 /DS NC R//W P25-P27 P04-P06 P14-P15 P07 VCC P16-P17 XTAL2 Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe No Connection Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1, Pins 6,7 Crystal Oscillator DS97Z8X1500 Direction In/Output In/Output In/Output Output Output In/Output In/Output In/Output In/Output In/Output Output Table 2. 44-Pin PLCC Pin Identification Pin # Symbol Function Direction 28 29-31 32 33 34 35 36 37 38 39 40-41 42-43 44 XTAL1 P31-P33 P34 /AS R//RL /RESET P35 P37 P36 P30 P00-P01 P10-P11 P02 Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Input Input Output Output Input Input Output Output Output Input In/Output In/Output In/Output PRELIMINARY 5 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PIN IDENTIFICATION (Continued) 33 P21 P22 P23 P24 /DS NC R//W P25 P26 P27 P04 23 22 34 44-Pin QFP 12 11 44 1 P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31 Figure 5. 44-Pin QFP Pin Configuration Standard Mode Table 3. 44-Pin QFP Pin Identification Table 3. 44-Pin QFP Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1-2 3-4 5 6-7 8-9 10 11 12-14 15 16 17 18 19 20 21 P05-P06 P14-P15 P07 VCC P16-P17 XTAL2 XTAL1 P31-P33 P34 /AS R//RL /RESET P35 P37 P36 Port 0, Pins 5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 In/Output In/Output In/Output 22 23-24 25-26 27 28-29 30-31 32 33-37 38 39 40 41-43 44 P30 P00-P01 P10-P11 P02 GND P12-P13 P03 P20-24 /DS NC R//W P25-P27 P04 Port 3, Pin 0 Port 0, Pin 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe No Connection Read/Write Port 2, Pins 5,6,7 Port 0, Pin 4 Input In/Output In/Output In/Output 6 In/Output Output Input Input Output Output Input Input Output Output Output PRELIMINARY In/Output In/Output In/Output Output Output In/Output In/Output DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Table 4. 40-Pin DIP Package Pin Identification EPROM Mode NC D5 D6 D7 NC NC NC NC NC NC VCC NC NC NC /CE /OE EPM VPP NC NC 1 40 40-Pin DIP 20 21 NC D4 D3 D2 D1 D0 NC NC NC GND /PGM NC NC CLK CLR NC NC NC NC NC Figure 6. 40-Pin DIP Pin Configuration EPROM Mode DS97Z8X1500 Pin # Symbol Function 1 2-4 5-10 11 NC D5-D7 NC VCC No Connection Data 5,6,7 No Connection Power Supply 12-14 15 16 17 18 19-25 26 27 28-29 30 31 32-34 35-39 40 NC /CE /OE EPM VPP NC CLR CLK NC /PGM GND NC D0-D4 NC No Connection Chip Select Output Enable EPROM Prog. Mode Prog. Voltage No Connection Clear Clock No Connection Prog. Mode Ground No Connection Data 0,1,2,3,4 No Connection PRELIMINARY 1 Direction In/Output Input Input Input Input Input Input Input In/Output 7 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PIN IDENTIFICATION (Continued) 6 D1 D2 D3 D4 NC NC NC D5 D6 D7 NC 1 40 39 7 44 -Pin PLCC 17 29 28 18 NC NC NC NC NC NC NC NC VPP EPM /OE Figure 7. 44-Pin PLCC Pin Configuration EPROM Programming Mode Table 5. 44-Pin PLCC Pin Configuration EPROM Programming Mode Pin # Symbol Function 1-2 3-5 6-10 11-13 14-16 17-22 23-24 25-27 28 GND NC D0-D4 NC D5-D7 NC VCC NC /CE Ground No Connection Data 0,1,2,3,4 No Connection Data 5,6,7 No Connection Power Supply No Connection Chip Select 8 Direction Table 5. 44-Pin PLCC Pin Configuration EPROM Programming Mode Pin # Symbol Function Direction 29 30 /OE EPM Input Input 31 VPP Output Enable EPROM Prog. Mode Prog. Voltage 32-39 40 41 42-43 44 NC CLR CLK NC /PGM No Connection Clear Clock No Connection Prog. Mode In/Output In/Output Input PRELIMINARY Input Input Input Input DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog 1 33 D1 D2 D3 D4 NC NC NC D5 D6 D7 NC 23 22 34 44 -Pin QFP 12 11 44 1 NC NC NC NC NC NC NC NC VPP EPM /OE Figure 8. 44-Pin QFP Pin Configuration EPROM Programming Mode Table 6. 44-Pin QFP Pin Identification EPROM Programming Mode Pin # Symbol Function 1-5 6-7 NC VCC No Connection Power Supply 8-10 11 12 13 NC /CE /OE EPM 14 VPP No Connection Chip Select Output Enable EPROM Prog. Mode Prog. Voltage 15-22 23 NC CLR No Connection Clear DS97Z8X1500 Table 6. 44-Pin QFP Pin Identification EPROM Programming Mode Direction Pin # Symbol Function Direction CLK NC /PGM GND NC D0-D4 NC D5-D7 NC Clock No Connection Prog. Mode Ground No Connection Data 0,1,2,3,4 No Connection Data 5,6,7 No Connection Input Input Input Input 24 25-26 27 28-29 30-32 33-37 38-40 41-43 44 Input Input In/Output In/Output Input PRELIMINARY 9 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PIN IDENTIFICATION (Continued) P25 P26 P27 P04 P05 P06 P07 VCC XTAL2 XTAL1 P31 P32 P33 P34 1 28 28-Pin DIP/SOIC 14 15 P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35 4 XXX P05 XXX P06 XXX P07 VCC XXX XXX XT2 XXX XT1 XXX P31 Figure 9. Standard Mode 28-Pin DIP/SOIC Pin Configuration 1 5 26 25 28-Pin PLCC 11 12 19 18 P21 XXX XXX P20 XXX P03 XXX VSS XXX P02 XXX P01 XXX P00 Figure 10. Standard Mode 28-Pin PLCC Pin Configuration Table 7. 28-Pin DIP/SOIC/PLCC Pin Identification Standard Mode Pin # Symbol Function 1-3 4-7 8 P25-P27 P04-P07 VCC Port 2, Pins 5,6, In/Output Port 0, Pins 4,5,6,7 In/Output Power Supply 9 10 11-13 14-15 16 17 18 19-21 22 XTAL2 XTAL1 P31-P33 P34-P35 P37 P36 P30 P00-P02 VSS Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1,2 Ground Output Input Input Output Output Output Input In/Output 23 24-28 P03 P20-P24 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 In/Output In/Output 10 Direction PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog D5 D6 D7 NC NC NC NC VCC NC /CE /OE EPM VPP NC 1 28 28-Pin DIP/SOIC 14 15 Table 8. 28-Pin EPROM Pin Identification EPROM Mode D4 D3 D2 D1 D0 NC VSS /PGM CLK CLR NC NC NC NC Figure 11. EPROM Programming Mode 28-Pin DIP/SOIC Pin Configuration 4 XXX NC XXX NC XXX NC VCC XXX XXX NC XXX /CE XXX /OE 1 5 26 25 28-Pin PLCC 11 12 19 18 Pin # Symbol Function Direction 1-3 4-7 8 D5-D7 NC VCC Data 5,6,7 No Connection Power Supply In/Output 9 10 11 12 NC /CE /OE EPM 13 VPP No connection Chip Select Output Enable EPROM Prog. Mode Prog. Voltage 14-18 19 20 21 22 NC CLR CLK /PGM VSS No Connection Clear Clock Prog. Mode Ground 23 24-28 NC D0-D4 No Connection Data 0,1,2,3,4 1 Input Input Input Input Input In/Output D1 XXX XXX D0 XXX NC XXX VSS XXX /PGM XXX CLK XXX CLR Figure 12. EPROM Programming Mode 28-Pin PLCC Pin Configuration DS97Z8X1500 PRELIMINARY 11 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog ABSOLUTE MAXIMUM RATINGS Parameter Min Max Units Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] -40 -65 -0.6 +105 +150 +7 C C V Voltage on VDD Pin with Respect to VSS -0.3 +7 V Voltage on XTAL1, P32, P33 and /RESET Pins with Respect to VSS [Note 2] -0.6 VDD+1 V Total Power Dissipation Maximum Allowable Current out of VSS 1.21 220 W mA Maximum Allowable Current into VDD 180 mA +600 +600 25 25 3 A A mA mA mA Maximum Allowable Current into an Input Pin [Note 3] Maximum Allowable Current into an Open-Drain Pin [Note 4] Maximum Allowable Output Current Sunk by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin Maximum Allowable Output Current Sunk by /RESET Pin -600 -600 Notes: 1. This applies to all pins except XTAL pins and where otherwise noted. 2. There is no input protection diode from pin to VDD. 3. This excludes XTAL pins. 4. Device pin is not at an output Low state. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power dissipation should not exceed 1.2 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [ IDD - (sum of IOH) ] + sum of [ (VDD - VOH) x IOH ] + sum of (V0L x I0L) STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Test Load). From Output Under Test 150 pF Figure 13. Test Load Diagram 12 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog CAPACITANCE TA = 25C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND. Parameter 1 Min Max 0 0 0 12 pF 12 pF 12 pF Input capacitance Output capacitance I/O capacitance DC ELECTRICAL CHARACTERISTICS TA= 0 C to +70 C Sym Parameter VCC Note [3] Min Max Typical @ 25C Units Conditions Notes VCH Clock Input High Voltage 3.5V 5.5V 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 1.8 2.5 V V VCL Clock Input Low Voltage 3.5V 5.5V GND-0.3 GND-0.3 0.2 VCC 0.2 VCC 0.9 1.5 V V VIH Input High Voltage 3.5V 5.5V 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 2.5 2.5 V V VIL Input Low Voltage 3.5V 5.5V GND-0.3 GND-0.3 0.2 VCC 0.2 VCC 1.5 1.5 V V VOH Output High Voltage Low EMI Mode 3.5V 5.5V VCC-0.4 VCC -0.4 3.3 4.8 V V IOH = - 0.5 mA VOH1 Output High Voltage 3.5V 5.5V VCC-0.4 VCC-0.4 3.3 4.8 V V IOH = -2.0 mA IOH = -2.0 mA VOL Output Low Voltage Low EMI Mode 3.5V 5.5V 0.4 0.4 0.2 0.2 V V IOL = +1.0 mA IOL = +1.0 mA VOL1 Output Low Voltage 3.5V 5.5V 0.4 0.4 0.1 0.1 V V IOL = + 4.0 mA IOL = + 4.0 mA 8 8 VOL2 Output Low Voltage 3.5V 5.5V 1.2 1.2 0.5 0.5 V V IOL = + 10 mA IOL = + 10 mA 8 8 VRH Reset Input High Voltage 3.5V 5.5V .8 VCC .8 VCC VCC VCC 1.7 2.1 V V 13 13 VRL Reset Input Low Voltage 3.5V 5.5V GND -0.3 GND -0.3 0.2 VCC 0.2 VCC 1.3 1.7 V V 13 13 VOLR Reset Output Low Voltage 3.5V 5.5V 0.6 0.6 0.3 0.2 V V VOFFSET Comparator Input Offset Voltage Input Common Mode Voltage Range 3.5V 5.5V 3.5V 5.5V 10 10 0 0 25 25 VCC -1.0V VCC -1.0V mV mV V V IIL Input Leakage 3.5V 5.5V -1 -1 2 2 0.032 0.032 A A VIN = 0V, VCC VIN = 0V, VCC IOL Output Leakage 3.5V 5.5V -1 -1 2 2 0.032 0.032 A A VIN = 0V, VCC VIN = 0V, VCC VICR DS97Z8X1500 PRELIMINARY Driven by External Clock Generator Driven by External Clock Generator IOL = +1.0 mA IOL = +1.0 mA 13 13 10 10 13 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA= 0 C to +70 C Sym Parameter IIR Reset Input Current ICC Supply Current ICC1 Standby Current Halt Mode VCC Note [3] 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V Min Max Typical @ 25C Units -20 -20 -130 -180 15 20 4 6 -65 -112 5 15 2 4 A A mA mA mA mA 3 5 10 10 15 30 1.5 3 2 3 7 10 mA mA A A A A Conditions @ 12 MHz @ 12 MHz VIN = 0V, VCC @ 12 MHz Clock Divide by 16 @ 12 MHz VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC Notes 4,5 4,5 4,5 4,5 ICC2 Standby Current Stop Mode 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 4,5 4,5 6,11 6,11 6,11,14 6,11,14 IALL Auto Latch Low Current 3.5V 5.5V 0.7 1.4 8 15 2.4 4.7 A A 0V <VIN<VCC 0V <VIN<VCC 9 9 IALH Auto Latch High Current 3.5V 5.5V -0.6 -1 -5 -8 -1.8 -3.8 A A 0V<VIN<VCC 0V<VIN<VCC 9 9 TPOR Power On Reset 3.5V 5.5V VLV Auto Reset Voltage 3.0 2.0 2.3 24 13 3.0 7 4 2.8 ms ms V 1,7 Notes: 1. Device does function down to the Auto Reset voltage. 2. GND=0V 3. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees only 3.5V. 4. All outputs unloaded, I/O pins floating, inputs at rail. 5. CL1= CL2 = 22 pF 6. Same as note [4] except inputs at VCC. 7. Max. temperature is 70C. 8. STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected 10. For analog comparator inputs when analog comparators are enabled. 11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. 12. Typicals are at VCC = 5.0V and VCC = 3.5V 13. Z86E43/743/E44 only. 14. WDT running 14 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog TA=-40 C to +105 C Sym Parameter VCC Note [3] Min Max Typical @ 25C Units Conditions VCH Clock Input High Voltage 4.5V 5.5V 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 2.5 2.5 V V Driven by External Clock Generator VCL Clock Input Low Voltage 4.5V 5.5V GND-0.3 GND-0.3 0.2 VCC 0.2 VCC 1.5 1.5 V V Driven by External Clock Generator VIH Input High Voltage 4.5V 5.5V 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 2.5 2.5 V V VIL Input Low Voltage 4.5V 5.5V GND-0.3 GND-0.3 0.2 VCC 0.2 VCC 1.5 1.5 V V VOH Output High Voltage Low EMI Mode Output High Voltage 4.5V 5.5V VCC-0.4 VCC-0.4 4.8 4.8 V V IOH = - 0.5 mA IOH = - 0.5 mA 8 8 4.5V 5.5V VCC-0.4 VCC-0.4 4.8 4.8 V V IOH = -2.0 mA IOH = -2.0 mA 8 8 VOH1 VOL Output Low Voltage Low EMI Mode 4.5V 5.5V 0.4 0.4 0.2 0.2 V V IOL = +1.0 mA IOL = +1.0 mA VOL1 Output Low Voltage 4.5V 5.5V 0.4 0.4 0.1 0.1 V V IOL = + 4.0 mA IOL = +4.0 mA 8 8 VOL2 Output Low Voltage 4.5V 5.5V 1.2 1.2 0.5 0.5 V V IOL = + 12 mA IOL = + 12 mA 8 8 VRH Reset Input High Voltage 4.5V 5.5V VCC VCC 1.7 2.1 V V VOLR Reset Output Low Voltage 4.5V 5.5V 0.6 0.6 0.3 0.2 V V VOFFSET Comparator Input Offset Voltage VICR Input Common Mode Voltage Range IIL Input Leakage 4.5V 5.5V 4.5V 5.5V 0 0 25 25 VCC-1.5V VCC-1.5V 4.5V 5.5V 4.5V 5.5V -1 -1 -1 -1 2 2 2 2 <1 <1 <1 <1 A A A A 4.5V 5.5V 4.5V 5.5V 4.5V -18 -18 -180 -180 20 20 6 -112 -112 15 15 2 A A mA mA mA 5.5V 6 4 mA 4.5V 5.5V 4.5V 5.5V 10 10 40 40 2 3 10 10 A A A A IOL Output Leakage IIR Reset Input Current ICC Supply Current ICC1 Standby Current Halt Mode ICC2 Standby Current (Stop Mode) DS97Z8X1500 .8 VCC .8 VCC 10 10 PRELIMINARY 1 Notes 13 13 IOL = +1.0 mA IOL = +1.0 mA mV mV V V 13 13 10 10 VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC @ 12 MHz @ 12 MHz VIN = 0V, VCC @ 12 MHz VIN = 0V, VCC @ 12 MHz VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC 13 13 4,5 4,5 4,5 4,5 6,11 6,11 6,11,14 6,11,14 15 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA=-40 C to +105 C Sym Parameter VCC Note [3] Min Max Typical @ 25C Units Conditions Notes IALL Auto Latch Low Current 4.5V 5.5V 1.4 1.4 20 20 4.7 4.7 A A 0V < VIN < VCC 0V < VIN < VCC 9 9 IALH Auto Latch High Current 4.5V 5.5V -1.0 -1.0 -10 -10 -3.8 -3.8 A A 0V < VIN < VCC 0V < VIN < VCC 9 9 TPOR Power On Reset 4.5V 5.5V VLV Auto Reset Voltage 2.0 2.0 2.0 14 14 3.3 4 4 2.8 ms ms V 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 16 1 Device does function down to the Auto Reset voltage. GND=0V The VCC voltage specification of 5.5V guarantees 5.0V 0.5V. All outputs unloaded, I/O pins floating, inputs at rail. CL1= CL2 = 22 pF Same as note [4] except inputs at VCC. Maximum temperature is 70C STD Mode (not Low EMI Mode) Auto Latch (mask option) selected For analog comparator inputs when analog comparators are enabled. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. Typicals are at VCC = 5.0V Z86E43/743/E44 only. WDT is not running. PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog 1 R//W , /DM 13 12 19 Port 0 16 18 Port 1 3 A7 - A0 1 D7 - D0 IN 2 9 /AS 11 8 4 6 5 /DS (Read) 17 10 Port1 A7 - A0 D7 - D0 OUT 14 15 7 /DS (W rite) Figure 14. External I/O or Memory Read/Write Timing (Z86E43/743/E44 Only) DS97Z8X1500 PRELIMINARY 17 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA = 0C to 70C 12 MHz No Symbol Note [3] VCC Parameter 1 TdA(AS) 2 TdAS(A) 3 TdAS(DR) 4 TwAS Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width 5 TdAS(DS) Address Float to /DS Fall 6 TwDSR /DS (Read) Low Width 7 TwDSW /DS (Write) Low Width 8 TdDSR(DR) 9 ThDR(DS) 10 TdDS(A) 11 TdDS(AS) /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay 12 TdR/W(AS) 13 TdDS(R/W) 14 TdDW(DSW) 15 TdDS(DW) 16 TdA(DR) 17 TdAS(DS) Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay 18 TdDM(AS) /DM Valid to /AS Rise Delay 19 ThDS(AS) /DS Valid to Address Valid Hold Time R//W Valid to /AS Rise Delay /DS Rise to R//W Not Valid 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V Min Max 35 35 45 45 250 250 55 55 0 0 200 200 110 110 150 150 0 0 45 55 30 45 45 45 45 45 55 55 45 55 310 310 65 65 35 35 35 35 Units Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 2 2 1,2 1,2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 2 2 2 2 2 2 Notes: 1. When using extended memory timing, add 2 TpC. 2. Timing numbers given are for minimum TpC. 3. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees only 3.5V Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0. 18 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog No Symbol TA = -40C to 105C 12 MHz Note [3] VCC Min Max Parameter 1 TdA(AS) 2 TdAS(A) 3 TdAS(DR) 4 TwAS Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width 5 TdAS(DS) Address Float to /DS Fall 6 TwDSR /DS (Read) Low Width 7 TwDSW /DS (Write) Low Width 8 TdDSR(DR) 9 ThDR(DS) 10 TdDS(A) 11 TdDS(AS) /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay 12 TdR/W(AS) 13 TdDS(R/W) 14 TdDW(DSW) 15 TdDS(DW) 16 TdA(DR) 17 TdAS(DS) Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay 18 TdDM(AS) /DM Valid to /AS Rise Delay 19 ThDS(AS) /DS Valid to Address Valid Hold Time R//W Valid to /AS Rise Delay /DS Rise to R//W Not Valid 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 35 35 45 45 250 250 55 55 0 0 200 200 110 110 150 150 0 0 45 55 45 45 45 45 45 45 55 55 55 55 310 310 65 65 35 35 35 35 Units Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 2 2 1,2 1,2 2 2 1 1,2 1,2 1,2 1,2 1,2 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 2 2 2 2 2 2 Notes: 1. When using extended memory timing, add 2 TpC. 2. Timing numbers given are for minimum TpC. 3. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees only 3.5V Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. For Standard Mode (not Low-EMI Mode for outputs) with SMR, D1 = 0, D0 = 0. DS97Z8X1500 PRELIMINARY 19 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS (Continued) 3 1 Clock 2 7 2 3 7 TIN 4 5 6 IRQN 8 9 Clock Setup 11 Stop Mode Recovery Source 10 Figure 15. Additional Timing Diagram 20 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Additional Timing Table (Divide-By-One Mode) TA = 0 C to +70 C 4 MHz No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC 3 TwC Clock Input Rise & Fall Times Input Clock Width 4 TwTinL 5 TwTinH 6 TpTin 7 TrTin, TfTin Timer Input Rise & Fall Timer TwIL Int. Request Low Time TwIL Int. Request Low Time TwIH Int. Request Input High Time Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time 8A 8B 9 10 11 Timer Input Low Width Timer Input High Width Timer Input Period VCC Note [6] 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 1 6 MHz Min Max Min Max Units Notes 250 250 DC DC 25 25 166 166 DC DC 25 25 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,2,7,8 1,2,7,8 1,3,7,8 1,3,7,8 1,2,7,8 1,2,7,8 4,8 4,8 100 100 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 3.5V 5.5V 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC ns ns 5TpC 5TpC 4,8,9 4,8,9 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 1, POR STOP Mode Delay is on. 5. Reg. WDTMR. 6. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 = 0. 8. Maximum frequency for internal system clock is 4 MHz when using Low EMI OSC PCON Bit D7 = 0. 9. For RC and LC oscillator, and for oscillator driven by clock driver. DS97Z8X1500 PRELIMINARY 21 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Additional Timing Table (Divide-By-One Mode) TA = -40 C to +105 C 4 MHz No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC 3 TwC Clock Input Rise & Fall Times Input Clock Width 4 TwTinL 5 TwTinH 6 TpTin 7 TrTin, TfTin Timer Input Rise & Fall Timer TwIL Int. Request Low Time TwIL Int. Request Low Time TwIH Int. Request Input High Time Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time 8A 8B 9 10 11 Timer Input Low Width Timer Input High Width Timer Input Period VCC Note [6] 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 6 MHz Min Max Min Max Units Notes 250 250 DC DC 25 25 166 166 DC DC 25 25 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,2,7,8 1,2,7,8 1,3,7,8 1,3,7,8 1,2,7,8 1,2,7,8 4,8 4,8 100 100 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 4.5V 5.5V 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC ns ns 5TpC 5TpC 4,8,9 4,8,9 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 1, POR STOP Mode Delay is on. 5. Reg. WDTMR. 6. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 = 0. 8. Maximum frequency for internal system clock is 4 MHz when using Low EMI OSC PCON Bit D7 = 0. 9. For RC and LC oscillator, and for oscillator driven by clock driver. 22 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Handshake Timing Diagrams 1 Data In Valid Data In Next Data In Valid 1 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Figure 16. Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Figure 17. Output Handshake Timing DS97Z8X1500 PRELIMINARY 23 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Additional Timing Table (Divide by Two Mode) TA = 0 C to +70 C 4 MHz 12 MHz No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC 3 TwC Clock Input Rise & Fall Times Input Clock Width 4 TwTinL 5 TwTinH 6 TpTin 7 TrTin, TfTin Timer Input Rise & Fall Timer TwIL Int. Request Low Time TwIL Int. Request Low Time TwIH Int. Request Input High Time Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time Twdt Watch-Dog Timer Delay Time Before Timeout 8A 8B 9 10 11 12 Timer Input Low Width Timer Input High Width Timer Input Period VCC Note [6] 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V Min Max Min Max 62.5 62.5 DC DC 15 15 250 250 DC DC 25 25 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 31 31 70 70 5TpC 5TpC 8TpC 8TpC 31 31 70 70 5TpC 5TpC 8TpC 8TpC 100 100 70 70 5TpC 5TpC 5TpC 5TpC 12 12 70 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 10 5 20 10 40 20 160 80 Units Conditions Notes ns ns 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,2,7,8 1,2,7,8 1,3,7,8 1,3,7,8 1,2,7,8 1,2,7,8 4,8 4,8 ms ms ms ms ms ms ms ms 4,8 4,8 5,11 5,11 5,11 5,11 5,11 5,11 5,11 5,11 5TpC 5TpC 10 5 20 10 40 20 160 80 D0 = 0 D1 = 0 D0 = 1 D1 = 0 D0 = 0 D1 = 1 D0 = 1 D1 = 1 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33) 3. Interrupt request via Port 3 (P30) 4. SMR-D5 = 1, POR STOP Mode Delay is on 5. Reg. WDTMR 6. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 = 0 8. Maximum frequency for internal system clock is 2 MHz when using Low EMI OSC PCON Bit D7 = 0. 9. For RC and LC oscillator, and for oscillator driven by clock driver. 10. Standard Mode (not Low EMI output ports) 11. Using internal RC 24 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Additional Timing Table (Divide by Two Mode) TA = -40 C to +105 C No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC 3 TwC Clock Input Rise & Fall Times Input Clock Width 4 TwTinL 5 TwTinH 6 TpTin 7 TrTin, TfTin Timer Input Rise & Fall Timer TwIL Int. Request Low Time TwIL Int. Request Low Time TwIH Int. Request Input High Time Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time Twdt Watch-Dog Timer Delay Time Before Timeout 8A 8B 9 10 11 12 Timer Input Low Width Timer Input High Width Timer Input Period VCC Note [6] 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 1 4 MHz 12 MHz Min Max Min Max 62.5 62.5 DC DC 15 15 250 250 DC DC 25 25 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 31 31 70 70 5TpC 5TpC 8TpC 8TpC 31 31 70 70 5TpC 5TpC 8TpC 8TpC 100 100 70 70 5TpC 5TpC 5TpC 5TpC 12 12 70 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 5 5 10 10 20 20 80 80 Units Conditions Notes ns ns 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,2,7,8 1,2,7,8 1,3,7,8 1,3,7,8 1,2,7,8 1,2,7,8 4,8 4,8 ms ms ms ms ms ms ms ms 4,8 4,8 5,11 5,11 5,11 5,11 5,11 5,11 5,11 5,11 5TpC 5TpC 5 5 10 10 20 20 80 80 D0 = 0 D1 = 0 D0 = 1 D1 = 0 D0 = 0 D1 = 1 D0 = 1 D1 = 1 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33) 3. Interrupt request via Port 3 (P30) 4. SMR-D5 = 1, POR STOP Mode Delay is on 5. Reg. WDTMR 6. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 = 0 8. Maximum frequency for internal system clock is 2 MHz when using Low EMI OSC PCON Bit D7 = 0. 9. For RC and LC oscillator, and for oscillator driven by clock driver. 10. Standard Mode (not Low EMI output ports) 11. Using internal RC DS97Z8X1500 PRELIMINARY 25 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PIN FUNCTIONS EPROM Programming Mode D7-D0 Data Bus. The data can be read from or written to external memory through the data bus. VCC Power Supply. This pin must supply 5V during the EPROM read mode and 6V during other modes. /CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. /OE Output Enable (active Low). This pin drives the direction of the Data Bus. When this pin is Low, the Data Bus is output, when High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the different EPROM Program Mode by applying different voltages. VPP Program Voltage. This pin supplies the program voltage. /PGM Program Mode (active Low). When this pin is Low, the data is programmed to the EPROM through the Data Bus. CLR Clear (active High). This pin resets the internal address counter at the High Level. CLK Address Clock. This pin is a clock input. The internal address counter increases by one for each clock cycle. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above VCC occur on pins P31 and /RESET. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the VPP, EPM, /OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP mode include the following: Using a clamping diode to VCC Adding a capacitor to the affected pin Enable EPROM/Test Mode Disable OTP option bit. Standard Mode XTAL Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, RC network, or external single-phase clock to the on-chip oscillator input. 26 XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network to the on-chip oscillator output. R//W Read/Write (output, write Low). The R//W signal is Low when the CCP is writing to the external program or data memory (Z86E43/743/E44 only). /RESET Reset (input, active Low). Reset will initialize the MCU. Reset is accomplished either through Power-On, Watch-Dog Timer reset, STOP-Mode Recovery, or external reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin low for the POR time. Any devices driving the reset line must be open-drain in order to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. After the POR time, /RESET is a Schmitt-triggered input. (/Reset is available on Z86E43/743/E44 only.) To avoid asynchronous and noisy reset problems, the Z86E43/743/E44 is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC/2. Program execution begins at location 000CH, 5-10 TpC cycles after /RESET is released. For Power-On Reset, the reset output time is 5 ms. The Z86E43/743/E44 does not reset WDTMR, SMR, P2M, and P3M registers on a STOP-Mode Recovery operation. /ROMless (input, active Low). This pin, when connected to GND, disables the internal ROM and forces the device to function as a Z86C90/C89 ROMless Z8. (Note that, when left unconnected or pulled High to VCC, the device functions normally as a Z8 ROM version). Note: When using in ROM Mode in High EMI (noisy) environment, the ROMless pins should be connected directly to VCC. /DS (output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid. /AS (output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle for external memory transfer. Address output is from Port 0/Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Under program control, /AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/Write. PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines can be configured under software control as a nibble I/O port, or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble programmed. Either nibble output that can be globally programmed as push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port 0 can be placed under handshake control. In Handshake Mode, Port 3 lines P32 and P35 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to Port 0's upper nibble. The lower nibble must have the same direction as the upper nibble. For external memory references, Port 0 provides address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. In ROMless mode, after a hardware reset, Port 0 is configured as address lines A15-A8, and extended timing is set to accommodate slow memory access. The initialization routine can include reconfiguration to eliminate this extended timing mode. In ROM mode, Port 0 is defined as input after reset. Port 0 can be set in the High-Impedance Mode if selected as an address output state, along with Port 1 and the control signals /AS, /DS, and R//W (Figure 18). 4 Port 0 (I/O) MCU 4 Handshake Controls /DAV0 and RDY0 (P32 and P35) Open-Drain OEN PAD Out 1.5 2.3V Hysteresis In Auto Latch R 500 k Figure 18. Port 0 Configuration DS97Z8X1500 PRELIMINARY 27 1 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PIN FUNCTIONS (Continued) Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOScompatible port with multiplexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines can be programmed as inputs or outputs or can be configured under software control as an Address/Data port for interfacing external memory. The input buffers are Schmitt-triggered and the output buffers can be globally programmed as either push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port 1 can be placed under handshake control. In this configuration, Port 3, lines P33 and P34 are used as the handshake controls RDY1 and /DAV1 (Ready and Data Available). To interface external memory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 outputs the additional lines (Figure 19). Port 1 can be placed in the high-impedance state along with Port 0, /AS, /DS, and R//W, allowing the Z86E43/743/E44 to share common resources in multiprocessor and DMA applications. In ROM mode, Port 1 is defined as input after reset. Port 2 (I/O) MCU Handshake Controls /DAV1 and RDY1 (P33 and P34) Open-Drain OEN PAD Out 1.5 2.3V Hysteresis In Auto Latch R 500 k Figure 19. Port 1 Configuration (Z86E43/743/E44 Only) 28 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines can be configured under software control as an input or output, independently. All input buffers are Schmitt-triggered. Bits programmed as outputs can be globally programmed as either push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. When used as an I/O port, Port 2 can be placed under handshake control. After reset, Port 2 is defined as an input. In Handshake Mode, Port 3 lines P31 and P36 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to bit 7 of Port 2 (Figure 20). Port 2 (I/O) MCU Handshake Controls /DAV2 and RDY2 (P31 and P36) Open-Drain OEN PAD Out 1.5 2.3V Hysteresis In Auto Latch R 500 K Figure 20. Port 2 Configuration DS97Z8X1500 PRELIMINARY 29 1 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PIN FUNCTIONS (Continued) Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible port with four fixed inputs (P33-P30) and four fixed outputs (P37-P34). These eight lines can be configured by software for interrupt and handshake control functions. Port 3, Pin 0 is Schmitt- triggered. P31, P32, and P33 are standard CMOS inputs with single trip point (no Auto Latches) and P34, P35, P36, and P37 are push-pull output lines. Low EMI output buffers can be globally programmed by the software. Two on-board comparators can process analog signals on P31 and P32 with reference to the voltage on P33. The analog function is enabled by setting the D1 of Port 3 Mode Register (P3M). The comparator output can be outputted from P34 and P37, respectively, by setting PCON register Bit D0 to 1 state. For the interrupt function, P30 and P33 are falling edge triggered interrupt inputs. P31 and P32 can be programmed as falling, rising or both edges triggered interrupt inputs (Figure 21). Access to Counter/Timer 1 is made through P31 (TIN) and P36 (TOUT). Handshake lines for Port 0, Port 1, and Port 2 are also available on Port 3 (Table 9). 30 Note: When enabling or disabling analog mode, the following is recommended: 1. Allow two NOP delays before reading this comparator output. 2. Disable global interrupts, switch to analog mode, clear interrupts, and then re-enable interrupts. 3. IRQ register bits 3 to 0 must be cleared after enabling analog mode. Note: P33-P30 differs from the Z86C33/C43/233/243 in that there is no clamping diode to VCC due to the EPROM high-voltage circuits. Exceeding the VIH maximum specification during standard operating mode may cause the device to enter EPROM mode. PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog 1 MCU Port 3 (I/O or Control) Auto Latch R 500 K P30 P30 Data Latch IRQ3 R247 = P3M D1 1 = Analog 0 = Digital DIG. P31 (AN1) IRQ2, Tin, P31 Data Latch + AN. - P32 (AN2) IRQ0, P32 Data Latch + P33 (REF) - IRQ1, P33 Data Latch From Stop Mode Recovery Source Figure 21. Port 3 Configuration DS97Z8X1500 PRELIMINARY 31 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PIN FUNCTIONS (Continued) Table 9. Port 3 Pin Assignments Pin I/O P30 P31 IN IN P32 P33 P34 P35 P36 IN IN OUT OUT OUT P37 OUT CTC1 TIN Analog Interrupt AN1 IRQ3 IRQ2 AN2 REF AN1-Out IRQ0 IRQ1 P1 HS P2 HS Ext D/R D/R D/R R/D /DM R/D TOUT R/D An2-Out Comparator Inputs. Port 3, P31, and P32, each have a comparator front end. The comparator reference voltage P33 is common to both comparators. In analog mode, P31 and P32 are the positive input of the comparators and P33 is the reference voltage of the comparators. Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33-P31) that are not externally driven. Whether this level is 0 or 1, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Auto Latches are available on Port 0, Port 1, Port 2, and P30. There are no Auto Latches on P31, P32, and P33. Low EMI Emission. The Z86E43/743/E44 can be programmed to operate in a low EMI Emission Mode in the PCON register. The oscillator and all I/O ports can be programmed as low EMI emission mode independently. Use of this feature results in: 32 P0 HS The pre-drivers slew rate reduced to 10 ns typical. Low EMI output drivers have resistance of 200 Ohms (typical). Low EMI Oscillator. Internal SCLK/TCLK= XTAL operation limited to a maximum of 4 MHz - 250 ns cycle time, when Low EMI Oscillator is selected. Note for emulation only: Do not set the emulator to emulate Port 1 in low EMI mode. Port 1 must always be configured in Standard Mode. PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION The MCU incorporates the following special functions to enhance the standard Z8 architecture to provide the user with increased design flexibility. RESET. The device is reset in one of three ways: 1. Power-On Reset 2. Watch-Dog Timer 3. Stop-Mode Recovery Source Note: Having the Auto Power-on Reset circuitry built-in, the MCU does not need to be connected to an external power-on reset circuit. The reset time is Tpor. The MCU does not re-initialize WDTMR, SMR, P2M, and P3M registers to their reset values on a Stop-Mode Recovery operation. 65535 4096/8192/16384 Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) Program Memory. The MCU can address up to 4/8/16 KB of Internal Program Memory (Figure 22). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. For EPROM mode, byte 12 (000CH) to address 4095 (0FFFH)/8191 (1FFFH)/16384 (3FFFH), consists of programmable EPROM. After reset, the program counter points at the address 000CH, which is the starting address of the user program. In ROMless mode, the Z86E43/743/E44 can address up to 64 KB of External Program Memory. The ROM/ROMless option is only available on the 44-pin devices. ROM Mode ROMless Mode External ROM and RAM On-Chip EPROM External ROM and RAM 11 IRQ5 IRQ5 10 IRQ5 IRQ5 9 IRQ4 IRQ4 8 IRQ4 IRQ4 7 IRQ3 IRQ3 6 IRQ3 IRQ3 5 IRQ2 IRQ2 4 IRQ2 IRQ2 3 IRQ1 IRQ1 2 IRQ1 IRQ1 1 IRQ0 IRQ0 0 IRQ0 IRQ0 4095/8191/16383 Location of First Byte of Instruction Executed After RESET Note: The device V CC must rise up to the operating VCC specification before the TPOR expires. 12 (Z86E43/743/E44 Only) Figure 22. Program Memory Map DS97Z8X1500 PRELIMINARY 33 1 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) EPROM Protect. When in ROM Protect Mode, and executing out of External Program Memory, instructions LDC, LDCI, LDE, and LDEI cannot read Internal Program Memory. When in EPROM Protect Mode and executing out of Internal Program Memory, instructions LDC, LDCI, LDE, and LDEI can read Internal Program Memory. Data Memory (/DM). In ROM Mode, the Z86E43/743/E44 can address up to 60/56/48 KB of external data memory beginning at location 4096/8192/16384. In ROMless mode, the Z86E43/743/E44 can address up to 64 KB of data memory. External data memory may be included with, or separated from, the external program memory space. /DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space (Figure 23). The state of the /DM signal is controlled by the type of instruction being executed. An LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references data (/DM active Low) memory. EPROM ROMless Mode External Data Memory External Data Memory 65535 4096/8192/16384 4095/8191/16383 Not Addressable 0 (Z86E43/743/E44 Only) Figure 23. Data Memory Map 34 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Register File. The register file consists of three I/O port registers, 236/125 general-purpose registers, 15 control and status registers, and three system configuration registers in the expanded register group. The instructions can access registers directly or indirectly through an 8-bit address field. This allows a short 4-bit register address using the Register Pointer (Figure 24). In the 4-bit mode, the reg- ister file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group. Note: Register Group E0-EF can only be accessed through working register and indirect addressing modes. R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Bank Working Register Pointer Default After Reset = 00H Figure 24. Register Pointer Register Expanded Register File (ERF). The register file has been expanded to allow for additional system control registers, mapping of additional peripheral devices and input/output ports into the register address area. The Z8 register address space R0 through R15 is implemented as 16 groups of 16 registers per group (Figure 26). These register banks are known as the Expanded Register File (ERF). DS97Z8X1500 The low nibble (D3-D0) of the Register Pointer (RP) select the active ERF Bank, and the high nibble (D7-D4) of register RP select the working register group. Three system configuration registers reside in the Expanded Register File at bank FH: PCON, SMR, and WDTMR. The rest of the Expanded Register is not physically implemented and is reserved for future expansion. PRELIMINARY 35 1 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) r7 r6 r5 r4 r3 r2 r1 r0 R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF Register Group F F0 EF 80 7F 70 6F 60 5F 50 4F 40 3F 30 2F Specified Working Register Group The lower nibble of the register file address provided by the instruction points to the specified register. 20 1F 10 0F 00 Register Group 1 R15 to R0 Register Group 0 R15 to R4* I/O Ports R3 to R0* * Expanded Register Bank (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253 (RP). Figure 25. Register Pointer 36 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Z8(R) STANDARD CONTROL REGISTERS 1 RESET CONDITION D7 D6 D5 D4 D3 D2 D1 D0 REGISTER REGISTER POINTER 7 6 5 4 3 2 Working Register Group Pointer 1 % FF SPL 0 0 0 0 0 0 0 0 % FE SPH 0 0 0 0 0 0 0 0 % FD RP 0 0 0 0 0 0 0 0 % FC FLAGS U U U U U U U U % FB IMR 0 U U U U U U U % FA IRQ 0 0 0 0 0 0 0 0 % F9 IPR U U U U U U U U % F8 P01M 0 1 0 0 1 1 0 1 * % F7 P3M 0 0 0 0 0 0 0 0 * % F6 P2M 1 1 1 1 1 1 1 1 % F5 PRE0 U U U U U U U 0 % F4 T0 U U U U U U U U % F3 PRE1 U U U U U U 0 0 % F2 T1 U U U U U U U U % F1 TMR 0 0 0 0 0 0 0 0 % F0 Reserved 0 Expanded Register Group Pointer Z8 Reg. File %FF %FO EXPANDED REG. BANK (F) REGISTER * %7F * ** Reserved %0F %00 % (F) 0F WDTMR % (F) 0E Reserved % (F) 0D SMR2 % (F) 0C Reserved % (F) 0B SMR % (F) 0A Reserved % (F) 09 Reserved % (F) 08 Reserved % (F) 07 Reserved % (F) 06 Reserved % (F) 05 Reserved % (F) 04 Reserved % (F) 03 Reserved % (F) 02 Reserved % (F) 01 Reserved % (F) 00 PCON EXPANDED REG. BANK (0) REGISTER Notes: U = Unknown For ROMless reset condition: "10110110" * * * Will not be reset with a STOP Mode Recovery ** Will not be reset with a STOP Mode Recovery, except Bit D0. RESET CONDITION U U U 0 1 1 0 1 U U U U U U 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 0 RESET CONDITION % (0) 03 P3 1 1 1 1 U U U U % (0) 02 P2 U U U U U U U U % (0) 01 P1 U U U U U U U U % (0) 00 P0 U U U U U U U U Figure 26. Expanded Register File Architecture DS97Z8X1500 PRELIMINARY 37 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. The register R254 is general-purpose on Z86E33/733/E34. R254 and R255 are set to 00H after any reset or STOPMode Recovery. RAM Protect. The upper portion of the RAM's address spaces 80H to EFH (excluding the control registers) can be protected from reading and writing. This option can be selected during the EPROM Programming Mode. After this option is selected, the user can activate this feature from the internal EPROM. D6 of the IMR control register (R251) is used to turn off/on the RAM protect by loading a 0 or 1, respectively. A "1" in D6 indicates RAM Protect enabled. Stack. The Z86E43/743/E44 external data memory or the internal register file can be used for the stack. The 16-bit Stack Pointer (R254-R255) is used for the external stack, which can reside anywhere in the data memory for ROMless mode, but only from 4096/8192/16384 to 65535 in ROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack on the Z8 that resides within the 236 general-purpose registers (R4-R239). SPH (R254) can be used as a general-purpose register when using internal stack only. R254 and R255 are set to 00H after any reset or Stop- Mode Recovery. 38 Counter/Timers. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 27). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256), that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counters can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching one (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and can be either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. Port 3 line P36 serves as a timer output (TOUT) through which T0, T1, or the internal clock can be output. The counter/timers can be cascaded by connecting the T0 output to the input of T1. PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog OSC 1 Internal Data Bus D1 (SMR) Write Write Read /2 PRE0 Initial Value Register T0 Initial Value Register 6-Bit Down Counter 8-bit Down Counter T0 Current Value Register D0 (SMR) / 16 /4 IRQ4 Internal Clock TOUT /2 External Clock P36 Clock Logic /4 Internal Clock Gated Clock Triggered Clock TIN P31 Write 6-Bit Down Counter 8-Bit Down Counter PRE1 Initial Value Register T1 Initial Value Register Write IRQ5 T1 Current Value Register Read Internal Data Bus Figure 27. Counter/Timer Block Diagram DS97Z8X1500 PRELIMINARY 39 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Interrupts. The MCU has six different interrupts from six different sources. The interrupts are maskable and prioritized (Figure 28). The six sources are divided as follows: four sources are claimed by Port 3 lines P33-P30) and two in counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table 10). IRQ0 IRQ2 IRQ1, 3, 4, 5 Interrupt Edge Select IRQ (D6, D7) IRQ IMR 6 IPR Global Interrupt Enable Interrupt Request Priority Logic Vector Select Figure 28. Interrupt Block Diagram Table 10. Interrupt Types, Sources, and Vectors 40 Name Source Vector Location IRQ0 IRQ1 IRQ2 /DAV0, IRQ0 IRQ1 /DAV2, IRQ2, TIN 0, 1 2, 3 4, 5 IRQ3 IRQ4 IRQ5 IRQ3 T0 TI 6, 7 8, 9 10, 11 Comments External (P32), Rising/Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising/Falling Edge Triggered External (P30), Falling Edge Triggered Internal Internal PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority Register (IPR). An interrupt machine cycle is activated when an interrupt request is granted. Thus, disabling all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. All interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling or both edge triggered, and are programmable by the user. The software may poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in bits D7 and D6 of the IRQ Register (R250). The configuration is shown in Table 11. IRQ C1 D6 P31 P32 0 0 1 1 0 1 0 1 F F R R/F F R F R/F Clock. The on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, RC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 10 KHz to 16 MHz max, with a series resistance (RS) less than or equal to 100 Ohms. The crystal should be connected across XTAL1 and XTAL2 using the vendor's recommended capacitor values from each pin directly to device pin Ground. The RC oscillator option can be selected in the programming mode. The RC oscillator configuration must be an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to Ground (Figure 29). XTAL1 XTAL1 XTAL2 XTAL2 C1 R XTAL2 XTAL2 Ceramic Resonator or Crystal C1, C2 = 33 pF TYP * F = 8 MHz 1 Notes: F = Falling Edge R = Rising Edge L C2 Interrupt Edge D7 XTAL1 XTAL1 C1 Table 11. IRQ Register Configuration C2 LC C1, C2 = 22 pF RC @ 5V Vcc (TYP) L = 130 H * F = 3 MHz * C1 = 100 pF R = 2K F = 6 MHz External Clock * Typical value including pin parasitics Figure 29. Oscillator Configuration DS97Z8X1500 PRELIMINARY 41 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR timer allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (Opcode=FFH) immediately before the appropriate sleep instruction, that is: FF 6F 1. Power fail to Power OK status FF 7F 2. Stop-Mode Recovery (if D5 of SMR=0) 3. WDT time-out The POR time is a nominal 5 ms. Bit 5 of the STOP mode Register (SMR) determines whether the POR timer is bypassed after STOP-Mode Recovery (typical for an external clock and RC/LC oscillators with fast start up times). HALT. Turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupt IRQ0, IRQ1, and IRQ2 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. NOP STOP or NOP HALT ; clear the pipeline ; enter STOP Mode ; clear the pipeline ; enter HALT Mode STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 microamperes or less. STOP Mode is terminated by one of the following resets: either by WDT time-out, POR, a Stop-Mode Recovery Source, which is defined by the SMR register or external reset. This causes the processor to restart the application program at address 000CH. Port Configuration Register (PCON). The PCON register configures the ports individually; comparator output on Port 3, open-drain on Port 0 and Port 1, low EMI on Ports 0, 1, 2 and 3, and low EMI oscillator. The PCON register is located in the expanded register file at Bank F, location 00 (Figure 30). PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output 0 Port 1 Open Drain 1 Port 1 Push-pull Active* 0 Port 0 Open Drain 1 Port 0 Push-pull Active* 0 Port 0 Low EMI 1 Port 0 Standard* 0 Port 1 Low EMI 1 Port 1 Standard* 0 Port 2 Low EMI 1 Port 2 Standard* 0 Port 3 Low EMI 1 Port 3 Standard* * Default Setting After Reset Low EMI Oscillator 0 Low EMI 1 Standard* Figure 30. Port Configuration Register (PCON) (Write Only) 42 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Comparator Output Port 3 (D0). Bit 0 controls the comparator output in Port 3. A "1" in this location brings the comparator outputs to P34 and P37, and a "0" releases the Port to its standard I/O configuration. The default value is 0. Port 1 Open-Drain (D1). Port 1 can be configured as an open-drain by resetting this bit (D1=0) or configured as push-pull active by setting this bit (D1=1). The default value is 1. Port 0 Open-Drain (D2). Port 0 can be configured as an open-drain by resetting this bit (D2=0) or configured as push-pull active by setting this bit (D2=1). The default value is 1. Low EMI Port 0 (D3). Port 0 can be configured as a Low EMI Port by resetting this bit (D3=0) or configured as a Standard Port by setting this bit (D3=1). The default value is 1. Low EMI Port 1 (D4). Port 1 can be configured as a Low EMI Port by resetting this bit (D4=0) or configured as a Standard Port by setting this bit (D4=1). The default value is 1. Note: The emulator does not support Port 1 low EMI mode and must be set D4 = 1. Low EMI Port 3 (D6). Port 3 can be configured as a Low EMI Port by resetting this bit (D6=0) or configured as a Standard Port by setting this bit (D6=1). The default value is 1. Low EMI OSC (D7). This bit of the PCON Register controls the low EMI noise oscillator. A "1" in this location configures the oscillator with standard drive. While a "0" configures the oscillator with low noise drive, however, it does not affect the relationship of SCLK and XTAL. The low EMI mode will reduce the drive of the oscillator (OSC). The default value is 1. Note: 4 MHz is the maximum external clock frequency when running in the low EMI oscillator mode. Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of Stop-Mode Recovery (Figure 31). All bits are Write Only except bit 7 which is a Read Only. Bit 7 is a flag bit that is hardware set on the condition of STOP Recovery and reset by a power-on cycle. Bit 6 controls whether a low or high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4 of the SMR register specify the Stop-Mode Recovery Source. The SMR is located in Bank F of the Expanded Register File at address 0BH. Low EMI Port 2 (D5). Port 2 can be configured as a Low EMI Port by resetting this bit (D5=0) or configured as a Standard Port by setting this bit (D5=1). The default value is 1. DS97Z8X1500 PRELIMINARY 43 1 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) SMR (F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide by 16 0 OFF ** 1 ON External Clock Divide by 2 0 SCLK/TCLK =XTAL/2* 1 SCLK/TCLK =XTAL Stop Mode Recovery Source 000 POR and/or External Reset * 001 P30 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0:3 111 P2 NOR 0:7 Stop Delay 0 OFF 1 ON * Stop Recovery Level 0 Low * 1 High Stop Flag 0 POR* 1 Stop Recovery * Default setting after RESET. ** Default setting after RESET and STOP-Mode Recovery. Figure 31. STOP-Mode Recovery Register (Write-Only Except Bit D7, Which is Read-Only) 44 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog SCLK/TCLK Divide-by-16 Select (D0). This bit of the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-two circuitry. When this bit is 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided by two. The SCLK/TCLK is equal to the external clock frequency when this bit is set (D1=1). Using this bit together with D7 of PCON further helps lower EMI (i.e., D7 (PCON) = 0, D1 (SMR) = 1). The default setting is zero. STOP-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR register specify the wake up source of the STOP-Mode Recovery (Figure 32). Table 12 shows the SMR source selected with the setting of D2 to D4. P33P31 cannot be used to wake up from STOP mode when programmed as analog inputs. When the STOP-Mode Recovery sources are selected in this register then SMR2 register bits D0, D1 must be set to zero. Note: If the Port2 pin is configured as an output, this output level will be read by the SMR circuitry.. SMR2 D1 D0 0 0 SMR2 D1 D0 0 1 VDD P20 P20 P23 P27 SMR2 D1 D0 1 0 SMR D4 D3 D2 0 0 0 VDD P30 P31 P32 SMR D4 0 0 0 D3 0 1 1 D2 SMR D4 D3 D2 1 0 0 1 0 1 P33 SMR D4 D3 D2 1 0 1 SMR D4 D3 D2 1 1 0 P20 P20 P23 P27 SMR D4 D3 D2 1 1 1 P27 To POR RESET Stop-Mode Recovery Edge Select (SMR) To P33 Data Latch and IRQ1 MUX P33 From Pads Digital/Analog Mode Select (P3M) Figure 32. Stop-Mode Recovery Source DS97Z8X1500 PRELIMINARY 45 1 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Table 12. Stop-Mode Recovery Source D4 D3 D2 SMR Source selection 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 0 1 POR recovery only P30 transition P31 transition (Not in analog mode) P32 transition (Not in analog mode) P33 transition (Not in analog mode) P27 transition Logical NOR of Port 2 bits 0-3 Logical NOR of Port 2 bits 0-7 Stop-Mode Recovery Delay Select (D5). The 5 ms RESET delay after Stop-Mode Recovery is disabled by programming this bit to a zero. A "1" in this bit will cause a 5 ms RESET delay after Stop-Mode Recovery. The default condition of this bit is 1. If the fast wake up mode is selected, the Stop-Mode Recovery source needs to be kept active for at least 5TpC. Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is disabled after Power-On Reset and initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT is driven either by an on-board RC oscillator or an external oscillator from XTAL1 pin. The POR clock source is selected with bit 4 of the WDT register. Note: Execution of the WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. WDT Time-Out Period (D0 and D1). Bits 0 and 1 control a tap circuit that determines the time-out periods that can be obtained (Table 13). The default value of D0 and D1 are 1 and 0, respectively. Table 13. Time-out Period of WDT D1 D0 0 0 1 1 0 1 0 1 Time-out of Time-out of the Internal the System RC OSC Clock 5 ms 10 ms* 20 ms 80 ms 128 SCLK 256 SCLK* 512 SCLK 2048 SCLK Stop-Mode Recovery Level Select (D6). A "1" in this bit defines that a high level on any one of the recovery sources wakes the MCU from STOP Mode. A 0 defines low level recovery. The default value is 0. Notes: *The default setting is 10 ms. Cold or Warm Start (D7). This bit is set by the device upon entering STOP Mode. A "0" in this bit indicates that the device has been reset by POR (cold). A "1" in this bit indicates the device was awakened by a SMR source (warm). WDT During HALT Mode (D2). This bit determines whether or not the WDT is active during HALT Mode. A "1" indicates that the WDT is active during HALT. A "0" disables the WDT in HALT Mode. The default value is "1". Stop-Mode Recovery Register 2 (SMR2). This register contains additional Stop-Mode Recovery sources. When the Stop-Mode Recovery sources are selected in this register then SMR Register Bits D2, D3, and D4 must be 0. WDT During STOP Mode (D3). This bit determines whether or not the WDT is active during STOP mode. A "1" indicates active during STOP. A "0" disables the WDT during STOP Mode. This is applicable only when the WDT clock source is the internal RC oscillator. SMR:10 D1 D0 0 0 1 46 0 1 0 Operation Description of Action POR and/or external reset recovery Logical AND of P20 through P23 Logical AND of P20 through P27 Clock Source For WDT (D4). This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XTAL1, and the WDT is stopped in STOP Mode. The default configuration of this bit is 0, which selects the RC oscillator. PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Permanent WDT. When this feature is enabled, the WDT is enabled after reset and will operate in Run and Halt Mode. The control bits in the WDTMR do not affect the WDT operation. If the clock source of the WDT is the internal RC oscillator, then the WDT will run in STOP mode. If the clock source of the WDT is the XTAL1 pin, then the WDT will not run in STOP mode. Note: WDT time-out in STOP Mode will not reset SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers, but will activate the Tpor delay. WDTMR Register Accessibility. The WDTMR register is accessible only during the first 60 internal system clock cycles from the execution of the first instruction after Power-On Reset, Watch-Dog reset or a STOP-Mode Recovery (Figures 33 and 34). After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in Bank F of the Expanded Register File at address location 0FH. Clock Free WDT Reset. The WDT will enable the Z8 to reset the I/O pins whenever the WDT times out, even without a clock source running on the XTAL1 and XTAL2 pins. WDTMR Bit D4 must be 0 for the clock Free WDT to work. The I/O pins will default to their default settings WDTMR (F) 0F D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP 00 01 * 10 11 INT RC OSC System Clock 5 ms 128 SCLK 10 ms 256 SCLK 20 ms 512 SCLK 80 ms 2048 SCLK WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL Reserved (Must be 0) * Default setting after RESET Figure 33. Watch-Dog Timer Mode Register Write Only DS97Z8X1500 PRELIMINARY 47 1 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers /Reset Zilog 4 Clock Filter /Clear CLK 18 Clock RESET Generator RESET Internal /RESET WDT Select (WDTMR) WDT TAP SELECT CLK Source Select (WDTMR) XTAL M U X Internal RC OSC. VDD VLV + 5ms POR 5ms 15ms 25ms 100ms CK WDT/POR Counter Chain /CLR 2V Operating Voltage Det. - /WDT From Stop Mode Recovery Source Stop Delay Select (SMR) Figure 34. Resets and WDT 48 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Auto Reset Voltage. An on-board Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. Reset is globally driven if VCC is below VLV (Figure 35). 1 VCC (Volts) 3.7 3.5 3.3 3.1 2.9 2.7 2.5 2.3 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) Figure 35. Typical VLV Voltage vs Temperature DS97Z8X1500 PRELIMINARY 49 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Z8 CONTROL REGISTER DIAGRAMS PCON (FH) 00H D7 D6 D5 D4 WDTMR (F) 0F D3 D2 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 WDT TAP 00 01 * 10 11 Comparator Output Port 3 0 P34, P37 Standard* 1 P34, P37 Comparator Output 0 Port 1 Open-Drain 1 Port 1 Push-Pull Active* WDT During HALT 0 OFF 1 ON * 0 Port 0 Open-Drain 1 Port 0 Push-pull Active* 0 Port 0 Low EMI 1 Port 0 Standard* WDT During STOP 0 OFF 1 ON * 0 Port 1 Low EMI 1 Port 1 Standard* XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL 0 Port 2 Low EMI 1 Port 2 Standard* Reserved (Must be 0) 0 Port 3 Low EMI 1 Port 3 Standard* * Default Setting After Reset Must Be 1 for Z86E33/733/E34 INT RC OSC System Clock 5 ms 128 SCLK 10 ms 256 SCLK 20 ms 512 SCLK 80 ms 2048 SCLK * Default setting after RESET Low EMI Oscillator 0 Low EMI 1 Standard* Figure 38. Watch-Dog Timer Mode Register Write Only Figure 36. Port Configuration Register Write Only SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 SMR (FH) 0B D7 D6 D5 D4 D3 D2 Stop-Mode Recovery Source 2 00 POR only* 01 AND P20,P21,P22,P23 10 AND P20,P21,P22,P23,P24, P25,P26,P27 D1 D0 SCLK/TCLK Divide-by-16 0 OFF ** 1 ON Reserved (Must be 0) Note: Not used in conjunction with SMR Source External Clock Divide by 2 0 SCLK/TCLK =XTAL/2* 1 SCLK/TCLK =XTAL Stop Mode Recovery Source 000 POR Only and/or External Reset* 001 P30 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON* Stop Recovery Level 0 Low* 1 High Figure 39. STOP-Mode Recovery Register 2 Write Only R240 D7 D6 D5 D4 D3 D2 D1 Stop Flag 0 POR* 1 Stop Recovery D0 Reserved (Must be 0) Figure 40. Reserved * Default setting after RESET. ** Default setting after RESET and STOP-Mode Recovery. Not used in conjunction with SMR2 Source Figure 37. STOP-Mode Recovery Register Write Only Except Bit D7, Which is Read Only 50 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog R241 TMR R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Count Mode 0 T1 Single Pass* 1 T1 Modulo N 0 No Function* 1 Load T0 0 Disable T0 Count* 1 Enable T0 Count Clock Source 1 T1 Internal 0 T1 External Timing Input (TIN Mode) 0 No Function* 1 Load T1 0 Disable T1 Count* 1 Enable T1 Count Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) *Default After Reset TIN 00 01 10 Modes External Clock Input* Gate Input Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) TOUT Modes 00 Not Used* 01 T0 Out 10 T1 Out 11 Internal Clock Out 1 D5 D4 D3 D2 D1 D0 Figure 43. Prescaler 1 Register F3H: Write Only R244 T0 D7 D6 D5 D4 D3 D2 D1 D0 Default After Reset = 00H T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When Read) Figure 41. Timer Mode Register F1H: Read/Write Figure 44. Counter/Timer 0 Register F4H; Read/Write R242 T1 D7 D6 D5 D4 D3 D2 D1 D0 T1 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T1 Current Value (When Read) R245 PRE0 D7 D6 D5 D4 D3 D2 D1 D0 Count Mode 0 T1 Single Pass 1 T1 Modulo N Figure 42. Counter/Timer 1 Register F2H: Read/Write Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Figure 45. Prescaler 0 Register F5H: Write Only DS97Z8X1500 PRELIMINARY 51 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog Z8 CONTROL REGISTER DIAGRAMS (Continued) R246 P2M R248 P01M D7 D6 D7 D6 D5 D4 D3 D2 D1 D0 * Default After Reset D5 D4 D3 D2 D1 D0 P03 - P00 Mode 00 Output 01 Input* 1X A11 - A8 P20 - P27 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input* Stack Selection 0 External 1 Internal* P17 - P10 Mode 00 Byte Output 01 Byte Input* 10 AD7 - AD0 11 High-Impedance AD7 - AD0, /AS, /DS, /R//W, A11 - A8, A15 - A12, If Selected Figure 46. Port 2 Mode Register F6H: Write Only R247 P3M D7 D6 External Memory Timing 0 Normal* 1 Extended D5 D4 D3 D2 D1 D0 P07 - P04 Mode 00 Output 01 Input* 1X A15 - A12 0 Port 2 Open-Drain 1 Port 2 Push-pull Active 0 P31, P32 Digital Mode 1 P31, P32 Analog Mode Reset Condition = 0100 1101B For ROMless Condition = 1011 0110B Z86E33/733/E34 Must be 00 * Default After Reset 0 P32 = Input P35 = Output 1 P32 = /DAV0/RDY0 P35 = RDY0//DAV0 00 01 10 11 P33 = Input P34 = Output P33 = Input P34 = /DM P33 = /DAV1/RDY1 P34 = RDY1//DAV1 0 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = /DAV2/RDY2 P36 = RDY2//DAV2 Figure 48. Port 0 and 1 Mode Register F8H: Write Only R249 IPR D7 D6 D5 D4 0 P30 = Input P37 = Output Reserved (Must be 0) Default After Reset = 00H Z86E33/733/E34 Must Be 00 Figure 47. Port 3 Mode Register F7H: Write Only D3 D2 D1 D0 Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0) Figure 49. Interrupt Priority Register F9H: Write Only 52 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog R253 RP R250 IRQ D7 D6 D5 D4 D3 D2 IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P30 Input IRQ4 = T0 IRQ5 = T1 Default After Reset = 00H 1 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 Inter Edge P31 P32 P31 P32 P31 P32 P31 P32 Expanded Register Bank Working Register Pointer Default After Reset = 00H = 00 = 01 = 10 = 11 Figure 53. Register Pointer FDH: Read/Write R254 SPH Figure 50. Interrupt Request Register FAH: Read/Write D7 D6 D5 D4 D3 D2 D1 D0 (Z86E43/743/E44) Stack Pointer Upper Byte (SP8 - SP15) R251 IMR (Z86E33/733/E34) 0 = 0 State 1 = 1 State D7 D6 D5 D4 D3 D2 D1 D0 Default after Reset = 00H 1 Enables IRQ5-IRQ0 (D0 = IRQ0) Figure 54. Stack Pointer High FEH: Read/Write 1 Enables RAM Protect 1 Enables Interrupts This option must be selected when ROM code is submitted for ROM Masking, otherwise this control bit is disabled permanently. R255 SPL D7 D6 D5 D4 D3 Figure 51. Interrupt Mask Register FBH: Read/Write D2 D1 D0 Stack Pointer Lower Byte (SP0 - SP7) Default after Reset = 00H R252 FLAGS D7 D6 D5 D4 D3 D2 D1 D0 Figure 55. Stack Pointer Low FFH: Read/Write User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 52. Flag Register FCH: Read/Write DS97Z8X1500 PRELIMINARY 53 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PACKAGE INFORMATION Figure 56. 40-Pin DIP Package Diagram Figure 57. 44-Pin PLCC Package Diagram 54 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog 1 Figure 58. 44-Pin QFP Package Diagram Figure 59. 28-Pin DIP Package Diagram DS97Z8X1500 PRELIMINARY 55 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog PACKAGE INFORMATION (Continued) Figure 60. 28-Pin SOIC Package Diagram Figure 61. 28-Pin PLCC Package Diagram 56 PRELIMINARY DS97Z8X1500 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog ORDERING INFORMATION Z86E43/743/E44 (12 MHz) 1 40-Pin DIP 44-Pin PLCC 44-Pin QFP Z86E4312PSC Z86E4312PEC Z8674312PSC Z8674312PEC Z86E4412PSC Z86E4412PEC Z86E4312VSC Z86E4312VEC Z8674312VSC Z8674312VEC Z86E4412VSC Z86E4412VEC Z86E4312FSC Z86E4312FEC Z8674312FSC Z8674312FEC Z86E4412FSC Z86E4412FEC Z86E33/733/E34 (12 MHz) 28-Pin DIP 28-Pin SOIC 28-Pin PLCC Z86E3312PSC Z86E3312PEC Z8673312PSC Z8673312PEC Z86E3412PSC Z86E3412PEC Z86E3312SSC Z86E3312SEC Z8673312SSC Z8673312SEC Z86E3412SSC Z86E3412SEC Z86E3312VSC Z86E3312VEC Z8673312VSC Z8673312VEC Z86E3412VSC Z86E3412VEC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package Speed P = Plastic DIP V = Plastic Chip Carrier F = Plastic Quad Flat Pack S = SOIC (Small Outline Integrated Circuit) 12 = 12 MHz Environmental C = Plastic Standard Temperature S = 0 C to +70 C E = -40 C to +105 C Example: Z 86E43 12 P S C is a Z8E43, 12 MHz, DIP, 0 to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix DS97Z8X1500 PRELIMINARY 57 Z86E33/733/E34/E43/743/E44 CMOS Z8 OTP Microcontrollers Zilog (c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com 58 PRELIMINARY DS97Z8X1500