PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843011-01 is a Fibre Channel Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS843011-01 uses a 26.5625MHz crystal to synthesize 106.25MHz or a 25MHz crystal to synthesize 100MHz. The ICS843011-01 has excellent <1ps phase jitter performance, over the 637kHz - 10MHz integration range. The ICS843011-01 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * 1 differential 3.3V LVPECL output ICS * Crystal oscillator interface designed for 26.5625MHz, 18pF parallel resonant crystal * Output frequency: 106.25MHz or 100MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.56ps (typical) * RMS phase noise at 106.25MHz Phase noise: Offset Noise Power 100Hz .................. -98 dBc/Hz 1KHz .............. -122.3 dBc/Hz 10KHz .............. -135.4 dBc/Hz 100KHz .............. -135.2 dBc/Hz * 3.3V operating supply * 0C to 70C ambient operating temperature FREQUENCY TABLE Crystal (MHz) Output Frequency (MHz) 26.5625 106.25 25 100 BLOCK DIAGRAM XTAL_IN OSC XTAL_OUT PIN ASSIGNMENT Phase Detector VCO 637.5MHz w/ 26.5625MHz Ref. /6 nQ0 Q0 VCCA XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 Q0 nQ0 VCC nc ICS843011-01 M = /24 (fixed) 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843011AG-01 www.icst.com/products/hiperclocks.html REV. A APRIL 7, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 2, 3 4 VCCA XTAL_OUT, XTAL_IN VEE Power 5 nc Unused Input Power Description Analog supply pin. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. No connect. 6 VCC Power Core supply pin. 7, 8 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 843011AG-01 Test Conditions Minimum Typical 4 www.icst.com/products/hiperclocks.html 2 Maximum Units pF REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 IEE Power Supply Current 55 V mA TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units 28.33 MHz NOTE 1: Outputs terminated with 50 to VCC - 2V. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 23.33 Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW TABLE 5. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter FOUT tjit(O) Test Conditions Output Frequency RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Minimum Typical 93.33 106.25MHz; Integration Range: 637kHz - 10MHz 100MHz; Integration Range: 637kHz - 10MHz 20% to 80% Maximum Units 113.33 MHz 0.56 ps 0.54 ps 350 ps 50 % NOTE 1: Please refer to the Phase Noise Plot. 843011AG-01 www.icst.com/products/hiperclocks.html 3 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 100MHZ 0 -10 -20 Fibre Channel Filter 100MHz RMS Phase Noise Jitter 637kHz to 10MHz = 0.54ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 -120 NOISE POWER dBc Hz -30 -40 -50 -130 -140 -150 -190 100 -160 -170 -180 Phase Noise Result by adding a Fibre Channel Filter to raw data 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 106.25MHZ 0 -10 -20 Fibre Channel Filter 106.25MHz -50 -60 -70 -80 RMS Phase Noise Jitter 637kHz to 10MHz = 0.56ps (typical) -90 Raw Phase Noise Data -100 -110 -120 -130 NOISE POWER dBc Hz -30 -40 -140 -190 100 -150 -160 -170 -180 Phase Noise Result by adding Fibre Channel Filter to raw data 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843011AG-01 www.icst.com/products/hiperclocks.html 4 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot Qx SCOPE Noise Power VCC, VCCA LVPECL Phase Noise Mask nQx VEE f1 -1.3V 0.165V Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQ0 80% Q0 80% VSW I N G Pulse Width t odc = Clock Outputs PERIOD 20% 20% t PW tR tF t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843011AG-01 OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 5 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843011-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01F 10 V CCA .01F 10F FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS843011-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 843011AG-01 www.icst.com/products/hiperclocks.html 6 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. TERMINATION FOR ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50 125 FOUT FIN Zo = 50 Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 Zo = 50 VCC - 2V RTT 84 FIGURE 3A. LVPECL OUTPUT TERMINATION 843011AG-01 125 84 FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843011-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843011-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 55mA = 190.57mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 190.6mW + 30mW = 220.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.221W * 90.5C/W = 90C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 8-PIN TSSOP, FORCED CONVECTION JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 843011AG-01 0 1 2.5 101.7C/W 90.5C/W 89.8C/W www.icst.com/products/hiperclocks.html 8 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = V OH_MAX (V CCO_MAX * -V OH_MAX OL_MAX CCO_MAX -V CC_MAX - 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX - 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX - (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V OL_MAX - (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843011AG-01 www.icst.com/products/hiperclocks.html 9 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7C/W 90.5C/W 89.8C/W TRANSISTOR COUNT The transistor count for ICS843011-01 is: 1662 843011AG-01 www.icst.com/products/hiperclocks.html 10 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR FOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843011AG-01 www.icst.com/products/hiperclocks.html 11 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011-01 FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843011AM-01 11A01 8 Lead TSSOP tube 0C to 70C ICS843011AM-01T 11A01 8 Lead TSSOP 2500 tape & reel 0C to 70C The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843011AG-01 www.icst.com/products/hiperclocks.html 12 REV. A APRIL 7, 2005