6 GHz to 18 GHz, Front-End IC
Data Sheet ADTR1107
Rev. A Document Feedback
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FEATURES
Operates from 6 GHz to 18 GHz
25 dBm typical transmit state PSAT
22 dB typical transmit state small signal gain
18 dB typical receive state small signal gain
2.5 dB typical receive state noise figure
Coupled power amplifier output for power detection
APPLICATIONS
Phased array antenna
Military radar
Weather radar
Communication links
Electronic warfare
FUNCTIONAL BLOCK DIAGRAM
VGG_PA VDD_PA
V
DD_LN
A
V
GG_LN
A
V
SS_SW CTRL_SW
V
DD_SW
CPLR_OUT
ANT
RX_OUT
TX_IN
ADTR1107
22146-001
Figure 1.
GENERAL DESCRIPTION
The ADTR1107 is a compact, 6 GHz to 18 GHz, front-end IC
with an integrated power amplifier, low noise amplifier (LNA),
and a reflective single-pole double-throw (SPDT) switch. These
integrated features make the device ideal for phased array antenna
and radar applications. The front-end IC offers 25 dBm of
saturated output power (PSAT) and 22 dB small signal gain in
transmit state, and 18 dB small signal gain and 2.5 dB noise
figure in receive state. The device has a directional coupler for
power detection. The input/outputs (I/Os) are internally matched
to 50 Ω. The ADTR1107 is supplied in a 5 mm × 5 mm,
24-terminal, land grid array (LGA) package.
ADTR1107 Data Sheet
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Absolute Maximum Ratings ........................................................... 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions ............................ 7
Interface Schematics .................................................................... 8
Typical Performance Characteristics ............................................. 9
Transmit State ................................................................................9
Receive State ................................................................................ 16
Theory of Operation ...................................................................... 23
Applications Information ............................................................. 24
Recommended Bias Sequencing .............................................. 24
Typical Application Circuit ...................................................... 25
Interfacing the ADTR1107 to the ADAR1000 X Band and KU
Band Beamformer ............................................................................ 26
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
4/2020—Rev. 0 to Rev. A
Changes to VDD_LNA Parameter, Table 4 ................................. 5
1/2020—Revision 0: Initial Version
Data Sheet ADTR1107
Rev. A | Page 3 of 28
SPECIFICATIONS
Transmit state, VDD_PA = 5 V, IDQ_PA = 220 mA, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 0 V, receive state off (VDD_LNA = 0 V,
VGG_LNA = 0 V), TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OVERALL FUNCTION
Frequency Range 6 14 GHz
TRANSMIT STATE
Small Signal Gain 19.5 21.5 dB TX_IN to ANT
Gain Flatness ±0.8 dB
Input Return Loss 13 dB TX_IN to ANT
Output Return Loss 15 dB TX_IN to ANT
Output 1 dB Compression (OP1dB) 21 23 dBm TX_IN to ANT
Saturated Output Power (PSAT) 25 dBm
Output Third-Order Intercept (OIP3) 31 dBm TX_IN to ANT output power (POUT) per tone = 8 dBm
Noise Figure 9 dB TX_IN to ANT
Coupling Factor 23.5 dB Coupling factor = ANT POUT − CPLR_OUT POUT
Isolation
TX_IN to RX_OUT 40 dB Receive state off
ANT to RX_OUT 64 dB Receive state off
RF Settling Time
0.1 dB 17 ns 50% CTRL_SW to 0.1 dB of final RF output
0.05 dB 22 ns 50% CTRL_SW to 0.05 dB of final RF output
Switching Speed
Rise and Fall Time tRISE, tFALL 2 ns 10% to 90% of RF output
Turn On and Turn Off Time tON, tOFF 10 ns 50% CTRL_SW to 90% of RF output
VDD_PA 3.3 5.0 5.5 V
Quiescent Current (IDQ_PA) 220 mA
Adjust VGG_PA voltage between −1.75 V and
−0.25 V to achieve the desired IDQ_PA
Transmit state, VDD_PA = 5 V, IDQ_PA = 220 mA, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 0 V, receive state off, TA = 25°C,
unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OVERALL FUNCTION
Frequency Range 14 18 GHz
TRANSMIT STATE
Small Signal Gain 20 22 dB TX_IN to ANT
Gain Flatness ±0.6 dB
Input Return Loss 12 dB TX_IN to ANT
Output Return Loss 11 dB TX_IN to ANT
OP1dB 19 21.5 dBm TX_IN to ANT
PSAT 24 dBm TX_IN to ANT
OIP3 31.5 dBm TX_IN to ANT POUT per tone = 8 dBm
Noise Figure 6.5 dB TX_IN to ANT
Coupling Factor 18 dB Coupling factor = ANT POUT − CPLR_OUT POUT
Isolation
TX_IN to RX_OUT 39 dB Receive state off
ANT to RX_OUT 64 dB Receive state off
ADTR1107 Data Sheet
Rev. A | Page 4 of 28
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
RF Settling Time
0.1 dB 17 ns 50% CTRL_SW to 0.1 dB of final RF output
0.05 dB 22 ns 50% CTRL_SW to 0.05 dB of final RF output
Switching Speed
Rise and Fall Time tRISE, tFALL 2 ns 10% to 90% of RF output
Turn On and Turn Off Time tON, tOFF 10 ns 50% CTRL_SW to 90% of RF output
VDD_PA 3.3 5.0 5.5 V
IDQ_PA 220 mA
Adjust VGG_PA voltage between −1.75 V and −0.25 V to
achieve the desired IDQ_PA
Receive state, self biased, VDD_LNA = 3.3 V, VGG_LNA = 0 V, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 3.3 V, transmit state
off (VDD_PA = 0 V, VGG_PA = −1.75 V), TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OVERALL FUNCTION
Frequency Range 6 14 GHz
RECEIVE STATE
Small Signal Gain 15.5 17.5 dB ANT to RX_OUT
Gain Flatness ±0.6 dB
Input Return Loss 13 dB ANT to RX_OUT
Output Return Loss 14 dB ANT to RX_OUT
OP1dB 12 14 dBm ANT to RX_OUT
PSAT 16 dBm
OIP3 26 dBm ANT to RX_OUT POUT per tone = 0 dBm
Noise Figure 2.5 dB ANT to RX_OUT
Isolation
ANT to TX_IN 32 dB Transmit state off
RX_OUT to TX_IN 48 dB Transmit state off
RF Settling Time
0.1 dB 17 ns 50% CTRL_SW to 0.1 dB of final RF output
0.05 dB 22 ns 50% CTRL_SW to 0.05 dB of final RF output
Switching Speed
Rise and Fall Time tRISE, tFALL 2 ns 10% to 90% of RF output
Turn On and Turn Off Time tON, tOFF 10 ns 50% CTRL_SW to 90% of RF output
VDD_LNA 2.0 3.3 3.6 V
IDQ_LNA 80 mA Self biased
Receive state, self biased, VDD_LNA = 3.3 V, VGG_LNA = 0 V, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 3.3 V, transmit state
off, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OVERALL FUNCTION
Frequency Range 14 18 GHz
RECEIVE STATE
Small Signal Gain 16 18 dB ANT to RX_OUT
Gain Flatness ±0.9 dB
Input Return Loss 13 dB ANT to RX_OUT
Output Return Loss 18 dB ANT to RX_OUT
OP1dB 12 14 dBm ANT to RX_OUT
PSAT 16.5 dBm ANT to RX_OUT
Data Sheet ADTR1107
Rev. A | Page 5 of 28
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OIP3 25.5 dBm ANT to RX_OUT POUT per tone = 0 dBm
Noise Figure 3 dB ANT to RX_OUT
Isolation
ANT to TX_IN 26 dB Transmit state off
RX_OUT to TX_IN 46 dB Transmit state off
RF Settling Time
0.1 dB 17 ns 50% CTRL_SW to 0.1 dB of final RF output
0.05 dB 22 ns 50% CTRL_SW to 0.05 dB of final RF output
Switching Speed
Rise and Fall Time tRISE, tFALL 2 ns 10% to 90% of RF output
Turn On and Turn Off Time tON, tOFF 10 ns 50% CTRL_SW to 90% of RF output
VDD_LNA 2.0 3.3 3.6 V
IDQ_LNA 80 mA Self biased
SPDT switch bias at VDD_SW = 3.3 V, VSS_SW = −3.3 V.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT VDD_SW and VSS_SW
Positive IDD_SW 14 μA
Negative ISS_SW 120 μA
DIGITAL CONTROL INPUTS CTRL_SW
Voltage
Low 0 0.8 V
High 1.2 3.3 V
Current (Low and High) <1 μA
ADTR1107 Data Sheet
Rev. A | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Transmit State (PA On), Receive State Off
VDD_PA 5.5 V
VGG_PA −2 V to +0 V
Continuous Wave (CW) RF Input Power
(RFIN) at TX_IN
20 dBm
Continuous Power Dissipation (PDISS)
(TA = 85°C, Derate 18.98 mW/°C
1.71 W
Above 85°C)
Receive State (LNA On), Transmit State Off
VDD_LNA 4 V
VGG_LNA −2 V to +0.2 V
CW RFIN at ANT 20 dBm
PDISS (TA = 85°C, Derate 5.04 mW/°C
Above 85°C)
0.453 W
Transmit and Receive States
Output Load Voltage Standing Wave
Ratio (VSWR)
7:1
VDD_SW Range −0.3 V to +3.6 V
VSS_SW Range −3.6 V to +0.3 V
VDD_CTRL Range −0.3 V to VDD + 0.3 V
Channel Temperature 175°C
Maximum Peak Reflow Temperature
(Moisture Sensitivity Level 3, MSL3)1
260°C
Storage Temperature Range −40°C to +125°C
Operating Temperature Range −40°C to +85°C
ESD Sensitivity (Human Body Model) Class 1B
(Passed ±500 V)
1 See the Ordering Guide section for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the thermal resistance from the operating portion of the
device to the outside surface of the package (case) closest to the
device mounting area.
Table 7. Thermal Resistance1
Package Type θJC Transmit State θJC Receive State Unit
CC-24-8 52.7 198.4 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with 36 thermal vias. Refer to the JEDEC standard JESD51 for
additional information.
ESD CAUTION
Table 8. Signal Path Truth Table
State CTRL_SW RF Signal Path
Transmit Low TX_IN to ANT
Receive High ANT to RX_OUT
Data Sheet ADTR1107
Rev. A | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
1
3
4
2
7
GND
RX_OUT
GND
GND
5
6
TX_IN
GND GND
14
GND
15
GND
16
GND
17
ANT
18
GND
VGG_PA
8
VDD_PA
9
NIC
10
NIC
11
GND
12 19
CPLR_OUT VDD_SW
20
CTRL_SW
21
VSS_SW
22
GND
23
VGG_LNA
24
VDD_LNA
ADTR1107
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NO INTERNAL CONNECTION.
SOLDER THESE PINS TO A LOW
IMPEDANCE GROUND PLANE.
2. EXPOSED PAD. MUST BE CONNECTED
TO RF/DC GROUND.
22146-002
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1, 3, 4, 6, 11, 13
to 16, 18, 22
GND Ground. Solder these pins to a low impedance ground plane.
2 RX_OUT Receive Path Output. This pin is dc-coupled to ground and ac matched to 50 Ω.
5 TX_IN Transmit Path Input. This pin is dc-coupled to ground and ac matched to 50 Ω.
7 VGG_PA Power Amplifier Gate Bias. This pin is used to set the desired quiescent current of the amplifier.
8 VDD_PA Power Amplifier Drain Bias Voltage.
9, 10 NIC No Internal Connection. Solder these pins to a low impedance ground plane.
12 CPLR_OUT Transmit Path Coupled Port. This port is used in connection with a detector to monitor transmitted power.
17 ANT RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω.
19 VDD_SW SPDT Switch Positive Bias Voltage.
20 CTRL_SW Switch Digital Control. This pin controls the state of the SPDT switch.
21 VSS_SW SPDT Switch Negative Bias Voltage.
23 VGG_LNA
LNA Gate Voltage Bias. This pin is used to set the desired quiescent current of the LNA. If this pin is
supplied with 0 V or is connected to ground, the LNA runs in self bias mode at a typical current of 80 mA.
24 VDD_LNA LNA Drain Voltage Bias.
EPAD Exposed Pad. Must be connected to RF/dc ground.
ADTR1107 Data Sheet
Rev. A | Page 8 of 28
INTERFACE SCHEMATICS
GND
22146-003
Figure 3. GND Interface Schematic
ANT
22146-00
4
Figure 4. ANT Interface Schematic
V
DD_S
W
VDD_SW
CTRL_S
W
22146-005
Figure 5. CTRL_SW and VDD_SW Interface Schematic
V
DD_P
A
22146-006
Figure 6. VDD_PA Interface Schematic
GG_P
22146-007
Figure 7. VGG_PA Interface Schematic
V
DD_LN
A
22146-008
Figure 8. VDD_LNA Interface Schematic
VGG_LNA
22146-009
Figure 9. VGG_LNA Interface Schematic
RX_OUT
8kΩ
22146-010
Figure 10. RX_OUT Interface Schematic
TX_IN
2.5kΩ
22146-011
Figure 11. TX_IN Interface Schematic
Data Sheet ADTR1107
Rev. A | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
TRANSMIT STATE
30
25
20
–20
0
–10
10
15
5
–5
–15
026201282416 18 221410462
BROADBAND GAIN AND RETURN LOSS (dB)
FREQUENCY (GHz)
S11 (dB)
S21 (dB)
S22 (dB)
22146-012
Figure 12. Broadband Gain and Return Loss vs. Frequency, 10 MHz to 26 GHz,
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA,
Receive State Off
26
24
12
20
16
22
18
14
52017131171915 16 18141291068
GAIN (dB)
FREQUENCY (GHz)
5.0V
4.0V
3.3V
22146-013
Figure 13. Gain vs. Frequency for Various VDD_PA, Transmit State, Path =
TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
0
–4
–20
–12
–8
–16
INPUT RETURN LOSS (dB)
+85°C
+25°C
–40°C
52017131171915 16 18141291068
FREQUENCY (GHz)
22146-014
Figure 14. Input Return Loss vs. Frequency for Various Temperatures, Transmit
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
26
24
12
20
16
22
18
14
52017131171915 16 18141291068
GAIN (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-015
Figure 15. Gain vs. Frequency for Various Temperatures, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
26
24
12
20
16
22
18
14
52017131171915 16 18141291068
GAIN (dB)
FREQUENCY (GHz)
250mA
220mA
200mA
180mA
150mA
22146-016
Figure 16. Gain vs. Frequency for Various IDQ_PA, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, Receive State Off
0
–4
–20
–12
–8
–16
OUTPUT RETURN LOSS (dB)
+85°C
+25°C
–40°C
52017131171915 16 18141291068
FREQUENCY (GHz)
22146-017
Figure 17. Output Return Loss vs. Frequency for Various Temperatures, Transmit
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
ADTR1107 Data Sheet
Rev. A | Page 10 of 28
0
–10
–90
–80
–50
–30
–20
–60
–40
–70
REVERSE ISOLATION (dB)
+85°C
+25°C
–40°C
52017131171915 16 18141291068
FREQUENCY (GHz)
22146-018
Figure 18. Reverse Isolation vs. Frequency for Various Temperatures,Transmit
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
0
–10
–70
–50
–30
–20
–60
–40
TX_IN TO RX_OUT ISOLATION (dB)
+85°C
+25°C
–40°C
52017131171915 16 18141291068
FREQUENCY (GHz)
22146-019
Figure 19. TX_IN to RX_OUT Isolation vs. Frequency for Various Temperatures,
Transmit State, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
16
14
4
6
10
12
8
618161412817151310 1179
NOISE FIGURE (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-020
Figure 20. Noise Figure vs. Frequency for Various Temperatures, Transmit
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
36
32
8
16
24
28
12
20
34
10
18
26
30
14
22
CLRP_OUT COUPLING FACTOR (dB)
+85°C
+25°C
–40°C
52017131171915 16 18141291068
FREQUENCY (GHz)
22146-021
Figure 21. CLPR_OUT Coupling Factor vs. Frequency for Various
Temperatures, Transmit State, Coupling Factor = ANT POUT − CPLR_OUT POUT,
VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
0
–10
–90
–80
–50
–30
–20
–60
–40
–70
ANT TO RX_OUT ISOLATION (dB)
+85°C
+25°C
–40°C
52017131171915 16 18141291068
FREQUENCY (GHz)
22146-022
Figure 22. ANT to RX_OUT Isolation vs. Frequency for Various Temperatures,
Transmit State, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
16
14
4
6
10
12
8
618161412817151310 1179
NOISE FIGURE (dB)
FREQUENCY (GHz)
5.0V
4.0V
3.3V
22146-023
Figure 23. Noise Figure vs. Frequency for Various VDD_PA, Transmit State,
Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
Data Sheet ADTR1107
Rev. A | Page 11 of 28
16
14
4
6
10
12
8
618161412817151310 1179
NOISE FIGURE (dB)
FREQUENCY (GHz)
250mA
220mA
200mA
180mA
150mA
22146-024
Figure 24. Noise Figure vs. Frequency for Various IDQ_PA, Transmit State , Path =
TX_IN to ANT, VDD_PA = 5 V, Receive State Off
28
10
20
24
12
26
16
22
14
18
OP1dB (dBm)
52017131171915 16 18141291068
FREQUENCY (GHz)
5.0V
4.0V
3.3V
22146-025
Figure 25. OP1dB vs. Frequency for Various VDD_PA, Transmit State, Path =
TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
30
28
10
20
24
12
26
16
22
14
18
PSAT (dBm)
52017131171915 16 18141291068
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-026
Figure 26. PSAT vs. Frequency for Various Temperatures, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
28
10
20
24
12
26
16
22
14
18
OP1dB (dBm)
52017131171915 16 18141291068
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-027
Figure 27. OP1dB vs. Frequency for Various Temperatures,Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
28
10
20
24
12
26
16
22
14
18
OP1dB (dBm)
52017131171915 16 18141291068
FREQUENCY (GHz)
250mA
220mA
200mA
180mA
150mA
22146-028
Figure 28. OP1dB vs. Frequency for Various IDQ_PA, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, Receive State Off
30
28
10
20
24
12
26
16
22
14
18
PSAT (dBm)
52017131171915 16 18141291068
FREQUENCY (GHz)
5.0V
4.0V
3.3V
22146-029
Figure 29. PSAT vs. Frequency for Various VDD_PA, Transmit State, Path =
TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
ADTR1107 Data Sheet
Rev. A | Page 12 of 28
30
28
10
20
24
12
26
16
22
14
18
PSAT (dBm)
250mA
220mA
200mA
180mA
150mA
52017131171915 16 18141291068
FREQUENCY (GHz)
22146-030
Figure 30. PSAT vs. Frequency for Various IDQ_PA,Transmit State, Path = TX_IN
to ANT, VDD_PA = 5 V, Receive State Off
35
30
0
20
10
25
15
5
52017131171915 16 18141291068
PAE (%)
FREQUENCY (GHz)
5.0V
4.0V
3.3V
22146-031
Figure 31. Power Added Efficiency (PAE) vs. Frequency for Various VDD_PA,
Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off, PAE
Measured at PSAT
30
25
20
0
10
15
5
–20 –16 84–8 –4 0–12
P
OUT
(dBm), GAIN (dB), PAE (%)
I
DD
_PA (mA)
INPUT POWER (dBm)
P
OUT
GAIN
PAE
I
DD
_PA
330
310
210
230
270
290
250
22146-032
Figure 32. POUT, Gain, PAE and Power Amplifier Supply Current (IDD_PA) vs. Input
Power, 6 GHz, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA =
220 mA, Receive State Off
35
30
0
20
10
25
15
5
52017131171915 16 18141291068
PAE (%)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-033
Figure 33. PAE vs. Frequency for Various Temperatures, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off, PAE
Measured at PSAT
35
30
0
20
10
25
15
5
52017131171915 16 18141291068
PAE (%)
FREQUENCY (GHz)
250mA
220mA
200mA
180mA
150mA
22146-034
Figure 34. PAE vs. Frequency for Various IDQ_PA, Transmit State, Path = TX_IN
to ANT, VDD_PA = 5 V, Receive State Off, PAE Measured at PSAT
30
25
20
0
10
15
5
450
410
210
250
330
370
290
–20 –16 84–8 –4 0–12
P
OUT
(dBm), GAIN (dB), PAE (%)
I
DD
_PA (mA)
INPUT POWER (dBm)
P
OUT
GAIN
PAE
I
DD
_PA
22146-035
Figure 35. POUT, Gain, PAE and IDD_PA vs. Input Power, 10 GHz, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Data Sheet ADTR1107
Rev. A | Page 13 of 28
30
25
20
0
10
15
5
450
410
210
250
330
370
290
–20 105–10 –5 0–15
P
OUT
(dBm), GAIN (dB), PAE (%)
I
DD
_PA (mA)
INPUT POWER (dBm)
P
OUT
GAIN
PAE
I
DD
_PA
22146-036
Figure 36. POUT, Gain, PAE and IDD_PA vs. Input Power, 14 GHz, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
2.0
0
1.0
1.5
0.5
–20 100–15 5–10 –5
POWER DISSIPATION (W)
INPUT POWER (dBm)
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
MAX P
DISS
22146-037
Figure 37. Power Dissipation vs. Input Power at TA = 85°C, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
52017131171915 16 18141291068
FREQUENCY (GHz)
40
35
0
5
25
15
30
20
10
OIP3 (dBm)
5.0V
4.0V
3.3V
22146-038
Figure 38. OIP3 vs. Frequency for Various VDD_PA, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
30
25
20
0
10
15
5
330
310
210
230
270
290
250
–20 5–10 –5 0–15
P
OUT
(dBm), GAIN (dB), PAE (%)
I
DD
_PA (mA)
INPUT POWER (dBm)
P
OUT
GAIN
PAE
I
DD
_PA
22146-039
Figure 39. POUT, Gain, PAE and IDD_PA vs. Input Power, 18 GHz, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
52017131171915 16 18141291068
FREQUENCY (GHz)
+85°C
+25°C
–40°C
40
35
0
5
25
15
30
20
10
OIP3 (dBm)
22146-040
Figure 40. OIP3 vs. Frequency for Various Temperatures, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA,
Receive State Off
40
35
0
5
25
15
30
20
10
52017131171915 16 18141291068
OIP3 (dBm)
FREQUENCY (GHz)
250mA
220mA
200mA
180mA
150mA
22146-041
Figure 41. OIP3 vs. Frequency for Various IDQ_PA, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off
ADTR1107 Data Sheet
Rev. A | Page 14 of 28
40
35
0
5
25
15
30
20
10
52017131171915 16 18141291068
OIP3 (dBm)
FREQUENCY (GHz)
8dBm
6dBm
4dBm
22146-042
Figure 42. OIP3 vs. Frequency for Various POUT/Tone, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
70
65
10
45
55
25
60
35
50
15
30
40
20
618161412817151310 1179
OIP2 (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-043
Figure 43. Output Second-Order Intercept (OIP2) vs. Frequency for Various
Temperatures, POUT/Tone = 8 dBm, Transmit State, Path = TX_IN to ANT,
VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
70
65
10
45
55
25
60
35
50
15
30
40
20
618161412817151310 1179
OIP2 (dBm)
FREQUENCY (GHz)
250mA
220mA
200mA
180mA
150mA
22146-044
Figure 44. OIP2 vs. Frequency for Various IDQ_PA, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off
70
60
0
20
40
50
10
30
48657
IM3 (dBc)
P
OUT
/TONE (dBm)
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
22146-045
Figure 45. Third-Order Intermodulation Distortion Relative to Carrier (IM3)
vs. POUT/Tone, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA =
220 mA, Receive State Off
70
65
10
45
55
25
60
35
50
15
30
40
20
618161412817151310 1179
OIP2 (dBm)
FREQUENCY (GHz)
5.0V
4.0V
3.3V
22146-046
Figure 46. OIP2 vs. Frequency for Various VDD_PA, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
70
65
10
45
55
25
60
35
50
15
30
40
20
618161412817151310 1179
OIP2 (dBm)
FREQUENCY (GHz)
8dBm
6dBm
4dBm
22146-047
Figure 47. OIP2 vs. Frequency for Various POUT/Tone, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Data Sheet ADTR1107
Rev. A | Page 15 of 28
400
200
325
375
250
275
300
350
225
–20 1050–5–10–15
I
DD
_PA (mA)
INPUT POWER (dBm)
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
22146-048
Figure 48. IDD_PA vs. Input Power for Various Frequencies, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
800
–100
300
600
700
100
500
200
0
400
–1.75 –0.25–0.50–0.75–1.00–1.25–1.50
I
DQ
_PA (mA)
VGG_PA (V)
2
2146-049
Figure 49. IDQ_PA vs. VGG_PA, VDD_PA = 5 V, Transmit State, Path = TX_IN to
ANT, VDD_PA = 5 V, Receive State Off
0.2
–0.5
–0.1
0.1
–0.3
–0.2
0
–0.4
–20 1050–5–10–15
I
GG
_PA (mA)
INPUT POWER (dBm)
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
22146-050
Figure 50. Power Amplifier Gate Current (IGG_PA) vs. Input Power for Various
Frequencies, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA =
220 mA, Receive State Off
ADTR1107 Data Sheet
Rev. A | Page 16 of 28
RECEIVE STATE
25
20
–20
0
–10
10
15
5
–5
–15
026201282416 18 221410462
BROADBAND GAIN AND RETURN LOSS (dB)
FREQUENCY (GHz)
S11 (dB)
S21 (dB)
S22 (dB)
22146-051
Figure 51. Broadband Gain and Return Loss vs. Frequency, 10 MHz to 26 GHz,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
22
20
8
16
12
18
14
10
52017131171915 16 18141291068
GAIN (dB)
FREQUENCY (GHz)
2.0V
3.0V
3.3V
3.6V
22146-052
Figure 52. Gain vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off
0
–4
–20
–12
–8
–16
52017131171915 16 18141291068
INPUT RETURN LOSS (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-053
Figure 53. Input Return Loss vs. Frequency for Various Temperatures,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
22
20
8
16
12
18
14
10
52017131171915 16 18141291068
GAIN (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-054
Figure 54. Gain vs. Frequency for Various Temperatures, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
22
20
8
16
12
18
14
10
52017131171915 16 18141291068
GAIN (dB)
FREQUENCY (GHz)
50mA
100mA
85mA, SELF BIAS MODE
22146-055
Figure 55. Gain vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off
0
–4
–20
–12
–8
–16
52017131171915 16 18141291068
OUTPUT RETURN LOSS (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-056
Figure 56. Output Return Loss vs. Frequency for Various Temperatures,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
Data Sheet ADTR1107
Rev. A | Page 17 of 28
0
–10
–60
–50
–30
–20
–40
52017131171915 16 18141291068
REVERSE ISOLATION (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-057
Figure 57. Reverse Isolation vs. Frequency for Various Temperatures, Receive
State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA =
0 V, Transmit State Off
0
–10
–50
–30
–20
–40
52017131171915 16 18141291068
ANT TO TX_IN ISOLATION (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-058
Figure 58. ANT to TX_IN Isolation vs. Frequency for Various Temperatures,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
6.0
5.5
0
4.5
2.5
3.5
1.5
5.0
4.0
2.0
3.0
1.0
0.5
42016 1814121068
NOISE FIGURE (dB)
FREQUENCY (GHz)
2.0V
3.0V
3.3V
3.6V
22146-059
Figure 59. Noise Figure vs. Frequency for Various VDD_LNA, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off
0
–10
–70
–60
–50
–30
–20
–40
52017131171915 16 18141291068
RX_OUT TO TX_IN ISOLATION (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-060
Figure 60. RX_OUT to TX_IN Isolation vs. Frequency for Various
Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode,
VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off
6.0
5.5
0
4.5
2.5
3.5
1.5
5.0
4.0
2.0
3.0
1.0
0.5
42016 1814121068
NOISE FIGURE (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-061
Figure 61. Noise Figure vs. Frequency for Various Temperatures, Receive
State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
6.0
5.5
0
4.5
2.5
3.5
1.5
5.0
4.0
2.0
3.0
1.0
0.5
42016 1814121068
NOISE FIGURE (dB)
FREQUENCY (GHz)
50mA
100mA
85mA, SELF BIAS MODE
22146-062
Figure 62. Noise Figure vs. Frequency for Various IDQ_LNA, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled
VGG_LNA, Transmit State Off
ADTR1107 Data Sheet
Rev. A | Page 18 of 28
22
20
0
16
8
12
4
18
14
6
10
2
52017131171915 16 18141291068
OP1dB (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-063
Figure 63. OP1dB vs. Frequency for Various Temperatures, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
22
20
0
16
8
12
4
18
14
6
10
2
52017131171915 16 18141291068
OP1dB (dBm)
FREQUENCY (GHz)
50mA
100mA
85mA, SELF BIAS MODE
22146-064
Figure 64. OP1dB vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off
22
20
0
16
8
12
4
18
14
6
10
2
52017131171915 16 18141291068
P
SAT
(dBm)
FREQUENCY (GHz)
2.0V
3.0V
3.3V
3.6V
22146-065
Figure 65. PSAT vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off
22
20
0
16
8
12
4
18
14
6
10
2
52017131171915 16 18141291068
OP1dB (dBm)
FREQUENCY (GHz)
2.0V
3.0V
3.3V
3.6V
22146-066
Figure 66. OP1dB vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off
22
20
0
16
8
12
4
18
14
6
10
2
52017131171915 16 18141291068
P
SAT
(dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-067
Figure 67. PSAT vs. Frequency for Various Temperatures, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State = Off
22
20
0
16
8
12
4
18
14
6
10
2
52017131171915 16 18141291068
P
SAT
(dBm)
FREQUENCY (GHz)
50mA
100mA
85mA, SELF BIAS MODE
22146-068
Figure 68. PSAT vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off
Data Sheet ADTR1107
Rev. A | Page 19 of 28
25
0
20
10
15
5
52017131171915 16 18141291068
PAE (%)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-069
Figure 69. PAE vs. Frequency for Various Temperatures, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off, PAE Measured at PSAT
25
0
20
10
15
5
52017131171915 16 18141291068
PAE (%)
FREQUENCY (GHz)
50mA
100mA
85mA, SELF BIAS MODE
22146-070
Figure 70. PAE vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off, PAE Measured at PSAT
25
20
–5
0
10
15
5
110
105
80
85
95
100
90
–20 40–12 –8 –4–16
P
OUT
(dBm), GAIN (dB), PAE (%)
I
DD
_LNA (mA)
INPUT POWER (dBm)
P
OUT
GAIN
PAE
I
DD
_LNA
22146-071
Figure 71. POUT, Gain, PAE and IDD_LNA vs. Input Power, 10 GHz, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V,
Transmit State Off
25
0
20
10
15
5
52017131171915 16 18141291068
PAE (%)
FREQUENCY (GHz)
2.0V
3.0V
3.3V
3.6V
22146-072
Figure 72. PAE vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off, PAE
Measured at PSAT
25
20
–5
0
10
15
5
110
105
80
85
95
100
90
–20 20–4–8–16 –2–6–12 –10–18 –14
P
OUT
(dBm), GAIN (dB), PAE (%)
I
DD
_LNA (mA)
INPUT POWER (dBm)
P
OUT
GAIN
PAE
I
DD
_LNA
22146-073
Figure 73. POUT, Gain, PAE and IDD_LNA vs. Input Power, 6 GHz, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V,
Transmit State Off
25
20
–5
0
10
15
5
110
105
80
85
95
100
90
–20 50–10 –5–15
P
OUT
(dBm), GAIN (dB), PAE (%)
I
DD
_LNA (mA)
INPUT POWER (dBm)
P
OUT
GAIN
PAE
I
DD
_LNA
22146-074
Figure 74. POUT, Gain, PAE and IDD_LNA vs. Input Power, 14 GHz, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V,
Transmit State Off
ADTR1107 Data Sheet
Rev. A | Page 20 of 28
25
20
–5
0
10
15
5
110
105
80
85
95
100
90
–20 20–4–8–16 –2–6–12 –10–18 –14
P
OUT
(dBm), GAIN (dB), PAE (%)
I
DD
_LNA (mA)
INPUT POWER (dBm)
P
OUT
GAIN
PAE
I
DD
_LNA
22146-075
Figure 75. POUT, Gain, PAE and IDD_LNA vs. Input Power, 18 GHz, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
30
15
24
18
21
27
52017131171915 16 18141291068
OIP3 (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-076
Figure 76. OIP3 vs. Frequency for Various Temperatures, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
30
0
20
10
15
25
5
52017131171915 16 18141291068
OIP3 (dBm)
FREQUENCY (GHz)
50mA
100mA
85mA, SELF BIAS MODE
22146-077
Figure 77. OIP3 vs. Frequency for Various IDQ_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
Controlled VGG_LNA, Transmit State Off
0.5
0.4
0
0.2
0.3
0.1
–20 6–12 2–18 –6–10 4–16 –2–4–8–14 0
POWER DISSIPATION (W)
INPUT POWER (dBm)
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
MAX P
DISS
22146-078
Figure 78. Power Dissipation vs. Input Power at TA = 85°C, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
30
15
24
18
21
27
52017131171915 16 18141291068
OIP3 (dBm)
FREQUENCY (GHz)
2.0V
3.0V
3.3V
3.6V
22146-079
Figure 79. OIP3 vs. Frequency for Various VDD_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V,
Transmit State Off
30
0
20
10
15
25
5
52017131171915 16 18141291068
OIP3 (dBm)
FREQUENCY (GHz)
0dBm
5dBm
22146-080
Figure 80. OIP3 vs. Frequency for Various POUT/Tone, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
Data Sheet ADTR1107
Rev. A | Page 21 of 28
70
60
0
20
40
50
10
30
052413
IM3 (dBc)
P
OUT
/TONE (dBm)
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
22146-081
Figure 81. IM3 vs. POUT/Tone, Receive State, Path = ANT to RX_OUT, Self
Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off
45
40
0
20
30
10
35
15
25
5
618161412817151310 1179
OIP2 (dBm)
FREQUENCY (GHz)
2.0V
3.0V
3.3V
3.6V
22146-082
Figure 82. OIP2 vs. Frequency for Various VDD_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V,
Transmit State Off
45
40
0
20
30
10
35
15
25
5
618161412817151310 1179
OIP2 (dBm)
FREQUENCY (GHz)
0dBm
5dBm
22146-083
Figure 83. OIP2 vs. Frequency for Various POUT/Tone, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
45
40
0
20
30
10
35
15
25
5
618161412817151310 1179
OIP2 (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
22146-084
Figure 84. OIP2 vs. Frequency for Various Temperatures, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
45
40
0
20
30
10
35
15
25
5
618161412817151310 1179
OIP2 (dBm)
FREQUENCY (GHz)
50mA
100mA
85mA, SELF BIAS MODE
22146-085
Figure 85. OIP2 vs. Frequency for Various IDQ_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
Controlled VGG_LNA, Transmit State Off
90
70
80
85
75
–20 50–5–10–15
I
DD
_LNA (mA)
INPUT POWER (dBm)
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
22146-086
Figure 86. IDD_LNA vs. Input Power for Various Frequencies, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
ADTR1107 Data Sheet
Rev. A | Page 22 of 28
120
–20
0
40
80
100
20
60
–1.5 –1.0 –0.5 0
IDQ_LNA (mA)
VGG_LNA (V)
2
2146-087
Figure 87. IDQ_LNA vs. VGG_LNA, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Receive State, Path = ANT to RX_OUT, Transmit State Off
120
0
40
80
100
20
60
03.62.7 3.32.1 2.4 3.01.81.51.20.90.60.3
I
DQ
_LNA (mA)
V
DD
_LNA (V)
22146-088
Figure 88. IDQ_LNA vs. VDD_LNA, Self Biased Mode, VGG_LNA = 0 V, Receive
State, Path = ANT to RX_OUT, Transmit State Off
Data Sheet ADTR1107
Rev. A | Page 23 of 28
THEORY OF OPERATION
The ADTR1107 is a multichip transmit/receive module that
consists of an LNA, a medium power amplifier, and a silicon
SPDT reflective switch. The ANT antenna port is dc-coupled to
0 V and no dc block is required at this port when the RF line
potential is equal to 0 V. The switch has an integrated driver to
perform logic functions internally and provides a simplified
complementary metal-oxide semiconductor (CMOS)/low
voltage transistor to transistor logic (LVTTL)-compatible
control interface. The driver features a single digital control
input pin, CTRL_SW. The logic level applied to CTRL_SW
determines whether the ADTR1107 is in transmit state or
receive state (see Table 8).
The receive path contains a self biased LNA with optional bias
control using the VGG_LNA pin for bias adjustment. For self
biased operation, the VGG_LNA pin is set to 0 V or connected
to ground. The receive path output (RX_OUT) is dc-coupled to
ground through an 8 kΩ resistor. No dc block is required at this
port when the RF line potential is equal to 0 V.
The transmit path contains a power amplifier. The bias
current is set using VGG_PA. The transmit path input (TX_IN)
is dc-coupled to ground through a 2.5 kΩ resistor. No dc block
is required at this port when the RF line potential is equal to 0 V.
A directional coupler is incorporated into the ADTR1107 to
allow for monitoring of the transmit power level.
ADTR1107 Data Sheet
Rev. A | Page 24 of 28
APPLICATIONS INFORMATION
The basic connections for operating the ADTR1107 are shown
in Figure 89. The power amplifier on the transmit path is biased
with +5 V on the VDD_PA pin and a voltage from −1.75 V to
−0.25 V is applied to the VGG_PA pin to achieve 220 mA
quiescent current.
The LNA on the receive path operates as either self biased or
external biased mode. For self biased mode, apply 3.3 V to the
VDD_LNA pin and leave the VGG_LNA pin supplied with 0 V
or connected to ground. For external biased mode, apply +3.3 V
to the VDD_LNA pin and adjust the VGG_LNA pin with a voltage
range of −1.5 V to 0 V to achieve the desired IDQ_PA.
The SPDT switch is biased with +3.3 V on the VDD_SW pin
and −3.3 V on the VSS_SW pin. The CTRL_SW pin sets the
path state shown in Table 8. High logic state is set at 3.3 V and
low logic state is set at 0 V.
All required decoupling capacitors for the dc power supply
lines are internal to the ADTR1107.
RECOMMENDED BIAS SEQUENCING
The recommended bias sequence during transmit state
power-up is as follows:
1. Connect all GND pins to ground.
2. Set the VDD_SW pin to 3.3 V.
3. Set the VSS_SW pin to −3.3 V.
4. Set the CTRL_SW pin to 0 V.
5. Set the VGG_LNA pin to 0 V.
6. Set the VDD_LNA pin to 0 V.
7. Set the VGG_PA pin to −1.75 V.
8. Set the VDD_PA pin to 5 V.
9. Increase the VGG_PA voltage to achieve the desired
IDQ_PA.
10. Apply the RF signal to the TX_IN pin.
The recommended transmit state bias sequence during
power-down is as follows:
1. Turn off the RF signal.
2. Decrease the VGG_PA voltage to −1.75 V.
3. Set the VDD_PA pin to 0 V.
4. Set the VSS_SW pin to 0 V.
5. Set the VDD_SW pin to 0 V.
The recommended bias sequence during receive state power-up
is as follows:
1. Connect all GND pins to ground.
2. Set the VDD_SW pin to 3.3 V.
3. Set the VSS_SW pin to −3.3 V.
4. Set the CTRL_SW pin to 3.3 V.
5. Set the VGG_PA pin to −1.75 V.
6. Set the VDD_PA pin to 0 V.
7. Set the VGG_LNA pin to 0 V.
8. Set the VDD_LNA pin to 3.3 V.
9. Apply the RF signal to the ANT pin.
The recommended receive state bias sequence during
power-down is as follows:
1. Turn off the RF signal.
2. Set the VDD_LNA pin to 0 V.
3. Set the CTRL_SW pin to 0 V.
4. Set the VSS_SW pin to 0 V.
5. Set the VDD_SW pin to 0 V.
All measurements and data shown in this data sheet were taken
using the typical application circuit (see Figure 89) and biased
per the conditions in this section, unless otherwise noted. The
bias conditions described in this section are the operating
points recommended to optimize the overall device performance.
Operation using other bias conditions can result in performance
that differs from what is shown in the Typical Performance
Characteristics section. To obtain optimal performance while
not damaging the device, follow the recommended biasing
sequences described in this section and adhere to the values
shown in the Absolute Maximum Ratings section.
Data Sheet ADTR1107
Rev. A | Page 25 of 28
TYPICAL APPLICATION CIRCUIT
21
9
7
23
10
19
824
5
217
PAD
22
18
16
15
14
13
11
6
4
3
1
20
12
GND
GND
GND
GND
TX_IN
RX_OUT
GND
GND
GND
GND
GND
ANT
PAD
VGG_LNA
GND
CTRL_SW
VSS_SW
VDD_SW
VDD_LNA
VDD_PA
NIC
GND
NIC
CPLR_OUT
VGG_PA
ADTR1107
GND
–1.75V TO –0.25V
+5V
+3.3V
+3.3
V
COUPLED
OUTPUT
RECEIVE PATH OUTPUT
TRANSMIT PATH INPUT
–3.3V
0V
0V/+3.3V
22146-090
Figure 89. Typical Application Circuit
ADTR1107 Data Sheet
Rev. A | Page 26 of 28
INTERFACING THE ADTR1107 TO THE ADAR1000 X BAND AND KU BAND BEAMFORMER
ADTR1107 can be interfaced to the ADAR1000 X band and Ku
band quad beamformer IC, as shown in Figure 91. Note that
only a single channel of the ADAR1000 is shown in Figure 91
and additional components have been omitted for clarity. The
ADAR1000 provides multiple bias voltages and control signals,
resulting in a glueless interface and no need for any additional
control signals to the ADTR1107. The gate voltage for the
ADTR1107 power amplifier (VGG_PA) is provided by the
ADAR1000 PA_BIAS3 pin. One of four independent negative
gate voltages is needed for power amplifier gate biasing. Each
voltage is set by an 8-bit digital-to-analog converter (DAC)
with an output voltage range of 0 V to −4.8 V. The typical gate
voltage required to bias the ADTR1107 power amplifier is −1.1 V
(see Figure 49). This voltage can be asserted by the ADAR1000
TR input pin (rising edge enables the power amplifier) or by a
serial peripheral interface (SPI) write. Asserting the ADAR1000
TR pin switches the polarity of the ADAR1000 TR_SW_NEG pin
and TR_SW_POS pin. The TR_SW_POS pin can drive the
gates of up to four switches and can be used to control the
ADTR1107 SPDT switch.
While the ADTR1107 LNA gate voltage is self biased (the
VGG_LNA pin is connected to 0 V or grounded), the voltage
can also be controlled from the ADAR1000. In this case, there
is a single LNA_BIAS voltage (0 V to −4.8 V) controlled by an
8-bit DAC that can be used to bias four ADTR1107 devices
connected to each ADAR1000.
The ADTR1107 CPLR_OUT coupler output can be tied back to
one of the four ADAR1000 RF detector inputs (DET1 to DET4).
These diode based RF detectors have an input range of −20 dBm to
+10 dBm. The coupling factor of the ADTR1107 directional
coupler ranges from 28 dB at 6 GHz to 18 dB at 18 GHz. At
12 GHz, with a coupling factor of 22 dB and a maximum power
amplifier output of 26 dBm, the coupled output power is a
maximum of 4 dBm. If the coupler output is connected directly
to the detector input, this connection provides a detection range of
24 dB. Figure 90 shows the relationship between the ADTR1107
output power and the ADC code of the ADAR1000 detector at
12 GHz. In this case, the ADTR1107 output power is swept to a
maximum level of approximately 22 dBm.
100
0.1
1
10
52319 211715131197
ADAR1000 RF DETECTOR OUTPUT CODE (Decimal)
ADTR1107 OUTPUT POWER (dBm)
22146-091
Figure 90. ADAR1000 RF Detector Output Code vs. ADTR1107 Output Power
at 12 GHz
Data Sheet ADTR1107
Rev. A | Page 27 of 28
VDD_LNA
VGG_LNA
VSS_SW
VGG_PA
VDD_PA CPLR_OUT
ANT
RX_OUT
TX_IN
CTRL_SW
VDD_SW
GND
PA BIAS PA_BIAS3
RF_IO
RX3
TX3
A
VDD1 AVDD3
SPI
SDO
CSB
SDIO
SCLK
ADDR1
ADDR0
RX_LOAD
TX_LOAD
TR
TO PA
BIAS
PA_ON
ADAR1000
DET3
ADC
LNA BIAS
+3.3
V
–
5
V
+3.3V
+3.3V –3.3V
TR_SW_POS
+5V
LDO
1.8V
100kΩ
LNA_BIAS
1
ADTR1107
TO ADDITIONAL LNA
GATES
1
LNA_BIAS IS A SINGLE PIN THAT CAN DRIVE UP TO FOUR GATES AND
IS AN OPTIONAL CONNECTION THAT CAN BE USED TO VARY THE BIAS
CURRENT OF THE ADTR1107.
22146-092
Figure 91. Interfacing the ADTR1107 to the ADAR1000 X and Ku Band Beamformer, One Channel Shown
ADTR1107 Data Sheet
Rev. A | Page 28 of 28
OUTLINE DIMENSIONS
0
3-26-2019-
B
P
KG-005635
5.10
5.00 SQ
4.90
TOP VIEW BOTTOM VIEW
SIDE VIEW
1
6
7
12
13
18
19 24
0.65
BSC
0.15
REF
3.25 REF
SQ
0.35
0.30
0.25
0.356
0.326
0.296
0.50
0.45
0.40
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
0.70 REF
1.13
MAX
3.30 SQ
BSC
SEATING
PLANE
PIN 1
INDIC
A
TOR
C 0.30 × 0.45°
PIN 1
INDICATOR
AREA
Figure 92. 24-Terminal Land Grid Array [LGA]
(CC-24-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description3 Package Option
ADTR1107ACCZ −40°C to +85°C 3 24-Terminal Land Grid Array [LGA] CC-24-8
ADTR1107ACCZ-R7 −40°C to +85°C 3 24-Terminal Land Grid Array [LGA] CC-24-8
ADTR1107-EVAL Evaluation Board
1 Z = RoHS Compliant Part.
2 See the Absolute Maximum Ratings section for additional information.
3 The lead finish of the ADTR1107ACCZ and the ADTR1107ACCZ-R7 is nickel palladium gold (NiPdAu).
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D22146-4/20(A)