MAX509AEAP - Maxim Integrated Products, Inc.

_______________General Description

The MAX509/MAX510 are quad, serial-input, 8-bit volt-

age-output digital-to-analog converters (DACs). They

operate with a single +5V supply or dual ±5V supplies.

Internal, precision buffers swing rail-to-rail. The refer-

ence input range includes both supply rails.

The MAX509 has four separate reference inputs, allow-

ing each DAC's full-scale range to be set independently.

20-pin DIP, SSOP, and SO packages are available. The

MAX510 is identical to the MAX509 except it has two ref-

erence inputs, each shared by two DACs. The MAX510

is housed in space-saving 16-pin DIP and SO packages.

The serial interface is double-buffered: A 12-bit input

shift register is followed by four 8-bit buffer registers and

four 8-bit DAC registers. A 12-bit serial word is used to

load data into each register. Both input and DAC regis-

ters can be updated independently or simultaneously

with single software commands. Two additional asyn-

chronous control pins provide simultaneous updating

(LDAC) or clearing (CLR) of input and DAC registers.

The interface is compatible with MicrowireTM and SPI/

QSPITM. All digital inputs and outputs are TTL/CMOS

compatible. A buffered data output provides for read-

back or daisy-chaining of serial devices.

____________________________Features

♦Single +5V or Dual ±5V Supply Operation

♦Output Buffer Amplifiers Swing Rail-to-Rail

♦Reference Input Range Includes Both Supply Rails

♦Calibrated Offset, Gain, and Linearity (1LSB TUE)

♦10MHz Serial Interface, Compatible with SPI, QSPI

(CPOL = CPHA = 0) and Microwire

♦Double-Buffered Registers for Synchronous

Updating

♦Serial Data Output for Daisy-Chaining

♦Power-On Reset Clears Serial Interface and Sets

All Registers to Zero

______________Ordering Information

Ordering Information continued on last page.

* Dice are specified at +25°C, DC parameters only.

**Contact factory for availability and processing to MIL-STD-883.

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

________________________________________________________________

Maxim Integrated Products

OUTC

OUTD

VDD

REFC

REFB

VSS

OUTA

OUTB

TOP VIEW

MAX509

REFD

N.C.

SCLK

DGND

N.C.

AGND

REFA

DIN

CLR

DOUT

LDAC

DIP/SO/SSOP

_________________Pin Configurations

MAX509

OUTA

DAC A

DAC B

DAC C

DAC D

REFAREFB

DAC

REG A

DECODE

CONTROL

INPUT

REG A

DAC

REG B

INPUT

REG B

DAC

REG C

INPUT

REG C

DAC

REG D

INPUT

REG D

12-BIT

SHIFT

SR

CONTROL

CS DIN SCLK REFC REFD

OUTB

OUTC

OUTD

DOUT LDAC

CLR VDD

DGND VSS

AGND

_______________Functional Diagrams

19-0155; Rev 2; 1/96

PART TEMP. RANGE PIN-PACKAGE

MAX509ACPP 0°C to +70°C 20 Plastic DIP

MAX509BCPP 0°C to +70°C 20 Plastic DIP

MAX509ACWP 0°C to +70°C 20 Wide SO

±1

±1 1/2

±1

MAX509BCWP 20 Wide SO ±1 1/2

MAX509ACAP 0°C to +70°C 20 SSOP ±1

0°C to +70°C

MAX509BCAP 0°C to +70°C 20 SSOP ±1 1/2

MAX509BC/D 0°C to +70°C Dice* ±1 1/2

Pin Configurations continued at end of data sheet.

Functional Diagrams continued at end of data sheet.

TUE

(LSB)

Microwire is a trademark of National Semiconductor. SPI and QSPI are trademarks of Motorola.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

2 _______________________________________________________________________________________

VDD to DGND ..............................................................-0.3V, +6V

VDD to AGND...............................................................-0.3V, +6V

VSS to DGND...............................................................-6V, +0.3V

VSS to AGND...............................................................-6V, +0.3V

VDD to VSS.................................................................-0.3V, +12V

Digital Input Voltage to DGND ......................-0.3V, (VDD + 0.3V)

REF_....................................................(VSS - 0.3V), (VDD + 0.3V)

OUT_..............................................................................VDD, VSS

Maximum Current into Any Pin............................................50mA

Continuous Power Dissipation (TA= +70°C)

16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW

16-Pin Wide SO (derate 9.52mW/°C above +70°C).........762mW

16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW

20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW

20-Pin Wide SO (derate 10.00mW/°C above +70°C).......800mW

20-Pin SSOP (derate 10.00mW/°C above +70°C)............800mW

20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW

Operating Temperature Ranges:

MAX5_ _ _C_ _.....................................................0°C to +70°C

MAX5_ _ _E_ _..................................................-40°C to +85°C

MAX5_ _ _MJ_ ................................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

ELECTRICAL CHARACTERISTICS

(VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX,

unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Note: The outputs may be shorted to VDD, VSS, or AGND if the package power dissipation is not exceeded. Typical short-circuitcurrent

to AGND is 50mA. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND.

ABSOLUTE MAXIMUM RATINGS

Resolution 8 Bits

±1MAX5_ _A

VREF = +4V,

VSS = 0V or -5V ±10% MAX5_ _B ±1MAX5_ _A

Total Unadjusted Error VREF = -4V,

VSS = -5V ±10% ±1.5

LSB

Differential Nonlinearity ±1 LSBGuaranteed monotonic 14MAX5_ _C 16MAX5_ _E

MAX5_ _B

±10 µV/°CCode = FF hex

14MAX5_ _C

Full-Scale Error ±14 mVCode = FF hex

±10 µV/°CCode = 00 hex

Zero-Code-Error Supply Rejection 12mV

Code = 00 hex,

VSS = 0V 20MAX5_ _M

SYMBOL

TUE

DNL

±14MAX5_ _C ±16MAX5_ _E

Zero-Code Error

Code = 00 hex,

VSS = -5V ±10% ±20

MAX5_ _M

ZCE

±1.5

Code = 00 hex, VDD = 5V ±10%,

VSS = 0V or -5V ±10%

Zero-Code

Temperature Coefficient

18MAX5_ _E

Full-Scale-Error Supply Rejection Code = FF hex,

VDD = +5V ±10%,

VSS = 0V or -5V ±10% 112

MAX5_ _M

Full-Scale-Error

Temperature Coefficient

STATIC ACCURACY

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX,

unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Voltage Range

SYMBOL

VSS VDD V

MAX509 16 24

MAX510

Input Resistance (Note 1) 812 kΩCode = 55 hex

MAX509 15

(Note 4)AC Feedthrough -70 dB

(Note 3)Channel-to-Channel Isolation -60 dB

MAX510

Input Capacitance (Note 2) 30 pFCode = 00 hex

VREF = 4V, load regulation ≤1/4LSB 2

Full-Scale Output Voltage VSS VDD V

Resistive Load

kΩ

Input High Voltage 2.4 VVIH

VREF = -4V, VSS = -5V ±10%,

load regulation ≤1/4LSB

VREF = VDD MAX5_ _C/E,

load regulation ≤1LSB

VREF = VDD MAX5_ _M,

load regulation ≤2LSB

Input Low Voltage 0.8 VVIL VIN = 0V or VDD

Input Current 1.0 µAIIN (Note 5)Input Capacitance 10 pFCIN

ISOURCE = 0.2mAOutput High Voltage VDD - 0.5 VVOH ISINK = 1.6mAOutput Low Voltage 0.4 VVOL

MAX5_ _E 0.7

MAX5_ _C 1.0

MAX5_ _M

Voltage-Output Slew Rate 0.5 V/µsPositive and negative

To 1/2LSB, 10kΩII 100pF loadOutput Settling Time (Note 6) 6 µs

Digital Feedthrough 5 nV-s

Wideband Amplifier Noise 60 MHzVREF = 0.5Vp-p, 3dB bandwidthMultiplying Bandwidth 1

VREF = 4Vp-p at 1kHz, VDD = 5V,

code = FF hex

Digital-to-Analog Glitch Impulse

Code 128➝127 12 nV-s

Code = 00 hex, all digital inputs

from 0V to VDD

Signal-to-Noise + Distortion Ratio VREF = 4Vp-p at 20kHz, VSS = -5V ±10% 74 dBSINAD

µVRMS

REFERENCE INPUTS

DAC OUTPUTS

DIGITAL INPUTS

DIGITAL OUTPUTS

DYNAMIC PERFORMANCE

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX,

unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Positive Supply Voltage

SYMBOL

4.5 5.5 VFor specified performanceVDD

Negative Supply Voltage -5.5 0 VFor specified performanceVSS 510

Positive Supply Current 512

mAIDD

Negative Supply Current mAISS 510

MAX5_ _C/E

MAX5_ _M

MAX5_ _C/E

512MAX5_ _M

VSS = -5V ±10%, outputs

unloaded, all digital

inputs = 0V or VDD

Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.

Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.

Note 3: VREF = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the

code of all other DACs to 00 hex.

Note 4: VREF = 4Vp-p, 10kHz. DAC code = 00 hex.

Note 5: Guaranteed by design.

Note 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.

TIMING CHARACTERISTICS

(VDD = +5V ±10%, VSS = 0V to -5V, VREF = 4V, AGND = DGND = 0V, CL= 50pF, TA= TMIN to TMAX, unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

CLR Pulse Width Low

SYMBOL

50 25 ns

MAX5_ _M

MAX5_ _C/E 40 20

tCLW

MAX5_ _M 50 25 ns

MAX5_ _C/E 40 20

SCLK Fall to CS Rise Hold Time 0 nstCSH2

SCLK Fall to CS Fall Hold Time 0 ns(Note 7)tCSH0 40MAX5_ _C/E

10 100MAX5_ _C/E

MAX5_ _C/E 40

40MAX5_ _C/E

20 12.5MAX5_ _C/E

DIN to SCLK Rise Hold Time 0 nstDH

SCLK Rise to CS Rise Hold Time (Note 9) 40 nstCSH1

LDAC Pulse Width Low

(Notes 7, 8) 0 ns

tLDW

tCLL

CS Rise to LDAC Fall Setup Time

40MAX5_ _C/E

CS Fall to SCLK Setup Time 50 ns

MAX5_ _M

tCSS

DIN to SCLK Rise Setup Time 50 ns

MAX5_ _M

tDS

SCLK Clock Frequency 20 10 MHz

MAX5_ _M

fCLK

SCLK Pulse Width High 50 ns

MAX5_ _M

tCH

SCLK Pulse Width Low MAX5_ _M 50 nstCL

SCLK to DOUT Valid 10 100 ns

MAX5_ _M

tDO

Note 7: Guaranteed by design.

Note 8: If LDAC is activated prior to CS's rising edge, it must stay low for tLDW or longer after CS goes high.

Note 9: Minimum delay from 12th clock cycle to CS rise.

Outputs unloaded, all

digital inputs = 0V or VDD

POWER SUPPLIES

SERIAL INTERFACE TIMING

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

_______________________________________________________________________________________

00 1.2

OUTPUT SINK CURRENT

vs. (VOUT - VSS)

MAX509-FG01

VOUT - VSS (V)

IOUT (mA)

0.8

0.2 0.6 1.0

0.4

VDD = VREF = +5V

VSS = GND = 0V

ALL DIGITAL INPUTS = 00 HEX

-25

03.6 4.6

-20

MAX509-FG10

VOUT (V)

IOUT (mA)

4.4

-10

-5

3.8 4.0

-15

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE

4.8 5.0

4.2

VDD = VREF = +5V

VSS = GND

DIGITAL INPUT = FF HEX

0-60 -20 40 100

SUPPLY CURRENT

vs. TEMPERATURE

MAX509-FG02

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

20 80

-40 0 60 120 140

IDD

ISS

VDD = +5.5V

VSS = -5.5V

VREF = -4.75

ALL DIGITAL INPUTS = +5V

0-5 5

SUPPLY CURRENT

vs. REFERENCE VOLTAGE

MAX509-FG03

VREF VOLTAGE (V)

IDD (mA)

-4 -2 2

431-1-3

VDD = +5V

ALL LOGIC

INPUTS = +5V

VSS = -5V VSS = 0V

1k 10k 100k

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

-40

MAX509-FG06

FREQUENCY (Hz)

RELATIVE OUTPUT (dB)

-30

-20

-10

1M 10M

VDD = +5V

VSS = AGND

VREF = 2.5VDC + 0.5Vp-p SINE WAVE

-40

-90 02 6 10

THD + NOISE AT DAC OUTPUT

vs. REFERENCE AMPLITUDE

-80

-50

MAX509-FG04

REFERENCE AMPLITUDE (Vp-p)

THD + NOISE (dB)

-60

-70

-85

-75

-65

-55

-45

0.01%

0.1%

FREQ = 20kHz

FREQ = 1kHz

VDD = +5V

VSS = -5V

INPUT CODE = FF HEX

THD + NOISE (%)

-20

-80

10 1k 100k

THD + NOISE AT DAC OUTPUT

vs. REFERENCE FREQUENCY

-70

MAX509-FG05

REFERENCE FREQUENCY (Hz)

THD + NOISE (dB)

-60

-50

-40

-90

-30

100 10k

VREF = 8Vp-p

VREF = 1Vp-p

VREF = 4Vp-p

VDD = +5V

VSS = -5V

INPUT CODE = FF HEX

FREQ = SWEPT

10%

0.1%

0.01%

THD + NOISE (%)

1k 10k 100k

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

-40

MAX509-FG07

FREQUENCY (Hz)

RELATIVE OUTPUT (dB)

-30

-20

-10

1M 10M

VDD = +5V

VSS = AGND

VREF = 2.5VDC + 0.05Vp-p SINE WAVE

1k 10k 100k

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

-40

MAX509-FG08

FREQUENCY (Hz)

RELATIVE OUTPUT (dB)

-30

-20

-10

1M 10M

VDD = +5V

VSS = -5V

VREF = 2.5VDC + 4Vp-p SINE WAVE

__________________________________________Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

MAX509/MAX510

Quad, Serial 8-DACs

with Rail-to-Rail Outputs

6 _______________________________________________________________________________________

____________________________Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)



A = REFA, 10Vp-p

B = OUTA, 100µV/div, UNLOADED

TIMEBASE = 10µs/div

VDD = +5V, VSS = -5V

CODE = ALL 0s

REFERENCE FEEDTHROUGH AT 40kHz



A = REFA, 10Vp-p

B = OUTA, 50µV/div, UNLOADED

TIMEBASE = 1ms/div

REFERENCE FEEDTHROUGH AT 400Hz



A = REFA, 10Vp-p

B = OUTA, 50µV/div, UNLOADED

TIMEBASE = 50µs/div



REFERENCE FEEDTHROUGH AT 10kHz



5V 50µV

100µS



A = REFA, 10Vp-p

B = OUTA, 50µV/div, UNLOADED

TIMEBASE = 100µs/div

REFERENCE FEEDTHROUGH AT 4kHz



5.0

3.6

0-4

ZERO-CODE ERROR

vs. NEGATIVE SUPPLY VOLTAGE

3.8

4.8

MAX509-FG09

VSS (V)

ZERO-CODE ERROR (mV)

-3

4.4

4.0

-1 -2

4.6

3.4

4.2

-5 -6

VDD = +5V

VREF = +4V 

A = CS, 2V/div

B = OUTA, 20mV ˜

TIMEBASE = 200ns/div

WORST-CASE 1LSB DIGITAL STEP CHANGE





200nS

2V 20mV

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

_______________________________________________________________________________________

5V 100mV

1µS



A = DIGITAL INPUT, 5V/div

B = OUT_ , 2V/div

TIMEBASE = 1µs/div

VDD = +5V

REF_ = +4V

ALL BITS OFF TO ALL BITS ON

RL = 10kΩ, CL = 100pF

POSITIVE SETTLING TIME

(VSS = AGND OR -5V)



5V 100mV

1µS



A = DIGITAL INPUT, 5V/div

B = OUT_ , 2V/div

TIMEBASE = 1µs/div

VDD = +5V

REF_ = +4V

ALL BITS ON TO ALL BITS OFF

RL = 10kΩ, CL = 100pF

NEGATIVE SETTLING TIME

(VSS = AGND)



____________________________Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)



A = SCLK, 333kHz

B = OUT_, 10mV/div

TIMEBASE = 2µs/div

CLOCK FEEDTHROUGH



5V 100mV

1µS



A = DIGITAL INPUT, 5V/div

B = OUT_ , 2V/div

TIMEBASE = 1µs/div

VDD = +5V

REF_ = +4V

ALL BITS ON TO ALL BITS OFF

RL = 10kΩ, CL = 100pF

NEGATIVE SETTLING TIME

(VSS = -5V)



MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

8 _______________________________________________________________________________________

NAME FUNCTION

1OUTB DAC B Voltage Output

2 OUTA DAC A Voltage Output

3 VSS Negative Power Supply, 0V to -5V ±10%. Connect to AGND for single-supply operation.

MAX509 MAX510

4 REFB Reference Voltage Input for DAC B

– REFAB Reference Voltage Input for DACs A and B

5 REFA Reference Voltage Input for DAC A

6 AGND Analog Ground

–

7, 14 N.C. Not Internally Connected

8 DGND Digital Ground

–

______________________________________________________________Pin Description

10 DOUT8

9LDAC

11 CLR

12 DIN10

13 SCLK11

15 CS

16 REFD Reference Voltage Input for DAC D–

– REFCD Reference Voltage Input for DACs C and D13

Load DAC Input (active low). Driving this asynchronous input low (level sensitive)

transfers the contents of each input latch to its respective DAC latch.

Serial Data Output. Can sink and source current. Data at DOUT is adjustable to be

clocked out on rising or falling edge of SCLK.

17 REFC Reference Voltage Input for DAC C–

18 VDD Positive Power Supply, +5V ±10%14

19 OUTD DAC D Output Voltage15

20 OUTC DAC C Output Voltage16

Clear DAC input (active low). Driving CLR low causes an asynchronous clear of input

and DAC registers and sets all DAC outputs to zero.

Serial Data Input. TTL/CMOS-compatible input. Data is clocked into DIN on the

rising edge of SCLK. CS must be low for data to be clocked in.

Serial Clock Input. Data is clocked in on the rising edge and clocked out on either the

rising (default) or the falling edge.

Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming

commands are executed when CS rises.

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

_______________________________________________________________________________________ 9

• • •

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

DACA

DATA FROM PREVIOUS DATA INPUT DATA FROM PREVIOUS DATA INPUT

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

DACD

A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 C1 C0 D7

A0 C1 C0 D7

D6 D5 D4 D3 D2 D1 D0 A1

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 D6 D5 D4 D3 D2 D1 D0 A1

DOUT

MODE 0

DOUT

MODE 1

(DEFAULT)

DIN

SCLK

• • •

INSTRUCTION

EXECUTED

Figure 1. MAX509/MAX510 3-Wire Interface Timing

_______________Detailed Description

Serial Interface

At power-on, the serial interface and all DACs are

cleared and set to code zero. The serial data output

(DOUT) is set to transition on SCLK's rising edge.

The MAX509/MAX510 communicate with microproces-

sors through a synchronous, full-duplex, 3-wire inter-

face (Figure 1). Data is sent MSB first and can be

transmitted in one 4-bit and one 8-bit (byte) packet or

in one 12-bit word. If a 16-bit control word is used, the

first four bits are ignored. A 4-wire interface adds a line

for LDAC and allows asynchronous updating. The serial

clock (SCLK) synchronizes the data transfer. Data is

transmitted and received simultaneously.

Figure 2 shows a detailed serial interface timing.

Please note that the clock should be low if it is stopped

between updates. DOUT does not go into a high-

impedance state if the clock or CS is high.

Serial data is clocked into the data registers in MSB-

first format, with the address and configuration infor-

mation preceding the actual DAC data. Data is

clocked in on SCLK's rising edge while CS is low. Data

at DOUT is clocked out 12 clock cycles later, either at

SCLK's rising edge (default or mode 1) or falling edge

(mode 0).

Chip select (CS) must be low to enable the DAC. If CS

is high, the interface is disabled and DOUT remains

unchanged. CS must go low at least 40ns before the

first rising edge of the clock pulse to properly clock in

the first bit. With CS low, data is clocked into the

MAX509/MAX510's internal shift register on the rising

edge of the external serial clock. SCLK can be driven

at rates up to 12.5MHz.

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

10 ______________________________________________________________________________________

• • •

tLDW

SCLK

DIN

DOUT

LDAC

tDO

tDH

tDS

tCSH0 tCSS tCH

tCL tCSH1

tCSH2

tCLL

NOTE: TIMING SPECIFICATION tCLL IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.

Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)

Table 1. Serial-Interface Programming Commands

Mode 0, DOUT clocked out on falling edge of SCLK.

All DACs updated from input registers.

Mode 1, DOUT clocked out on rising edge of SCLK

(default). All DACs updated from respective input

registers.

“LDAC” Command, all DACs updated from respective

input registers.

12-Bit Serial Word

FunctionLDAC

D7 . . . . . . . . D0

XX X X X X X X X1

XX X X X X X X X0

No Operation (NOP), shifts data in shift register.XX X X X X X X X X Update all DACs from shift register.X8-Bit DAC DataX

Load input and DAC register A.

Load input and DAC register B.

Load input and DAC register C.

Load input and DAC register D.

8-Bit DAC Data

Load DAC A input register, DAC output unchanged.

Load DAC B input register, DAC output unchanged.

Load DAC C input register, DAC output unchanged.

Load DAC D input register, DAC output unchanged.

8-Bit DAC Data

Serial Input Data Format and Control Codes

The 12-bit serial input format shown in Figure 3 com-

prises two DAC address bits (A1, A0), two control bits

(C1, C0) and eight bits of data (D0...D7).

The 4-bit address/control code configures the DAC as

shown in Table 1.

Load Input Register, DAC Registers Unchanged

(Single Update Operation)

When performing a single update operation, A1 and A0

select the respective input register. At the rising edge

of CS, the selected input register is loaded with the cur-

rent shift-register data. All DAC outputs remain

unchanged. This preloads individual data in the input

Load Input and DAC Registers

This command directly loads the selected DAC register

at CS's rising edge. A1 and A0 set the DAC address.

Current shift-register data is placed in the selected

input and DAC registers.

For example, to load all four DAC registers simultaneously

with individual settings (DAC A = 1V, DAC B = 2V, DAC

C = 3V and DAC D = 4V), five commands are required.

First, perform four single input register update opera-

tions. Next, perform an “LDAC” command as a fifth

command. All DACs will be updated from their respec-

tive input registers at the rising edge of CS.

Update All DACs from Shift Registers

All four DAC registers are updated with shift-register

data. This command allows all DACs to be set to any

analog value within the reference range. This command

can be used to substitute CLR if code 00 hex is pro-

grammed, which clears all DACs.

No Operation (NOP)

The NOP command (no operation) allows data to be shift-

ed through the MAX509/MAX510 shift register without

affecting the input or DAC registers. This is useful in daisy

chaining (also see the

Daisy-Chaining Devices

section).

For this command, the data bits are "Don't Cares." As an

example, three MAX509/MAX510s are daisy-chained (A, B

and C), and DAC A and DAC C need to be updated. The

36-bit-wide command would consist of one 12-bit word for

device C, followed by an NOP instruction for device B and

a third 12-bit word with data for device A. At CS's rising

edge, only device B is not updated.

“LDAC” Command (Software)

All DAC registers are updated with the contents of their

respective input registers at CS's rising edge. With the

exception of using CS to execute, this performs the

same function as the asynchronous LDAC.

Set DOUT Phase – SCLK Rising (Mode 1, Default)

Mode 1 resets the serial output DOUT to transition at

SCLK's rising edge. This is the MAX509/MAX510’s

default setting after the supply voltage has been

applied.

The command also loads all DAC registers with the con-

tents of their respective input registers, and is identical to

the “LDAC” command.

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

______________________________________________________________________________________ 11

This is the first bit shifted in

A1 A0C1 C0 D7D6  ● ● ● D1 D0 DIN

DOUT

Control and

Address bits 8-bit DAC data

MSB LSB

Figure 3. Serial Input Format

(LDAC = H)

(LDAC = x)

(LDAC = H)

1 01 1 xxxxxxxx

D0D1D2D3D4D5D6D7C0

8-Bit DAC Data0 0x 0 D0

D1D2D3D4D5D6D7

xxx xxxxx0 0x 1 D0D1D2D3D4D5D6D7C0

1 00 x xxx xxx xx

D0D1D2D3D4D5D6D7C0

8-Bit Data0 1Address D0

D1D2D3D4D5D6D7

8-Bit Data1 1Address D0

D1D2D3D4D5D6D7

Set DOUT Phase – SCLK Falling (Mode 0)

This command resets DOUT to transition at SCLK's falling

edge. Once this command is issued, the phase of DOUT is

latched and will not change except on power-up or if the

specific command is issued that sets the phase to rising

edge.

The same command also updates all DAC registers with

the contents of their respective input registers, identical to

the “LDAC” command.

LDAC Operation (Hardware)

LDAC is typically used in 4-wire interfaces (Figure 7).

LDAC allows asynchronous hardware control of the DAC

outputs and is level-sensitive. With LDAC low, the DAC reg-

isters are transparent and any time an input register is

updated, the DAC output immediately follows.

Clear DACs with CLR

Strobing the CLR pin low causes an asynchronous clear of

input and DAC registers and sets all DAC outputs to zero.

Similar to the LDAC pin, CLR can be invoked at any time,

typically when the device is not selected (CS = H). When

the DAC data is all zeros, this function is equivalent to the

"Update all DACs from Shift Registers" command.

Digital Inputs and Outputs

Digital inputs and outputs are compatible with both TTL and

5V CMOS logic. The power-supply current (IDD) depends

on the input logic levels. Using CMOS logic to drive CS,

SCLK, DIN, CLR and LDAC turns off the internal level trans-

lators and minimizes supply currents.

Serial Data Output

DOUT is the output of the internal shift register. DOUT can be

programmed to clock out data on SCLK's falling edge (mode

0) or rising edge (mode 1). In mode 0, output data lags the

input data by 12.5 clock cycles, maintaining compatibility with

Microwire, SPI, and QSPI. In mode 1, output data lags the input

by 12 clock cycles. On power-up, DOUT defaults to mode 1

timing. DOUT never three-states; it always actively drives either

high or low and remains unchanged when CS is high.

Interfacing to the Microprocessor

The MAX509/MAX510 are Microwire, SPI, and QSPI compati-

ble. For SPI and QSPI, clear the CPOL and CPHA configura-

tion bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA

= 1 configuration can also be used if the DOUT output is

ignored.

The MAX509/MAX510 can interface with Intel's

80C5X/80C3X family in mode 0 if the SCLK clock polarity is

inverted. More universally, if a serial port is not available,

three lines from one of the parallel ports can be used for bit

manipulation.

Digital feedthrough at the voltage outputs is greatly mini-

mized by operating the serial clock only to update the regis-

ters. Also see the Clock Feedthrough photo in the

Typical

Operating Characteristics

section. The clock idle state is low.

Daisy-Chaining Devices

Any number of MAX509/MAX510s can be daisy-chained by

connecting the DOUT pin of one device to the DIN pin of the

following device in the chain. The NOP instruction (Table 1)

allows data to be passed from DIN to DOUT without chang-

ing the input or DAC registers of the passing device. A three-

wire interface updates daisy-chained or individual

MAX509/MAX510s simultaneously by bringing CS high.

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

12 ______________________________________________________________________________________

SCLK

DIN

DOUT



I/0

MICROWIRE

PORT

MAX509

MAX510

THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE

MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.

Figure 4. Connections for Microwire

DOUT

DIN

SCLK

MISO

MOSI

SCK

I/0

SPI

PORT

MAX509

MAX510

THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE

MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.

CPOL = 0, CPHA = 0

Figure 5. Connections for SPI

(LDAC = x)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

xxxxxxxx1 0 1 0

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

______________________________________________________________________________________ 13

SCLK

DIN

MAX509

MAX510

SCLK

DIN

MAX509

MAX510

SCLK

DIN

MAX509

MAX510

SCLK

DIN

MAX509

MAX510

DOUT DOUT DOUT

SCLK

DIN

SCLK

DIN

TO OTHER

SERIAL DEVICES

Figure 6. Daisy-chained or individual MAX509/MAX510s are simultaneously updated by bringing CS high. Only three wires are

required.

LDAC

SCLK

DIN

MAX509

MAX510

LDAC

SCLK

DIN

MAX509

MAX510

LDAC

SCLK

DIN

MAX509

MAX510

TO OTHER

SERIAL

DEVICES

DIN

SCLK

LDAC

CS1

CS2

CS3

Figure 7. Multiple MAX509/MAX510 DACs sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by

enabling individual CS.

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

14 ______________________________________________________________________________________

If multiple devices share a common DIN line, Figure 7's

configuration provides simultaneous update by strob-

ing LDAC low. CS1, CS2, CS3... are driven separately,

thus controlling which data are written to devices 1, 2, 3....

Analog Section

DAC Operation

The MAX509/MAX510 contain four matched voltage-

output DACs. The DACs are inverted R-2R ladder net-

works that convert 8-bit digital words into equivalent

analog output voltages in proportion to the applied ref-

erence voltages. Each DAC in the MAX509 has a sepa-

rate reference input, while the two reference inputs in

the MAX510 each share a pair of DACs. The two refer-

ence inputs permit different full-scale output voltage

ranges for each pair of DACs. A simplified diagram of

one of the four DACs is shown in Figure 8.

Reference Input

The MAX509/MAX510 can be used for multiplying

applications. The reference accepts both DC and AC

signals. The voltage at each REF input sets the full-

scale output voltage for its respective DAC(s). If the ref-

erence voltage is positive, both the MAX509 and

MAX510 can be operated from a single supply. If dual

supplies are used, the reference input can vary from

VSS to VDD, but is always referred to AGND. The input

impedance at REF is code dependent, with the lowest

value (16kΩfor the MAX509 and 8kΩfor the MAX510)

occurring when the input code is 55 hex or 0101 0101.

The maximum value, practically infinity, occurs when

the input code is 00 hex. Since the REF input imped-

ance is code dependent, the DAC's reference sources

must have a low output impedance (no more than 32Ω

for the MAX509 and 16Ωfor the MAX510) to maintain

output linearity. The REF input capacitance is also code

dependent: 15pF typical for the MAX509 and 30pF

typical for the MAX510.

The output voltage for any DAC can be represented by

a digitally programmable voltage source as:

VOUT = (NB x VREF) / 256

where NB is the numerical value of the DAC's binary

input code.

Output Buffer Amplifiers

All MAX509/MAX510 voltage outputs are internally

buffered by precision unity-gain followers that slew at

up to 1V/µs. The outputs can swing from VSS to VDD.

With a 0V to +4V (or +4V to 0V) output transition, the

amplifier outputs will settle to 1/2LSB in typically 6µs

when loaded with 10kΩin parallel with 100pF.

The buffer amplifiers are stable with any combination of

resistive loads ≥2kΩand capacitive loads ≤300pF.

__________Applications Information

Power Supply and

Reference Operating Ranges

The MAX509/MAX510 are fully specified to operate with

VDD = 5V ±10% and VSS = 0V to -5.5V. 8-bit perfor-

mance is guaranteed for both single- and dual-supply

operation. The zero-code output error is less than 14mV

when operating from a single +5V supply.

The DACs work well with reference voltages from VSS

to VDD. The reference voltage is referred to AGND.

The preferred power-up sequence is to apply VSS and

then VDD, but bringing up both supplies at the same

time is also acceptable. In either case, the voltage

applied to REF should not exceed VDD during power-

up or at any other time. If proper power sequencing is

not possible, connect an external Schottky diode

between VSS and AGND to ensure compliance with the

Absolute Maximum Ratings

. Do not apply signals to

the digital inputs before the device is fully powered up.

Power-Supply Bypassing

and Ground Management

In single-supply operation (AGND = DGND = VSS =

0V), AGND, DGND and VSS should be connected

together in a "star" ground at the chip. This ground

should then return to the highest quality ground avail-

able. Bypass VDD with a 0.1µF capacitor, located as

close to VDD and DGND as possible. In dual-supply

operation, bypass VSS to AGND with 0.1µF.

Careful PC board layout minimizes crosstalk among

DAC outputs, reference inputs, and digital inputs.

Figures 9 and 10 show suggested circuit board layouts

to minimize crosstalk.

RRR

2R 2R 2R 2R 2R

D0 D5 D6 D7

REF_

AGND

SHOWN FOR ALL 1 ON DAC

OUT_

Figure 8. DAC Simplified Circuit Diagram

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

______________________________________________________________________________________ 15

Unipolar-Output, 2-Quadrant Multiplication

In unipolar operation, the output voltages and the refer-

ence input(s) are the same polarity. Figures 11 and 12

show the MAX509/MAX510 unipolar configurations.

Both devices can be operated from a single supply if

the reference inputs are positive. If dual supplies are

used, the reference input can vary from VSS to VDD.

Table 2 shows the unipolar code.

Bipolar-Output, 2-Quadrant Multiplication

Bipolar-output, 2-quadrant multiplication is achieved by

offsetting AGND positively or negatively. Table 3 shows

the bipolar code.

AGND can be biased above DGND to provide an arbi-

trary nonzero output voltage for a 0 input code, as

shown in Figure 13. The output voltage at OUTA is:

VOUTA = VBIAS + (NB/256)(VIN),

Figure 9. Suggested MAX509 PC Board Layout for Minimizing

Crosstalk (Bottom View)

OUTC

OUTD

VDD

REFC

REFD

OUTB

OUTA

VSS

REFB

REFA

SYSTEM GND

AGND

Figure 10. Suggested MAX510 PC Board Layout for Minimizing

Crosstalk (Bottom View)

OUTC

OUTD

VDD

REFCD

OUTB

OUTA

VSS

REFAB

SYSTEM GND

AGND

DAC CONTENTS

MSB LSB

ANALOG

OUTPUT

1 1 1 1 1 1 1 1 255

+VREF (––––)

256

1 0 0 0 0 0 0 1 129

+VREF (––––)

256

1 0 0 0 0 0 0 0 128 VREF

+VREF (––––)= + ––––

256 2

0 1 1 1 1 1 1 1 127

+VREF (––––)

256

0 0 0 0 0 0 0 0 0V

0 0 0 0 0 0 0 1 1

+VREF (––––)

256

Table 2. Unipolar Code Table

Note: 1LSB = (VREF) (2-8) = +VREF (––––)

256

Table 3. Bipolar Code Table

1 0 0 0

DAC CONTENTS

0 0 0 1

MSB LSB

ANALOG

OUTPUT

1 1 1 1 1 1 1 1 127

+VREF (––––)

128

+VREF (––––)

128

1 0 0 0 0 0 0 0 0V

0 1 1 1 1 1 1 1 1

-VREF (––––)

128

0 0 0 0 0 0 0 0 128

-VREF (––––)= -VREF

128

0 0 0 0 0 0 0 1 127

-VREF (––––)

128

MAX509/MAX510

where NB represents the digital input word. Since

AGND is common to all four DACs, all outputs will be

offset by VBIAS in the same manner. Do not bias AGND

more than +1V above DGND, or more than 2.5V below

DGND.

Figures 14 and 15 illustrate the generation of negative

offsets with bipolar outputs. In these circuits, AGND is

biased negatively (up to -2.5V with respect to DGND) to

provide an arbitrary negative output voltage for a 0

input code. The output voltage at OUTA is:

OUTA = -(R2/R1)(2.5V) + (NB/256)(2.5V)(R2/R1+1)

where NB represents the digital input word. Since

AGND is common to all four DACs, all outputs will be

offset by VBIAS in the same manner. Table 3, with

VREF = 2.5V, shows the digital code vs. output voltage

for Figure 14 and 15's circuits with R1 = R2. The

ICL7612 op amp is chosen because its common-mode

range extends to both supply rails.

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

16 ______________________________________________________________________________________

Figure 11. MAX509 Unipolar Output Circuit

REFD

DAC A

DAC B

DAC C

DAC D

REFCREFBREFA

MAX509

OUTA

OUTB

OUTC

OUTD

SERIAL

INTERFACE

NOT SHOWN

REFERENCE INPUTS (VSS TO VDD)

VDD

+5V

517418

-5V (OR GND)

SS AGND DGND

Figure 12. MAX510 Unipolar Output Circuit

DAC A

DAC B

DAC C

DAC D

REFAB

MAX510

OUTA

OUTB

OUTC

OUTD

SERIAL

INTERFACE

NOT SHOWN

REFERENCE INPUTS (VSS TO VDD)

VDD

+5V

414

-5V (OR GND)

SS AGND DGND

REFCD 13

Figure 13. MAX509/MAX510 AGND Bias Circuits (Positive

Offset)

DAC A

MAX509

518

AGND

2OUTA

DGND

VSS

REFA VDD

VIN

VBIAS

+5V

-5V (OR GND)

DAC A

MAX510

414

AGND

2OUTA

DGND

VSS

REFAB VDD

VIN

VBIAS

+5V

-5V (OR GND)

SERIAL INTERFACE NOT SHOWN

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

______________________________________________________________________________________ 17

Figure 14. MAX509 AGND Bias Circuit (Negative Offset)

DAC A

DAC B

DAC C

DAC D

MAX509

OUTA

OUTB

OUTC

OUTD

SERIAL

INTERFACE

NOT SHOWN

REFERENCE INPUTS

VDD

+5V

5174 18

-5V

VSS AGND DGND

0.1µF

MAX873

+5V

0.1µF

R1

330k

0.1%

+5V

+2.5V

0.1µF

-5V

R2

330k

0.1%

ICL7611A

4-Quadrant Multiplication

Each DAC output may be configured for 4-quadrant

multiplication using Figure 16 and 17's circuit. One op

amp and two resistors are required per channel. With

R1 = R2: VOUT = VREF [2(NB/256)-1]

where NB represents the digital word in DAC register A.

The recommended value for resistors R1 and R2 is

330kΩ(±0.1%). Table 3 shows the digital code vs. out-

put voltage for Figure 16 and 17's circuit.

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

18 ______________________________________________________________________________________

Figure 15. MAX510 AGND Bias Circuit (Negative Offset)

DAC A

DAC B

DAC C

DAC D

MAX510

OUTA

OUTB

OUTC

OUTD

SERIAL

INTERFACE

NOT SHOWN

REFERENCE INPUTS

VDD

+5V

414

-5V

VSS AGND DGND

0.1µF

MAX873

+5V

0.1µF

R1

330k

0.1%

+5V

+2.5V

0.1µF

-5V

R2

330k

0.1%

ICL7611A

DAC A

DAC B

DAC C

DAC D

MAX509

OUTA

OUTB

OUTC

OUTD

SERIAL

INTERFACE

NOT SHOWN

REFERENCE INPUTS (VSS TO VDD)

VDD

+5V

517418

AGND OR -5V

VSS AGND DGND

*CONNECT ICL7612A PIN 8 TO AGND

+5V

0.1µF

-5V

VOUT

+5V

R1 R2

0.1µF

VOUT

0.1µF

-5V

0.1µF

ICL7612A*

Figure 16. MAX509 Bipolar Output Circuit

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

______________________________________________________________________________________ 19

DAC A

DAC B

DAC C

DAC D

MAX510

OUTA

OUTB

OUTC

OUTD

SERIAL

INTERFACE

NOT SHOWN

REFERENCE INPUTS

VDD

+5V

414

AGND OR -5V

VSS AGND DGND

*CONNECT ICL7612A PIN 8 TO AGND

+5V

0.1µF

-5V

VOUT

+5V

0.1µF

VOUT

0.1µF

-5V

0.1µF

ICL7612A*

Figure 17. MAX510 Bipolar Output Circuit

TOP VIEW

OUTC

OUTD

VDD

REFCD

REFAB

VSS

OUTA

OUTB

MAX510

SCLK

DIN

CLR

DOUT

LDAC

DGND

AGND

DIP/Wide SO

____Pin Configurations (continued)

MAX509

OUTA

DAC A

DAC B

DAC C

DAC D

REFAREFB

DAC

REG A

DECODE

CONTROL

INPUT

REG A

DAC

REG B

INPUT

REG B

DAC

REG C

INPUT

REG C

DAC

REG D

INPUT

REG D

12-BIT

SHIFT

SR

CONTROL

CS DIN SCLK REFC REFD

OUTB

OUTC

OUTD

DOUT LDAC

CLR VDD

DGND VSS

AGND

__Functional Diagrams (continued)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600

MAX509/MAX510

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

___________________Chip Topography_Ordering Information (continued)

PART TEMP. RANGE PIN-PACKAGE

MAX509AEPP -40°C to +85°C 20 Plastic DIP

MAX509BEPP -40°C to +85°C 20 Plastic DIP

MAX509AEWP -40°C to +85°C 20 Wide SO

±1

±1 1/2

±1

MAX509BEWP -40°C to +85°C 20 Wide SO ±1 1/2

MAX509AEAP -40°C to +85°C 20 SSOP ±1

MAX509BEAP -40°C to +85°C 20 SSOP ±1 1/2

MAX509AMJP -55°C to +125°C 20 CERDIP** ±1

MAX509BMJP -55°C to +125°C 20 CERDIP** ±1 1/2

MAX510ACPE 16 Plastic DIP ±1

MAX510BCPE 0°C to +70°C 16 Plastic DIP ±1 1/2

MAX510ACWE 0°C to +70°C 16 Wide SO ±1

MAX510BCWE 0°C to +70°C 16 Wide SO ±1 1/2

MAX510AEPE -40°C to +85°C 16 Plastic DIP ±1

MAX510BEPE -40°C to +85°C 16 Plastic DIP ±1 1/2

MAX510AEWE -40°C to +85°C 16 Wide SO ±1

MAX510BEWE -40°C to +85°C 16 Wide SO ±1 1/2

0°C to +70°C

MAX510AMJE -55°C to +125°C 16 CERDIP** ±1

MAX510BMJE -55°C to +125°C 16 CERDIP** ±1 1/2

**Contact factory for availability and processing to MIL-STD-883.

________________________________________________________Package Information

DIM



A

A1

B

C

D

E

e

H

L

MIN

0.068

0.002

0.010

0.005

0.278

0.205



0.301

0.022

0˚

MAX

0.078

0.008

0.015

0.009

0.289

0.212



0.311

0.037

8˚

MIN

1.73

0.05

0.25

0.13

7.07

5.20



7.65

0.55

0˚

MAX

1.99

0.21

0.38

0.22

7.33

5.38



7.90

0.95

8˚

INCHES MILLIMETERS

20-PIN PLASTIC

SHRINK

SMALL-OUTLINE

PACKAGE

A1 C

0.127mm

0.004in.

0.65 BSC0.0256 BSC

21-0003A

REFC

(REFCD)

SCLK

REFB

(REFAB)

AGND

VSS OUTC OUTDVDD

CLR

DOUTLDAC

0.121"

(3.07mm)

0.128"

(3.25mm)

DGND

REFA

(REFAB)

DIN

REFD

(REFCD)

OUTA OUTB

MAX509/MAX510

NOTE: LABELS IN ( ) ARE FOR MAX510 ONLY.

TRANSISTOR COUNT: 2235;

SUBSTRATE CONNECTED TO VDD.

TUE

(LSB)