This is information on a product in full production.
September 2014 DocID022412 Rev 8 1/55
VNQ7040AY-E
Quad channel high-side driver with MultiSense analog feedback
for automotive applications
Datasheet
-
production data
Features
•General
– Quad channel smart high-side driver with
MultiSense analog feedback
– LED Mode for channel 0 and 1
– Very low standby current
– Compatible with 3 V and 5 V CMOS
outputs
•MultiSense diagnostic functions
– Multiplexed analog feedback of:
Load current with high precision
proportional current mirror;
V
CC
supply voltage;
T
CHIP
device temperature
– Overload and short to ground (power
limitation) indication
– Therm al sh utdow n indica tion
– OFF-state open load detection
– Output short to V
CC
detection
– Sense enable/disable
•Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Configurable latch-off on overtemperature
or power limitation with dedicated fault
reset pi n
– Loss of ground and loss of V
CC
– Reverse battery through self turn-on
– Electros tatic disc har ge protecti on
Applications
•All types of Automotive resistive, inductive and
capacitive loads
•Specially intended for Automotive Turn
Indicators (up to P27W or SAE1156 and R5W
paralleled or LED Rear Combinations)
Description
The VNQ7040AY-E is a quad channel high-side
driver manufactured using the latest ST
proprietary VIPower
®
technology and housed in
PowerSSO-36 package. The device is designed
to drive 12 V automotive grounded loads through
a 3 V and 5 V CMOS-compatible interface, and to
provide protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions such as high precision proportional load
current sense, supply voltage feedback and chip
temperature sense, in addition to the detection of
overload and short circuit to ground, short to V
CC
and OFF-state open-load.
The device features a dedicated LED Mode.
Max transient supply voltage V
CC
41 V
Operati ng vol tage range V
CC
4 to 28 V
Typ. on-state resistance (per ch) R
ON
40 mΩ
Current lim itation (typ) I
LIMH
34 A
Standby current (max) I
STBY
0.5 µA
PowerSSO-36
www.st.com
Contents VNQ7040AY-E
2/55 DocID022412 Rev 8
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Elect rical char acteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3.1 General electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.2 Bulb mode (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Electrical characteristics curves - Bulb Mode . . . . . . . . . . . . . . . . . . . . . . 21
2.4.1 LED Mode (Channel 0 and 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 Electrical characteristics curves - LED mode . . . . . . . . . . . . . . . . . . . . . . 28
2.5.1 Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.2 Immunity to electrical transient disturbances on VCC (ISO 7637-2) . . . 34
3 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1 Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3 Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4 Negati v e voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 Prot e ction against reverse battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 Immunit y against transient electrical disturbances . . . . . . . . . . . . . . . . . . 37
4.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4 Multisense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4.1 Principle of Multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.2 T
CASE
and V
CC
monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4.3 Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 43
4.5 Maximum demagnetization energy (V
CC
= 16 V) . . . . . . . . . . . . . . . . . . . 44
5 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DocID022412 Rev 8 3/55
VNQ7040AY-E Contents
3
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1 ECOPACK
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.2 PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
List of tables VNQ7040AY-E
4/55 DocID022412 Rev 8
List of tables
Table 1. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Logic Inputs (7 V < V
CC
<28V; -40°C<T
j
< 150 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Protections (7 V < V
CC
<18V; -40°C<T
j
< 150 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. MultiSense (7 V < V
CC
<18V; -40°C<T
j
< 150 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power section in Bulb Mode (7 V < V
CC
<28V; -40°C<T
j
< 150 °C, unless otherwise
specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Switching in Bulb Mode (V
CC
=13V; -40°C<T
j
< 150 °C, unless otherwise specified). . 17
Table 11. MultiSense in Bulb Mode (7 V < V
CC
<18V; -40°C<T
j
< 150 °C). . . . . . . . . . . . . . . . . . 18
Table 12. Switching in LED Mode (V
CC
=13V; -40°C<T
j
< 150 °C, unless otherwise specified) . . 24
Table 13. Power section in LED Mode (7 V < V
CC
<28V; -40°C<T
j
< 150 °C, unless otherwise
specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. MultiSense in LED Mode (7 V < V
CC
<18V; -40°C<T
j
< 150 °C) . . . . . . . . . . . . . . . . . . 25
Table 15. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. MultiSense multiplexer addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 17. Bulb/LED Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 18. Electrical transient requirements (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19. Electrical transient requirements (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. Electrical transient requirements (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. ISO 7637-2 - electrical transient conduction along supply line. . . . . . . . . . . . . . . . . . . . . . 37
Table 22. MultiSense pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 23. PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 24. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 25. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 26. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DocID022412 Rev 8 5/55
VNQ7040AY-E List of figures
6
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Bulb Mode - I
OUT
/I
SENSE
vers us I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. Bulb Mode - current sense precision vs. I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. I
GND(ON)
vs. I
out
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Logic Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Logic Input low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Logic Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. FaultRST Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. On-state resistance vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. On-state resistance vs. V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19. Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. Won vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 21. Woff vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 22. I
LIMH
vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 23. OFF-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 24. V
sense
clamp vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 25. V
senseh
vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 26. LED Mode - I
OUT
/I
SENSE
versus I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 27. LED Mode - current sense precision vs. I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 28. On-state resistance vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 29. On-state resistance vs. V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 30. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 31. Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 32. Won vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 33. Woff vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 34. I
LIMH
vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 35. Switching times and Pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 36. MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 37. Multisense timings (chip temperature and VCC sense mode) . . . . . . . . . . . . . . . . . . . . . . 31
Figure 38. T
DSKON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 39. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 40. Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 41. Multisense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 42. Multisense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 43. Analogue HSD – open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 44. Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 45. GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 46. Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 47. PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 48. Rthj-amb vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . . 46
List of figures VNQ7040AY-E
6/55 DocID022412 Rev 8
Figure 49. PowerSSO-36 thermal impedance junction ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 50. Thermal fitting model of a HSD in PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 51. PowerSSO-36 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 52. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 53. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DocID022412 Rev 8 7/55
VNQ7040AY-E Block diagram and pin description
54
1 Block diagram and pin description
Figure 1. Block diagram
Table 1. Pin functions
Name Function
V
CC
Battery connection.
OUTPUT
0,1,2,3
Power output.
GND Ground connection.
INPUT
0,1,2,3
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V
CMOS outputs. They control output switch state.
MultiSense Multiplexed analog sense output pin; it delivers a current proportional to
the selected diagnostic: load current, supply voltage or chip temperature.
SEn Active hig h comp ati ble wi th 3 V and 5 V CMOS outputs pin; it ena ble s the
MultiSense diagnostic pin
LED
0,1
Active high compatible with 3 V and 5 V CMOS outputs pin; they enable
the LED mode on logic high level (see Table 15: Truth t abl e).
SEL
0,1,2
Active high compatible with 3 V and 5 V CMOS outputs pin; they address
the MultiSense multiplexer (see Table 15: Truth table).
FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches
the output in case of fault; If kept low, sets the outputs in auto-restart
mode.
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Block diagram and pin description VNQ7040AY-E
8/55 DocID022412 Rev 8
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin MultiSense N.C. Output Input SEn, SELx, LEDx,
FaultRST
Floating Not allowed X
(1)
1. X: do not care.
XX X
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DocID022412 Rev 8 9/55
VNQ7040AY-E Electrical specification
54
2 Electrical specification
Fig ure 3. Current and voltage conven tions
1. V
Fn
= V
OUTn
- V
CC
2.1 Absolute maximum ratings
S tressing the device above the rating listed in Table 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions in table below for extended periods may affect device reliability.
V
Fn
I
S
I
GND
V
CC
V
CC
OUTPUT
0,1,2,3
I
OUT
I
SENSE
I
FR
V
SEL
FaultRST
V
FR
V
SENSE
V
OUT
MultiSense
INPUT
0,1,2,3
SEn
SEL
0,1,2
V
IN
I
SEn
I
SEL
I
IN
LED
0,1
I
LED
V
SEn
V
LED
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
DC supply voltage 38
V
-V
CC
Reverse DC sup ply voltage 16
V
CCPK
Maximu m transient su pply volt age (ISO7637-2 :2004 Pulse 5b
level IV clamped to 40 V; R
L
=4Ω)40
V
CCJS
Maximum jump start voltage for single pulse short circuit
protection 28
-I
GND
DC reverse ground pin current 200 mA
I
OUT
OUTPUT
0,1,2,3
DC output current Internally limited
A-I
OUT_0,1
OUTPUT
0,1
Reverse DC output current 10
-I
OUT_2,3
OUTPUT
2,3
Reverse DC output current 10
I
IN
INPUT
0,1,2,3
DC input current
-1 to 10 mA
I
LED
LED
0,1
DC input current
I
SEn
SEn DC input current
I
SEL
SEL
0,1,2
DC input current
I
FR
FaultRST DC input current -1 to 10 mA
Electrical specification VNQ7040AY-E
10/55 DocID022412 Rev 8
2.2 Thermal data
V
FR
FaultRST DC input volt ag e 7.5 V
I
SENSE
MultiSense pin DC output current (V
GND
=V
CC
and
V
SENSE
<0V) -10 mA
MultiSense pin DC output current in reverse (V
CC
< 0 V) 20 mA
E
MAX
Maximum switching energy (single pulse)
(T
DEMAG
=0.4ms; T
jstart
=150°C) 36 mJ
V
ESD
Electrostatic discharge (JEDEC 22A-11 4F)
– INPUT
0,1,2,3
– MultiSense
–LED
0,1
, SEn, SEL
0,1,2
, FaultRST
– OUTPUT
0,1,2,3
–V
CC
4000
2000
4000
4000
4000
V
V
V
V
V
V
ESD
Charge device model (CDM-AEC-Q100-011) 750 V
T
j
Junction operating temperature -40 to 150 °C
T
stg
Storage temperature -55 to 150
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data
Symbol Parameter Typ. value Unit
R
thj-board
Thermal resist a nce jun ction -boa rd (JEDEC JESD 51-5 / 51-8)
(1)(2)
1. One channel ON.
2. Device mounted on four-layers 2s2p PCB
4.9
°C/WR
thj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)
(1)(3)
3. Device mounted on two-layers 2s0p PC B with 2 cm
2
heatsink copper trace
52.5
R
thj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-7)
(1)(2)
18
DocID022412 Rev 8 11/55
VNQ7040AY-E Electrical specification
54
2.3 Electrical characteristics
7V<V
CC
<28V; -40°C<T
j
< 150 °C, unl es s othe rwis e spec if ied .
All typical values refer to V
CC
=13V; T
j
= 25 °C, unless otherwise specified.
2.3.1 General electrical specification
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC
Operating supply voltage 4 13 28
V
V
USD
Undervoltage shutdown 4
V
USDReset
Undervoltage shutdown
reset 5
V
USDhyst
Undervoltage shutdown
hysteresis 0.3
V
clamp
Clamp voltage I
S
=20mA; 25°C<T
j
< 150 °C 41 46 52 V
I
S
= 20 mA; T
j
=-40°C 38 V
I
STBY
Supply current in standby at
V
CC
=13V
(1)
1. PowerMOS leakage included.
V
CC
=13V;
V
INx
=V
OUTx
=V
FR
=V
SEn
=0V;
V
SEL0,1,2
=0V; V
LED0,1
=0V;
T
j
=25°C
0.5 µA
V
CC
=13V;
V
INx
=V
OUTx
=V
FR
=V
SEn
=0V;
V
SEL0,1,2
=0V; V
LED0,1
=0V;
T
j
=85°C
(2)
0.5 µA
V
CC
=13V;
V
INx
=V
OUTx
=V
FR
=V
SEn
=0V;
V
SEL0,1,2
=0V; V
LED0,1
=0V;
T
j
=125°C;
3µA
t
D_STBY
Standby mode blanking time
V
CC
=13V;
V
INx
=V
OUTx
=V
FR
=0V;
V
SEL0,1,2
=0V; V
LED0,1
=0V;
V
SEn
=5V to 0V
60 300 550 µs
I
S(ON)
Supply cu rrent V
CC
=13V;
V
SEn
=V
FR
=V
SEL0,1
=0V;
V
INx
=5V; I
OUT0,1,2,3
=0A; 10 16 mA
I
GND(ON)
Control st a ge current
consumption in ON st ate. All
channels active.
V
CC
=13V; V
SEn
=5V;
V
FR
=V
SEL0,1
=0V; V
INx
=5V;
I
OUT0,1,2,3
=2.5A 18.5 mA
I
L(off)
Off-state output current at
V
CC
=13V
(1)
V
INx
=V
OUTx
=0V; V
CC
=13V;
T
j
=25°C 00.010.5µA
V
INx
=V
OUTx
=0V; V
CC
=13V;
T
j
=125°C 03
V
F
Output - V
CC
diode
voltage
(3)
I
OUT
=-2.5A; T
j
= 150 °C 0.7 V
Electrical specification VNQ7040AY-E
12/55 DocID022412 Rev 8
2. Parameter specified by design; not subject to production test.
3. For each channel.
Table 6. Logic Inputs (7 V < V
CC
< 28 V; -40 °C < T
j
<150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
INPUT
0,1,2,3
characteristics
V
IL
Input low lev el volt a ge 0.9 V
I
IL
Low level input current V
IN
=0.9V 1 µA
V
IH
Input high level voltage 2.1 V
I
IH
High level inpu t current V
IN
=2.1V 10 µA
V
I(hyst)
Input hyste r es is voltage 0.2 V
V
ICL
Input clam p voltage I
IN
=1mA 5.3 7.2 V
I
IN
=-1mA -0.7
FaultRST characteristics
V
FRL
Input low lev el volt a ge 0.9 V
I
FRL
Low level input current V
IN
=0.9V 1 µA
V
FRH
Input high level voltage 2.1 V
I
FRH
High level inpu t current V
IN
=2.1V 10 µA
V
FR(hyst)
Input hyste r es is voltage 0.2 V
V
FRCL
Input clam p voltage I
IN
=1mA 5.3 7.5 V
I
IN
=-1mA -0.7
SEL
0,1,2
characteristics (7 V < V
CC
<18V)
V
SELL
Input low lev el volt a ge 0.9 V
I
SELL
Low level input current V
IN
=0.9V 1 µA
V
SELH
Input high level voltage 2.1 V
I
SELH
High level inpu t current V
IN
=2.1V 10 µA
V
SEL(hyst)
Input hyste r es is voltage 0.2 V
V
SELCL
Input clam p voltage I
IN
=1mA 5.3 7.2 V
I
IN
=-1mA -0.7
LED
0,1
characteristics (7 V < V
CC
<18V)
V
LEDL
Input low lev el volt a ge 0.9 V
I
LEDL
Low level input current V
IN
=0.9V 1 µA
V
LEDH
Input high level voltage 2.1 V
I
LEDH
High level inpu t current V
IN
=2.1V 10 µA
V
LED(hyst)
Input hyste r es is voltage 0.2 V
DocID022412 Rev 8 13/55
VNQ7040AY-E Electrical specification
54
V
LEDCL
Input clam p voltage I
IN
=1mA 5.3 7.2 V
I
IN
=-1mA -0.7
SEn characteristics ( 7 V < V
CC
<18V)
V
SEnL
Input low lev el volt a ge 0.9 V
I
SEnL
Low level input current V
IN
=0.9V 1 µA
V
SEnH
Input high level voltage 2.1 V
I
SEnH
High level inpu t current V
IN
=2.1V 10 µA
V
SEn(hyst)
Input hyste r es is voltage 0.2 V
V
SEnCL
Input clam p voltage I
IN
=1mA 5.3 7.2 V
I
IN
=-1mA -0.7
Table 7. Protections (7 V < V
CC
< 18 V; -40 °C < T
j
< 150 °C)
Symbol Pa ramet er Test conditions Min. Typ. Max. Unit
T
TSD
Shutdown temperature 150 175 200
°C
T
R
Reset tempera ture
(1)
1. Parameter guaranteed by design and characterization; not subject to production test.
T
RS
+1 T
RS
+5
T
RS
Thermal reset of fault
diagnostic indication V
FR
=0V; V
SEn
=5 V 135
T
HYST
Thermal hys teresis
(T
TSD
-T
R
)
(1)
5
ΔT
J_SD
Dynamic temperature 60 K
t
LATCH_RST
Fault res et ti me for output
unlatch
(1)
V
FR
=5Vto0V;
V
SEn
=5V; V
INx
=5V;
V
SEL0,1,2
=0V 31020µs
V
DEMAG
Turn-off output voltage
clamp
I
OUT
=2A; L=6mH;
T
j
=-40°C V
CC
-38 V
I
OUT
=2A; L=6mH;
T
j
=25°Cto150°C V
CC
-41 V
CC
-46 V
CC
-52 V
V
ON
Output voltage drop
limitation I
OUT
=0.25A 20 mV
Table 6. Logic Inputs (7 V < V
CC
< 28 V; -40 °C < T
j
< 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specification VNQ7040AY-E
14/55 DocID022412 Rev 8
Table 8. MultiSense (7 V < V
CC
< 18 V; -40 °C < T
j
<150°C)
Symbol Parameter Test conditions Min. Typ. Ma x. Unit
V
SENSE_CL
Multi Sen se cl am p
voltage V
SEn
=0V; I
SENSE
=1mA -17 -12 V
V
SEn
=0V; I
SENSE
=-1mA -0.7 V
Cur rent Sense charac teristi cs
I
SENSE
0
MultiS en se lea ka ge
current
MultiSense disabled: V
SEn
=0V; 0 0.5
µA
MultiSense disabled:
-1 V < V
SENSE
<5V
(1)
-0.5 0.5
MultiSense enabled: V
SEn
=5V
All channels ON; I
OUTX
=0A; Ch
X
diagnostic selected;
–E.G. Ch
0
:
V
IN0
=5V; V
IN1,2,3
=5V;
V
SEL0,1,2
=0V; I
OUT0
= 0 A;
I
OUT1,2,3
=2.5A
02
MultiSense enabled: V
SEn
=5V
Ch
X
OFF; Ch
X
diagnostic selected:
–E.G. Ch
0
:
V
IN0
=0V; V
IN1,2,3
=5V;
V
SEL0,1,2
=0V; I
OUT0
= 0 A;
I
OUT1,2,3
=2.5A
02
V
OUT_MSD(1)
Output Voltage for
Multi Sen se shutdo w n
V
SEn
=5V; R
SENSE
=2.7kΩ
– E.g. Ch
0
:
V
IN0
=5V; V
SEL0,1,2
=0V;
I
OUT0
=2.5A
5V
V
SENSE_SAT
Multisense saturation
voltage
V
CC
=7V; R
SENSE
= 2.7 K;
V
SEn
=5V; V
IN0
=5V; V
SEL0,1,2
=0V;
I
OUT0
= 4.5 A; T
j
=150°C 5V
I
SENSE_SAT(1)
CS saturation current V
CC
=7V; V
SENSE
=4V; V
IN0
=5V;
V
SEn
=5V; V
SEL0,1,2
=0V; T
j
= 150°C 4mA
I
OUT_SAT_BULB(1)
Output saturation
current in BUL B mode V
CC
=7V; V
SENSE
=4V; V
IN0
=5V;
V
SEn
=5V; V
SEL0,1,2
=0V; T
j
= 150°C 8A
I
OUT_SAT_LED(1)
Output saturation
current in LED mode V
CC
=7V; V
SENSE
=4V; V
IN0
=5V;
V
SEn
=5V; V
SEL0,1,2
=0V; T
j
= 150°C 2.3 A
OFF-state diagnostic
V
OL
OFF state open load
volt a ge det ection
threshold
V
SEn
=5V; Ch
X
OFF; Ch
X
diagnostic
selected
– E.G: Ch
0
V
IN0
=0V; V
SEL0,1,2
=0V
234V
I
L(off2)
OFF state output sink
current V
IN
=0V; V
OUT
=V
OL
;
T
j
= -40°C to 125°C -100 -15 µA
DocID022412 Rev 8 15/55
VNQ7040AY-E Electrical specification
54
t
DSTKON
OFF state diagnostic
delay time from falling
edge of INPUT (see
Figure 35)
V
SEn
=5V; Ch
X
ON to OFF transition;
Ch
X
diagnostic s elect ed
– E.G: Ch
0
V
IN0
= 5 V to 0 V; V
SEL0,1,2
=0V;
V
OUT0
>4V
100 350 700 µs
t
D_OL_V
Settling time for valid
OFF-state open load
diagnostic indication
from rising edge of SEn
V
INx
=0V; V
FR
=0V; V
SEL0,1,2
=0V;
V
OUT0
=4V; V
SEn
=0V to 5V 60 µs
t
D_VOL
OFF state diagnostic
delay time from rising
edge of V
OUT
V
SEn
=5V; Ch
X
OFF;
Ch
X
diagnostic s elect ed
– E.G: Ch
0
V
IN0
=0V; V
SEL0,1,2
=0V;
V
OUT0
=0V to 4V
530µs
Chip temperature analog feedback
V
SENSE_TC
MultiS en se out put
volt a ge prop orti ona l to
chip temp erature
V
SEn
=5V; V
SEL0
=0V; V
SEL1
=0V;
V
SEL2
=5V; R
SENSE
=1KΩ;
V
INx
=0V; T
j
=-40°C 2.325 2.41 2.495 V
V
SEn
=5V; V
SEL0
=0V; V
SEL1
=0V;
V
SEL2
=5V; R
SENSE
=1KΩ;
V
INx
=0V; T
j
=25°C 1.985 2.07 2.155 V
V
SEn
=5V; V
SEL0
=0V; V
SEL1
=0V;
V
SEL2
=5V; R
SENSE
=1KΩ;
V
INx
=0V; T
j
=125°C 1.435 1.52 1.605 V
dV
SENSE_TC
/dT
(2)
Tempera ture co ef ficient T
j
= -40°C to 150°C -5.5 mV/K
Transfer function V
SENSE_TC
(T) = V
SENSE_TC
(T
0
)+dV
SENSE_TC
/dT * (T-T
0
)
V
CC
supply voltage analog feedback
V
SENSE_VCC
MultiS en se out put
volt a ge prop orti ona l to
V
CC
suppl y vol t age
V
CC
=13V; V
SEn
=5V;
V
SEL0,1,2
=5V; V
INx
=0V;
R
SENSE
=1KΩ
3.16 3.23 3.3 V
Transfer function
(2)
V
SENSE_VCC
=V
CC
/4
Fault diagnostic feedback (see Table 15)
V
SENSEH
MultiS en se out put
volt a ge in faul t
condition
(
V
CC
=13V; R
SENSE
=1kΩ56.6V
I
SENSEH
MultiS en se out put
current in fault condition V
CC
=13V; V
SENSE
= 5 V 7 20 30 mA
MultiSense timings (Chip Temperature Sense mode - see Figure 37)
t
DSENSE3H
V
SENSE_TC
settling time
from rising edge of SEn
V
SEn
= 0 V to 5 V;
V
SEL0
=V
SEL1
=0V; V
SEL2
=5V;
R
SENSE
=1kΩ
60 µs
Table 8. MultiSense (7 V < V
CC
< 18 V; -40 °C < T
j
< 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Ma x. Unit
Electrical specification VNQ7040AY-E
16/55 DocID022412 Rev 8
t
DSENSE3L
V
SENSE_TC
disable
delay time from falling
edge of SEn
V
SEn
= 5 V to 0 V;
V
SEL0
=V
SEL1
=0V; V
SEL2
=5V;
R
SENSE
=1kΩ
20 µs
MultiSense timings (V
CC
Voltage Sense mode - see Figure 37)
t
DSENSE4H
V
SENSE_VCC
settling
time from ris ing edge of
SEn
V
SEn
= 0 V to 5 V;
V
SEL0
=V
SEL1
=V
SEL2
=5V;
R
SENSE
=1kΩ
60 µs
t
DSENSE4L
V
SENSE_VCC
disable
delay time from falling
edge of SEn
V
SEn
= 5 V to 0 V;
V
SEL0
=V
SEL1
=V
SEL2
=5V;
R
SENSE
=1kΩ
20 µs
MultiSense Timings (Multiplexer transition times)
(3)
t
D_XtoY
MultiSense
transition
delay from Ch
X
to Ch
Y
V
IN2
=5V; V
IN3
=5V;
V
SEn
=5V; V
SEL0
= 0 V to 5 V;
V
SEL1
=5V; V
SEL2
=0V; I
OUT2
= 0 A;
I
OUT3
= 2.5 A; R
SENSE
=1kΩ
20 µs
t
D_CStoTC
MultiSense
transition
delay from curr ent
sense to T
C
sense
V
IN0
=5V; V
SEn
=5V; V
SEL0
=0V;
V
SEL1
=V
SEL2
= 0 V to 5 V;
I
OUT0
=1.25A; R
SENSE
=1kΩ
60 µs
t
D_TCtoCS
MultiSense
transition
delay fromT
C
sense to
current sense
V
IN0
=5V; V
SEn
=5V; V
SEL0
=0V;
V
SEL1
=V
SEL2
= 5 V to 0 V;
I
OUT0
=1.25A; R
SENSE
=1kΩ
20 µs
t
D_CStoVCC
MultiSense
transition
delay from curr ent
sense to V
CC
sense
V
IN2
=5V; V
SEn
=5V; V
SEL0
=5V;
V
SEL1
=5V; V
SEL2
= 0 V to 5 V;
I
OUT2
=1.25A; R
SENSE
=1kΩ
60 µs
t
D_VCCtoCS
MultiSense
transition
delay from V
CC
sense
to current sens e
V
IN2
=5V; V
SEn
=5V; V
SEL1
=5V;
V
SEL0
=V
SEL2
= 5 V to 0 V;
I
OUT2
=1.25A; R
SENSE
=1kΩ
20 µs
t
D_TCtoVCC
MultiSense
transition
delay from T
C
sense to
V
CC
sense
V
SEn
=5V; V
SEL1,2
=5V;
V
SEL0
= 0 V to 5 V; R
SENSE
=1kΩ20 µs
t
D_VCCtoTC
MultiSense
transition
delay from V
CC
sense
to T
C
sense
V
SEn
=5V; V
SEL1,2
=5V;
V
SEL0
= 5 V to 0 V; R
SENSE
=1kΩ20 µs
t
D_CStoVSENSEH
MultiSense
transition
delay from stable
current sense on Ch
X
to
V
SENSEH
on Ch
Y
V
IN0
=5V; V
IN1
=0V; V
OUT1
>4V;
V
SEn
=5V; V
SEL2
=0V; V
SEL1
=0V;
V
SEL0
= 0 V to 5 V; I
OUT0
= 2.5 A;
R
SENSE
=1kΩ
60 µs
1. Parameter guaranteed by design and characterization; not subject to production test.
2. V
CC
sensing and T
C
sensing are referred to GND potential.
3. Transiti on delay ar e measured up to +/- 10% o f final con ditions.
Table 8. MultiSense (7 V < V
CC
< 18 V; -40 °C < T
j
< 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Ma x. Unit
DocID022412 Rev 8 17/55
VNQ7040AY-E Electrical specification
54
2.3.2 Bulb mode (default)
Table 9. Power section in Bulb Mode (7 V < V
CC
< 28 V; -40 °C < T
j
< 150 °C, unless
otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
R
ON_0,1,2,3_BULB
On-state resistance in
Bulb Mode Ch0, Ch1,
Ch2 and Ch3
I
OUT
= 2.5 A; T
j
= 25°C 40
mΩ
I
OUT
= 2.5 A; T
j
= 150°C 80
I
OUT
= 2.5 A; V
CC
=4V;
T
j
=25°C 60
R
ON_REV_0,1,2,3
On-state resistance in
Reverse Battery Ch0,
Ch1, Ch2 and Ch3
V
CC
=-13V;
I
OUT
=-2.5A; T
j
= 25°C 40 mΩ
I
LIMH_0,1,2,3_BULB(1)
1. Parameter guaranteed by an indirect test sequence.
DC short c ircui t c urre nt
in Bulb Mode Ch0,
Ch1, Ch2 and Ch3
V
CC
= 13 V 24 34 48
A
4V<V
CC
<18V
(2)
2. Parameter guaranteed by design and characterization; not subject to production test.
48
I
LIML_0,1,2,3_BULB
Short circuit current
during thermal cycling
in Bulb Mode Ch0,
Ch1, Ch2 and Ch3
V
CC
=13V;
T
R
<T
j
<T
TSD
9
V
ON_0,1,2,3_BULB
Output voltage drop
limitation in Bulb Mode
Ch0, Ch1, Ch2 and
Ch3
I
OUT
=0.25A 20 mV
Table 10. Switching in Bulb Mode (V
CC
= 13 V; -40 °C < T
j
< 150 °C, unl ess other w ise
specified)
Symbol Parameter Test
conditions Min. Typ. Max. Unit
Channel 0, 1, 2 and 3
t
d(on)_0,1,2,3(1)
Turn-on del ay time at
T
j
=25°C R
L
=5.2Ω10 60 120 µs
t
d(off)_0,1,2,3(1)
Turn-off delay time at
T
j
=25°C R
L
=5.2Ω10 50 100
(dV
OUT
/dt)
on_0,1,2,3(1)
Turn-on vo lt ag e slo pe at
T
j
=25°C R
L
=5.2Ω0.1 0.5 0.7 V/µs
(dV
OUT
/dt)
off_0,1,2,3(1)
Turn-off voltage slope at
T
j
=25°C R
L
=5.2Ω0.1 0.5 0.7
W
ON_0,1,2,3
Switching energy losses at
turn-on (t
won
)R
L
=5.2Ω—0.20.52
(2)
mJ
Electrical specification VNQ7040AY-E
18/55 DocID022412 Rev 8
W
OFF_0,1,2,3
Switching energy losses at
turn-off (t
woff
)R
L
=5.2Ω—0.20.5
(2)
mJ
t
SKEW_0,1,2,3(1)
Differential pulse skew
(t
PHL
- t
PLH
)R
L
=5.2Ω-65 -15 35 µs
1. See Figure 35: Switching times and Pulse skew.
2. Parameter guaranteed by design and characterization, not subject to production test.
Table 11. MultiSense in Bulb Mode (7 V < V
CC
< 18 V; -40 °C < T
j
<150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Current sense characteristics
Channe l 0, 1, 2 and 3
K
OL_CH0,1_B
I
OUT
/I
SENSE
I
OUT
= 10 mA;
V
SENSE
= 0.5 V; V
SEn
=5V 430
K
OL_CH2,3_B
I
OUT
/I
SENSE
I
OUT
= 10 mA;
V
SENSE
= 0.5 V; V
SEn
=5V 430
dK
cal
/K
cal(1)(2)
Current sense ratio drift at
calibration point
I
CAL
=30mA;
I
OUT
= 10 mA to 50 mA;
V
SENSE
= 0.5 V; V
SEn
=5V -35 35 %
K
LED_CH0,1_B
I
OUT
/I
SENSE
I
OUT
=0.05A;
V
SENSE
= 0.5 V; V
SEn
=5V 720 1440 2160
K
LED_CH2,3_B
I
OUT
/I
SENSE
I
OUT
=0.05A;
V
SENSE
= 0.5 V; V
SEn
=5V 720 1440 2160
K
0_CH0,1_B
I
OUT
/I
SENSE
I
OUT
=0.25A;
V
SENSE
= 0.5 V; V
SEn
=5V 930 1550 2170
K
0_CH2,3_B
I
OUT
/I
SENSE
I
OUT
=0.25A;
V
SENSE
= 0.5 V; V
SEn
=5V 930 1550 2170
dK
0
/K
0(1)(2)
Current sense ratio drift I
OUT
=0.25A;
V
SENSE
= 0.5 V; V
SEn
=5V -20 20 %
K
1_CH0,1_B
I
OUT
/I
SENSE
I
OUT
= 0.5 A; V
SENSE
=4V;
V
SEn
=5V 1110 1590 2070
K
1_CH2,3_B
I
OUT
/I
SENSE
I
OUT
= 0.5 A; V
SENSE
=4V;
V
SEn
=5V 1085 1550 2015
dK
1
/K
1(1)(2)
Current sense ratio drift I
OUT
= 0 .5 A; V
SENSE
=4V;
V
SEn
=5V -15 15 %
K
2_CH0,1_B
I
OUT
/I
SENSE
I
OUT
=2A; V
SENSE
=4V;
V
SEn
=5V 1160 1450 1740
K
2_CH2,3_B
I
OUT
/I
SENSE
I
OUT
=2A; V
SENSE
=4V;
V
SEn
=5V 1130 1410 1690
Table 10. Switching in Bulb Mode (V
CC
= 13 V; -40 °C < T
j
< 150 °C, unl ess other w ise
specified) (continued)
Symbol Parameter Test
conditions Min. Typ. Max. Unit
DocID022412 Rev 8 19/55
VNQ7040AY-E Electrical specification
54
dK
2
/K
2(1)(2)
Current sense ratio drift I
OUT
=2A; V
SENSE
=4V;
V
SEn
=5V -10 10 %
K
3_CH0,1_B
I
OUT
/I
SENSE
I
OUT
=6A; V
SENSE
=4V;
V
SEn
=5V 1295 1440 1585
K
3_CH2,3_B
I
OUT
/I
SENSE
I
OUT
=6A; V
SENSE
=4V;
V
SEn
=5V 1260 1400 1540
dK
3
/K
3(1)(2)
Current sense ratio drift I
OUT
=6A; V
SENSE
=4V;
V
SEn
=5V -5 5 %
MultiSense timings (Current Sense mode see Figure 36)
Channe l 0, 1, 2 and 3
t
DSENSE1H
Current sense settling time
from rising edge of SEn
V
IN
=5V; V
SEn
= 0 V to
5V;
R
SENSE
=1kΩ; R
L
=5.2Ω
60 µs
t
DSENSE1L
Current se nse disable
delay tim e from falling edge
of SEn
V
SEn
= 5 V to 0 V;
R
SENSE
=1kΩ; R
L
=5.2Ω520µs
t
DSENSE2H
Current sense settling time
from rising edge of INPUT
V
IN
= 0 V to 5 V;
V
SEn
=5V;
R
SENSE
=1kΩ; R
L
=5.2Ω
100 250 µs
Δt
DSENSE2H
Current sense settling time
from rising edge of I
OUT
(dyna mi c resp onse to a
step change of I
OUT
)
V
IN
=5V; V
SEn
=5V;
R
SENSE
=1kΩ; R
L
=5.2Ω100 µs
t
DSENSE2L
Current se nse turn-off
delay tim e from falling edge
of INPUT
V
IN
= 5 V to 0 V;
V
SEn
=5V; R
SENSE
=1kΩ;
R
L
=5.2Ω
50 250 µs
1.
Parameter specified by design; not subject to production test.
2.
All values refer to V
CC
=13V; T
j
= 25 °C, unless otherwise specif ied.
Table 11. MultiSense in Bulb Mode (7 V < V
CC
< 18 V; -40 °C < T
j
< 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specification VNQ7040AY-E
20/55 DocID022412 Rev 8
Figure 4. Bulb Mode - I
OUT
/I
SENSE
ver sus I
OUT
Figure 5. Bulb Mode - current sense precision vs. I
OUT
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DocID022412 Rev 8 21/55
VNQ7040AY-E Electrical specification
54
2.4 Electrica l characteristics curves - Bulb Mode
Figure 6. OFF-state output current Figure 7. Standby current
Figure 8. I
GND(ON)
vs. I
out
Figure 9. Logic Input high level voltage
Figure 10. Logic Input low level voltage Figure 11. High level logic input current
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Electrical specification VNQ7040AY-E
22/55 DocID022412 Rev 8
Figure 12. Low level logic input current Figure 13. Logic Input hysteresis voltage
Figure 14. FaultRST Input clamp voltage Figure 15. Undervoltage shutdown
Figure 16. On-state resistance vs. T
case
Figure 17. On-state resistance vs. V
CC
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DocID022412 Rev 8 23/55
VNQ7040AY-E Electrical specification
54
Figure 18. Turn-on v oltage slope Figure 19. Turn-off voltage slope
Figure 20. Won vs. T
case
Figure 21. Woff vs. T
case
Figure 22. I
LIMH
vs. T
case
Figure 23. OFF-state open-load voltage
detection thre shold
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Electrical specification VNQ7040AY-E
24/55 DocID022412 Rev 8
2.4.1 LED Mode (Channel 0 and 1)
Figure 24. V
sense
clamp vs. T
case
Figure 25. V
senseh
vs. T
case
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Table 12. Switching in LED Mode (V
CC
= 13 V; -40 °C < T
j
< 150 °C, unless otherwise
specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)_0,1_LED(1)
1. See Figure 35: Switching times and Pulse skew.
Tur n-on delay time at
T
j
=25°C R
L
=22.8Ω10 65 120 µs
t
d(off)_0,1_LED(1)
Turn-off delay time at
T
j
=25°C R
L
=22.8Ω10 40 100
(dV
OUT
/dt)
on_0,1_LED(1)
Turn-on voltage slope at
T
j
=25°C R
L
=22.8Ω0.2 0.5 0.8 V/µs
(dV
OUT
/dt)
off_0,1_LED(1)
Turn-o ff vol tage slope at
T
j
=25°C R
L
=22.8Ω0.1 0.5 0.7
W
ON_0,1_LED
Switching energy losses
at turn-on (t
won
)R
L
=22.8Ω—0.040.1
(2)
2. Parameter guaranteed by design and characterization, not subject to production test.
mJ
W
OFF_0,1_LED
Switching energy losses
at turn-off (t
woff
)R
L
=22.8Ω— 0.045 0.11
(2)
mJ
t
SKEW_0,1_LED(1)
Differential Pulse skew
(t
PHL
- t
PLH
)R
L
=22.8Ω-75 -25 25 µs
DocID022412 Rev 8 25/55
VNQ7040AY-E Electrical specification
54
Table 13. Power section in LED Mode (7 V < V
CC
< 28 V; -40 °C < T
j
< 150 °C, unless
otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
R
ON_0,1_LED
On-state resistance in
LED Mode Ch0 and
Ch1
I
OUT
=0.57A; T
j
=25°C 140
mΩ
I
OUT
=0.57A; T
j
= 150°C 280
I
OUT
=0.57A; V
CC
=5V;
T
j
=25°C 210
I
LIMH_0,1_LED(1)
1. Parameter guaranteed by an indirect test sequence.
DC short circuit current
in Bulb Mode Ch0 and
Ch1
V
CC
=13V 5.5 8 11
A
4V<V
CC
<18V
(2)
2. Parameter guaranteed by design and characterization; not subject to production test.
I
LIML_0,1_LED
Short circui t curre nt
during thermal cycling
in Bulb Mode Ch0 and
Ch1
V
CC
=13V;
T
R
<T
j
<T
TSD
2
V
ON_0,1_LED
Output voltage drop
limitation in LED Mode
Ch0 and Ch1 I
OUT
=0.07A 20 mV
Table 14. MultiSense in LED Mode (7 V < V
CC
< 18 V; -40 °C < T
j
<150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K
OL
I
OUT
/I
SENSE
I
OUT
= 0.01 A;
V
SENSE
=0.5V; V
SEn
=5V 120
dK
cal
/K
cal(1)(2)
Current sense ratio drift
at calibration point
I
cal
= 17.5 mA;
I
OUT
= 10 mA to 25 mA;
V
SENSE
=0.5V; V
SEn
=5V -30 30 %
K
LED
I
OUT
/I
SENSE
I
OUT
= 0.025 A; V
SENSE
=0.5
V; V
SEn
=5V 150 380 610
dK
LED
/K
LED(1)(2)
Current sense ratio drift I
OUT
= 0.025 A;
V
SENSE
=0.5V; V
SEn
=5V -25 25 %
K
0_CH0,1_L
I
OUT
/I
SENSE
I
OUT
= 0.15 A; V
SENSE
=4V;
V
SEn
=5V 240 405 570
dK
0
/K
0(1)(2)
Current sense ratio drift I
OUT
= 0.15 A; V
SENSE
=4V;
V
SEn
=5V -15 15 %
K
1_CH0,1_L
I
OUT
/I
SENSE
I
OUT
= 0.7 A; V
SENSE
=4V;
V
SEn
=5V 300 380 460
dK
1
/K
1(1)(2)
Current sense ratio drift I
OUT
= 0.7 A; V
SENSE
=4V;
V
SEn
=5V -8 8 %
MultiSense timings (Current Sense mode - see Figure 36)
t
DSENSE1H
Current sense settling
time from rising edge of
SEn
V
IN
=5V;
V
SEn
= 0 V to 5 V;
R
SENSE
=1kΩ; R
L
=22.8Ω
60 µs
Electrical specification VNQ7040AY-E
26/55 DocID022412 Rev 8
Figure 26. LED Mode - I
OUT
/I
SENSE
versus I
OUT
t
DSENSE1L
Current sense disable
delay time from falling
edge of SEn
V
SEn
= 5 V to 0 V;
R
SENSE
=1kΩ; R
L
=22.8Ω520µs
t
DSENSE2H
Current sense settling
time from rising edge of
INPUT
V
IN
= 0 V to 5 V; V
SEn
=5V;
R
SENSE
=1kΩ; R
L
=22.8Ω250 µs
Δt
DSENSE2H
Current sense settling
time from rising edge of
I
OUT
(dynamic
response to a step
change of I
OUT
)
V
IN
=5V; V
SEn
=5V;
R
SENSE
=1kΩ; R
L
=22.8Ω100 µs
t
DSENSE2L
Current sense turn-off
delay time from falling
edge of INPUT
V
IN
= 5 V to 0 V; V
SEn
=5V;
R
SENSE
=1kΩ; R
L
=22.8Ω50 250 µs
1.
Parameter specified by design; not subject to production test.
2.
All values refer to V
CC
=13V; T
j
= 25 °C, unless otherwise specif ied.
Table 14. MultiSense in LED Mode (7 V < V
CC
< 18 V; -40 °C < T
j
< 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
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Electrical specification VNQ7040AY-E
28/55 DocID022412 Rev 8
2.5 Electrica l characteristics curves - LED mode
Figure 28. On-state resistance vs. T
case
Figure 29. On-state resistance vs. V
CC
Figure 30. Turn-on v oltage slope Figure 31. Turn-off voltage slope
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DocID022412 Rev 8 29/55
VNQ7040AY-E Electrical specification
54
Figure 32. Won vs. T
case
Figure 33. Woff vs. T
case
Figure 34. I
LIMH
vs. T
case
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Electrical specification VNQ7040AY-E
30/55 DocID022412 Rev 8
Figure 35. Switching times and Pulse skew
Figure 36. MultiSense timings (current sense mode)
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DocID022412 Rev 8 31/55
VNQ7040AY-E Electrical specification
54
Figure 37. Multisense timings (chip temperature and V
CC
sense mode)
Figure 38. T
DSKON
-
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6(Q
9&&
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Electrical specification VNQ7040AY-E
32/55 DocID022412 Rev 8
2.5.1 Truth tables
Table 15. Truth table
Mode Conditions IN
X
FR SEn SEL
X
OUT
X
MultiSense Comments
Standby All logic inputs
low LLL L L Hi-Z Low quiescent
current consumption
Normal Nominal loa d
connected;
T
j
< 150°C
LX
Refer to
Table 16
L
Refer to
Table 16
HL H Outputs configured
for auto-restart
HH H Outputs configured
for Latch-off
Overload
Overload or
short to GND
causing:
T
j
>T
TSD
or
ΔT
j
>ΔT
j_SD
LX
Refer to
Table 16
L
Refer to
Table 16
HL H Output cycles with
temperature
hysteresis
H H L Output latches-off
Under-voltage V
CC
<V
USD
(falling) XXX X L
LHi-Z
Hi-Z
Re-start when
V
CC
>V
USD
+
V
USDhyst
(rising)
OFF-state
diagnostics Short to V
CC
LX Refer to
Table 16 HRefer to
Table 16
Open load L X H External pull-up
Negative
output voltage In ductiv e load s
turn off LX Refer to
Table 16 <0V Refer to
Table 16
Table 16. MultiSense multiplexer addressing
SEn SEL
2
SEL
1
SEL
0
MUX
channel
MultiSense output
Normal mode Overlo ad OFF-state
diag.
(1)
Negative
output
LXXX Hi-Z
HLLL
Channel 0
diagnostic I
SENSE
=
1/K * I
OUT0
V
SENSE
=
V
SENSEH
V
SENSE
=
V
SENSEH
Hi-Z
HLLH
Channel 1
diagnostic I
SENSE
=
1/K * I
OUT1
V
SENSE
=
V
SENSEH
V
SENSE
=
V
SENSEH
Hi-Z
HLHL
Channel 2
diagnostic I
SENSE
=
1/K * I
OUT2
V
SENSE
=
V
SENSEH
V
SENSE
=
V
SENSEH
Hi-Z
HLHH
Channel 3
diagnostic I
SENSE
=
1/K * I
OUT3
V
SENSE
=
V
SENSEH
V
SENSE
=
V
SENSEH
Hi-Z
HHL L T
CHIP
Sense V
SENSE
=V
SENSE_TC
HHL HV
CC
Sense V
SENSE
=V
SENSE_VCC
DocID022412 Rev 8 33/55
VNQ7040AY-E Electrical specification
54
HHHL T
CHIP
Sense V
SENSE
=V
SENSE_TC
HHHHV
CC
Sense V
SENSE
=V
SENSE_VCC
1. In case the output channel corresponding to the selected MUX channel is latched off while the
relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic.
Example 1: FR = 1; IN
0
=0; OUT
0
= L (latched); MUX channel = channel 0 diagnostic;
Mutisens e = 0
Example 2: FR = 1; IN
0
=0; OUT
0
= latched, V
OUT0
>V
OL
; MUX channe l = channel 0
diagnostic; Mutisense = V
SENSEH
Table 17. Bulb/LED Mode Configuration
LED
1
LED
0
Configuration
Channel 1 Channel 0
L L Bulb Bulb
L H Bulb LED
H L LED Bulb
HH LED LED
Table 16. MultiSense multiplexer addressing (continued)
SEn SEL
2
SEL
1
SEL
0
MUX
channel
MultiSense output
Normal mode Overlo ad OFF-state
diag.
(1)
Negative
output
Electrical specification VNQ7040AY-E
34/55 DocID022412 Rev 8
2.5.2 Immunity to electric al tran sie nt di sturbanc es on V
CC
(ISO 7637-2)
Table 18. Electrical transient requirements (part 1/3)
ISO 7637 -2:
2004(E)
test pulse
Test levels
(1)
1. The above test levels must be considered referred to V
CC
= 13.5V except for pulse 5b.
Number of
pulses or
test times
Burst cycle / pulse
repetition time Delays and
Impedance
III IV Min. Max.
1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω
2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω
3a -100V -150V 1h 90 ms 100ms 0.1µs, 50Ω
3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω
4 -6V -7V 1 pulse 100ms, 0.01Ω
5b
(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
+65V +87V 1 pulse 400ms, 2Ω
Table 19. Electrical transient requirements (part 2/3)
ISO 763 7-2:
2004E
test pulse
Test level results
III VI
1C C
2a C C
3a C C
3b C C
4C C
5b
(1)
1. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
Table 20. Electrical transient requirements (part 3/3)
Class Contents
C All functions of the device performed as designed after exposure to disturbance.
EOne or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
DocID022412 Rev 8 35/55
VNQ7040AY-E Protections
54
3 Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔT
j
through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as soon
as ΔT
j
exceeds the safety level of ΔT
j_SD
. According to the voltage level on the FaultRST
pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the
maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently ,
reduces thermo-mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon as
its junction temperature drops to T
R
(see Table 7, FaultRST = Low) or remains off
(FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as
the other components of the system (e.g. bonding wires, wiring harness, connectors, loads,
etc.) from excessive current flow. Consequently, in case of short circuit, overload or during
load power-up, the output current is clamped to a safety level, I
LIMH
, by operating the output
power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain
value, V
DEMAG
(see Table 7), allowing the inductor energy to be dissipated without
damaging the device.
Application information VNQ7040AY-E
36/55 DocID022412 Rev 8
4 Application information
Figure 39. Application diagram
4.1 Protection against rever se ba ttery
Figure 40. Simplified internal structure
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DocID022412 Rev 8 37/55
VNQ7040AY-E Application information
54
The device does not need any external components to protect the internal logic in case of a
reverse battery condition. The protection is provided by internal structures.
In addition, due to the fact that the output MOSFET turns on even in reverse battery mode,
thus providing the same low ohmic path as in regular operating conditions, no additional
power dissipation has to be considered.
4.2 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the V
CC
pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 21.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:201 1(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through V
CC
and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal oper a tion after the test”.
4.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the V
CC
line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prot
) in line bot h to
prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.
Table 21. ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse seve rity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time Pulse duration and
pulse generator
internal impedance
Level U
S(1)
1. U
S
is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
min max
1 III -112V 500 pulses 0,5 s 2ms, 10Ω
2a III +55V 500 pulses 0,2 s 5 s 50μs, 2Ω
3a IV -220V 1h 90 ms 100 ms 0.1μs, 50Ω
3b IV +150V 1h 90 ms 100 ms 0.1μs, 50Ω
4
(2)
2. Test pulse from ISO 7637-2:2004(E).
IV -7V 1 pulse 100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test B
(3)
3. With 40 V external suppressor referred to ground (-40°C < T
j
< 150°C).
40V 5 pulse 1 min 400ms, 2Ω
Application information VNQ7040AY-E
38/55 DocID022412 Rev 8
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
V
CCpeak
/I
latchup
≤ R
prot
≤ (V
OHμC
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= -150 V; I
latchup
≥ 20mA; V
OHμC
≥ 4.5V
7.5 kΩ ≤ R
prot
≤ 140 kΩ.
Recommended values: R
prot
=15kΩ
4.4 Mu ltisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(Multisense) delivering the following signals:
•Current monitor: current mirror of channel output current
•V
CC
monitor: voltage propotional to V
CC
•T
CASE
: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in Table 16.
DocID022412 Rev 8 39/55
VNQ7040AY-E Application information
54
Figure 41. Multisense and diagnostic – block diagram
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40/55 DocID022412 Rev 8
4.4.1 Principle of Multisense signal generation
Figure 42. Multisense block diagram
Current monitor
When current mode is selected in the Multisense, this output is capable to provide:
•Current mirror proportional to the load current in normal operation, deliv erin g
current proportional to the load according to known ratio named K
•Diagnostics flag in fault conditions delivering fixed voltage V
SENSEH
The current delivered by the current sense circuit, I
SENSE
, can be easily converted to a
voltage V
SENSE
by using an external sense resistor, R
SENSE
, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), V
SENSE
calculation
can be done using simple equations
Current provided by Multisense output: I
SENSE
= I
OUT
/K
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DocID022412 Rev 8 41/55
VNQ7040AY-E Application information
54
Voltage on R
SENSE
:
V
SENSE
= R
SENSE .
I
SENSE
= R
SENSE .
I
OUT
/K
Where :
•V
SENSE
is voltage measurable on R
SENSE
resistor
•I
SENSE
is current provided from Multisense pin in current output mode
•I
OUT
is current flowing through output
•K factor represent the ratio between PowerMOS cells and SenseMOS cells; its spread
includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between I
OUT
and I
SENSE
.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the Multisense pin
which is switched to a “current limited” voltage source, V
SENSEH
(see Table 8).
In any case, the current sourced by the Multisense in this condition is limited to I
SENSEH
(see
Table 8).
Figure 43. Analogue HSD – open-load detection in off-s tate
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Application information VNQ7040AY-E
42/55 DocID022412 Rev 8
Figure 44. Open-load / short to V
CC
condition
4.4.2 T
CASE
and V
CC
monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because of a
voltage shift is generated between device GND and the microcontroller input GND
reference.
Figure 45 shows link between V
MEASURED
and real V
SENSE
signal.
Table 22. MultiSense pin le vels in off-state
Condition Output MultiSense SEn
Open-load
V
OUT
>V
OL
Hi-Z L
V
SENSEH
H
V
OUT
<V
OL
Hi-Z L
0H
Short to V
CC
V
OUT
>V
OL
Hi-Z L
V
SENSEH
H
Nominal V
OUT
<V
OL
Hi-Z L
0H
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DocID022412 Rev 8 43/55
VNQ7040AY-E Application information
54
Figure 45. GND voltage shift
V
CC
monitor
Battery monitoring channel provides V
SENSE
= V
CC
/ 4.
Case temperature monitor
Case temperature monitor is capable to provide information about actual device
temperature. Since diode is used for temperature sensing, following equation describe link
between temperature and output V
SENSE
level:
V
SENSE_TC
(T) = V
SENSE_TC
(T
0
)+dV
SENSE_TC
/dT*(T-T
0
)
where dV
SENSE_TC
/ dT ~ typically -5.5 mV/K (for temperature range (-40
o
C to +150
o
C).
4.4. 3 Short to V
CC
and OFF-state open-load detection
Short to V
CC
A short circuit between V
CC
and output is indicated by the relevant current sense pin set to
V
SENSEH
during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor R
PU
connecting
the output to a positive supply voltage V
PU
.
It is preferable V
PU
to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
R
PU
must be selected in order to ensure V
OUT
> V
OLmax
in accordance with to following
equation:
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Application information VNQ7040AY-E
44/55 DocID022412 Rev 8
Equation 2
4.5 Maximum demagnetization energy (V
CC
= 16 V)
Figure 46. Maximum turn off current ver sus inductance
RPU VPU 4–
IL off2()min @ 4V
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Package and PCB thermal data VNQ7040AY-E
46/55 DocID022412 Rev 8
Figure 48. Rthj-amb vs PCB copper area in open box free air condition
Table 23. PCB properties
Dimension Value
Board finish thickness 1.6 mm +/- 10%
Board dimension 129 mm x 60 mm
Board Material FR4
Cu thickness (outer layers) 0.070 mm
Cu thickness (inner layers) 0.035 mm
Thermal vias separation 1.2 mm
Thermal via diameter 0.3 mm +/- 0.08 mm
Cu thickness on vias 0.025 mm
Footprint dimension 4.1 mm x 6.5 mm
("1($'5
57+MDPE
57+MDPE
DocID022412 Rev 8 47/55
VNQ7040AY-E Package and PCB thermal data
54
Figure 49. PowerSSO-36 thermal impedance junction ambient
Figure 50. Thermal fitting model of a HSD in PowerSSO-36
("1($'5
=7+Σ&:
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48/55 DocID022412 Rev 8
Table 24. Thermal parameters
Area/island (cm
2
)FP284L
R1 = R7 = R9 = R11 (°C/W) 1.2
R2 = R8 = R10 = R12 (°C/W) 2.3
R3 (°C/W) 3.5 3.5 3.5 3.5
R4 (°C/W) 7 6 6 4
R5 (°C/W) 20 14 10 2
R6 (°C/W) 30 26 15 7
C1 = C7 = C9 = C11 (W·s/°C) 0.0006
C2 = C8 = C10 = C12 (W·s/°C) 0.003
C3 (W·s/°C) 0.02 0.02 0.02 0.01
C4 (W·s/°C) 0.5 0.8 0.8 0.8
C5 (W·s/°C) 1 2 3 10
C6 (W·s/°C) 3 5 9 18
DocID022412 Rev 8 49/55
VNQ7040AY-E Package information
54
6 Package information
6.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
6.2 PowerSSO-36 mechani cal data
Figure 51. PowerSSO-36 package dimensions
Package information VNQ7040AY-E
50/55 DocID022412 Rev 8
l
Table 25. PowerSSO-36 mechanical data
Symbol millimeters
Min Typ Max
A 2.15 - 2.45
A2 2.15 - 2.35
a1 0 - 0.1
b 0.18 - 0.36
c 0.23 - 0.32
D 10.10 - 10.50
E 7.4 - 7.6
e-0.5-
e3 - 8.5 -
F-2.3-
G- -0.1
H 10.1 - 10.5
h--0.4
k0°-8°
L 0.55 - 0.85
M-4.3-
N--10°
O-1.2
Q-0.8-
S-2.9-
T-3.65-
U-1.0-
X
(1)
1. Corresponding to internal variation C.
4.3 - 5.2
Y
(1)
6.9 - 7.5
DocID022412 Rev 8 51/55
VNQ7040AY-E Package information
54
6.3 Packing information
Figure 52. PowerSSO-36 tube shipment (no suffix)
Figure 53. PowerSSO-36 tape and reel shipment (suffix “TR”)
A
CB
All dimensions are in mm.
Base q.ty 49
Bul k q.ty 1225
Tube length (± 0.5) 532
A3.5
B13.8
C (± 0.1) 0.6
Base q.ty 1000
Bulk q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 24.4
N (min) 100
T (max) 30.4
REEL DIMENSIO NS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
All dimensions are in mm.
Tape width W 24
Tape hole sp aci ng P0 (± 0.1) 4
Com p onent spacing P 12
Hole diameter D (± 0.05) 1.55
Hole diameter D1 (min) 1.5
Hole position F (± 0.1) 11.5
Compartment depth K (max) 2.85
Hole spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo componen ts Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
DocID022412 Rev 8 53/55
VNQ7040AY-E Revision history
54
8 Revision history
Table 27. Document revision history
Date Revision Changes
14-N ov-2011 1 Initial release.
14-Feb-2013 2 Updated Figure 2: Configuration diagram (top view)
Table 1: Pi n func tio ns:
– GND: updated function description
20-Mar-2013 3
Updated Features list
Updated Tab le 1: Pin functio ns and Table :
Table 3: Absolute maximu m ratings:
–V
CC
, -V
CC
, V
FR
, -I
OUT_0,1
, -I
OUT_2,3
: updated value
–V
CCPK
, I
SENSE
, V
ESD
: updated parameter and value
–V
CCJS
: added row
–-V
SENSE
: removed row
Updated Tab le 4: Thermal dat a
Table 5: Power section:
–V
USDReset
, I
GND(ON)
: added row
–t
D_STBY
: updated test conditions and value
–V
clamp
, I
STBY
, I
S(ON)
, I
L(off)
: updated test conditions row
Table 7: Protections (7 V < V
CC
<18V; -40°C<T
j
<150°C):
–V
DEMAG
, T
HYST
: updated value
–t
LATCH_RST
: updated test conditions and values
Table 8: MultiSense (7 V < V
CC
<18V; -40°C<T
j
<150°C):
–V
SENSE_CL
, V
OL
, t
STKON
, t
D_VOL
, t
DSENSE3H
, t
DSENSE3L
, t
DSENSE4H
,
t
DSENSE4L
, t
D_XtoY
, t
D_CStoTC
, t
D_TCtoCS
, t
D_CStoVCC
, t
D_VCCtoCS
,
t
D_TCtoVCC
, t
D_VCCtoTC
, t
D_CStoVSENSEH
: updated test conditions
–I
SENSE0
, I
L(off2)
, V
SENSE_TC
, V
SENSE_VCC
, V
SENSEH
: updated test
conditions and values
–V
OUT_MSD
, V
SENSE_SAT
, I
SENSE_SAT
, I
OUT_SAT_BULB
, I
OUT_SAT_LED
,
t
D_OL_V
: added rows
–I
SENSEH
: updated value
Ta ble 9: Power section in Bulb Mode (7 V < V
CC
<28V; -
40 °C < T
j
< 150 °C, unless otherwise specified):
–R
ON_0,1,2,3_BULB
: updated test conditions and values
–R
ON_REV_0,1,2,3
: updated valu e
Updated Table 10: Switching in Bulb Mode (V
CC
=13V; -
40 °C < T
j
< 150 °C, unless otherwise specified), Table 11: MultiSense
in Bulb Mode (7 V < V
CC
<18V; -40°C<T
j
<150°C), Table 12:
Switching in LED Mode (V
CC
=13V; -40°C<T
j
< 150 °C, unl es s
otherwi se sp eci fie d) and Table 14: MultiSense in LED Mode
(7 V < V
CC
<18V; -40°C<T
j
<150°C)
Removed Figure: Switchin g times and Figure: Puls e skew
Added Figure 35: Sw itching times and Pulse skew
Updated Figure 36: MultiSense timings (current sense mode) and
Figure 37: Multisense timings (chip temperature and VCC sense mode)
Revision history VNQ7040AY-E
54/55 DocID022412 Rev 8
20-Mar-2013 3
(cont’d)
Added Figure 38: T
DSKON
Table 15: Truth table:
– Overloa d: updated conditions
Updated Tab le 16: MultiSense mul tip le xer addressing
Removed Section: Wave forms
22-Jul-2013 4
Table 10: Switching in Bulb Mode (V
CC
=13V; -40°C<T
j
<150°C,
unless oth erwis e spe ci fied ):
–t
SKEW_0,1,2,3
: updated values
Updated Table 11: MultiSense in Bulb Mode (7 V < V
CC
<18V; -
40 °C < T
j
<150°C)
Table 12: Switching in LED Mode (V
CC
=13V; -40°C<T
j
<150°C,
unless oth erwis e spe ci fied ):
–t
SKEW_0,1_LED
: updated values
Updated Table 14: MultiSense in LED Mode (7 V < V
CC
<18V; -
40 °C < T
j
<150°C)
18-Sep-2013 5 Updated disclaimer.
11-Feb-2014 6
Updated Table 10: Switching in Bulb Mode (V
CC
=13V; -
40 °C < T
j
< 150 °C, unless otherwise specified) and Table 12:
Switching in LED Mode (V
CC
=13V; -40°C<T
j
< 150 °C, unl es s
otherwi se sp eci fie d)
19-Jun-2014 7
Table 3: Absolute maximu m ratings:
–E
MAX
: updated valu e
Table 4: T herm al dat a
Added Figure 4: B u lb Mode - I
OUT
/I
SENSE
versus I
OUT
and Figure 5:
Bulb Mode - current sense precision vs. I
OUT
Added Section 2.4: Electrical characteristics curves - Bulb Mode
Added Figure 26: LED Mode - I
OUT
/I
SENSE
versu s I
OUT
and Figure 27:
LED Mode - current sense precision vs. I
OUT
Added Section 2.5: Electrical characteristics curves - LED mode
Removed Sectio n: Immun ity to elect rical trans ient dis turbances o n VCC
(ISO 7637-2)
Added Chapter 3: Protections, Chapter 4: Application information and
Chapter 5: Package and PCB thermal data
30-Sep-2014 8 Updated Chapter 5: Package and PCB thermal data
Table 27. Document revision history (continued)
Date Revision Changes
DocID022412 Rev 8 55/55
VNQ7040AY-E
55
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