SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14060B is a 14-stage binary ripple counter with an on-chip oscillator buffer. The oscillator configuration allows design of either RC or crystal oscillator circuits. Also included on the chip is a reset function which places all outputs into the zero state and disables the oscillator. A negative transition on Clock will advance the counter to the next state. Schmitt trigger action on the input line permits very slow input rise and fall times. Applications include time delay circuits, counter controls, and frequency dividing circuits. P SUFFIX PLASTIC CASE 648 * * * * D SUFFIX SOIC CASE 751B Fully static operation Diode Protection on All Inputs Supply Voltage Range = 3.0 V to 18 V Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range * Buffered Outputs Available from Stages 4 Through 10 and 12 Through 14 * Common Reset Line * Pin-for-Pin Replacement for CD4060B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD TA = - 55 to 125C for all packages. TRUTH TABLE Clock Reset Output State X L L H No Change Advance to next state All Outputs are low Plastic Ceramic SOIC PIN ASSIGNMENT Q12 1 16 VDD Q13 2 15 Q10 Q14 3 14 Q8 Q6 4 13 Q9 Q5 5 12 RESET Q7 6 11 CLOCK Q4 7 10 OUT 1 VSS 8 9 OUT 2 X = Don't Care LOGIC DIAGRAM OUT 2 9 Q4 OUT 1 Q5 7 10 Q12 1 5 Q13 2 Q14 3 CLOCK 11 C C R Q C Q C R Q C Q C R Q C Q C R Q C Q C R Q C Q C Q R Q RESET 12 Q6 = PIN 4 Q7 = PIN 6 Q8 = PIN 14 Q9 = PIN 13 Q10 = PIN 15 VDD = PIN 16 VSS = PIN 8 REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14060B 1 IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII v v IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIIII IIII III IIIIIIII III IIII III IIIIII IIII III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIII IIIIII IIIIIIIIII IIII III IIII III III IIII III IIII III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit - 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin 10 mA PD Power Dissipation, per Package 500 mW Tstg Storage Temperature - 65 to + 150 _C 260 _C TL Lead Temperature (8-Second Soldering) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages - 12 mW/_C From 100_C To 125_C ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VDD Vdc - 55_C Min Max Min 25_C Typ # Max 125_C Min Max Unit Output Voltage Vin = VDD or 0 "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 V Vin = 0 or VDD "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- V Input Voltage (VO = 4.5 or 0.5 V) (VO = 9.0 or 1.0 V) (VO = 13.5 or 1.5 V) "0" Level VIL 5.0 10 15 -- -- -- 1.5 3.0 4.0 -- -- -- 2.25 4.50 6.75 1.5 3.0 4.0 -- -- -- 1.5 3.0 4.0 (VO = 0.5 or 4.5 V) (VO = 1.0 or 9.0 V) (VO = 1.5 or 13.5 V) "1" Level VIH 5.0 10 15 3.5 7.0 11.0 -- -- -- 3.5 7.0 11.0 2.75 5.50 8.25 -- -- -- 3.5 7.0 11.0 -- -- -- Input Voltage "0" Level (VO = 4.5 Vdc) (For Input 11 (VO = 9.0 Vdc) and Output 10) (VO = 13.5 Vdc) VIL 5.0 10 15 -- -- -- 1.0 2.0 2.5 -- -- -- 2.25 4.50 6.75 1.0 2.0 2.5 -- -- -- 1.0 2.0 2.5 5.0 10 15 4.0 8.0 12.5 -- -- -- 4.0 8.0 12.5 2.75 5.50 8.25 -- -- -- 4.0 8.0 12.5 -- -- -- 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- IOL 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 0.88 2.25 8.8 -- -- -- 0.36 0.9 2.4 -- -- -- mA Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 A Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Quiescent Current (Per Package) IDD 5.0 10 15 -- -- -- 5.0 10 20 -- -- -- 0.005 0.010 0.015 5.0 10 20 -- -- -- 150 300 600 A IT 5.0 10 15 (VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc) "1" Level VIH Output Drive Current (VOH = 2.5 V) (Except Source (VOH = 4.6 V) Pins 9 and 10) (VOH = 9.5 V) (VOH = 13.5 V) IOH (VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Sink V V Vdc Vdc mA IT = (0.25 A/kHz) f + IDD IT = (0.54 A/kHz) f + IDD IT = (0.85 A/kHz) f + IDD A # Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. MC14060B 2 MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIII IIIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIII IIIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) Characteristic Symbol VDD Vdc Min Typ # Max Unit Output Rise Time (Counter Outputs) tTLH 5.0 10 15 -- -- -- 40 25 20 200 100 80 ns Output Fall Time (Counter Outputs) tTHL 5.0 10 15 -- -- -- 50 30 20 200 100 80 ns Propagation Delay Time Clock to Q4 tPLH tPHL 5.0 10 15 -- -- -- 415 175 125 740 300 200 ns 5.0 10 15 -- -- -- 1.5 0.7 0.4 2.7 1.3 1.0 s twH 5.0 10 15 100 40 30 65 30 20 -- -- -- ns f 5.0 10 15 -- -- -- 5 14 17 3.5 8 12 MHz tTLH tTHL 5.0 10 15 tw 5.0 10 15 120 60 40 40 15 10 -- -- 5.0 10 15 -- -- -- 170 80 60 350 160 100 Clock to Q14 Clock Pulse Width Clock Pulse Frequency Clock Rise and Fall Time Reset Pulse Width Propagation Delay Time Reset to On tPHL ns No Limit ns -- ns #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD VDD 500 F PULSE GENERATOR CLOCK NC NC CLOCK NC NC Q4 OUT1 Q5 OUT2 Qn R VSS 20 ns CLOCK PULSE GENERATOR 0.01 F ID 90% 50% 10% CL VSS CL CL CL 20 ns CL CL 20 ns 90% 50% 10% CLOCK 20 ns tPLH VDD VSS 50% DUTY CYCLE Figure 1. Power Dissipation Test Circuit and Waveform MOTOROLA CMOS LOGIC DATA Q4 OUT1 Q5 OUT2 Qn R Q tTLH tWH tPHL 90% 50% 10% tTHL Figure 2. Switching Time Test Circuit and Waveforms MC14060B 3 CLOCK 11 f 10 OUT 1 RESET if 1 kHz f 100 kHz and 2Rtc < RS < 10Rtc (f in Hz, R in ohms, C in farads) 9 OUT 2 Rtc RS [ 2.3 R1tcCtc The formula may vary for other frequencies. Recommended maximum value for the resistors in 1 M. Ctc Figure 3. Oscillator Circuit Using RC Configuration TYPICAL RC OSCILLATOR CHARACTERISTICS 100 VDD = 15 V 4.0 f, OSCILLATOR FREQUENCY (kHz) FREQUENCY DEVIATION (%) 8.0 0 1.0 V - 4.0 - 8.0 5.0 V - 12 RTC = 56 k C = 1000 pF - 16 - 55 - 25 100 CLOCK 11 5 2 1 0.5 f AS A FUNCTION OF C (RTC = 56 k) (RS = 120 k) 125 0.1 1.0 k 10 k 100 k RTC, RESISTANCE (OHMS) 0.001 0.01 C, CAPACITANCE (F) 10 OUT 1 9 OUT 2 18M RO CT Figure 6. Typical Crystal Oscillator Circuit 1.0 M 0.1 IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII Figure 5. RC Oscillator Frequency as a Function of RTC and C 500 kHz Circuit 32 kHz Circuit Unit Crystal Characteristics Resonant Frequency Equivalent Resistance, RS 500 1.0 32 6.2 kHz k External Resistor/Capacitor Values RO CT CS 47 82 20 750 82 20 k pF pF + 6.0 + 2.0 + 2.0 + 2.0 ppm ppm + 100 + 120 ppm - 160 - 560 ppm Characteristic RESET CS 10 0.0001 Figure 4. RC Oscillator Stability f AS A FUNCTION OF RTC (C = 1000 pF) (RS 2RTC) 20 0.2 RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25C RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C 0 25 50 75 TA, AMBIENT TEMPERATURE (C) VDD = 10 V 50 Frequency Stability Frequency Changes as a Function of VDD (TA = 25_C) VDD Change from 5.0 V to 10V VDD Change from 10 V to 15 V Frequency Change as a Function of Temperature (VDD = 10 V) TA Change from - 55_C to + 25_C Complete Oscillator* TA Change from + 25_C to + 125_C Complete Oscillator* * Complete oscillator includes crystal, capacitors, and resistors. Figure 7. Typical Data for Crystal Oscillatgor Circuit MC14060B 4 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B- C L DIM A B C D E F G H K L M N -T- K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L S -T- SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14060B 5 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C -T- SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC14060B 6 *MC14060B/D* MOTOROLA CMOS LOGIC DATA MC14060B/D