STANDARD MICROSYSTEMS COM 8017 SS COM 8502 Universal Asynchronous Receiver/Transmitter UART Pin Configuration = FEATURES vec 1 ~~ 40 TOP S a O Single +5V Power Supply Gnd 3 38 H NDB! a ; oo ROE [4 37 1] NDB2 (Direct TTL Compatibility no interfacing circuits Roe C5 367 NSB required RO? qd 6 350 NPB Roe (17 34 cs C Full or Half Duplex Operationcan receive and Ae g 3 % H ws transmit simultaneously at different baud rates Ros [10 3119 Tos Roz [11 30 ToS C1 Fully Double Buffered eliminates need for precise RDI 4 12 29 Tp4 oo RPE [13 28 [] TD3 external timing RFE C14 27 f] 102 C Start Bit Verification decreases error rate ewe ; Q A te0 C1 Fully Programmable data word length; parity mode; ALEE C a ; A re number of stop bits: one, one and one-half, or two ADA (19 22 TBMT rsi J 20 217 MR CJ High Speed Operation 40K baud, 200ns strobes gn SP P PACKAGE: 40-Pin D.LP. OO Master Reset Resets ail status outputs (Tri-State Outputs bus structure oriented Functional Block Diagram CJ Low Power minimum power requirements TD1 TD2 TD3 TD4 TDS TD6 TD7 TOB 7 Input Protected eliminates handling problems C1 Ceramic or Plastic Dip Package easy board insertion C1 Compatible with COM 2017, COM 2502 (1 Compatible with COM 8116, COM 8126, COM 8136, COM 8146, COM 8046 Baud Rate Generators TRANSMITTER 25 SHIFT TSO REGISTER TCP TEOC GENERAL DESCRIPTION cst t SWE 35 22 The Universal Asynchronous Receiver/Transmitter is NSBL25 STATUS yee an MOS/LSI monolithic circuit that performs ail the Nr ea Se won fo] RFE NDB1 38 REGISTER BUFFER 54 ROR receiving and transmitting functions associated with POE}? REGISTER [194 RDA asynchronous data communications. This circuit is fabricated using SMCs patented COPLAMOSS tech- nology and employs depletion mode loads, allowing operation from a single +5V supply. The duplex mode, baud rate, data word length, parity mode, and number of stop bits are independently programmable through the use of external controls. There may be 5, 6, 7 or 8 data bits, odd/even or no parity, and 1, or 2 stop bits. In addition the COM 8017 will provide 1.5 stop bits when programmed for 5 data bits and 2 stop bits. The UART RDE 9 can operate in either the full or half duplex mode. These programmable features provide the user with the ability to interface with all asynchronous peripherais. if t__18) spar RCP RECEIVER 20) HIFT RSI Si REGISTER RECEIVER BUFFER REGISTER 5 6 7 8 9 10 jit ji2 RD8 RD7 RD6 RDS RD4 RD3 RD2 RD1 Wh 153DESCRIPTION OF OPERATION TRANSMITTER At start-up the power is turned on, a clock whose frequency is 16 times the desired baud rate is applied and master reset is pulsed. Under these conditions TBMT, TEOC, and TSO are all at a high level (the tine is marking). When TBMT and TEOC are high, the control bits may be set. After this has been done the data bits may be set. Normally, the control bits are strobed into the transmitter prior to the data bits. However, as long as minimum puise width specifications are not violated, TDS and CS may occur simulta- neously. Once the date strobe (TDS) has been pulsed the TBMT signal goes tow, indicating that the data bits buffer register is full and unavailable to receive new data. If the transmitter shift register is transmitting pre- viously loaded data the TBMT signal remains low. If the transmitter shift register is empty, or when itis through transmitting the previous character, the data in the buffer register is loaded immediately into the transmitter shift register and data transmission commences. TSO goes low (the start bit), TEOC goes low, the TBMT goes high indicating that the data in the data bits buffer register has been loaded into the transmitter shift register and that the data bits buffer register is available to be loaded with new data. If new data is loaded into the data bits buffer register at this time, TBMT goes lowandremainsin this state until the present transmission is completed. One full character time is available for loading the next character with nolossin speed of transmission. This is an advantage of double buffering. Data transmission proceeds in an orderly manner: start bit, data bits, parity bit (if selected), and the stop bit(s). When the last stop bit has been on the line for one bit time TEOC goes high. If TBMT is low, transmission begins immediately. If TBMT is high the transmitter is completely at rest and, if desired, new control bits may be loaded prior to the next data transmission. ODD/EVEN PARITY SELECT NO NUMBER NUMBER OF PARITY STOP BITS DATA BITS cor oee CONTROL BITS HOLDING REGISTER To RECEIVER 16xT Ly LOAD CLOCK tine GENERATOR SHIFT TRANSMITTER BLOCK DIAGRAM O88 DB7 DB6 0B5 DB4 0B3 DB2 OB1 DATA BITS HOLDING REGISTER BUFFER STEERING LOGIC + TRANSMITTER SHIFT REGISTER PARITY BIT GENERATION LOGIC DATA STROBE TRANSMITTER BUFFER EMPTY | R F/F s OUTPUT Loaic SERIAL OUTPUT END OF > CHARACTER DESCRIPTION OF OPERATION RECEIVER At start-up the power is turned on, a clock whose frequency is 16 times the desired baud rate is applied and master reset is pulsed. The data available (RDA) signal is now low. There is one set of control bits for both the receiver and transmitter. Data reception begins when the serial input tine transitions from mark (high) to space (low). If the RSI line remains spacing for a1/2 bittime, agenuine start bit is verified. Should the line return to a mark- 154 ing condition prior toa 1/2 bit time, the start bit veri- fication process begins again. A mark to space transition must occur in order to initiate start bit verification. Once a start bit has been verified, data reception proceeds in an orderly manner: start bit verified and received, data bits received, parity bit received (if selected) and the stop bit(s) received. If the transmitted parity bit does not agree with the received parity bit, the parity error flip-fiop of thestatus word buffer register is set high, indicating a parity error. However, if the no parity mode is se- lected, the parity error flip-flop is unconditionally held low, inhibiting a parity error indication. If a stop bitis not received, due to an improperly framed character, the framing error flip-flop is set high, indicating a framing error. Once a full character has been received internal logic looks at the data available (RDA) signal. If, at this instant, the RDA signal is high the receiver not been read out and the over-run flip-flop is set high. The only way the receiver is aware that data has been read out is by having the data available reset low. At this time the RDA output goes high indicating that all outputs are available to be examined. The receiver shift register is now available to begin re- ceiving the next character. Due to the double buf- fered receiver, a full character time is available to remove the received character. assumes that the previously received character has =z io) roa a) Ui wo RECEIVER BLOCK DIAGRAM FRAMING ERROR PARITY ERROR TRANSMITTER BUFFER EMPTY OVER RUN AND GATE ROB RD7 ROS ADS RO4 AD3 RO2 ADI DATA AVAILABLE DATA STATUS ENABLE AND GATE WORD RESET DATA ILABLE STATUS WORD DATA BITS HOLDING REGISTER BUFFER HOLDING REGISTER CONTROL BITS FROM HOLDING REGISTER | + + SERIAL START BIT PARITY BIT RIGHT RECEIVER SHIFT (INPUT VERIFICATION CHECKING LOGIC JUSTIFY LOGIC cp REGISTER 16xR 4 I CLOCK TIMING GENERATOR DESCRIPTION OF PIN FUNCTIONS PINNO. SYMBOL NAME FUNCTION 1 Vcc Power Supply +5 volt Supply 2 NC No Connection No Connection 3 GND Ground Ground 4 RDE Received Data A low-level input enables the outputs (RD8-RD1) of the Enable receiver buffer register. 5-12 RD8-RD1 Receiver Data These are the 8 tri-state data outputs enabled by RDE. Outputs Unused data output lines, as selected by NDB1 and NDB2, have a low-level output, and received characters are right justified, i.e. the LSB always appears on the RD1 output. 13 RPE Receiver Parity This tri-state output (enabled by SWE) is at a high-level if Error the received character parity bit does not agree with the selected parity. 14 RFE Receiver Framing This tri-state output (enabled by SWE) is at a high-level if Error the received character has no valid stop bit. 155DESCRIPTION OF PIN FUNCTIONS PINNO. SYMBOL NAME FUNCTION 16 ROR Receiver Over This tri-state output (enabled by SWE) is at a high-level if Run the previously received character is not read (RDA output not reset) before the present character is transferred into the receiver buffer register. 16 SWE Status Word A low-level input enables the outputs (RPE, RFE, ROR, Enable RDA, and TBMT) of the status word buffer register. 17 RCP Receiver Clock This input is a clock whose frequency is 16 times (16X) the desired receiver baud rate. 18 RDAR Receiver Data A low-level input resets the RDA output to a low-level. Available Reset 19 RDA Receiver Data This tri-state output (enabled by SWE) is at a high-level Available when an entire character has been received and transferred into the receiver buffer register. 20 RS! Receiver Serial This input accepts the serial bit input stream. A high-level Input (mark) to low-level (space) transition is required to initiate data reception. 21 MR Master Reset This input should be pulsed to a high-level after power turn-on. This sets TSO, TEOC, and TBMT to a high-level and resets RDA, RPE, RFE and ROR to a low-level. 22 TBMT Transmitter This tri-state output (enabled by SWE) is at a high-level Buffer Empty when the transmitter buffer register may be loaded with new data. 23 TDS Transmitter A low-level input strobe enters the data bits into the Data Strobe transmitter buffer register. 24 TEOC Transmitter End This output appears as ahigh-level eachtimea full character of Character is transmitted. It remains at this level until the start of transmission of the next character or for one-half of a TCP period in the case of continuous transmission. 25 TSO Transmitter This output serially provides the entire transmitted Serial Output character. TSO remains at a high-level when no data is being transmitted. 26-33 TD1-TD8 Transmitter There are 8 data input lines (strobed by TDS) available. Data Inputs Unused data input lines, as selected by NDB1 and NDB2, may be in either logic state. The LSB should always be placed on TD1. 34 cs Control Strobe A high-level input enters the contro! bits (NDB1, NDB2, NSB, POE and NPB) into the control bits holding register. This line may be strobed or hard wired to a high-level. 35 NPB No Parity Bit A high-level input eliminates the parity bit from being transmitted; the stop bit(s) immediately follow the last data bit. In addition, the receiver requires the stop bit(s) to follow immediately after the last data bit. Also, the RPE output is forced to a low-level. See pin 39, POE. 156DESCRIPTION OF PIN FUNCTION PINNO. SYMBOL NAME FUNCTION 36 NSB Number of This input selects the number of stop bits. A low-level input Stop Bits selects 1 stop bit; a high-level input selects 2 stop bits. Selection of 2 stop bits when programming a 5 data bit word generates 1.5 stop bits from the COM 8017 or COM 8017/H. 37-38 NDB2, NDB1 Number of Data Bits/Character These 2 inputs are internally decoded to select either 5, 6, 7, or 8 data bits/character as per the following truth table: NDB2 NDB1 data bits/character 5 = Qo = oO wa Imre Irie OND 39 POE Odd/Even Parity Select The logic level on this input, in conjunction with the NPB input, determines the parity mode for both the receiver and transmitter, as per the following truth table: NPB POE MODE L L odd parity L H even parity H xX no parity X = don't care 40 TCP Transmitter Clock This input is a clock whose frequency is 16 times (16X) the desired transmitter baud rate. TRANSMITTER TIMING 8 BIT, PARITY, 2 STOP BITS TOS | TBMT lf | f TSO | START TEOC | seaee Toata ayPARITY| STOP 1 STOP 2] START TRANSMITTER START-UP vce LU LU TOS M Tso s SLL Lt - ee a Upon data transmission initiation, or when not transmitting at 100% line utilization, the start bit will be placed on the TSO line at the high to low transition of the TCP clock foltowing the trailing edge of TDS. RECEIVER TIMING 8 BIT, PARITY, 2 STOP BITS RS! START [DATA TT erase [DATA afpariry| STOP 1 STOP 2| START CENTER BIT | SAMPLE RDA He ee RDA be 1/16 Bit time = The RDA line was previously not reset (ROR = high-level). **The RDA line was previously reset (ROR = low-level). START BIT DETECT/VERIFY RSI $s If the RSI line remains spacing for a 1/2 bit time, a genuine start bit is verified. Should the line return toa marking condition prior to a 1/2 bit time, the start bit verification process begins again. 157MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ........ ccc cece cece eee eee eee e rete nneeee 0Cto+ 70C Storage Temperature Range ......... cece eee ee cette tence eect t ee nnene 55C to +150C Lead Temperature (Soldering, 10SC.)...... ccc cee cece cece tence etn e ene e nee neneaeanene +325C Positive Voltage on any Pin, with respect to ground ..... 1... kee cee cece eee eee eee enes +8.0V Negative Voltage on any Pin. with respect to ground ........ 2... ccc cece eee eee eet eee e eee eees 0.3V Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. NOTE: When powering this device from laboratory or system power supplies, itisimportant that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or glitches on their outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists it is suggested that at clamp circuit be used. ELECTRICAL CHARACTERISTICS (Ta =0C to 70C, Vcc = +5V +5%, unless otherwise noted) Parameter Min. | Typ. | Max. | Unit Comments D.C. CHARACTERISTICS INPUT VOLTAGE LEVELS Low-level, Vit 0 0.8 Vv High-level, Vin 2.0 Voc Vv OUTPUT VOLTAGE LEVELS Low-level, Vor 0.4 Vo |lo.=1.6mA High-level, Vou 2.4 Vo | lon = 100uA INPUT CURRENT Low-level, lit 300 vA |Vin= Gno OUTPUT CURRENT ee Leakage, ILo +10 uA | SWE =RDE = Vin, 0 S Vout = +5V Short circuit, los** 30 mA |VouTt =0V INPUT CAPACITANCE All inputs, Cin 5 10 pf OUTPUT CAPACITANCE Le All outputs, Cour 10 20 pf |SWE=RDE=Vin POWER SUPPLY CURRENT loc 25 mA |All outputs = Vou, All inputs = Vcc A.C. CHARACTERISTICS Ta = +25C CLOCK FREQUENCY COM8502, COM 8017 DC 640 KHz | RCP TCP PULSE WIDTH Clock 0.7 us |RCP, TCP Master reset 500 ns |MR Control strobe 200 ns |CS Transmitter data strobe 200 ns |TOS Receiver data available reset 200 ns |RDAR INPUT SET-UP TIME Data bits 20 ns |TO1-TD8& Control bits 20 ns_ |NPB, NSB, NDB2, NDB1, POE INPUT HOLD TIME Data bits =0 ns |TD1-TD8 Control bits 20 ns_ |NPB, NSB, NDB2, NDB1, POE STROBE TO OUTPUT DELAY Load = 20pf +1 TTL input Receive data enable 350 ns_ |RDE: Tro, Teoo Status word enable 350 ns | SWE: Tro, Teoo OUTPUT DISABLE DELAY 350 ns |RDE, SWE **Not more than one output should be shorted at a time. NOTES: 1. If the transmitter is inactive (TEOC and TBMT are ata high-level) the start bit will appear on the TSO line within one clock period (TCP) after the trailing edge of TDS. 2. The start bit (mark to space transition) will always be detected within one clock period of RCP, guaranteeing a maximum start bit slippage of 1/16th of a bit time. 3. The tri-state output has 3 states: 1) low impedance to Vcc 2) low impedance to GND 3) high impedance OFF = 10M ohms The OFF state is controlled by the SWE and 158 inputs.DATA/CONTROL TIMING DIAGRAM =ha Vix TDS Vit TSET-uP /< Tpw THOLD Vi DATA INPUTS vin tr=tf=20ns Tset-up = 0 THOLD 20 Tew: cs ViH 4 VIL TSET-UP THOLD controt inputs V4 VIL ' Input information (Data/Control) need only be valid during the last Tew, min time of the input strobes ( TOS, CS). OUTPUT TIMING DIAGRAM RDE, SWE vir Outputs Disabled OUTPUTS a Vou (RD1-RD8, RDA, RPE, ROR, RFE, TBMT) VoL < Treo1, TPDO NOTE: Waveform drawings not to scale for clarity. RDAR n\n 200ns Vit (a a a \ VoL RDA <_ 300ns _>} 159 z S = o lows 7)FLOW CHARTTRANSMITTER FLOW CHART RECEIVER 1 TURN POWER ON 2 PULSE EXTERNAL RESET 3. SELECT BAUD AATE 16 x CLK TURAN POWEA ON PULSE EXTERNAL RESET SELECT BAUD RATE 16 x CLK SET CONTAOL BITS BONS I TBMT -1 FOC 1 $0. 1(STOP BIT) SET CONTROL BITS PULSE CS TRANSMITTER SHIFT REGISTER PTY > EOC 1) HAS THE LINE NO TRANSITIONED FROM MARKING TO, SPACING 7 YES HAS. A START NO BIT BEEN VERIFIED 8-16 x CLK yes LOAD STAAT BIT INTO RECEIVER SHIFT REGISTER HAS NO 1 BIT TIME ELAPSED ? 16-16 x CLK 1 LOAD TRANSMITTER SHIFT AEGIST! ry 2 SO OISTAAT BIT) 3 EOC ER YES SHIFT AND LOAD DATA BIT INTO HAS 1 BIT TIME ELAPSED ? (16-16 x CLK) YES SHIFT 1 BIT RIGHT IN THE TRANSMITTER SHIFT REGISTER RECEIVER SHIFT REGISTER HAS THE NO. SELECTEO NUMBE: OF DATA BITS BEEN, RECEIVE! TRANSMIT START BIT, DATA BITS. SELECTED PARITY MODE. AND STOP BIT(S) HAS THE LAST STOP BIT BEEN ON THE LINE FOR 1 BIT TIME ? YES HAS NO 1 BIT TIME ELAPSED 2 ves HAS SET PARITY NO THE PROPER \_YES| SET PARITY ERROR REGISTER PARITY BIT BEEN ERROR REGISTER To1 RECEIVED Too 3 HAS NO 1 BIT TIME ELAPSED 2 YES SET FRAMING NO ASTOP BIT YES | SET FRAMING EAROA REGISTER BEEN RECEIVED EAROR REGISTER 1 g Too THERE NEW CONTROL BITS .yeg, 7 SET OVER-RUN N 1s YES SET OVER-RUN REGISTER O RDA =0 REGISTER TO1 7 TOO TRANSFER DATA BITS FROM SHIFT REGISTER TO DATA BITS HOLDING REGISTER DA=1 EXAMINE OUTPUTS 1 STROBE STATUS WORD ENABLE 2 STROBE DATA ENABLE RESET DATA AVAILABLE DA = 0 STANDARD MICROSYSTEMS CORPORATION 3S Marcus 8ivd., Hauppauge. MY. 11788 4516) 273-3100 TWX-590-227-8898 Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applica- tions; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best product possible. 160