DF36012GFYV - Renesas Electronics

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On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

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April 1st, 2010

Renesas Electronics Corporation

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H8/300H Series

Software Manual

User’s Manual

Rev. 3.00 2004.12

Renesas 16-Bit Single-Chip

Microcomputer

H8 Family/H8/300H Series

Rev. 3.00 Dec 13, 2004 page ii of xiv

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circuit application examples contained in these materials.

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subject to change by Renesas Technology Corp. without notice due to product improvements or

other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or

an authorized Renesas Technology Corp. product distributor for the latest product information

before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

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from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means,

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contained therein.

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and

more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Keep safety first in your circuit designs!

Notes regarding these materials

Rev. 3.00 Dec 13, 2004 page iii of xiv

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

used as test pins or to reduce noise. If something is connected to the NC pins, the

operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through cu rrent f lows internally, and a malfunction may occur.

3. Processing befo re Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the

chip and a low level is input on the reset pin. During the period where th e states are

undefined, the register settings and the ou tput state of each pin are also undefined. Design

your system so that it does not malfunction because of processing while it is in this

undefined state. For those products which have a reset function, reset the LSI immediately

after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Address

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these address. Do not access these registers; the system’s

operation is not guaranteed if they are accessed.

Rev. 3.00 Dec 13, 2004 page iv of xiv

Rev. 3.00 Dec 13, 2004 page v of xiv

Preface

The H8/300H Series is b uilt around a 32-bit H8/300H CPU core with sixteen 16-bit reg ister s,

a concise, optimized instruction set designed for high-speed operation, and a 16-Mbyte linear

address space. For easy migration from the H8/300 Series, the instruction set is upward-

compatible with the H8/300 Series at the object-co de level. Programs coded in the high - level

language C can be compiled to high-speed executable code.

This manual gives details of the H8/300H CPU instructions and can be used with all

microcontrollers in the H8/300H Series.

For hard war e details, re f er to the relevant microcontro ller hardware manual.

Rev. 3.00 Dec 13, 2004 page vi of xiv

Rev. 3.00 Dec 13, 2004 page vii of xiv

Main Revisions for this Edition

Item Page Revisions (See Manual for Details)

All All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors,

and other Hitachi brand names changed to Renesas Technology

Corp.

Designation for categories changed from “series” to “group”

Rev. 3.00 Dec 13, 2004 page viii of xiv

Rev. 3.00 Dec 13, 2004 page ix of xiv

Contents

Section 1 CPU.................................................................................................................... 1

1.1 Overview........................................................................................................................... 1

1.1.1 Features................................................................................................................ 1

1.1.2 Differences from H8/300 CPU............................................................................. 2

1.2 CPU Operating Modes ...................................................................................................... 3

1.3 Address Space................................................................................................................... 7

1.4 Register Configuration...................................................................................................... 8

1.4.1 Overview.............................................................................................................. 8

1.4.2 General Registers ................................................................................................. 9

1.4.3 Control Registers.................................................................................................. 10

1.4.4 Initial Register Values.......................................................................................... 11

1.5 Data Formats ..................................................................................................................... 12

1.5.1 General Register Data Formats ............................................................................ 12

1.5.2 Memory Data Formats ......................................................................................... 14

1.6 Instruction Set ................................................................................................................... 15

1.6.1 Overview.............................................................................................................. 15

1.6.2 Instructions and Addressing Modes ..................................................................... 16

1.6.3 Tables of Instructions Classified by Function...................................................... 18

1.6.4 Basic Instruction Formats..................................................................................... 26

1.6.5 Addressing Modes and Effective Address Calculation........................................ 28

Section 2 Instruction Descriptions................................................................................ 35

2.1 Tables and Symbols...........................................................................................................35

2.1.1 Assembler Format................................................................................................ 36

2.1.2 Operation.............................................................................................................. 37

2.1.3 Condition Code .................................................................................................... 38

2.1.4 Instruction Format................................................................................................ 38

2.1.5 Register Specification........................................................................................... 39

2.1.6 Bit Data Access in Bit Manipulation Instructions................................................ 40

2.2 Instruction Descriptions .................................................................................................... 41

2.2.1 (1) ADD (B).......................................................................................................... 42

2.2.1 (2) ADD (W)......................................................................................................... 43

2.2.1 (3) ADD (L) .......................................................................................................... 44

2.2.2 ADDS.............................................................................................................. 45

2.2.3 ADDX ............................................................................................................. 46

2.2.4 (1) AND (B).......................................................................................................... 47

2.2.4 (2) AND (W)......................................................................................................... 48

Rev. 3.00 Dec 13, 2004 page x of xiv

2.2.4 (3) AND (L) .......................................................................................................... 49

2.2.5 ANDC.............................................................................................................. 50

2.2.6 BAND.............................................................................................................. 51

2.2.7 Bcc................................................................................................................... 52

2.2.8 BCLR............................................................................................................... 54

2.2.9 BIAND ............................................................................................................ 56

2.2.10 BILD................................................................................................................ 57

2.2.11 BIOR ............................................................................................................... 58

2.2.12 BIST ................................................................................................................ 59

2.2.13 BIXOR............................................................................................................. 60

2.2.14 BLD................................................................................................................. 61

2.2.15 BNOT.............................................................................................................. 62

2.2.16 BOR................................................................................................................. 64

2.2.17 BSET............................................................................................................... 65

2.2.18 BSR ................................................................................................................. 67

2.2.19 BST.................................................................................................................. 69

2.2.20 BTST............................................................................................................... 70

2.2.21 BXOR.............................................................................................................. 72

2.2.22 (1) CMP (B).......................................................................................................... 73

2.2.22 (2) CMP (W)......................................................................................................... 74

2.2.22 (3) CMP (L) .......................................................................................................... 75

2.2.23 DAA ................................................................................................................ 76

2.2.24 DAS................................................................................................................. 78

2.2.25 (1) DEC (B)........................................................................................................... 80

2.2.25 (2) DEC (W).......................................................................................................... 81

2.2.25 (3) DEC (L)........................................................................................................... 82

2.2.26 (1) DIVXS (B)....................................................................................................... 83

2.2.26 (2) DIVXS (W) ..................................................................................................... 85

2.2.26 (3) DIVXS............................................................................................................. 87

2.2.27 (1) DIVXU (B)...................................................................................................... 91

2.2.27 (2) DIVXU (W)..................................................................................................... 92

2.2.28 (1) EEPMOV (B) .................................................................................................. 97

2.2.28 (2) EEPMOV (W)................................................................................................. 98

2.2.29 (1) EXTS (W)........................................................................................................ 100

2.2.29 (2) EXTS (L)......................................................................................................... 101

2.2.30 (1) EXTU (W)....................................................................................................... 102

2.2.30 (2) EXTU (L) ........................................................................................................ 103

2.2.31 (1) INC (B)............................................................................................................ 104

2.2.31 (2) INC (W)........................................................................................................... 105

2.2.31 (3) INC (L)............................................................................................................ 106

Rev. 3.00 Dec 13, 2004 page xi of xiv

2.2.32 JMP.................................................................................................................. 107

2.2.33 JSR................................................................................................................... 108

2.2.34 (1) LDC (B)........................................................................................................... 110

2.2.34 (2) LDC (W).......................................................................................................... 111

2.2.35 (1) MOV (B) ......................................................................................................... 113

2.2.35 (2) MOV (W) ........................................................................................................ 114

2.2.35 (3) MOV (L).......................................................................................................... 115

2.2.35 (4) MOV (B) ......................................................................................................... 116

2.2.35 (5) MOV (W) ........................................................................................................ 118

2.2.35 (6) MOV (L).......................................................................................................... 120

2.2.35 (7) MOV (B) ......................................................................................................... 122

2.2.35 (8) MOV (W) ........................................................................................................ 124

2.2.35 (9) MOV (L).......................................................................................................... 126

2.2.36 MOVFPE......................................................................................................... 128

2.2.37 MOVTPE......................................................................................................... 129

2.2.38 (1) MULXS (B)..................................................................................................... 130

2.2.38 (2) MULXS (W).................................................................................................... 131

2.2.39 (1) MULXU (B).................................................................................................... 132

2.2.39 (2) MULXU (W)................................................................................................... 133

2.2.40 (1) NEG (B) .......................................................................................................... 134

2.2.40 (2) NEG (W) ......................................................................................................... 135

2.2.40 (3) NEG (L)........................................................................................................... 136

2.2.41 NOP................................................................................................................. 137

2.2.42 (1) NOT (B) .......................................................................................................... 138

2.2.42 (2) NOT (W) ......................................................................................................... 139

2.2.42 (3) NOT (L)........................................................................................................... 140

2.2.43 (1) OR (B)............................................................................................................. 141

2.2.43 (2) OR (W)............................................................................................................ 142

2.2.43 (3) OR (L) ............................................................................................................. 143

2.2.44 ORC................................................................................................................. 144

2.2.45 (1) POP (W).......................................................................................................... 145

2.2.45 (2) POP (L)............................................................................................................ 146

2.2.46 (1) PUSH (W) ....................................................................................................... 147

2.2.46 (2) PUSH (L)......................................................................................................... 148

2.2.47 (1) ROTL (B)........................................................................................................ 149

2.2.47 (2) ROTL (W)....................................................................................................... 150

2.2.47 (3) ROTL (L) ........................................................................................................ 151

2.2.48 (1) ROTR (B) ........................................................................................................ 152

2.2.48 (2) ROTR (W)....................................................................................................... 153

2.2.48 (3) ROTR (L)........................................................................................................ 154

Rev. 3.00 Dec 13, 2004 page xii of xiv

2.2.49 (1) ROTXL (B) ..................................................................................................... 155

2.2.49 (2) ROTXL (W) .................................................................................................... 156

2.2.49 (3) ROTXL (L)...................................................................................................... 157

2.2.50 (1) ROTXR (B)..................................................................................................... 158

2.2.50 (2) ROTXR (W).................................................................................................... 159

2.2.50 (3) ROTXR (L) ..................................................................................................... 160

2.2.51 RTE ................................................................................................................. 161

2.2.52 RTS.................................................................................................................. 163

2.2.53 (1) SHAL (B)........................................................................................................ 164

2.2.53 (2) SHAL (W)....................................................................................................... 165

2.2.53 (3) SHAL (L) ........................................................................................................ 166

2.2.54 (1) SHAR (B)........................................................................................................ 167

2.2.54 (2) SHAR (W)....................................................................................................... 168

2.2.54 (3) SHAR (L)........................................................................................................ 169

2.2.55 (1) SHLL (B)......................................................................................................... 170

2.2.55 (2) SHLL (W)........................................................................................................ 171

2.2.55 (3) SHLL (L)......................................................................................................... 172

2.2.56 (1) SHLR (B)......................................................................................................... 173

2.2.56 (2) SHLR (W) ....................................................................................................... 174

2.2.56 (3) SHLR (L)......................................................................................................... 175

2.2.57 SLEEP............................................................................................................. 176

2.2.58 (1) STC (B) ........................................................................................................... 177

2.2.58 (2) STC (W).......................................................................................................... 178

2.2.59 (1) SUB (B)........................................................................................................... 180

2.2.59 (2) SUB (W).......................................................................................................... 182

2.2.59 (3) SUB (L)........................................................................................................... 183

2.2.60 SUBS............................................................................................................... 184

2.2.61 SUBX .............................................................................................................. 185

2.2.62 TRAPA............................................................................................................ 186

2.2.63 (1) XOR (B).......................................................................................................... 187

2.2.63 (2) XOR (W)......................................................................................................... 188

2.2.63 (3) XOR (L) .......................................................................................................... 189

2.2.64 XORC.............................................................................................................. 190

2.3 Instruction Set Summary................................................................................................... 191

2.4 Instruction Codes............................................................................................................... 205

2.5 Operation Code Map......................................................................................................... 213

2.6 Number of States Required for Instruction Execution....................................................... 217

2.7 Condition Code Modification............................................................................................ 228

2.8 Bus Cycles During Instruction Execution......................................................................... 233

Rev. 3.00 Dec 13, 2004 page xiii of xiv

Section 3 Processing States ............................................................................................ 245

3.1 Overview........................................................................................................................... 245

3.2 Program Execution State................................................................................................... 246

3.3 Exception-Handling State.................................................................................................. 246

3.3.1 Types of Exception Handling and Their Priority ................................................. 247

3.3.2 Exception-Handling Sequences............................................................................ 248

3.4 Bus-Released State............................................................................................................ 250

3.5 Reset State......................................................................................................................... 250

3.6 Power-Down State............................................................................................................. 250

3.6.1 Sleep Mode........................................................................................................... 250

3.6.2 Software Standby Mode....................................................................................... 250

3.6.3 Hardware Standby Mode ...................................................................................... 251

Section 4 Basic Timing.................................................................................................... 253

4.1 Overview........................................................................................................................... 253

4.2 On-Chip Memory (RAM, ROM)....................................................................................... 253

4.3 On-Chip Supporting Modules........................................................................................... 255

4.4 External Data Bus .............................................................................................................. 256

Rev. 3.00 Dec 13, 2004 page xiv of xiv

Section 1 CPU

Rev. 3.00 Dec 13, 2004 page 1 of 258

REJ09B0213-0300

Section 1 CPU

1.1 Overview

The H8/300H CPU is a high-speed central processing un it with an internal 32-bit architecture that

is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general

registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

1.1.1 Features

The H8/300H CPU has the following features.

• Upward-compa tible with H8/300 CPU

 Can execute H8/300 object programs

• General-register architecture

 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit

registers)

• Sixty-two basic instructions

 8/16/32-b it ar ithmetic and logic in str uctions

 Multiply and divide instructio ns

 Powerful bit-manipulatio n instructions

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, or @aa:24]

 Immediate [#xx:8, #xx: 16, or #xx: 3 2]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

• 16-Mbyte address space

• High-speed operation

 All frequen tly-used instructio ns execute in two to four states

 Maximum clock frequency: 16 MHz

 8/16/32-bit register-register add/subtract: 125 ns

 8 × 8-bit register-register multiply: 875 ns

Section 1 CPU

Rev. 3.00 Dec 13, 2004 page 2 of 258

REJ09B0213-0300

 16 ÷ 8-bit register-register divide: 875 ns

 16 × 16-bit register-register multiply: 1375 ns

 32 ÷ 16-bit register-register divide: 1375 ns

• Two CPU operating modes

 Normal mode

 Advanced mode

• Low-power mode

 Transition to power-down state by SLEEP instruction

1.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8/300H CPU has the following enhancements.

• More general registers

Eight 16-bit registers have been added.

• Expanded address space

Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions

Signed multiply/divide instr uctions and other instructions have been added.

Section 1 CPU

Rev. 3.00 Dec 13, 2004 page 3 of 258

REJ09B0213-0300

1.2 CPU Operating Modes

The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a

maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. The mode is

selected at the mod e pins of the microcontroller. Fo r fu r ther in formation, refer to the relevant

hardware manual.

CPU operating modes

Normal mode

Advanced mode

Maximum 64 kbytes, program

and data areas combined

Maximum 16 Mbytes, program

and data areas combined

Figure 1.1 CPU Operating Modes

(1) Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

Address Space: A maximum address space of 64 kbytes can be accessed, as in the H8/300 CPU.

Extended Regist ers (En): The extended registers (E0 to E7) can be used as 16-bit data registers,

or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers.

When En is used as a 16-bit register it can contain any value, even when the corresponding

general register (R0 to R7) is used as an address register. If the general register is referenced in the

carry or borrow occurs, however, the value in the correspo ndin g extend ed reg ister will b e af fected.

Instruction Set: All additional instructions and addressing modes of the H8/300 CPU can be

used. If a 24-bit effective address (EA) is specified, only the lower 16 bits are used.

Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area

starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16

bits (figure 1.2). The exception vector table differs depending on the microcontro ller, so see the

microcontroller hardware manual for further information.

Section 1 CPU

Rev. 3.00 Dec 13, 2004 page 4 of 258

REJ09B0213-0300

H'0000

H'0001

H'0002

H'0003

H'0004

H'0005

H'0006

H'0007

H'0008

H'0009

Reset exception vector

Reserved for system use

Exception vector 1

Exception vector 2

Exception

vector table

Figure 1.2 Exception Vector Table (normal mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address to specify a memory operand that contains a branch address. In normal

mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses

can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the

exception vector table.

Stack Structure: When the program counter (PC) is pushed on the stack in a subroutine call, and

the PC and con dition-code register (CCR) are pushed on the stack in exception handling, they are

stored in the same way as in the H8/300 CPU. See figure 1.3.

(a) Subroutine branch (b) Exception handling

(16 bits) CCR

CCR*

(16 bits)

SP SP

Note: * Ignored at return.

Figure 1.3 Stack Structure (normal mode)

Section 1 CPU

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(2) Advanced Mode

In advanced mode the exception vector table and stack structure differ from the H8/300 CPU.

Address Space: Up to 16 Mbytes can be accessed linearly.

Extended Regist ers (En): The extended registers (E0 to E7) can be used as 16-bit data registers,

or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers.

When a 32-bit register is used as an address register, the upper 8 bits are ignored.

Instruction Set: All additional instructions and addressing modes of the H8/300H can be used.

Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top

area starting at H'000000 is allocated to the exception vector table in units of 32 bits. In each 32

bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 1.4).

The exception vector table differs depending on the microcontroller, so see the relevant hardware

manual for further information.

H'000000

H'000003

H'000004

H'00000B

H'00000C

Exception vector table

Don’t care

Reset exception vector

Reserved for system use

Don’t care

Exception vector

Figure 1.4 Exception Vector Table (advanced mode)

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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address to specify a memory operand that contains a branch address. In advanced

mode the operand is a 32-bit longword operand, of which the lower 24 bits are the branch address.

Branch addresses can be stored in the top area from H'000000 to H'0000FF. Note that this area is

also used for the exception vector table.

Stack Structure: When the program counter (PC) is pushed on the stack in a subroutine call, and

the PC and con dition-code register (CCR) are pushed on the stack in exception handling, they are

stored as shown in figure 1.5.

(24 bits)

CCR

(24 bits)

(a) Subroutine branch (b) Exception handling

SP SP

Reserved

Figure 1.5 Stack Structure (advanced mode)

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1.3 Address Space

Figure 1.6 shows a memory map of the H8/300 H CPU.

(a) Normal mode (b) Advanced mode

H'0000

H'FFFF

H'000000

H'FFFFFF

Figure 1.6 Memory Map

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1.4 Register Configuration

1.4.1 Overview

The H8/300H CPU has the internal registers shown in figure 1.7. There are two types of registers:

general and extend ed registers, and control registers.

I UHUNZVCCCR 76543210

23 0

15 07 07 0

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

General registers (Rn) and extended registers (En)

Control registers (CR)

Legend:

Stack pointer

Program counter

Condition code register

Interrupt mask bit

User bit or interrupt mask bit

Half-carry flag

Negative flag

Zero flag

Overflow flag

Carry flag

SP:

PC:

CCR:

Figure 1.7 CPU Registers

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1.4.2 General Registers

The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally

alike and can be used without distinction between data registers and address registers. When a

general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.

When the general registers are used as 32-bit registers or as address registers, they are designated

by the letters ER (E R0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and

RL (R0L to R7L). These registers are functionally equivalent, prov iding a maximum sixteen 8-bit

registers.

Figure 1.8 illustrates the usage of the general registers. The usage of each register can be selected

independently.

Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

(ER0 to ER7)

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Figure 1.8 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 1.9 shows the

stack.

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Free area

Stack area

SP (ER7)

Figure 1.9 Stack

1.4.3 Control Registers

The control registers are the 24-bit program counter (PC) and the 8-bit condition-code register

(CCR).

(1) Program Counter (PC)

This 24-b it coun ter indicates th e address of the next instruction the CPU will execute. Th e length

of all CPU instru ctions is 16 bits ( one word) or a multiple of 16 bits, so the least significant PC bit

is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0.

(2) Condition Code Register (CCR)

This 8-bit r egister contains internal CPU statu s in f ormation, including the interrupt mask bit (I)

and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted

regardless of the I bit setting.) The I bit is set to 1 by hardware at the start o f an exception-

handling sequence.

Bit 6—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and

XORC instructions. This bit can also be used as an interrupt mask bit. For details see the relev a nt

microcontroller hardware manual.

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Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B

instruction is ex ecuted, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0

otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is ex ecuted, the H flag is

set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,

SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or

borrow at bit 27, and cleared to 0 otherwise.

Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and

XORC instru ctions.

Bit 3—Negative Flag (N): Indicates the mo st significant bit (sign b it) of the result of an

instruction.

Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero

result.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other

times.

Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to sto r e the value shifted out of the end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions

leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits,

refer to the detailed descriptions of the instructions starting in section 2.2.1.

Oper ations can be pe rformed on the CCR bits by the LDC, STC, ANDC, ORC, and X ORC

instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch

(Bcc) instructions.

1.4.4 Initial Register Values

When the CPU is reset, the program counter (PC) is loaded from the vector table and the I bit in

the condition-code register (CCR) is set to 1. The o ther CCR bits and the general register s and

extended registers are not initialized. In particular, the stack poin ter (extended register E7 and

general register R7) is not initialized. Th e stack pointer must therefo r e be in itialized by an MOV.L

instruction executed immediately after a reset.

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1.5 Data Formats

The H8/300H CPU can process 1-bit, 4-bit, 8-bit (byte), 16-bit (word), and 32-bit (longword) data.

Bit-manipulation instructions op erate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte

operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit

BCD data.

1.5.1 General Register Data Formats

Figure 1.10 shows the data formats in general registers.

76543210 Don’t care

Don’t care 76543210

Don’t careUpper Lower

LSB

MSB LSB

Data type Register number Data format

1-bit data

4-bit BCD data

Byte data

RnH

RnL

RnH

RnL

RnH

RnL

MSB

Don’t care Upper Lower

Don’t care

Don’t care 70

Figure 1.10 General Register Data Formats

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MSB LSB

Word data

LSB

MSB

En Rn

General register ER

General register E

General register R

General register RH

General register RL

Most significant bit

Least significant bit

Legend:

ERn:

En:

Rn:

RnH:

RnL:

MSB:

LSB:

MSB LSB

Longword data ERn

Figure 1.10 General Register Data Formats (cont)

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1.5.2 Memory Data Formats

Figure 1.11 shows the data formats on memory. The H8/300H CPU can access word data and

longword data on memory, but word or longword data must begin at an even address. If an attempt

is made to access word or longword data at an odd address, no address error occurs but the least

significant bit of the address is regarded as 0, so the access starts at the preceding address. This

also applies to instruction fetches.

76543210

MSB LSB

MSB

LSB

MSB

LSB

Data type Data format

1-bit data

Byte data

Word data

Longword data

Address

Address L

Address 2M

Address 2M + 1

Address 2N

Address 2N + 1

Address 2N + 2

Address 2N + 3

Figure 1.11 Memory Data Formats

When ER7 is used as an address register to access the stack, the operand size should be word size

or longword size.

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1.6 Instruction Set

1.6.1 Overview

The H8/300H CPU has 62 types of instructions, which are classified by function in table 1.1. For a

detailed description of each instruction see section 2.2, Instruction Descriptions.

Table 1.1 Instruction Classification

Function Instructions Number

Data transfer MOV, PUSH*1, POP*2, MOVTPE, MOVFPE 3

Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,

DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS,

EXTU

Logic operations AND, OR, XOR, NOT 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8

Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,

BXOR, BIXOR, BLD, BILD, BST, BIST 14

Branch Bcc*2, JMP, BSR, JSR, RTS 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9

Block data transfer EEPMOV 1

Total 62 types

Notes: The shaded instructions are not present in the H8/300 instruction set.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@–SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L

ERn, @–SP.

2. Bcc is the generic designation of a conditional branch instruction.

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1.6.2 Instructions and Addressing Modes

Table 1.2 indicates the instructions available in the H8/300H CPU.

Table 1.2 Instruction Set Ov erview

Addressing Modes

Function Instruction

#xx

@ERn

@(d:16,ERn)

@(d:24,ERn)

@ERn+/@–ERn

@aa:8

@aa:16

@aa:24

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

MOV BWLBWL BWLBWLBWL BWLBBWLBWL————Data

transfer POP, PUSH————————————W

MOVFPE,

MOVTPE ———————B————

ADD, CMP BWL BWL———————————Arithmetic

operations SUB WL BWL———————————

ADDX,

SUBX B B———————————

ADDS,

SUBS —L

*1———————————

INC, DEC — BWL———————————

DAA, DAS —B———————————

MULXU,

DIVXU —BW———————————

MULXS,

DIVXS —BW———————————

NEG — BWL———————————

EXTU, EXTS — WL———————————

AND, OR,

XOR BWL BWL———————————Logic

operations

NOT — BWL———————————

Shift — BWL———————————

Bit manipulation — B B — — — B — — — — — —

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Addressing Modes

Function Instruction

#xx

@ERn

@(d:16,ERn)

@(d:24,ERn)

@ERn+/@–ERn

@aa:8

@aa:16

@aa:24

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

Branch Bcc, BSR ————————— ——

JMP, JSR — — ————— *2—— —

RTS ————————————

TRAPA ————————————System

control RTE ————————————

SLEEP ————————————

LDC B B WWWW—WW————

STC — B WWWW—WW————

ANDC,

ORC,

XORC

B————————————

NOP ————————————

EEPMOV.B————————————Block data

transfer EEPMOV.W————————————

Legend:

B: Byte

W: Word

L: Longword

: Newly added instruction in H8/300H CPU

Notes: 1. The operand size of the ADDS and SUBS instructions of the H8/300H CPU has been

changed to longword size. (In the H8/300 CPU it was word size.)

2. Because of its larger address space, the H8/300H CPU uses a 24-bit absolute address

for the JMP and JSR instructions. (The H8/300 CPU used 16 bits.)

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1.6.3 Tables of Instructions Classified by Function

Table 1.3 summarizes the instructions in each functional category. The no tation used in table 1.3

is defined next.

Operation Notation

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

CCR Condition cod e regist er

N N (negative) bit of CCR

Z Z (zero) bit of CCR

V V (overflow) bit of CCR

C C (carry) bit of CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

– Subtraction

×Multiplication

÷ Division

∧AND logical

∨OR logical

⊕Exclusive OR logical

→Move

¬Not

:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length

Note: *General registers include 8-bit registers (R0H/R0L to R7H/R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32 -bit registers (ER0 to ER7).

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Table 1.3 Instructions Classified by Functio n

Type Instruction Size*Function

Data transfer MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between

a general register and memory, or moves immediate

data to a general register.

MOVFPE B (EAs) → Rd

Moves external memory contents (addressed by

@aa:16) to a general register in synchronization with

an E clock.

MOVTPE B Rs → (EAd)

Moves general register contents to an external memory

location (addressed by @aa:16) in synchronization with

an E clock.

POP W/L @SP+ → Rn

Pops a register from the stack. POP.W Rn is identical

to MOV.W @SP+, Rn. POP.L ERn is identical to

MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a register onto the stack. PUSH.W Rn is

identical to MOV.W Rn, @–SP. PUSH.L ERn is

identical to MOV.L ERn, @–SP.

Arithmetic

operations ADD

SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general

registers, or on immediate data and data in a general

from data in a general register. Use the SUBX or ADD

instruction.)

ADDX

SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow

on byte data in two general registers, or on immediate

data and data in a general register.

INC

DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2.

(Byte operands can be incremented or decremented by

1 only.)

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Type Instruction Size*Function

Arithmetic

operations ADDS

SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in

a 32-bit register.

DAA

DAS B Rd decimal adjust → Rd

Decimal-a dju st s an additi on or subtrac t io n result in a

general register by referring to the CCR to produce 4-

bit BCD data.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general

registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16

bits → 32 bits.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general

registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16

bits → 32 bits.

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general

registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-

bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and

16-bit remainder.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general

registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-

bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and

16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in

another general register or with immediate data, and

sets the CCR according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two’s complement (arithmetic complement)

of data in a general register.

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Type Instruction Size*Function

Arithmetic

operations EXTS W/L Rd (sign extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register

to word data, or extends word data in the lower 16 bits

of a 32-bit register to longword data, by extending the

sign bit.

EXTU W/L Rd (zero extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register

to word data, or extends word data in the lower 16 bits

of a 32-bit register to longword data, by padding with

zeros.

Logic operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register

and another general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register

and another general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general

data.

NOT B/W/L ¬ (Rd) → (Rd)

Takes the one’s complement of general register

contents.

Shift operations SHAL

SHAR B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register

contents.

SHLL

SHLR B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

ROTL

ROTR B/W/L Rd (rotate) → Rd

Rotates general register contents.

ROTXL

ROTXR B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry bit.

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Type Instruction Size*Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory

operand to 1. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

Bit-manipulation

instructions

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory

operand to 0. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory

operand. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory

operand and sets or clears the Z flag accordingly. The

bit number is specified by 3-bit immediate data or the

lower three bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general

carry flag.

BIAND B C ∧ ¬ (<bit-No.> of <EAd>) → C

ANDs the carry flag with the inverse of a specified bit in

a general register or memory operand and stores the

result in the carry flag.

The bit number is specified by 3-bit immediate data.

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Type Instruction Size*Function

Bit-manipulation

instructions

BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general

carry flag.

BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C

ORs the carry flag with the inverse of a specified bit in

a general register or memory operand and stores the

result in the carry flag.

The bit number is specified by 3-bit immediate data.

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with a specified bit in a

general register or memory operand and stores the

result in the carry flag.

BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C

Exclusive-ORs the carry flag with the inverse of a

specified bit in a general register or memory operand

and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or

memory operand to the carry flag.

BILD B ¬ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a

general register or memory operand.

BIST B ¬ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a

specified bit in a general register or memory operand.

The bit number is specified by 3-bit immediate data.

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Type Instruction Size*Function

Branching

instructions Bcc — Branches to a specified address if a specified condition

is true. The branching conditions are listed below.

Mnemonic Description Condition

BRA(BT) Always (true) Always

BRN(BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

Bcc(BHS) Carry clear

(high or same) C = 0

BCS(BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z ∨ (N ⊕ V) = 0

BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP — Branches unconditionally to a specified address.

BSR — Branches to a subroutine at a specified address.

JSR — Branches to a subroutine at a specified address.

RTS — Returns from a subroutine.

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Type Instruction Size*Function

TRAPA — Starts trap-instruction exception handling.

System control

instructions RTE — Returns from an exception-handling routine.

SLEEP — Causes a transition to the power-down state.

LDC B/W (EAs) → CCR

Moves the sour ce opera nd cont ents to the condit ion

code register. Byte transfer is performed in the #xx:8,

Rs addressing mode and word transfer in other

addressing modes.

STC B/W CCR → (EAd)

Transfers the CCR contents to a destination loca tion.

Byte transfer is performed in the Rd addressing mode

and word transfer in other addressing modes.

ANDC B CCR ∧ #IMM → CCR

Logically ANDs the condition code register with

immediate data.

ORC B CCR ∨ #IMM → CCR

Logically ORs the condition code register with

immediate data.

XORC B CCR ⊕ #IMM → CCR

Logically ex clu si ve-O R s the cond iti on code register

with immediate data.

NOP — PC + 2 → PC

Only increments the program counter.

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Type Instruction Size*Function

Block data

transfer

instruction

EEPMOV.B — if R4L ≠ 0 then

Repeat @ER5 +→ @ER6 +

R4L – 1→R4L

Until R4L = 0

else next;

EEPMOV.W — if R4 ≠ 0 then

Repeat @ER5 +→ @ER6 +

R4 – 1→R4L

Until R4 = 0

else next;

Transfers a data block according to parameters set in

general registers R4L or R4, ER5, and R6.

R4L or R4: size of block (bytes)

ER5: starting source address

R6: starting destination address

Execution of the next instruction begins as soon as the

transfer is completed.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

1.6.4 Basic Instruction Formats

The H8/300H instr uctions consist of 2-b yte (1-word) units. An instruction consists of an oper ation

field (OP field), a register f ield ( r field) , an eff ectiv e addr ess extension (EA field), and a condition

field (cc).

Operation Field: Indicates the function of the instruction, the effective address, and the operation

to be carried out on the operand. The operation field always includes the first four bits of the

instruction. Some instructions have two operation fields.

registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register

field.

Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute

address, or a displacement. A 24-bit address or a displacement is treated as 32-bit data in which

the first 8 bits are 0.

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Condition Field: Specifies the branch ing condition of Bcc instructions.

Figure 1.12 shows examples of instruction formats.

op rn rm

NOP, RTS, etc.

ADD. Rn, Rm, etc.

MOV @(d:16, Rn), Rm

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

rn rm

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA @(d:8, PC)

Figure 1.12 Instruction Formats

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1.6.5 Addressing Modes and Effective Address Ca lculation

(1) Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 1.4. Each instruction uses a

subset of these addressing modes. Arithmetic and logic instructions can use the register direct and

immediate modes. Data transfer instructions can use all addressing modes except program-coun ter

relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or

absolute (8-bit) addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT,

and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the

operand.

Table 1.4 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn)

4 Register indirect with post-increment

@–ERn

5 Absolute addres s @aa:8/@aa:16/@aa:24

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

1 Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general

R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit

registers.

2 Register Indirect—@ERn: The register field of the instruction code specifies an address

3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit

displacement contained in the instruction is added to an address register (an extended register

paired with a general register) specified by the register field of the instruction, and the lower 24

bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended

when added.

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4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn), the lower 24 bits

of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is

added to the address register contents (32 bits) and the sum is stored in the address register.

The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or

longword access, the register value should be even.

• Register indirect with pre-decrem ent—@–ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the lower 2 4 bits of the result becom e s the address of a memory

operand. The result is also stored in the address register. The value subtracted is 1 for byte

access, 2 for word access, or 4 for longword access. For word or long word access, the resulting

5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute

address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long

(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all

assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension.

A 24-bit absolute address can access the entire address space. Table 1.5 indicates the accessible

address ranges.

Table 1.5 Absolute Address Access Ranges

Normal Mode Advanced Mode

8 bits

(@aa:8) H'FF00 to H'FFFF

(65,280 to 65,535) H'FFFF00 to H'FFFFF

(16,776,960 to 16,777,215)

16 bits

(@aa:16) H'0000 to H'FFFF

(0 to 65,535) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF

(0 to 32,767, 16,744,448 to 16,777,215)

24 bits

(@aa:24) H'0000 to H'FFFF

(0 to 65,535) H'00000 to H'FFFFF

(0 to 16,777,215)

For further details on the accessible range, see the relevant microcontro ller hardware manual.

6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16),

or 32-bit (#xx:32) immediate data as an operand.

The ADDS, SUBS, INC, and DEC instructions con tain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the second or fourth byte of the

instruction , specifying a bit numb er. The TRAPA instruction contain s 2-bit immediate data in the

second byte of the instruction, specifying a vector address.

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7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and

BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and

added to the 24-bit program counter (PC) contents to generate a branch address. The PC value to

which the displacement is added is the address of the first byte of the next in struction, so the

possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes

(–16383 to +16384 words) from the branch instruction. The resulting valu e should be an even

number.

8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

second byte of the instruction specifies a memory operand by an 8-bit absolute address. This

memory operand contains a branch address. The upper 8 bits of the absolute address are assumed

to be 0 (H'00), so the address range is 0 to 255 (H’0000 to H’00FF in normal mode, H'000000 to

H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the

branch address is 16 bits long. In advanced mode the memory operand is a longword operand. The

first byte is ignored and the branch address is 24 bits long. Note that the first part of the address

range is also the exception vector area. For further details see the relevant microcontroller

hardware manual.

(a) Normal mode (b) Advanced mode

Branch address

Specified

by @aa:8 Specified

by @aa:8 Reserved

Branch address

Figure 1.13 Branch Address Specification in Memory Indirect Mode

If an odd address is specified in word or longword memory access, or as a branch address, the

least significant bit is regarded as 0, causing access to be performed at the address preceding the

specified address. [See (2) Memory Data Formats in section 1.5.2 for further information.]

(2) Effective Address Calculation

Table 1.6 indicates how effective addresses are calculated in each addressing mode. In normal

mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

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• Register indirect with post-increment

@ERn+

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

(1) Register direct Rn

op Regm Regn Operands are contents of regm and regn

op reg

@(d:16, ERn)

op reg disp

(3)

op reg

• Register indirect with pre-decrement

@–ERn

op reg

(4)

Sign extension disp

1, 2, or 4

Byte

Word

Longword

Operand Size Added Value

31 0

31 0 23 0

23 0

Table 1.6 Effective Address Calculation

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No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

(5)

@aa:8

op abs

Absolute address

@aa:16

@aa:24

op abs

abs

(6) Immediate #xx:8/#xx:16/#xx:32

23 08 7

H'FFFF

23 016 15

Sign

extension

23 0

Operand is immediate data.

op IMM

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Effective Address Calculation Effective Address (EA)No. Addressing Mode and Instruction Format

dispop

absop

31 0

23 0

PC contents

Sign

extension disp

23 0

23 016 15

23 0

023

23 8 7

8 7

H'0000 abs

Memory contents H'00

H'0000 abs

Memory contents

(7) Program-counter relative

@(d:8, PC)/@(d:16, PC)

(8) Memory indirect @@aa:8

Normal mode

Advanced mode

15 0

Legend:

reg, regm, regn: General registers

op: Operation field

disp: Displacement

abs: Absolute address

IMM: Immediate data

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Section 2 Instruction Descriptions

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Section 2 Instruction Descriptions

2.1 Tables and Symbols

This section explains how to read the tables describing each instruction. Note that the descriptions

of some instructions extend over two pages or more.

Mnemonic (f ull name): Gives the full and mnemonic names of the instruction.

Type: Indicates the type of instruction.

Operation: Describes the instruction in symbolic notation. (See section 2.1.2, Operation.)

Assembly-Language Format: Indicates the assembly-language format of the instruction. (See

section 2.1.1, Assembler Format.)

Operand Size: Indicates the available operand sizes.

Condition Code: I ndicates the effect of instr uction exe cution on the flag bits in the CCR. (See

section 2.1.3, Condition Code.)

Description: Describes the operation of the instruction in detail.

Available Registers: Indicates which registers can be specified in the register field of the

instruction.

Operand Format and Number of States Required for Execution: Shows the addressing modes

and instruction format together with the number of states required for execution.

Notes: Gives notes concerning execution of the instruction.

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2.1.1 Assembler Format

Example: ADD. B <EAs>, Rd

Destination operan

Source operand

Size

Mnemonic

The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a

limited set of operand sizes.

The symbol <EA> indicates that two or more addressing modes can be used. The H8/300H CPU

supports the eight addressing modes listed next. Effective address calculation is described in

section 1.7, Effective Address Calculation.

Symbol Addressing Mode

Rn Register direct

@ERn Register indirect

@(d:16, ERn)/@(d:24, ERn) Register indirect with displacement (16-bit or 24-bi t)

@ERn+, @–ERn Register indirect wi th post-increment or pre-decrement

@aa:8/16/24 Absolute address (8-bit, 16-bit, or 24-bit)

#xx:8/16/32 Immediate (8-bit, 16-bit, or 32-bit)

@(d:8, PC)/@(d:16, PC) Program-counter relative (8-bit or 16-bit)

@@aa:8 Memory indirect

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2.1.2 Operation

The symbols used in the operation descriptions are defined as follows.

Symbol Meaning

Rd General destin atio n regist er*

Rs General source r egi ster *

Rn General register*

ERd General destination register (address register or 32-bit register)

ERs General source register (address register or 32-bit register)

ERn General register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

PC Program counter

SP Stack pointer

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

disp Displacement

→Transfer from the operand on the left to the operand on the right, or transition

from the state on the left to the state on the right

+ Addition of the operands on both sides

– Subtraction of the operand on the right from the operand on the left

×Multiplication of the operands on both sides

÷Division of the operand on the left by the operand on the right

∧Logical AND of the operands on both sides

∨Logical OR of the operands on both sides

⊕Logical exclusive OR of the operands on both sides

¬Logical NOT (logical complement)

( ) < > Contents of effective address of the operand

Note: *General registers include 8-bit registers (R0H to R7H and R0L to R7L), 16-bit registers

(R0 to R7 ad E0 to E7) and 32-bit registers.

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2.1.3 Condition Code

The symbols used in the condition-code description are defined as follows.

Symbol Meaning

↔

Changes according to the result of the instruction

* Undetermined (no guaranteed value)

0 Always cleared to 0

— Not affected by execution of the instruction

∆Varies depending on conditions; see the notes.

2.1.4 Instruction Format

The symbols used in the instruction format descriptions are listed below.

Symbol Meaning

IMM Immediate data (2, 3, 8, 16, or 32 bits)

abs Absolute address (8, 16, or 24 bits)

disp Displacement (8, 16, or 24 bits)

rs, rd, rn Register number (4 bits. The symbol rs corresponds to operand symbols such

as Rs. The symbol rd corresponds to operand symbols such as Rd. The symbol

rn corresponds to the operand symbol Rn.)

ers, erd, ern Register number (3 bits. The symbol ers corresponds to operand symbols such

as ERs. The symbol erd corresponds to operand symbols su ch as ERd and

@ERd. The symbol ern corresponds to the operand symbol ERn.)

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2.1.5 Register Specification

Address Register Specification: When a general register is used as an address register [@ERn,

@(d:16, ERn), @(d:24, ERn), @ERn+, or @–ERn], the register is specified by a 3-bit register

field (ers or erd). The lower 24 bits of the register are valid.

Data Register Specification: A general register can be used as a 32-bit, 16-bit, or 8-bit data

longword data register, it is specified by a 3-bit register field (ers, erd, or ern). When a 16-bit

lower 3 bits sp ecif y the register number. The upper bit is set to 1 to specify an extended r egister

(En) or cleared to 0 to specify a general register (Rn). When an 8-bit register is used as a byte data

number. The upper bit is set to 1 to specify a low register (RnL) or cleared to 0 to specify a high

Address Register

32-bit Register 16-bit Register 8-bit Register

Field General

000

001

111

ER0

ER1

ER7

0000

0001

0111

1000

1001

1111

0000

0001

0111

1000

1001

1111

R0H

R1H

R7H

E0L

E1L

E7L

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2.1.6 Bit Data Access in Bit Manipulation Instructions

Bit data is accessed as the n-th bit (n = 0, 1, 2, 3, …, 7) of a byte operand in a general register or

memory. The bit number is given by 3-bit immediate data, or by the lower 3 bits of a general

Example 1: To set bit 3 in R2H to 1

BSET R1L, R2H

R1L 011

Don’t care

001

R2H 10110

Bit number

Set to 1

Example 2: To load bit 5 at addr ess H'FFFF02 into the b it accumulator

BLD #5, @FFFF02

H'FF02 110

00101

Load

The operand size and addressing mode are as indicated fo r register or memory operand data.

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2.2 Instruction Descriptions

The instructions are described starting in section 2.2.1.

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2.2.1 (1) ADD (B)

ADD (ADD binary) Add Binary

Operation

Rd + (EAs) → Rd

Assembly-Language Format

ADD.B <EAs>, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a carry at bit 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 7;

otherwise cleared to 0.

Description

This instructio n adds the source operand to the contents of an 8-bit reg ister Rd (destination

operand) and stores the re sult in the 8-bit register Rd.

Available Registers

Rd: R0L to R7L, R0H to R7H

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate ADD. B #xx:8, Rd 8 rd IM M 2

Notes

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2.2.1 (2) ADD (W)

ADD (ADD binary) Add Binary

Operation

Rd + (EAs) → Rd

Assembly-Language Format

ADD.W <EAs>, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a carry at bit 11;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 15;

otherwise cleared to 0.

Description

This instructio n adds the source operand to the contents of a 16-bit reg ister Rd (destination

operand) and stores the re sult in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate ADD.W #xx:16, Rd 7 9 1 rd IMM 4

Notes

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2.2.1 (3) ADD (L)

ADD (ADD binary) Add Binary

Operation

ERd + (EAs) → ERd

Assembly-Language Format

ADD.L <EAs>, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a carry at bit 27;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 31;

otherwise cleared to 0.

Description

This instructio n adds the source operand to the contents of a 32-bit register ERd (destination

operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte No. of

States

Immediate ADD.L #xx:32, ERd 7 A 1 0 erd IMM 6

Notes

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2.2.2 ADDS

ADDS (ADD with Sign extension) Add Binary Address Data

Operation

Rd + 1 → ERd

Rd + 2 → ERd

Rd + 4 → ERd

Assembly-Language Format

ADDS #1, ERd

ADDS #2, ERd

ADDS #4, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

—— —— ————

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction adds the immediate value 1, 2, or 4 to the contents of a 32-bit register ERd.

Differing from the ADD instruction , it does n ot affect the condition code flags.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.3 ADDX

ADDX (ADD with eXtend carry) Add with Carry

Operation

Rd + (EAs) + C → Rd

Assembly-Language Format

ADDX <EAs>, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a carry at bit 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Previous value remains unchang ed if the

result is zero; otherwise cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 7;

otherwise cleared to 0.

Description

This instruction adds the source operand and carry flag to th e contents of an 8-bit register Rd

(destination register) and stores the resu lt in the 8-bit register Rd.

Available Registers

Rd: R0L to R7L, R0H to R7H

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate ADDX #xx:8, Rd 9 rd IMM 2

Notes

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2.2.4 (1) AND (B)

AND (AND logical) Logical AND

Operation

Rd ∧ (EAs) → Rd

Assembly-Language Format

AND.B <EAs>, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— 0 ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ANDs the source operand with the contents o f an 8- bit register Rd (destination

Available Registers

Rd: R0L to R7L, R0H to R7H

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immediate AND.B #xx:8, Rd E rd IMM 2

Notes

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2.2.4 (2) AND (W)

AND (AND logical) Logical AND

Operation

Rd ∧ (EAs) → Rd

Assembly-Language Format

AND.W <EAs>, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

——— 0 ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ANDs the source operand with the contents of a 16-bit register Rd (destination

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate AND.W #xx:16, Rd 7 9 6 rd IMM 4

Notes

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2.2.4 (3) AND (L)

AND (AND logical) Logical AND

Operation

ERd ∧ (EAs) → ERd

Assembly-Language Format

AND.L <EAs>, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

——— 0 ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ANDs the source operand with the contents o f a 32- bit register ERd (destination

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte No. of

States

Immediate AND.L #xx:32, ERd 7 A 6 0 erd IMM 6

Notes

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2.2.5 ANDC

ANDC (AND Control register) Logical AND with CCR

Operation

CCR ∧ #IMM → CCR

Assembly-Language Format

ANDC #xx:8, CCR

Operand Size

Byte

Condition Code

IUIHUNZVC

↔

I: Stores the corresponding bit of the result.

UI: Stores the corresponding bit of the result

H: Stores the corresponding bit of the result.

U: Stores the corresponding bit of the result

N: Stores the corresponding bit of the result.

Z: Stores the corresponding bit of the result.

V: Stores the corresponding bit of the result.

C: Stores the corresponding bit of the result.

Description

This instruction ANDs the contents of the condition - code register (CCR) with immediate data and

stores the result in the condition-code register. No interrupt requests, including NMI, are accepted

immediately af ter execution of this instru ction.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate ANDC #xx:8, CCR 0 6 IMM 2

Notes

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2.2.6 BAND

BAND (Bit AND) Bit Logical AND

Operation

C ∧ (<bit No.> of <EAd>) → C

Assembly-Language Format

BAND #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ——

↔

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Sto r es the result of the operation.

Description

This instruction ANDs a specified bit in the destination operand with the carry bit and stores the

result in the car r y bit. The bit number is specified by 3-bit immediate data. The destin ation

operand contents remain unchanged.

∧

Specified by #xx:3

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

0IMM rd 2

0erd 0 7 6 0IMM 0 6

Absolute address BA ND #xx:3.@aa:8 7E abs 7 6 0 IMM 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

See the corresponding LSI hardware manual for details on the access range for @aa : 8.

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2.2.7 Bcc

Bcc (Branch conditiona lly) Conditional Bra nch

Operation

If condition is tr ue, then

PC + disp → PC

else next;

Assembly-Language Format

Bcc disp

→ Condition field

Operand Size

—

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

If the condition specified in th e cond ition field (cc) is true, a displacement is added to the program

counter (PC) and execution br anches to the resulting address. The PC value used in the address

calculation is the starting address of the instruction immediately following the Bcc instruction.

The displacement is a signed 8-bit or 16-bit value. The branch destination address can be located

in the range from –126 to +128 bytes or –32766 to +32768 bytes from the Bcc instruction.

Mnemonic Meaning cc Condition Signed/Unsigned*

BRA (BT) Always (true) 0000 True

BRn (BF) Never (false) 0001 Fals e

BHI HIgh 0010 C ∨ Z = 0 X > Y (unsigned)

BLS Low or Same 0011 C ∨ Z = 1 X ≤ Y (uns i gned)

BCC (BHS) Carry Cl ear (High or Same) 0100 C = 0 X ≥ Y (unsigned)

BCS (BLO) Carry Set (LOw) 0101 C = 1 X < Y (unsigned)

BNE Not Equal 0110 Z = 0 X ≠ Y (unsigned or signed)

BEQ EQual 0111 Z = 1 X > Y (unsigned or signed)

BVC oVerflow Cl ear 1000 V = 0

BVS oVerfl ow Set 1001 V = 1

BPL PLus 1010 N = 0

BMI Minus 1011 N = 1

BGE Greater or Equal 1100 N ⊕ V = 0 X ≥ Y (signed)

BLT Less Than 1101 N ⊕ V = 1 X < Y (signed)

BGT Greater Than 1110 Z ∨ (N ⊕ V) = 0 X > Y (signed)

BLE Less or Equal 1111 Z ∨ (N ⊕ V) = 1 X ≤ Y (signed)

Note: *If the immedi ately preceding instruction is a CMP instructi on, X is the desti nat i o n operand and Y is the

source operand.

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Bcc

Bcc (Branch conditiona lly) Conditional Bra nch

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

BRA (BT) d:8 4 0 disp 4

Program-counter

relative d:16 5 8 0 0 disp 6

BRN (BF) d:8 4 1 disp 4Program-counter

relative d:16 5 8 1 0 disp 6

BHI d:8 4 2 disp 4Program-counter

relative d:16 5 8 2 0 disp 6

BLS d:8 4 3 disp 4Program-counter

relative d:16 5 8 3 0 disp 6

Bcc (BHS) d:8 4 4 disp 4Program-counter

relative d:16 5 8 4 0 disp 6

BCS (BLO) d:8 4 5 disp 4Program-counter

relative d:16 5 8 5 0 disp 6

BNE d:8 4 6 disp 4

Program-counter

relative d:16 5 8 6 0 disp 6

BEQ d:8 4 7 disp 4Program-counter

relative d:16 5 8 7 0 disp 6

BVC d:8 4 8 disp 4Program-counter

relative d:16 5 8 8 0 disp 6

BVS d:8 4 9 disp 4Program-counter

relative d:16 5 8 9 0 disp 6

BPL d:8 4 A disp 4Program-counter

relative d:16 5 8 A 0 disp 6

BMI d:8 4 B disp 4Program-counter

relative d:16 5 8 B 0 disp 6

BGE d:8 4 C disp 4

Program-counter

relative d:16 5 8 C 0 disp 6

BLT d:8 4 D disp 4Program-counter

relative d:16 5 8 D 0 disp 6

BGT d:8 4 E disp 4Program-counter

relative d:16 5 8 E 0 disp 6

BLE d:8 4 F disp 4Program-counter

relative d:16 5 8 F 0 disp 6

Notes

1. The branch destination address must be even.

2. In machine language BRA, BRN, BCC, and BCS are identical to BT, BF, BHS, and BLO,

respectively. The number of execution states for BRn (BF) is the same as for two NOP

instructions.

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2.2.8 BCLR

BCLR (Bit CLeaR) Bit Clear

Operation

0 → (<bit No.> of <EAd>)

Assembly-Language Format

BCLR #xx:3, <EAd>

BCLR Rn, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction clears a specified bit in the destination operand to 0. The bit number can be

specified by 3-bit immediate data, or by the lower three bits of a general register (Rn). The

specified bit is not tested. The condition-co de flags are not altered.

Specified by #xx:3 or Rn

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

Rn: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

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BCLR

BCLR (Bit CLeaR) Bit Clear

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address BCLR #xx:3, @aa:8 7 F abs 7 2 0 IMM 0 8

Absolute address BCLR Rn, @aa:8 7 F abs 6 2 rn 0 8

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.9 BIAND

BIAND (Bit Invert AND) Bit Logical AND

Operation

C ∧ [¬ (<bit No.> of <EAd>)] → C

Assembly-Language Format

BIAND #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ——

↔

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Sto r es the result of the operation.

Description

This instruction ANDs the inverse of a specified b it in the destin ation operand with the carry bit

and stores the result in the carry bit. The bit number is specified by 3-bit immediate data. The

destination operand contents remain unchanged.

C∧C

Specified by #xx:3

Bit No.

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address BIAND #xx: 3.@aa:8 7E abs 761IMM06

Note: * The addressing mode is the addressing mode of the destinati on operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.10 BILD

BILD (Bit Invert LoaD) Bit Load

Operation

¬ (<bit No.> of <EAd>) → C

Assembly-Language Format

BILD #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ——

↔

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Loaded with the inverse of the specified

bit.

Description

This instructio n loads the inverse o f a specified bit from the destin ation operand into th e carry bit.

The bit number is specified by 3-bit immediate data. The destination operand contents remain

unchanged.

Specified by #xx:3

Bit No.

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

1IMM rd 2

Absolute address B I LD #xx:3 . @ aa:8 7 E abs 7 7 1 IM M 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.11 BIOR

BIOR (Bit Invert inclusive OR) Bit Logical OR

Operation

C ∨ [¬ (<bit No.> of <EAd>)] → C

Assembly-Language Format

BIOR #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ——

↔

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Sto r es the result of the operation.

Description

This instructio n ORs the inverse o f a specified bit in the destination operand with the carry bit and

stores the resu lt in the carry bit. The bit number is sp ecif ied by 3-bit immediate data. The

destination operand contents remain unchanged.

C∨C

Specified by #xx:3

Bit No.

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address B I O R #xx: 3. @ aa:8 7E abs 741IMM06

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.12 BIST

BIST (Bit Invert STore) Bit Store

Operation

¬ C → (<bit No.> of <EAd>)

Assembly-Language Format

BIST #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instructio n stores the inverse of the carry bit in a specified bit locatio n in the destination

operand. The bit number is specified by 3-bit immediate data. Other bits in the destination operand

remain unchanged.

Specified by #xx:3

Bit No.

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address B IS T #xx: 3,@aa:8 7F abs 671IMM08

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.13 BIXOR

BIXOR (Bit Invert eXclusive OR) Bit Exclusive Logical OR

Operation

C ⊕ [¬ (<bit No.> of <EAd>)] → C

Assembly-Language Format

BIXOR #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ——

↔

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Sto r es the result of the operation.

Description

This instruction exclusively ORs the inverse of a specified bit in the destinatio n operand with the

carry bit and stores the result in the carry bit. The bit number is specified by 3-bit immediate data.

The destination operand contents remain unchanged.

Specified by #xx:3

⊕

Invert C

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address BIXOR #xx:3,@aa:8 7E abs 751IMM06

Note: * The addressing mode is the addressing mode of the destinati on operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.14 BLD

BLD (Bit LoaD) Bit Load

Operation

(<Bit No.> of <EAd>) → C

Assembly-Language Format

BLD #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ——

↔

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Loaded from the specified bit.

Description

This instructio n loads a specified bit fr om th e destination oper and into the carry bit. The bit

number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

07Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address BLD #xx:3,@aa:8 7E abs 770IMM06

Note: * The addressing mode is the addressing mode of the destinati on operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.15 BNOT

BNOT (Bit NOT) Bit NOT

Operation

¬ (<bit No.> of <EAd>) → (<bit No.> of

<EAd>)

Assembly-Language Format

BNOT #xx:3, <EAd>

BNOT Rn, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction inverts a specified bit in the destination operand. The bit number is specified by 3-

bit immediate data or by th e lower 3 bits of a general register. The specified bit is not tested. The

condition code remains unchanged.

70Bit No. Specified by #xx:3 or Rn

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

Rn: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

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BNOT

BNOT (Bit NOT) Bit NOT

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address BNOT #xx:3, @aa:8 7 F abs 7 1 0 IMM 0 8

Absolute address BNOT Rn, @aa:8 7 F abs 6 1 rn 0 8

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.16 BOR

BOR (bit inclusiv e OR) Bit Logical OR

Operation

C ∨ [(<bit No.> of <EAd>)] → C

Assembly-Language Format

BOR #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ——

↔

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Sto r es the result of the operation.

Description

This instruction ORs a specified bit in the destin ation operand with the carry bit and stores th e

result in the car r y bit. The bit number is specified by 3-bit immediate data. The destin ation

operand contents remain unchanged.

Specified by #xx:3

Bit No.

∨

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

0IMM rd 2

Absolute address BOR #xx:3,@aa:8 7 E abs 7 4 0 IMM 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.17 BSET

BSET (Bit SET) Bit Set

Operation

1 → (<bit No.> of <EAd>)

Assembly-Language Format

BSET #xx:3, <EAd>

BSET Rn, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instructio n sets a specified bit in the destination operand to 1. The bit number can be

specified by 3-bit immediate data, or by the lower three bits of a general register. The specified bit

is not tested. The condition code flags are not altered.

70Bit No.

Specified by #xx:3 or Rn

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

Rn: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

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BSET

BSET (Bit SET) Bit Set

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address BSET #xx:3, @aa:8 7 F abs 7 0 0 IMM 0 8

Absolute address BSET Rn, @aa:8 7 F abs 6 0 rn 0 8

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

<EAd> is byte data in a register or on memory.

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2.2.18 BSR

BSR (Branch t o SubRoutine) Branch to Subroutine

Operation

PC → @–SP

PC + disp → PC

Assembly-Language Format

BSR disp

Operand Size

—

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction branches to a subroutine at a specified address. It pushes the program counter

(PC) value onto the stack as a restart address, then adds a specified displacement to the PC value

and branches to the resulting address. The PC value pushed onto the stack is the address of the

instruction following the BSR instruction. The displacement is a signed 8-bit or 16-bit value, so

the possible branching range is –126 to +128 bytes or –32766 to +32768 bytes from the address of

the BSR instru ction.

Operand Format and Number of States Required for Execution

Instruction Format No. of States

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte Normal Advanced

d:8 5 5 disp 6 8Program-counter

relative BSR

d:16 5 C 0 0 disp 8 10

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BSR

BSR (Branch t o SubRoutine) Branch to Subroutine

Notes

The stack structure differs between normal mode and advanced mode. In normal mode only the

lower 16 bits of the program counter are pushed on the stack.

PC 23 16 15 8 7 0 Normal mode

PC 23 16 15 8 7 0 Advanced mode

Reserved

The branch address must be even.

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2.2.19 BST

BST (Bit STore) Bit Stor e

Operation

C → (<bit No.> of <EAd>)

Assembly-Language Format

BST #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instructio n stores the carry bit in a specified bit location in the destination operand. The b it

number is specified by 3-bit immediate data. Other bits in the destination operand remain

unchanged.

Specified by #xx:3

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

0IMM rd 2

Absolute address BST #xx:3,@aa:8 7 F abs 6 7 0 IMM 0 8

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.20 BTST

BTST (Bit TeST) Bit Test

Operation

¬ (<Bit No.> of <EAd>) → Z

Assembly-Language Format

BTST #xx:3, <EAd>

BTST Rn, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ——

↔

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Set to 1 if the specif ied bit is zero ;

otherwise cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction tests a specified b it in the destinatio n operand and sets or clears the Z flag

according to the result. The bit number can be specified by 3-bit immediate data, or by the lower

three bits of a general register. The destination operand remains unchanged.

70Bit No.

Test

Specified by #xx:3 or Rn

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

Rn: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

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BTST

BTST (Bit TeST) Bit Test

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address BTST #xx:3, @aa:8 7 E abs 7 3 0 IMM 0 6

Absolute address BTST Rn, @aa: 8 7 E abs 6 3 rn 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.21 BXOR

BXOR (Bit eXclusive OR) Bit Exclusive Logical OR

Operation

C ⊕ (<bit No.> of <EAd>) → C

Assembly-Language Format

BXOR #xx:3, <EAd>

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ——

↔

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Sto r es the result of the operation.

Description

This instructio n exclusively ORs a sp ecif ied bit in the destination operand with the carry bit and

stores the resu lt in the carry bit. The bit number is sp ecif ied by 3-bit immediate data. The

destination operand contents remain unchanged.

Specified by #xx:3

Bit No.

⊕

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode*Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address BXOR #xx: 3,@aa:8 7E abs 750IMM06

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.22 (1) CMP (B)

CMP (CoMPare) Compare

Operation

Rd – (EAs), set or clear CCR

Assembly-Language Format

CMP.B <EAs>, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a borrow at bit 3 ;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 7;

otherwise cleared to 0.

Description

This instruction subtracts the source operand from the contents of an 8-bit register Rd (destination

remain unchanged.

Available Registers

Rd: R0L to R7L, R0H to R7H

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate CMP.B #xx:8, Rd A rd IM M 2

Notes

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REJ09B0213-0300

2.2.22 (2) CMP (W)

CMP (CoMPare) Compare

Operation

Rd – (EAs), set CCR

Assembly-Language Format

CMP.W <EAs>, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a borrow at bit 11;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 15;

otherwise cleared to 0.

Description

This instruction subtracts the source operand from the contents of a 16-bit register Rd (destination

Rd remain unchanged.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate CMP.W #xx:16, Rd 7 9 2 rd IMM 4

Notes

Section 2 Instruction Descriptions

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REJ09B0213-0300

2.2.22 (3) CMP (L)

CMP (CoMPare) Compare

Operation

ERd – (EAs), set CCR

Assembly-Language Format

CMP.L <EAs>, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

—— —

↔

I: Previous value remains unchanged.

H: Set to 1 if there is a borrow at bit 2 7;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 31;

otherwise cleared to 0.

Description

This instruction subtracts the source operand from the contents of a 32 -bit register ERd

(destination register) and sets or clears the CCR bits according to the result. The contents of the

32-bit register ERd remain unchanged.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte No. of

States

Immediate CMP.L #xx:32, ERd 7 A 2 0 erd IMM 6

Notes

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REJ09B0213-0300

2.2.23 DAA

DAA (Decimal Adjust Add) Decimal Adjust

Operation

Rd (decimal adjust) → Rd

Assembly-Language Format

DAA Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

—— **

—

↔

H: Undete rmined (no guaranteed value).

N: Set to 1 if the adjusted re sult is negative;

otherwise cleared to 0.

Z: Set to 1 if the adjusted re sult is zero;

otherwise cleared to 0.

V: Undete rmined (no guaranteed value).

C: Set to 1 if there is a carry at bit 7;

otherwise left unchanged.

Description

Given that the resu lt of an addition operation performed by an ADD.B or ADDX instruction on

4-bit BCD data is contained in an 8-bit register Rd (destination register) and the carry and half-

carry flags, the DAA instruction adjusts the general register contents by adding H'00, H'06, H'60,

or H'66 according to the table below.

C Flag

before

Adjustment

Upper 4 Bits

before

Adjustment

H Flag

before

Adjustment

Lower 4 Bits

before

Adjustment

Value Added

(hexadecimal)

C Flag

after

Adjustment

0 0 to 9 0 0 to 9 00 0

0 0 to 8 0 A to F 06 0

0 0 to 9 1 0 to 3 06 0

0 A to F 0 0 to 9 60 1

0 9 to F 0 A to F 66 1

0 A to F 1 0 to 3 66 1

1 1 to 2 0 0 to 9 60 1

1 1 to 2 0 A to F 66 1

1 1 to 3 1 0 to 3 66 1

Available Registers

Rd: R0L to R7L, R0H to R7H

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 77 of 258

REJ09B0213-0300

DAA

DAA (Decimal Adjust Add) Decimal Adjust

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Valid results (8 -bit register Rd contents and C, V, Z, N, and H flags) are not assu red if this

instruction is executed under conditions other than those described above.

Section 2 Instruction Descriptions

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REJ09B0213-0300

2.2.24 DAS

DAS (Decimal Adju st Subtract) Decimal Adjust

Operation

Rd (decimal adjust) → Rd

Assembly-Language Format

DAS Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

—— —

—

↔

H: Undete rmined (no guaranteed value).

N: Set to 1 if the adjusted re sult is negative;

otherwise cleared to 0.

Z: Set to 1 if the adjusted re sult is zero;

otherwise cleared to 0.

V: Undete rmined (no guaranteed value).

C: Previous value remains unchanged.

Description

Given that the result of a subtraction operation performed by a SUB.B, SUBX.B, or NEG.B

instruction on 4-bit BCD data is contained in an 8-bit register Rd (destination register) and the

carry and half-carry flags, the DAS instruction adjusts the general register contents by adding

H'00, H'FA, H'A0, or H'9A according to the table below.

C Flag

before

Adjustment

Upper 4 Bits

before

Adjustment

H Flag

before

Adjustment

Lower 4 Bits

before

Adjustment

Value Added

(hexadecimal)

C Flag

after

Adjustment

0 0 to 9 0 0 to 9 00 0

0 0 to 8 1 6 to F FA 0

1 7 to F 0 0 to 9 A0 1

1 6 to F 1 6 to F 9A 1

Available Registers

Rd: R0L to R7 L, R0H to R7H

Section 2 Instruction Descriptions

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REJ09B0213-0300

DAS

DAS (Decimal Adju st Subtract) Decimal Adjust

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Valid results (8 -bit register Rd contents and C, V, Z, N, and H flags) are not assu red if this

instruction is executed under conditions other than those described above.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 80 of 258

REJ09B0213-0300

2.2.25 (1) DEC (B)

DEC (DECrement) Decrement

Operation

Rd – 1 → Rd

Assembly-Language Format

DEC.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs (the

previous value in Rd was H'80); otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction decrements an 8-bit register Rd (destination register) and stores the result in the 8-

bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

An overflow is caused by the operation H'80 – 1 → H'7F.

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REJ09B0213-0300

2.2.25 (2) DEC (W)

DEC (DECrement) Decrement

Operation

Rd – 1 → Rd

Rd – 2 → Rd

Assembly-Language Format

DEC.W #1, Rd

DEC.W #2, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

——— ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs (the

previous value in Rd was H'8000);

otherwise cleared to 0.

C: Previous value remains unchanged.

Description

This instruction subtracts the immediate value 1 or 2 from the contents of a 16-bit register Rd

(destination register) and stores the resu lt in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

An overflow is caused by the operations H'8000 – 1 → H'7FFF, H'8000 – 2 → H'7FFE, and

H'8001 – 2 → H'7FFF.

Section 2 Instruction Descriptions

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REJ09B0213-0300

2.2.25 (3) DEC (L)

DEC (DECrement) Decrement

Operation

ERd – 1 → ERd

ERd – 2 → ERd

Assembly-Language Format

DEC.L #1, ERd

DEC.L #2, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

——— ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction subtracts the immediate value 1 or 2 from the contents of a 32-bit register ERd

(destination register) and sto res the result in the 32-b it register ERd.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

An overflow is caused by the operations H'80000000 – 1 → H'7FFFFFFF, H'80000000 – 2 →

H'7FFFFFFE, an d H'80000001 – 2 → H'7FFFFFFF.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 83 of 258

REJ09B0213-0300

2.2.26 (1) DIVXS (B)

DIVXS (DIVide eXtend as Signed) Divide Signed

Operation

Rd ÷ Rs → Rd

Assembly-Language Format

DIVXS.B Rs, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— ———

↔

H: Previous value remains unchanged.

N: Set to 1 if the quotien t is n e gative;

otherwise cleared to 0.

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction divides the contents of a 16-bit register Rd (destination register) by the contents of

an 8-bit register Rs (source register) and stores the result in the 16-bit register Rd. The division is

signed. The operation performed is 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder. The

quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd.

Rd Rs Rd

Dividend ÷Divisor →Remainder Quotient

16 bits 8 bits 8 bits 8 bits

Valid results are not assured if division by zero is attempted or an overflow occurs. For

information on avoiding overflow, see DIVXS Instruction, Zero Divide, and Overflow.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0L to R7L, R0 H to R7H

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 84 of 258

REJ09B0213-0300

DIVXS (B)

DIVXS (DIVide eXtend as Signed) Divide Signed

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have

the same sign. The N flag may therefore be set to 1 when the quotient is zero.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 85 of 258

REJ09B0213-0300

2.2.26 (2) DIVXS (W)

DIVXS (DIVide eXtend as Signed) Divide Signed

Operation

ERd ÷ Rs → ERd

Assembly-Language Format

DIVXS.W Rs, ERd

Operand Size

Word

Condition Code

IUIHUNZVC

——— ———

↔

H: Previous value remains unchanged.

N: Set to 1 if the quotien t is n e gative;

otherwise cleared to 0.

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction divides the contents of a 32-bit register ERd (destination register) by the contents

of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The

division is signed. The operation performed is 32 bits ÷ 16 bits → 16-bit quotient and 16-bit

remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The

remainder is placed in the upper 16 bits (Ed).

ERd Rs ERd

Dividend ÷Divisor →Remainder Quotient

32 bits 16 bits 16 bits 16 bits

Valid results are not assured if division by zero is attempted or an overflow occurs. For

information on avoiding overflow, see DIVXS Instruction, Zero Divide, and Overflow.

Available Registers

ERd: ER0 to ER7

Rs: R0 to R7, E0 to E7

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 86 of 258

REJ09B0213-0300

DIVXS (W)

DIVXS (DIVide eXtend as Signed) Divide Signed

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have

the same sign. The N flag may therefore be set to 1 when the quotient is zero.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 87 of 258

REJ09B0213-0300

2.2.26 (3) DIVXS

DIVXS (DIVide eXtend as Signed) Divide Signed

DIVXS instruction, Division by Zero, and Overflow

Since the DIVXS instruction does not detect division by zero or overflow, applications should

detect and handle division by zero and overflow using techniques similar to those used in the

following program.

1. Programming solutio n fo r DIVXS.B R0L, R1

Example 1: Convert dividend and divisor to non-negative numbers, then use DIVXU

programming solution for zero divide and overflow

MOV.B R0L, R0L ; Test divisor

BEQ ZERODIV ; B ranch to ZERODIV if R0L = 0

ANDC #AF, CCR ; Clear CCR user bits (bits 6 and 4) to 0

BPL L1 ; Branch to L1 if N flag = 0 (positive divisor)

NEG.B R0L ; Take 2’s complement of R0L to make sign positive

ORC #10, CCR ; S et CCR bit 4 to 1

L1: MOV.W R1.R1 ; Test dividend

BPL L2 ; Branch to L2 if N flag = 0 (positive dividend)

NEG.W R1 ; Take 2’s complement of R1 to make sign positive

XORC #50, CCR ; I nvert CCR bits 6 and 4

L2: MOV.B R1H, R2L ;

EXTU.W R2 ;

DIVXU.B R0L, R2 ; Us e DIV XU.B instruction to divide non-negative dividend

MOV.B R2H, R1H ; by positive divisor

DIVXU.B R0L, R1 ; 16 bits ÷ 8 bits → quotient (16 bits) and remainder (8 bits)

MOV.B R2L, R2H ; (See DIVXU Instruction, Zero Divi de, and Overf l ow)

MOV.B R1L, R2L ;

STC CCR, R1L ; Copy CCR contents to R1L

BTST #6, R1L ; Test CCR bit 6

BEQ L3 ; Branch to L3 if bit 6 = 1

NEG.B R1H ; Take 2’s complement of R1H to make sign of remainder negative

L3: BTST #4, R1L ; Test CCR bit 4

BEQ L4 ; Branch to L4 if bit 4 = 1

NEG.W R2 ; Take 2’s complement of R2 to make sign of quotient negative

L4: RTS

ZERODIV: ; Zero-div i de handl i ng routine

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 88 of 258

REJ09B0213-0300

DIVXS

DIVXS (DIVide eXtend as Signed) Divide Signed

This program leaves a 16-bit quotient in R2 and an 8-bit remainder in R1H.

R1H

R0L Divisor

Dividend

Remainder

Quotient

Example 2: Sign extend the 8-bit divisor to 16 bits, sign extend the 16-bit dividend to 32 bits, and

then use DIVXS to divide

EXTS.W R0

BEQ ZERODIV

EXTS.L ER1

DIVXS.L R0,ER1

RTS

ZERODIV:

This program leaves the 16-bit quotient in R1 and the 8-bit remainder in E1 (in a 16-bit sign

extended format) .

ROL

ER1

R0L

Dividend

Divisor

Sign extension

Divisor

DividendSign extension

QuotientRemainder

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 89 of 258

REJ09B0213-0300

DIVXS

DIVXS (DIVide eXtend as Signed) Divide Signed

2. Programming solution for DIVXS.W R0, ER1

Example: Convert dividend and divisor to non-negative numbers, then use DIVXU programming

solution for zero divide and overflow

MOV.W R0, R0 ; Test divisor

BEQ ZERODIV ; Branch to ZERODIV if R0 = 0

ANDC #AF, CCR ; Clear CCR user bits (bits 6 and 4) to 0

BPL L1 ; Branch to L1 if N flag = 0 (positive divisor)

NEG.W R0 ; Take 2’s complement of R0 to make sign positive

ORC #10, CCR ; Set CCR bit 4 to 1

L1: MOV.L ER1,ER1 ; Test dividend

BPL L2 ; Branch to L2 if N flag = 0 (positive dividend)

NEG.L ER1 ; Take 2’s complement of ER1 to make sign positive

XORC #50,CCR ; Inve rt CCR bi ts 6 and 4

L2: MOV.W E1, R2 ;

EXTU.L ER2 ;

DIVXU.W R0, E2 ; Use DIVXU.W inst ruction to divide non-negative dividend

MOV.W E2, R1 ; by posit iv e divisor

DIVXU.W R0, ER1 ; 32 bits ÷ 16 bits → quotient (32 bits) and remainder

MOV.W R2, E2 (16 bi ts)

MOV.W R1, R2 (See DIVXU Instructi on, Zero Divi de, and Overf l ow)

STC CCR, R1L ; Copy CCR contents to R1L

BTST #6, R1L ; T e st CCR bit 6

BEQ L3 ; Branch to L3 if bit 6 = 1

NEG.W E1 ; Take 2’s complement of E1 to make sign of remainder negative

L3: BTST #4, R1L ; Test CCR bi t 4

BEQ L4 ; Branch to L4 if bit 4 = 1

NEG.L ER2 ; Take 2’s complement of ER2 to make sign of quotient negative

L4: RTS

ZERODIV: ; Zero-divide handli ng routine

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 90 of 258

REJ09B0213-0300

DIVXS

DIVXS (DIVide eXtend as Signed) Divide Signed

This program leaves a 32-bit quotient in ER2 and a 16-bit remainder in E1.

ER1

ER2

R0 Divisor

Dividend

Remainder

Quotient

The preceding two examples flag the status of the divisor and dividend in the UI and U bits in the

CCR, and modify the sign of the quotient and remainder in the unsigned division result of the

DIVXU instruction as sh own next.

UI U Divisor Dividend Remainder Quotient Sign Modification

0 0 Positive Positive Positive Positive No sign modification

0 1 Negative Positive Positive Negative Sign of quotient is reversed

1 0 Negative Negative Negative Positive Sign of remainder is reversed

1 1 Positive Negative Negative Negative Signs of quotient and remainder

are both reversed

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 91 of 258

REJ09B0213-0300

2.2.27 (1) DIVXU (B)

DIVXU (DIVide eXtend as Unsigned) Divide

Operation

Rd ÷ Rs → Rd

Assembly-Language Format

DIVXU.B Rs, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— ———

↔

H: Previous value remains unchanged.

N: Set to 1 if the divisor is negative;

otherwise cleared to 0.

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction divides the contents of a 16-bit register Rd (destination register) by the contents of

an 8-bit register Rs (source register) and stores the result in the 16-bit register Rd. The division is

unsigned. The operation performed is 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder. The

quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd.

Rd Rs Rd

Dividend ÷Divisor →Remainder Quotient

16 bits 8 bits 8 bits 8 bits

Valid results are not assured if division by zero is attempted or an overflow occurs. For

information on avoiding overflow, see DIVXU Instruction, Zero Divide, and Overflow.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 92 of 258

REJ09B0213-0300

2.2.27 (2) DIVXU (W)

DIVXU (DIVide eXtend as Unsigned) Divide

Operation

ERd ÷ Rs → ERd

Assembly-Language Format

DIVXU.W Rs, ERd

Operand Size

Word

Condition Code

IUIHUNZVC

——— ———

↔

H: Previous value remains unchanged.

N: Set to 1 if the divisor is negative;

otherwise cleared to 0.

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction divides the contents of a 32-bit register ERd (destination register) by the contents

of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The

division is unsigned. The operation performed is 32 bits ÷ 16 bits → 16-bit quotient and 16-bit

remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The

remainder is placed in the upper 8 bits of (Ed).

ERd Rs ERd

Dividend ÷Divisor →Remainder Quotient

32 bits 16 bits 16 bits 16 bits

Valid results are not assured if division by zero is attempted or an overflow occurs. For

information on avoiding overflow, see DIVXU Instruction, Zero Divide, and Overflow.

Available Registers

ERd: ER0 to ER7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 93 of 258

REJ09B0213-0300

DIVXU

DIVXU (DIVide eXtend as Unsigned) Divide

DIVXU Instruction, Zero Divide, and Overflo w

Zero divide and overflow are not detected in the DIVXU instructio n. A program like the following

can detect zero divisors and avoid overflow.

1. Programming solutions for DIVXU.B R0L, R1

Example 1: Divide upper 8 bits and lower 8 bits of 16-bit dividend separately and obtain 16-bit

quotient

CMP.B #0, R0L ; R0L = 0? (Zero divisor?)

BEQ ZERODIV ; Branc h to ZERODIV if R0L = 0

MOV.B R1H,R2L ; Copy upper 8 bits of dividend to R2L and

EXTU.W R2 (*1). ; zero-extend to 16 bits

DIVXU.B R0L, R2 (*2) ; Divide upper 8 bits of dividend

MOV.B R2H, R1H (*3) ; R2H → R1H (store partial remainder i n R1H)

DIVXU.B R0L, R1 (*4) ; Divide lower 8 bits of divi dend (incl udi ng repeated

division of upper 8 bits)

MOV.B R2L, R2H ; Store upper part of quoti ent in R2H

MOV.B R1L, R2L (*5) ; Store lower part of quotient in R2L

RTS

ZERODIV: ; Zero-divide handli ng routine

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 94 of 258

REJ09B0213-0300

DIVXU

DIVXU (DIVide eXtend as Unsigned) Divide

The resulting operation is 16 bits ÷ 8 bits → quotient (16 bits) and remainder (8 bits), and no

overflow occurs. The 16-bit quotient is stored in R2, the 8-bit remainder in R1H.

Remainder Quotient (low)

Quotient

R0L

( 1)*

( 2)*

( 3)*

( 4)*

( 5)*

Divisor

Dividend

Sign extension Dividend (high)

Remainder (part) Quotient (high)

Remainder (part) Dividend (low)

Section 2 Instruction Descriptions

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REJ09B0213-0300

DIVXU

DIVXU (DIVide eXtend as Unsigned) Divide

Example 2: Zero-extend divisor from 8 to 16 bits and dividend from 16 to 32 bits before dividing

EXTU.W R0 ; Zero-extend 8-bit divis or to 16 bits

BEQ ZERODIV ; Branch to ZERODIV if R0 = 0

EXTU.L ER1 ; Zero-extend 16-bit dividend t o 32 bits

EXTU.W R0, ER1 ; Divide using DIVXU.W

RTS

ZERODIV: ; Zero-divide handli ng routine

Instead of 16 bits ÷ 8 bits, the operation performed is 32 bits ÷ 16 bits → quotient (16 bits) and

remainder (16 bits), and no overflow occurs. The 16-bit quotient is stored in R1 and the 8-bit

remainder in the lower 8 bits of E1. The upper 8 bits of E1 are all 0.

ER1

R0L

ER1

Divisor

Dividend

Sign extension

Sign extension Dividend

Remainder Quotient

Divisor

R0L

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 96 of 258

REJ09B0213-0300

DIVXU

DIVXU (DIVide eXtend as Unsigned) Divide

2. Programming solutio n fo r DIVXU.W R0 , ER1

Example 1: Divide upper 16 bits and lower 16 bits of 32-bit dividend separately and obtain 32-bit

quotient

MOV.W R0, R0 ; R0 = 0? (Zero divisor?)

BEQ ZERODIV ; Branch to ZERODIV if R0 = 0

MOV.W E1,E2 ; Copy upper 16 bits of dividend to R2 and

EXTU.L ER2 (*1) ; zero-ext end to 32 bits

DIVXU.W R0, ER2 (*2) ; Divide upper 16 bits of dividend

MOV.W E2, E1 (*3) ; E2 → E1 (store partial remainder in E1)

DIVXU.W R0, ER1 (*4) ; Di vide lower 16 bits of dividend (includi ng repeated

division of upper 16 bits)

MOV.W R2, E2 ; Store upper part of quotient in E2

MOV.W R1, R2 (*5) ; Store lower part of quotient in R2

RTS

ZERODIV: ; Zero-div i de handl i ng routine

The resulting operation is 32 bits ÷ 1 6 bits → quotient (32 bits) and remainder (16 bits), and no

overflow occurs. The 32-bit quotient is stored in ER2, the 16-bit remainder in E1 .

Remainder Quotient (low)

Quotient

ER1

ER2

ER1

ER2

R0 Divisor

Dividend

Sign extension Dividend (high)

Remainder (part) Quotient (high)

Remainder (part) Dividend (low)

( 1)*

( 2)*

( 3)*

( 4)*

( 5)*

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2.2.28 (1) EEPMOV (B)

EEPMOV (MOVe data to EEPROM) Block Data Transfer

Operation

if R4L ≠ 0 then

repeat @ER5+ → @ER6+

R4L – 1 → R4L

until R4L = 0

else next;

Assembly-Language Format

EEPMOV.B

Operand Size

—

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction performs a block memory transfer. It moves data from the memory location

specified in ER5 to the memory location specified in ER6, increments ER5 and ER6, decrements

R4L, and repeats these op erations until R4L reaches zero. Execution then pro ceeds to the n ext

instruction . No interrupts are detected while th e block transfer is in progress. When the EEPMOV

instruction ends, R4L contains 0, and ER5 and ER6 contain the last transfer address + 1. The data

transfer is performed a byte at a time, with R4L indicating the number of bytes to be transferred.

The byte symbol in the assembly-language format designates the size of R4L (and limits the

maximum number of bytes that can be transferred to 255).

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

— EEPMOV.B 7 B 5 C 5 9 8 F 8+4n*

Note: *n is the initial val ue of R4L. Although n bytes of data are transferred, memory is accessed 2(n + 1)

times, requiring 4(n + 1) states. (n = 0, 1, 2, …, 255).

Notes

This instruction first reads the memory locations indicated by ER5 and ER6, then performs the

data transfer. The number of states required for execution differs from the H8/300 CPU.

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2.2.28 (2) EEPMOV (W)

EEPMOV (MOVe data to EEPROM) Block Data Transfer

Operation

if R4 ≠ 0 then

repeat @ER5+ → @ER6+

R4 – 1 → R4

until R4 = 0

else next;

Assembly-Language Format

EEPMOV.W

Operand Size

—

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction performs a block memory transfer. It moves data from the memory location

specified in ER5 to the memory location specified in ER6, increments ER5 and ER6, decrements

R4, and repeats th ese operations until R4 reaches zero. Execution then proceeds to the next

instruction. No interrupts except NMI are detected while the block transfer is in progress. When

the EEPMOV instruction ends, R4 contains 0, and ER5 and ER6 contain the last transfer address

+ 1. The data transfer is performed a byte at a time, with R4 indicating the number of bytes to be

transferred. The word symbol in the assembly-language format designates the size of R4 (allowing

a maximum 65535 bytes to be transferred).

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

— EEPMOV.W 7BD4598F8+4n

Note: n is t h e initial val ue of R4. Although n bytes of data are transferred, memory is accessed

2(n + 1) times, requiring 4(n + 1) states. (n = 0, 1, 2, …, 65535).

Notes

This instruction first reads memory at the addresses indicated by ER5 and ER6, then carries out

the block data transfer.

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EEPMOV (W)

EEPMOV (MOVe data to EEPROM) Block Data Transfer

EEPMOV.W Instruction and NMI Int errupt

If an NMI request occurs while the EEPMOV.W instruction is being executed, NMI interrupt

exception handling is carried out at the end of the current read-write cycle. Register contents are

then as follo ws:

ER5: address of the next byte to be transferred

ER6: destination address of the next byte

R4: number of bytes remaining to be transferred

The program counter value pushed on the stack in NMI interrupt exception handling is the address

of the next instruction after the EEPMOV.W instruction. Programs should be coded as follows to

allow for NMI interrupts during execu tion of the EEPMOV.W instruction.

Example:

L1: EEPMOV.W

MOV.W R4, R4

BNE L1

During execution of the EEPMOV.B instruction no interrupts are accepted, including NMI.

Section 2 Instruction Descriptions

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2.2.29 (1) EXTS (W)

EXTS (EXTend as Signed) Sign Extension

Operation

(<Bit 7> of Rd) → (<bits 15 to 8> of Rd>

Assembly-Language Format

EXTS.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction copies the sign of the lower 8 bits in a 16-b it r e gister Rd in the upward d irection

(copies Rd bit 7 to bits 15 to 8) to extend the data to signed word data.

Don’t care

8 bits

Sign bit

8 bits

Sign extension

8 bits 8 bits

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.29 (2) EXTS (L)

EXTS (EXTend a s Signed) Sign Extensio n

Operation

(<Bit 15> of ERd) → (<bits 31 to 16> of

ERd>)

Assembly-Language Format

EXTS.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

——— —— 0

↔

I: Previous value remains unchanged.

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction copies the sign of the lower 16 bits (general register Rd) in a 32-bit register ERd

in the upward direction (copies ERd bit 15 to bits 31 to 16) to extend the data to signed longword

data.

Don’t care

ERd

16 bits

Sign bit

16 bits

Sign extension

ERd

16 bits 16 bits

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.30 (1) EXTU (W)

EXTU (EXTend as Unsigned) Zero Extension

Operation

0 → (<bits 15 to 8> of Rd>)

Zero extend

Assembly-Language Format

EXTU.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

——— —— 00

↔

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n extends the lower 8 bits in a 1 6-bit register Rd to word data by padding with

zeros. That is, it clears the u pper 8 bits of Rd (bits 15 to 8) to 0.

Don’t care

8 bits 8 bits

Zero extension

8 bits 8 bits

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.30 (2) EXTU (L)

EXTU (EXTend as Unsigned) Zero Extension

Operation

0 → (<bits 31 to 16> of ERd>)

Zero extend

Assembly-Language Format

EXTU.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

——— —— 00

↔

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n extends the lower 16 b its ( general register Rd) in a 32-bit register ERd to

longword data by padding with zeros. That is, it clears the upper 16 bits of ERd (bits 31 to 16) to

Don’t care

ERd

16 bits 16 bits

Zero extension

ERd

16 bits 16 bits

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.31 (1) INC (B)

INC (INCrement) Increment

Operation

Rd + 1 → Rd

Assembly-Language Format

INC.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction increments an 8-bit register Rd ( destination register) and stores the result in the

8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

An overflow is caused by the operation H'7F + 1 → H'80.

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2.2.31 (2) INC (W)

INC (INCrement) Increment

Operation

Rd + 1 → Rd

Rd + 2 → Rd

Assembly-Language Format

INC.W #1, Rd

INC.W #2, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

——— ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n adds the immediate value 1 or 2 to the contents of a 16-bit register Rd ( destination

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

An overflow is caused by the operations H'7FFF + 1 → H'8000, H'7 FFF + 2 → H'8001, and

H'7FFE + 2 → H'8000.

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2.2.31 (3) INC (L)

INC (INCrement) Increment

Operation

ERd + 1 → ERd

ERd + 2 → ERd

Assembly-Language Format

INC.L #1, ERd

INC.L #2, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

——— ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction adds the immediate value 1 or 2 to the contents of a 32-bit register ERd

(destination register) and sto res the result in the 32-b it register ERd.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

An overf low is caused by the operations H'7FFFFFFF + 1 → H'80000000, H'7FFFFFFF + 2 →

H'80000001, and H'7FFFFFFE + 2 → H'80000000.

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2.2.32 JMP

JMP (JuMP) Unconditional Branch

Operation

Effective address → PC

Assembly-Language Format

JMP <EA>

Operand Size

—

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction branches unconditionally to a specified address

Available Registers

ERn: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format No. of States

Addressing

Mode Mnemonic Operands 1st byte 2n d byt e 3rd byte 4th byt e Nor m al Advan ce d

Absolute ad dress J MP @aa: 24 5 A abs 6

Memory indirect JMP @@aa:8 5 B abs 8 10

Notes

The structure of the branch address and the number of states required for execution differ between

normal mode and advanced mode.

The branch address must be even.

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2.2.33 JSR

JSR (Jump to SubRoutine) Jump to Subro ut ine

Operation

PC → @–SP

Effective address → PC

Assembly-Language Format

JSR <EA>

Operand Size

—

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction pushes the program counter on the stack as a return address, then branches to a

specified effective address. The program counter value pushed on the stack is the address of the

instructio n following the JSR instructio n.

Available Registers

ERn: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format No. of States

Addressing

Mode Mnemonic Operands 1st byte 2n d byt e 3rd byte 4th byt e Nor m al Advan ce d

Absolute ad dress JS R @aa:24 5 E abs 8 10

Memory indirect JSR @@aa:8 5 F abs 8 12

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JSR

JSR (Jump to SubRoutine) Jump to Subro ut ine

Notes

Note that the structures of the stack and branch addresses differ between normal and advanced

mode. Only the lower 16 bits of the PC are saved in normal mode.

The branch address must be even.

PC 23 16 15 8 7 0 Normal mode

PC 23 16 15 8 7 0 Advanced mode

Reserved

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2.2.34 (1) LDC (B)

LDC (LoaD to Control register) Load CCR

Operation

(EAs) → CCR

Assembly-Language Format

LDC.B <EAs>, CCR

Operand Size

Byte

Condition Code

IUIHUNZVC

↔

I: Loaded from the corresponding bit in the

source operand.

H: Loaded from the corresponding bit in the

source operand.

N: Loaded from the corresponding bit in the

source operand.

Z: Loaded from the corresponding bit in the

source operand.

V: Loaded from the corresponding bit in the

source operand.

C: Loaded from the corresponding bit in the

source operand.

Description

This instruction loads the source operand into the CCR.

Note that no in terrupts, even NMI interrupts, will be accepted at the point that this instruction

completes.

Available Registers

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate LDC. B #xx:8, CCR 0 7 IMM 2

Notes

Section 2 Instruction Descriptions

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2.2.34 (2) LDC (W)

LDC (LoaD to Control register) Load CCR

Operation

(EAs) → CCR

Assembly-Language Format

LDC.W <EAs>, CCR

Operand Size

Word

Condition Code

IUIHUNZVC

↔

I: Loaded from the corresponding bit in the

source operand.

H: Loaded from the corresponding bit in the

source operand.

N: Loaded from the corresponding bit in the

source operand.

Z: Loaded from the corresponding bit in the

source operand.

V: Loaded from the corresponding bit in the

source operand.

C: Loaded from the corresponding bit in the

source operand.

Description

This instruction loads the source operand contents into the condition-code register (CCR).

Although CCR is a byte register, the source operand is word size. The contents of the even address

are loaded into CCR.

No interrupt requests, including NMI, are accepted immediately after execution of this instruction.

Available Registers

ERs: ER0 to ER7

Section 2 Instruction Descriptions

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LDC (W)

LDC (LoaD to Control register) Load CCR

No. of

States

Mnemonic Operands

Addressing

Mode

Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

indirect

indirect with

displacement

indirect with

post-increment

LDC.W

@ERs,CCR

@(d:16,ERs),CCR

@(d:24,ERs),CCR

@ERs+,CCR

@aa:16,CCR

@aa:24,CCR

Absolute

address

ers

6B200disp

abs

disp

Operand Format and Number of States Required for Execution

Notes

Section 2 Instruction Descriptions

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2.2.35 (1) MOV (B)

MOV (MOVe data) Move

Operation

Rs → Rd

Assembly-Language Format

MOV.B Rs, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers one byte of data from an 8-bit register Rs to an 8-bit r egister Rd, tests the

transferred data, and sets condition-code flags according to the result.

Available Registers

Rd: R0L to R7L, R0H to R7H

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.35 (2) MOV (W)

MOV (MOVe data) Move

Operation

Rs → Rd

Assembly-Language Format

MOV.W Rs, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers one word of data from a 16-bit r egister Rs to a 16-bit r egister Rd, tests

the transferred data, and sets condition-code flag s according to the result.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.35 (3) MOV (L)

MOV (MOVe data) Move

Operation

ERs → ERd

Assembly-Language Format

MOV.L ERs, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers one longword of data fro m a 32-b it r e gister ERs to a 32-bit re gister ERd,

tests the transferred data, and sets condition-code flags according to the result.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

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2.2.35 (4) MOV (B)

MOV (MOVe data) Move

Operation

(EAs) → Rd

Assembly-Language Format

MOV.B <EAs>, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the source operand contents to an 8-bit register Rs, tests the transferred

data, and sets condition-code flags according to the result.

Available Registers

Rd: R0L to R7L, R0H to R7H

ERs: ER0 to ER7

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MOV (B)

MOV (MOVe data) Move

No. of

States

Mnemonic Operands

Addressing

Mode

Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte

Immediate

indirect with

displacement

indirect with

post-increment

MOV.B

#xx:8,Rd

@(d:16,ERs),Rd

@(d:24,ERs),Rd

@ERs+,Rd

@aa:8,Rd

@aa:16,Rd

Absolute

address

ers

6A200disp

abs

disp

MOV.B @aa:24,Rd

indirect MOV.B @ERs,Rd

IMM

Operand Format and Number of States Required for Execution

Notes

The MOV.B @ER7+, Rd instruction should never be used, because it leaves an odd value in the stack pointer (ER7).

For details refer to section 3.3.2, Exception Processing, or to the hardware manual.

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

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2.2.35 (5) MOV (W)

MOV (MOVe data) Move

Operation

(EAs) → Rd

Assembly-Language Format

MOV.W <EAs>, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the source operand contents to a 16-bit register Rd, tests the transferred

data, and sets condition-code flags according to the result.

Available Registers

Rd: R0 to R7, E0 to E7

ERs: ER0 to ER7

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MOV (W )

MOV (MOVe data) Move

No. of

States

Mnemonic Operands

Addressing

Mode

Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte

Immediate

indirect with

displacement

indirect with

post-increment

MOV.W

#xx:16,Rd

@(d:16,ERs),Rd

@(d:24,ERs),Rd

@ERs+,Rd

@aa:16,Rd abs

@aa:24,Rd abs

Absolute

address

200disp

disp

indirect MOV.W @ERs,Rd

IMM

ers

Operand Format and Number of States Required for Execution

Notes

1. The source operand <EAs> must be located at an even address.

2. In machine language, MOV.W @R7+, Rd is identical to POP.W Rd.

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2.2.35 (6) MOV (L)

MOV (MOVe data) Move

Operation

(EAs) → ERd

Assembly-Language Format

MOV.L <EAs>, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the source operand contents to a specified 32-bit register (ERd), tests the

transferred data, and sets condition-code flags according to the result. The first memory word

located at the effective address is stored in extended register Ed. Th e next word is stored in

general register Rd.

ERd Ed RdH RdL

MSB

LSB

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 121 of 258

REJ09B0213-0300

MOV (L)

MOV (MOVe data) Move

No. of

States

Mnemonic Operands

Addressing

Mode

Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

MOV.L

MOV.L disp

MOV.L

MOV.L @aa:24,ERd

#xx:32,Rd IMM

@ERs,ERd

@(d:16,ERs),ERd

@(d:24,ERs),ERd

@ERs+,ERd

@aa:16,ERd

ers

erd

200

abs

erd0

abs

ers0

disp

Immediate

indirect with

displacement

indirect with

post-increment

Absolute

address

indirect

Operand Format and Number of States Required for Execution

Notes

1. The source operand <EAs> must be located at an even address.

2. In machine language, MOV.L @ER7+, ERd is identical to POP.L ERd.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 122 of 258

REJ09B0213-0300

2.2.35 (7) MOV (B)

MOV (MOVe data) Move

Operation

Rs → (EAd)

Assembly-Language Format

MOV.B Rs, <EA d>

Operand Size

Byte

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the contents of an 8-bit register Rs (source operand) to a destination

location, tests th e transferred data, and sets condition-cod e flags according to the result.

Available Registers

Rs: R0L to R7L, R0 H to R7H

ERd: ER0 to ER7

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 123 of 258

REJ09B0213-0300

MOV (B)

MOV (MOVe data) Move

No. of

States

Mnemonic Operands

Addressing

Mode

Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte

indirect

indirect with

displacement

indirect with

pre-decrement

MOV.B

Rs,@ERd

Rs,@(d:16,ERd)

Rs,@(d:24,ERd)

Rs,@–ERd

Rs,@aa:8

Rs,@aa:16

Absolute

address

erd

6AA00disp

abs

disp

MOV.B Rs,@aa:24

Operand Format and Number of States Required for Execution

Notes

1. The MOV.B Rs, @–ER7 instruction should never be used, because it leaves an odd value in the stack pointer (ER7).

For details refer to section 3.3.2, Exception Processing, or to the hardware manual.

2. Execution of MOV.B RnL, @–ERn or MOV.B RnH, @–ERn first decrements ERn by one, then transfers the

designated part (RnL or RnH) of the resulting ERn value.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 124 of 258

REJ09B0213-0300

2.2.35 (8) MOV (W)

MOV (MOVe data) Move

Operation

Rs → (EAd)

Assembly-Language Format

MOV.W Rs, <EA d>

Operand Size

Word

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the contents of a 16-bit register Rs (source operand) to a destination

location, tests th e transferred data, and sets condition-cod e flags according to the result.

Available Registers

Rs: R0 to R7, E0 to E7

ERd: ER0 to ER7

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 125 of 258

REJ09B0213-0300

MOV (W )

MOV (MOVe data) Move

No. of

States

Mnemonic Operands

Addressing

Mode

Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte

indirect

indirect with

displacement

indirect with

post-increment

MOV.W

Rs,@ERd

Rs,@(d:16,ERd)

Rs,@(d:24,ERd)

Rs,@–ERd

Rs,@aa:16

erd

6BA00disp

abs

disp

MOV.W Rs,@aa:24

Absolute

address

Operand Format and Number of States Required for Execution

Notes

1. The destination operand <EAd> must be located at an even address.

2. In machine language, MOV.W Rs, @–R7 is identical to PUSH.W Rs.

3. Execution of MOV.W Rn, @–ERn first decrements ERn by 2, then transfers the resulting value.

Section 2 Instruction Descriptions

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REJ09B0213-0300

2.2.35 (9) MOV (L)

MOV (MOVe data) Move

Operation

ERs → (EAd)

Assembly-Language Format

MOV.L ERs, <EAd>

Operand Size

Longword

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the contents of a 32-bit register ERs (source operand) to a destination

location, tests th e tr ansferred data, and sets con dition-code flag s according to the result. The

extended register (Es) contents are stored at the first word indicated by the effective address. The

general register (Rs) contents are stored at the next word.

ERs Es RsH RsL

MSB

LSB

Available Registers

ERs: ER0 to ER7

ERd: ER0 to ER7

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 127 of 258

REJ09B0213-0300

MOV (L)

MOV (MOVe data) Move

No. of

States

Mnemonic Operands

Addressing

Mode

Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

indirect

indirect with

displacement

indirect with

pre-decrement

MOV.L

ERs,@ERd

ERs,@(d:16,ERd)

ERs,@(d:24,ERd)

ERs,@–ERd

ERs,@aa:16

ERs,@aa:24

Absolute

address

erd

ers

06BA00disp

abs

ers0

abs

ers

disp

Operand Format and Number of States Required for Execution

Notes

1. The destination operand <EAd> must be located at an even address.

2. In machine language, MOV.L ERs, @–ER7 is identical to PUSH.L ERs.

3. Execution of MOV.L ERn, @–ERn first decrements ERn by 4, then transfers the resulting value.

Section 2 Instruction Descriptions

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REJ09B0213-0300

2.2.36 MOVFPE

MOVFPE (MOVe From Peripheral with E clock) Move Data with E Clock

Operation

(EAs) → Rd

Synchronized with E clock

Assembly-Language Format

MOVFPE @aa:16, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfer s m e mory contents specified by a 16-bit absolute add r ess to a general

flags according to the result.

Note: Avoid using this instruction in microcontrollers not having an E clock output pin, or in

single-chip mode.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address MOVFPE @aa:16, Rd 6 A 4 rd abs *

Notes

1. This instruction cannot be used with addressing modes other than the above, and cannot

transfer word data or longword data.

2. Data transfer by this instr uction requires 9 to 16 states, so the execution time is va r iable. For

details, refer to the relevant microcontroller hardware m anual.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 129 of 258

REJ09B0213-0300

2.2.37 MOVTPE

MOVTPE (MOVe To Peripheral with E clock) Move Data with E Clock

Operation

Rs → (EAd)

Synchronized with E clock

Assembly-Language Format

MOVTPE Rs, @aa:16

Operand Size

Byte

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the contents of a general register Rs (source operand) to a destination

location specified by a 16-bit absolute address in synchronization with an E clock, tests the

transferred data, and sets condition-code flags according to the result.

Note: Avoid using this instruction in microcontrollers not having an E clock output pin, or in

single-chip mode.

Available Registers

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Absolute address MOVTPE Rs, @aa:16 6 A C rs abs *

Notes

1. This instruction cannot be used with addressing modes other than the above, and cannot

transfer word data or longword data.

2. Data transfer by this instr uction requires 9 to 16 states, so the execution time is v a r iable. For

details, refer to the relevant microcontroller hardware m anual.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 130 of 258

REJ09B0213-0300

2.2.38 (1) MULXS (B)

MULXS (MU Ltiply eXtend as Signed) Multiply Sig ned

Operation

Rd × Rs → Rd

Assembly-Language Format

MULXS.B Rs, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

———— ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction multiplies the lower 8 bits of a 16- bit register Rd (destin ation operand) by the

contents of an 8-bit register Rs (source operand) as signed data and stores the result in the 16-bit

The operation performed is 8-bit × 8-bit → 16-bit sign e d multiplication.

Rd Rs Rd

Don’t care Multiplicand ×Multiplier →Product

8 bits 8 bits 16 bits

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 131 of 258

REJ09B0213-0300

2.2.38 (2) MULXS (W)

MULXS (MU Ltiply eXtend as Signed) Multiply Sig ned

Operation

ERd × Rs → ERd

Assembly-Language Format

MULXS.W Rs, ERd

Operand Size

Word

Condition Code

IUIHUNZVC

———— ——

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination ope r and ) by the

contents of a 16-bit register Rs (source operand) as signed data and stores the result in the 32-bit

16-bit × 16- bi t → 32-bit signed multip lication.

ERd Rs ERd

Don’t care Multiplicand ×Multiplier →Product

16 bits 16 bits 32 bits

Available Registers

ERd: ER0 to ER7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 132 of 258

REJ09B0213-0300

2.2.39 (1) MULXU (B)

MULXU (MULtiply eXtend as Unsigned) Multiply

Operation

Rd × Rs → Rd

Assembly-Language Format

MULXU.B Rs, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction multiplies the lower 8 bits of a 16- bit register Rd (destin ation operand) by the

contents of an 8-bit register Rs (source operand) and stores the result in the 16-bit register Rd. If

Rd is a general register, Rs can be the upper part (RdH) or lower part (RdL) of Rd. The operation

performed is 8-bit × 8-bit → 16-bit multiplication.

Rd Rs Rd

Don’t care Multiplicand ×Multiplier →Product

8 bits 8 bits 16 bits

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 133 of 258

REJ09B0213-0300

2.2.39 (2) MULXU (W)

MULXU (MULtiply eXtend as Unsigned) Multiply

Operation

ERd × Rs → ERd

Assembly-Language Format

MULXU.W Rs, ERd

Operand Size

Word

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination ope r and ) by the

contents of a 16-bit register Rs (source operand) and stores the result in the 32-bit register ERd. Rs

can be the upper part (Ed) or lower part (Rd) of ERd. The operation performed is 16-bit × 16-bit

→ 32-bit multiplication.

ERd Rs ERd

Don’t care Multiplicand ×Multiplier →Product

16 bits 16 bits 32 bits

Available Registers

ERd: ER0 to ER7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 134 of 258

REJ09B0213-0300

2.2.40 (1) NEG (B)

NEG (NEGate) Negate Binary Signed

Operation

0 – Rd → Rd

Assembly-Language Format

NEG.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a borrow at bit 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 7;

otherwise cleared to 0.

Description

This instruction takes the two’s complement of the conten ts of an 8-bit register Rd ( destination

operand) and stores the result in the 8-bit register Rd (subtracting the register contents from H'00).

If the original contents of Rd was H'80, however, the result remains H'80.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

An overflow occurs if the previous contents of Rd was H'80.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 135 of 258

REJ09B0213-0300

2.2.40 (2) NEG (W)

NEG (NEGate) Negate Binary Signed

Operation

0 – Rd → Rd

Assembly-Language Format

NEG.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a borrow at bit 1 1;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 15;

otherwise cleared to 0.

Description

This instruction takes the two’s complement of the conten ts of a 16-bit register Rd (destination

operand) and stores the result in the 16-bit register Rd (subtracting the register contents from

H'0000). If the original contents of Rd was H'8000, however, the result remains H'8000.

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

An overflow occurs if the previous contents of Rd was H'8000.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 136 of 258

REJ09B0213-0300

2.2.40 (3) NEG (L)

NEG (NEGate) Negate Binary Signed

Operation

0 – ERd → ERd

Assembly-Language Format

NEG.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a borrow at bit 27;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 31;

otherwise cleared to 0.

Description

This instructio n takes the two’ s co mplement of the contents of a 32- bit register ERd (destination

operand) and stores the result in the 32-bit register ERd (subtracting the register contents from

H'00000000). If the original contents of ERd was H'80000000, however, the result remains

H'80000000.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

An overflow occurs if the previous contents of ERd was H'80000000.

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 137 of 258

REJ09B0213-0300

2.2.41 NOP

NOP (No OPeration) No Operation

Operation

PC + 2 → PC

Assembly-Language Format

NOP

Operand Size

—

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction only increments the program counter, causing the next instruction to be executed.

The internal state of the CPU does not change.

Available Registers

—

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

— NOP 0000 2

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 138 of 258

REJ09B0213-0300

2.2.42 (1) NOT (B)

NOT (NOT = log ical complement ) Logical Complement

Operation

¬ Rd → Rd

Assembly-Language Format

NOT.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction takes the one’s complement of the con tents of an 8-bit register Rd (destination

operand) and stores the re sult in the 8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 139 of 258

REJ09B0213-0300

2.2.42 (2) NOT (W)

NOT (NOT = log ical complement ) Logical Complement

Operation

¬ Rd → Rd

Assembly-Language Format

NOT.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the resu lt is zero (the previous

Rd value was H'FFFF) ; otherwise cleared

to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction takes the one’s complement of the con tents of a 16-bit register Rd (destination

operand) and stores the re sult in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 140 of 258

REJ09B0213-0300

2.2.42 (3) NOT (L)

NOT (NOT = log ical complement ) Logical Complement

Operation

¬ ERd → ERd

Assembly-Language Format

NOT.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

——— —— 0

↔

I: Previous value remains unchanged.

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n takes the one’s complement of the contents of a 32- bit register ERd (destin atio n

operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 141 of 258

REJ09B0213-0300

2.2.43 (1) OR (B)

OR (inclusive OR logical) Logical OR

Operation

Rd ∨ (EAs) → Rd

Assembly-Language Format

OR.B <EAs>, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ORs the source operand with the contents of an 8-bit register Rd ( destination

Available Registers

Rd: R0L to R7L, R0H to R7H

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immediate OR.B #xx:8, Rd C rd IMM 2

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 142 of 258

REJ09B0213-0300

2.2.43 (2) OR (W)

OR (inclusive OR logical) Logical OR

Operation

Rd ∨ (EAs) → Rd

Assembly-Language Format

OR.W <EAs>, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ORs the source operand with the contents of a 16-bit register Rd ( destination

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate OR.W #xx:16, Rd 7 9 4 rd I MM 4

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 143 of 258

REJ09B0213-0300

2.2.43 (3) OR (L)

OR (inclusive OR logical) Logical OR

Operation

ERd ∨ (EAs) → ERd

Assembly-Language Format

OR.L <EAs>, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ORs the source operand with the contents of a 32-bit register ERd ( destination

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte No. of

States

Immediate OR.L #xx:32,ERd 7 A 4 0 erd IMM 6

Notes

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 144 of 258

REJ09B0213-0300

2.2.44 ORC

ORC (inclusive OR Control register) Logical OR with CCR

Operation

CCR ∨ #IMM → CCR

Assembly-Language Format

ORC #xx:8, CCR

Operand Size

Byte

Condition Code

IUIHUNZVC

↔

I: Stores the corresponding bit of the result.

UI: Stor es the corresponding bit of the resu lt.

H: Stores the corresponding bit of the result.

U: Stores the corresponding bit of the result.

N: Stores the corresponding bit of the result.

Z: Stores the corresponding bit of the result.

V: Stores the corresponding bit of the result.

C: Stores the corresponding bit of the result.

Description

This instruction ORs the co ntents of th e con dition-cod e register (CCR) with im mediate data and

stores the result in the condition-code register. No interrupt requests, including NMI, are accepted

immediately af ter execution of this instru ction.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate ORC #xx:8, CCR 0 4 IM M 2

Notes

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2.2.45 (1) POP (W)

POP (POP data) Pop Data from Stack

Operation

@SP+ → Rn

Assembly-Language Format

POP.W Rn

Operand Size

Word

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction restores d a ta f rom the stack to a 16-bit general register Rn, tests the r e stored data,

and sets condition-code flags according to the result.

Available Registers

Rn: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

—POP.WRn6D7rn 6

Notes

POP.W Rn is identical to MOV.W @SP+, Rn .

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2.2.45 (2) POP (L)

POP (POP data) Pop Data from Stack

Operation

@SP+ → ERn

Assembly-Language Format

POP.L ERn

Operand Size

Longword

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n restores da ta f rom the stack to a 32-bit general register ERn, tests the re stored

data, and sets condition-code flags according to the result.

Available Registers

ERn: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

— POP.L ERn 01006D70ern10

Notes

POP.L ERn is identical to MOV.L @SP+, ERn.

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2.2.46 (1) PUSH (W)

PUSH (PUSH data) Push Data on Stack

Operation

Rn → @– SP

Assembly-Language Format

PUSH.W Rn

Operand Size

Word

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction saves data from a 16-bit register Rn onto the stack, tests the saved data, and sets

condition-code flags according to the result.

Available Registers

Rn: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

— PUSH.W Rn 6 D F rn 6

Notes

1. PUSH. W Rn is identical to MOV.W Rn, @–SP.

2. When PUSH.W R7 or PUSH.W E7 is executed, the value saved on the stack is the lower part

(R7) or upper part (E7) of the value of ER7 before execution minus two.

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2.2.46 (2) PUSH (L)

PUSH (PUSH data) Push Data on Stack

Operation

ERn → @–SP

Assembly-Language Format

PUSH.L ERn

Operand Size

Longword

Condition Code

IUIHUNZVC

——— —— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the data value is negative;

otherwise cleared to 0.

Z: Set to 1 if the data value is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction pushes data from a 32-bit register ERn onto the stack, tests the saved data, and

sets condition-code flags according to the result.

Available Registers

ERn: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

— PUSH.L ERn 0 1 0 0 6 D F 0 ern 10

Notes

1. PUSH.L ERn is iden tical to MOV.L ERn, @–SP.

2. When PUSH.L ER7 is executed, the value saved on the stack is the value of ER7 before

execution minus four.

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2.2.47 (1) ROTL (B)

ROTL (ROTate Left) Rotate

Operation

Rd (left ro tation) → Rd

Assembly-Language Format

ROTL.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 7.

Description

This instruction rotates the bits in an 8-bit register Rd ( destination register) one bit to the left. The

most significant bit is rotated to the least significant bit (bit 0), and also copied to the carry flag.

MSB LSB

7b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.47 (2) ROTL (W)

ROTL (ROTate Left) Rotate

Operation

Rd (left ro tation) → Rd

Assembly-Language Format

ROTL.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 15.

Description

This instruction rotates the bits in a 16-bit register Rd ( destination register) one bit to the left. The

most significant bit is rotated to the least significant bit (bit 0), and also copied to the carry flag.

MSB LSB

15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

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2.2.47 (3) ROTL (L)

ROTL (ROTate Left) Rotate

Operation

ERd (left rotation) → ERd

Assembly-Language Format

ROTL.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

———— —0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 31.

Description

This instruction rotates the bits in a 32-bit register ERd ( destination register) one bit to the left.

The most sign if ican t bit is rotated to the least sign if ican t bit (bit 0), and also copied to the carry

flag.

MSB LSB

31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.48 (1) ROTR (B)

ROTR (ROTate Right) Rotate

Operation

Rd (right rotation) → Rd

Assembly-Language Format

ROTR.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction rotates the bits in an 8-bit register Rd ( destination register) one bit to the right.

The least significant bit is rotated to the most significant bit ( bit 7), and also copied to the carry

flag.

MSB LSB

b7b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.48 (2) ROTR (W)

ROTR (ROTate Right) Rotate

Operation

Rd (right rotation) → Rd

Assembly-Language Format

ROTR.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to the right.

The least significan t b it is rotated to the most sig nificant bit (bit 15), and also copied to the carry

flag.

MSB LSB

b15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.48 (3) ROTR (L)

ROTR (ROTate Right) Rotate

Operation

ERd (right rotation) → ERd

Assembly-Language Format

ROTR.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction rotates the bits in a 32-bit register ERd (destination register) one bit to the right.

The least significant bit is rotated to the most significant bit ( bit 31), and also copied to the carry

flag.

MSB LSB

b31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.49 (1) ROTXL (B)

ROTXL (ROTate with eXtend carry Left) Rotate through Carry

Operation

Rd (left rotation through carry b it) → Rd

Assembly-Language Format

ROTXL.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 7.

Description

This instruction rotates the bits in an 8-bit register Rd (destination register) one bit to the left

through the carry f lag. The carry flag is rotated into the least significant bit (bit 0). The most

significant b it r otates into the carry flag.

MSB LSB

7b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.49 (2) ROTXL (W)

ROTXL (ROTate with eXtend carry Left) Rotate through Carry

Operation

Rd (left rotation through carry b it) → Rd

Assembly-Language Format

ROTXL.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 15.

Description

This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to the left

through the carry f lag. The carry flag is rotated into the least significant bit (bit 0). The most

significant b it r otates into the carry flag.

MSB LSB

15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.49 (3) ROTXL (L)

ROTXL (ROTate with eXtend carry Left) Rotate through Carry

Operation

ERd (left rotation through carry bit) → ERd

Assembly-Language Format

ROTXL.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 31.

Description

This instruction rotates the bits in a 32-bit register ERd ( destination register) one bit to the left

through the carry f lag. The carry flag is rotated into the least significant bit (bit 0). The most

significant b it r otates into the carry flag.

MSB LSB

31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.50 (1) ROTXR (B)

ROTXR (ROTate with eXtend carry Right) Rota te thro ugh Carry

Operation

Rd (right rotation through carry bit) → Rd

Assembly-Language Format

ROTXR.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction rotates the bits in an 8-bit register Rd ( destination register) one bit to the right

through the carry f lag. The carry flag is rotated into the most significant b it ( bit 7). The least

significant b it r otates into the carry flag.

LSBMSB

b7b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

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2.2.50 (2) ROTXR (W)

ROTXR (ROTate with eXtend carry Right) Rota te thro ugh Carry

Operation

Rd (right rotation through carry bit) → Rd

Assembly-Language Format

ROTXR.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to the right

through the carry f lag. The carry flag is ro tated into th e most sig nificant bit (bit 15). The least

significant b it r otates into the carry flag.

LSBMSB

b15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

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2.2.50 (3) ROTXR (L)

ROTXR (ROTate with eXtend carry Right) Rota te thro ugh Carry

Operation

ERd (right rotation through carry bit) → ERd

Assembly-Language Format

ROTXR.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction rotates the bits in a 32-bit register ERd (destination register) one bit to the right

through the carry f lag. The carry flag is ro tated into the most significant bit (bit 31). The least

significant b it r otates into the carry flag.

LSBMSB

b31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.51 RTE

RTE (ReTurn from Exception) Return from Exception Handling

Operation

@SP+ → CCR

@SP+ → PC

Assembly-Language Format

RTE

Operand Size

—

Condition Code

IUIHUNZVC

↔

I: Restored from the corresponding bit on

the stack.

UI: Restored from the co rresponding bit on

the stack.

H: Restored from the corresponding bit on

the stack.

U: Restored from the corresponding bit on

the stack.

N: Restored from the corresponding bit on

the stack.

Z: Restored from the corresponding bit on

the stack.

V: Restored from the corresponding bit on

the stack.

C: Restored from the corresponding bit on

the stack.

Description

This instruction returns from an exception-handling routine by restoring the condition-code

address restored to the program counter. The CCR and PC contents a t the time of execution of th is

instruction are lost.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

— RTE 5670 10

Section 2 Instruction Descriptions

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RTE

RTE (ReTurn fr om Exception) Return from Except ion Handling

Notes

The stack structure differs between normal mode and advanced mode.

PC 23 16 15 8 7 0

Normal mode

Don’t care CCR

PC 23 16 15 8 7 0

Advanced mode

CCR

Undet.

Section 2 Instruction Descriptions

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2.2.52 RTS

RTS (ReTurn fro m Subroutine) Return from Subrout ine

Operation

@SP+ → PC

Assembly-Language Format

RTS

Operand Size

—

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction returns from a subroutine by restoring the program counter (PC) from the stack.

Program execution continues from the address restored to the program counter. The PC contents at

the time of ex ecutio n of this instruction are lost.

Available Registers

—

Operand Format and Number of States Required for Execution

Instruction Format No. of States

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte Normal Advanced

—RTS 5470 810

Notes

The stack structure and number of states required for execution differ between normal mode and

advanced mode.

In normal mode, only the lower 16 bits of the program counter are restored.

PC 23 16 15 8 7 0

Normal mode PC 23 16 15 8 7 0

Advanced mode

Undet.

Don’t care

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2.2.53 (1) SHAL (B)

SHAL (SHift Arithmetic Left) Shift Arithmetic

Operation

Rd (left arith metic shift) → Rd

Assembly-Language Format

SHAL.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

————

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 7.

Description

This instruction shifts the b its in an 8-bit register Rd (destination operand) one bit to the left. The

most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

The SHAL instruction differs from the SHLL instruction in its effect on th e overflow flag.

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2.2.53 (2) SHAL (W)

SHAL (SHift Arithmetic Left) Shift Arithmetic

Operation

Rd (left arith metic shift) → Rd

Assembly-Language Format

SHAL.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

————

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 15.

Description

This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to th e left. The

most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

The SHAL instructio n differs from the SHLL instruction in its effect on the ov erflow flag.

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2.2.53 (3) SHAL (L)

SHAL (SHift Arithmetic Left) Shift Arithmetic

Operation

ERd (left arith metic shift) → ERd

Assembly-Language Format

SHAL.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

————

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 31.

Description

This instruction shifts the b its in a 32-bit register ERd (destination operand) one bit to the left. The

most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

The SHAL instruction differs from the SHLL instruction in its effect on th e overflow flag.

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2.2.54 (1) SHAR (B)

SHAR (SHift Arithmetic Right) Shift Arithmetic

Operation

Rd (right arithmetic shift) → Rd

Assembly-Language Format

SHAR.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to th e righ t. Bit

0 shifts into the carry flag. Bit 7 sh ifts into itself. Since bit 7 rema ins unaltered, th e sign does not

change.

LSB

b7b0

. . . . . .

MSB

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.54 (2) SHAR (W)

SHAR (SHift Arithmetic Right) Shift Arithmetic

Operation

Rd (right arithmetic shift) → Rd

Assembly-Language Format

SHAR.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

———— —0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in a 16-bit register Rd (destination operand) on e bit to the right. Bit

0 shifts into the carry flag. Bit 15 shifts into itself. Since bit 15 remains unaltered, th e sign does

not change.

LSB

b15 b0

. . . . . .

MSB

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.54 (3) SHAR (L)

SHAR (SHift Arithmetic Right) Shift Arithmetic

Operation

ERd (righ t arithmetic shift) → ERd

Assembly-Language Format

SHAR.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to th e righ t.

Bit 0 shifts into the carry flag. Bit 31 shifts in to itself. Since bit 3 1 re m a ins unaltered, th e sign

does not change.

LSB

b31 b0

. . . . . .

MSB

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.55 (1) SHLL (B)

SHLL (SHift Logical Left) Shift Logical

Operation

Rd (left logical shift) → Rd

Assembly-Language Format

SHLL.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

———— —0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 7.

Description

This instruction shifts the b its in an 8-bit register Rd (destination operand) one bit to the left. The

most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.

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2.2.55 (2) SHLL (W)

SHLL (SHift Logical Left) Shift Logical

Operation

Rd (left logical shift) → Rd

Assembly-Language Format

SHLL.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 15.

Description

This instruction shifts the b its in a 16-bit register Rd (destination operand) one bit to the left. The

most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

The SHLL instructio n differs from the SHAL instruction in its effect on th e overflo w f lag.

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2.2.55 (3) SHLL (L)

SHLL (SHift Logical Left) Shift Logical

Operation

ERd (left log ical shift) → ERd

Assembly-Language Format

SHLL.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

———— 0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 31.

Description

This instruction shifts the b its in a 32-bit register ERd (destination operand) one bit to the left. The

most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.

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2.2.56 (1) SHLR (B)

SHLR (SHift Logical Right) Shift Logical

Operation

Rd (right logical shift) → Rd

Assembly-Language Format

SHLR.B Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

———— 00

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to th e righ t. The

least significant bit shifts into the car ry flag. The most significan t bit (bit 7) is cleared to 0.

LSBMSB

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

Section 2 Instruction Descriptions

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2.2.56 (2) SHLR (W)

SHLR (SHift Logical Right) Shift Logical

Operation

Rd (right logical shift) → Rd

Assembly-Language Format

SHLR.W Rd

Operand Size

Word

Condition Code

IUIHUNZVC

———— 00

↔

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the b its in a 16-bit register Rd (destination operand) one bit to the right. The

least significant bit shifts into the car ry flag. The most significan t bit (bit 15) is cleared to 0.

LSBMSB

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.56 (3) SHLR (L)

SHLR (SHift Logical Right) Shift Logical

Operation

ERd (right logical shift) → ERd

Assembly-Language Format

SHLR.L ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

———— 00

↔

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to th e righ t.

The least significant bit shifts into th e carry flag. The most significant b it ( bit 31) is cleared to 0.

LSBMSB

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.57 SLEEP

SLEEP ( SLEEP ) Powe r-Dow n Mode

Operation

Program execution state → power-down mode

Assembly-Language Format

SLEEP

Operand Size

—

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

When the SLEEP instruction is executed, the CPU enters a power-down state. Its internal state

remains unchanged, but the CPU stops executing instructions and waits for an ex ception-handling

request. When it receives an exception-handling request, the CPU exits the power-down state and

begins the exception-handling sequence. Interrupt requests other than NMI cannot end the power-

down state if they are masked in the CPU.

Available Registers

—

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

— SLEEP 0180 2

Notes

For information about the power-down state, see the relevant microcontroller hardware manual.

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2.2.58 (1) STC (B)

STC (STore from Control register) Store CCR

Operation

CCR → Rd

Assembly-Language Format

STC.B CCR, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction copie s the CCR con te nts to an 8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.58 (2) STC (W)

STC (STore from Control register) Store CCR

Operation

CCR → (EAd)

Assembly-Language Format

STC.W CCR, < EAd>

Operand Size

Word

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction copies th e CCR contents to a de stination locatio n. Alth ough CCR is a byte

address.

Available Registers

ERd: ER0 to ER7

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STC (W)

STC (STore from Control register) Store CCR

No. of

States

Mnemonic Operands

Addressing

Mode

Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

indirect

indirect with

displacement

indirect with

pre-decrement

STC.W

CCR,@ERd

CCR,@(d:16,ERd)

CCR,@(d:24,ERd)

CCR,@–ERd

CCR,@aa:16

CCR,@aa:24

Absolute

address

erd

6BA00disp

abs

disp

Operand Format and Number of States Required for Execution

Notes

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2.2.59 (1) SUB (B)

SUB (SUBtra c t binary) Subtract Binary

Operation

Rd – Rs → Rd

Assembly-Language Format

SUB.B Rs, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a borrow at bit 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 7;

otherwise cleared to 0.

Description

This instruction subtracts the contents of an 8-bit register Rs (source operand) from the contents of

an 8-bit r egister Rd (destination operand) and stores the result in the 8- bit register Rd.

Available Registers

Rd: R0L to R7L, R0H to R7H

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

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SUB (B)

SUB (SUBtra c t binary) Subtract Binary

Notes

The SUB.B instruction can operate only on general registers. Immediate data can be subtracted

from general register contents by using the SUBX instruction. Before executing SUBX #xx:8, Rd,

first set the Z flag to 1 and clear the C flag to 0. The following coding examples can also be used

to subtract nonzero immediate data #IMM.

(1) ORC #H'05, CCR

SUBX #(IMM–1), Rd

(2) ADD #(0–IMM), Rd

XORC #H'01, CCR

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2.2.59 (2) SUB (W)

SUB (SUBtra c t binary) Subtract Binary

Operation

Rd – (EAs) → Rd

Assembly-Language Format

SUB.W <EAs>, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a borrow at bit 11;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 15;

otherwise cleared to 0.

Description

This instruction subtracts a source operand from the contents of a 16-bit register Rd (destination

operand) and stores the re sult in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate SUB.W #xx:16, Rd 7 9 3 rd IMM 4

Notes

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2.2.59 (3) SUB (L)

SUB (SUBtra c t binary) Subtract Binary

Operation

ERd – <EAs> → ERd

Assembly-Language Format

SUB.L <EAs>, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a borrow at bit 2 7;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 31;

otherwise cleared to 0.

Description

This instruction subtracts a source operand from the contents of a 32-bit register ERd (destination

operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

No. of

States

Immediate SUB.L #xx:32, ERd 7 A 3 0 erd IMM 6

Notes

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2.2.60 SUBS

SUBS (SUBtract with Sign ext ension) Subtract Binary Address Data

Operation

ERd – 1 → ERd

ERd – 2 → ERd

ERd – 4 → ERd

Assembly-Language Format

SUBS #1, ERd

SUBS #2, ERd

SUBS #4, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

————— ———

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction subtracts the immediate value 1, 2, or 4 from the contents of a 32-bit register ERd

(destination register). Dif fering from the SUB instru ction, it doe s not af fect the condition-co de

flags.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.61 SUBX

SUBX (SUBtract wit h eXt end carry) Subtract with Borro w

Operation

Rd – (EAs) – C → Rd

Assembly-Language Format

SUBX <EAs>, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

—— —

↔

H: Set to 1 if there is a borrow fr om b it 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow fr om bit 7;

otherwise cleared to 0.

Description

This instruction subtracts the source operand and carry flag from the contents of an 8-bit register

Rd (destination operand) and stores th e result in the 8-bit reg ister Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate SUBX #xx:8, Rd B rd IMM 2

Notes

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2.2.62 TRAPA

TRAPA (TRAP Always) Trap Unconditionally

Operation

PC → @–SP

CCR → @–SP

<Vector> → PC

Assembly-Language Format

TRAPA #x:2

Operand Size

—

Condition Code

IUIHUNZVC

1∆—

—— ———

I: Always set to 1.

U: See notes.

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchang ed.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction pushes the program counter (PC) and con dition-code register (CCR) on the sta c k,

then sets the I bit to 1 and branches to a new address. The new address is the contents of the vector

address corresponding to the specified vector number. The PC value pushed on the stack is the

starting address of the nex t in struction after the TRAPA instruction.

Vector Address

#x Normal Mode Advanced Mode

0 H'0010 to H'0011 H'000020 to H'000023

1 H'0012 to H'0013 H'000024 to H'000027

2 H'0014 to H'0015 H'000028 to H'00002B

3 H'0016 to H'0017 H'00002C to H'00002F

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

1. CCR bit 6 is set to 1 when used as an interrup t mask bit, but retains its previous value when

used as a user bit.

2. The stack and vector structure differ between normal mode and advanced mode.

Section 2 Instruction Descriptions

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2.2.63 (1) XOR (B)

XOR (eXclusive O R logical) Exclusive Logical OR

Operation

Rd ⊕ (EAs) → Rd

Assembly-Language Format

XOR.B <EAs>, Rd

Operand Size

Byte

Condition Code

IUIHUNZVC

———— —0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction exclusively ORs the source operand with the contents of an 8-bit register Rd

(destination register) and stores the resu lt in the 8-bit register Rd.

Available Registers

Rd: R0L to R7L, R0H to R7H

Rs: R0L to R7L, R0 H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate XOR.B #xx:8, Rd D rd IMM 2

Notes

Section 2 Instruction Descriptions

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2.2.63 (2) XOR (W)

XOR (eXclusive O R logical) Exclusive Logical OR

Operation

Rd ⊕ (EAs) → Rd

Assembly-Language Format

XOR.W <EAs>, Rd

Operand Size

Word

Condition Code

IUIHUNZVC

———— —0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction exclusively ORs the source operand with the contents of a 16-bit register Rd

(destination register) and stores the resu lt in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate XOR.W #xx:16, Rd 7 9 5 rd IMM 4

Notes

Section 2 Instruction Descriptions

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2.2.63 (3) XOR (L)

XOR (eXclusive O R logical) Exclusive Logical OR

Operation

ERd ⊕ (EAs) → ERd

Assembly-Language Format

XOR.L <EAs>, ERd

Operand Size

Longword

Condition Code

IUIHUNZVC

———— —0

↔

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; oth erwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction exclusively ORs the source operand with the contents of a 32-bit register ERd

(destination register) and sto res the result in the 32-b it register ERd.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte No. of

States

Immediate XOR.L #xx:32, ERd 7 A 5 0 erd IMM 6

Notes

Section 2 Instruction Descriptions

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2.2.64 XORC

XORC (eXclusive OR Control register) Exclusive Logical OR with CCR

Operation

CCR ⊕ #IMM → CCR

Assembly-Language Format

XORC #xx:8, CCR

Operand Size

Byte

Condition Code

IUIHUNZVC

↔

I: Stores the corresponding bit of the result.

UI: Stores the corresponding bit of the result.

H: Stores the corresponding bit of the result.

U: Stores the corresponding bit of the result.

N: Stores the corresponding bit of the result.

Z: Stores the corresponding bit of the result.

V: Stores the corresponding bit of the result.

C: Stores the corresponding bit of the result.

Description

This instr uction e xclusivel y ORs the contents of th e c ondition-code register (CCR) with

immediate da ta and stores the result in the condition-code register. No interrupt requests,

including NMI, are accepted immediately after execution of this instruction.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immediate XORC #xx:8, CCR 0 5 IMM 2

Notes

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2.3 Instruction Set Summary

Table 2.1 Instruction Set Summary

Addressing Modes

Function Instruction

#xx

@ERn

@(d:16,ERn)

@(d:24,ERn)

@ERn+/@–ERn

@aa:8

@aa:16

@aa:24

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

MOV BWL BWL BWL BWL BWL BWL B BWL BWL — — — —Data

transfer POP, PUSH————————————WL

MOVFPE,

MOVTPE ———————B—————

ADD, CMPBWLBWL———————————Arithmetic

operations SUB WLBWL———————————

ADDX,

SUBX B B———————————

ADDS,

SUBS — L ———————————

INC, DEC —BWL———————————

DAA, DAS —B———————————

MULXU,

DIVXU,

MULXS,

DIVXS

—BW———————————

NEG —BWL———————————

EXTU, EXTS—WL——————— ————

AND, OR,

XOR BWLBWL———————————Logic

operations

NOT —BWL———————————

Shift operati ons — BWL — — — — — — — — — — —

Bit manipulation — B B — — — B — — — — — —

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 192 of 258

REJ09B0213-0300

Addressing Modes

Function Instruction

#xx

@ERn

@(d:16,ERn)

@(d:24,ERn)

@ERn+/@–ERn

@aa:8

@aa:16

@aa:24

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

Branch Bcc, BSR ————————— ——

JMP, JSR — — ————— —— —

RTS ————————————

System

control TRAPA,

RTE,

SLEEP

————————————

LDC B BWWWW—WW————

STC —BWWWW—WW————

ANDC,

ORC,

XORC

B————————————

NOP ————————————

Block data transfer ————————————B

Legend:

B: Byte

W: Word

L: Longword

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 193 of 258

REJ09B0213-0300

Table 2.2 Instruction Set

(1) Data Transfer Instructions

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

MOV MOV.B #xx:8,Rd B 2 #xx:8→Rd8 — —

↔

0— 2 2

MOV.B Rs,R d B 2 Rs8→Rd8 — —

↔

0— 2 2

MOV.B @ERs,Rd B 2 @ERs→Rd8 — —

↔

0— 4 4

MOV.B @(d:16, ERs), Rd B 4 @(d:16,ERs)→Rd8 — —

↔

0— 6 6

MOV.B @(d:24,ERs),Rd B 8 @(d24:,ERs24)→Rd8 — —

↔

0 — 10 10

MOV.B @ERs+,Rd B 2 @ERs→Rd8,ERs32+1→ERs32 — —

↔

0— 6 6

MOV.B @aa:8,Rd B 2 @aa:8→Rd8 — —

↔

0— 4 4

MOV.B @aa:16,Rd B 4 @aa:16→Rd8 — —

↔

0— 6 6

MOV.B @aa:24,Rd B 6 @aa:24→Rd8 — —

↔

0— 8 8

MOV.B Rs,@ERd B 2 Rs8→@ERd24 — —

↔

0— 4 4

MOV.B Rs,@(d:16,ERd) B 4 Rd8→@(d:16,ERd) — —

↔

0— 6 6

MOV.B Rs,@(d:24,ERd) B 8 Rd8→@(d:24,ERd) — —

↔

0 — 10 10

MOV.B Rs,@–ERd B 2 ERd32-1→ERd32,Rs8→@ERd — —

↔

0— 6 6

MOV.B Rs,@aa:8 B 2 Rs8→@aa:8 — —

↔

0— 4 4

MOV.B Rs,@aa:16 B 4 Rs8→@aa:16 — —

↔

0— 6 6

MOV.B Rs,@aa:24 B 6 Rs8→@aa:24 — —

↔

0— 8 8

MOV.W #xx:16,Rd W 4 #xx:16→Rd16 — —

↔

0— 4 4

MOV.W Rs,Rd W 2 Rs16→Rd16 — —

↔

0— 2 2

MOV.W @ERs, R d W 2 @ERs24→Rd16 — —

↔

0— 4 4

MOV.W @(d:16,ERs),Rd W 4 @(d:16,ERs)→Rd16 — —

↔

0— 6 6

MOV.W @(d:24,ERs),Rd W 8 @(d:24,ERs)→Rd16 — —

↔

0 — 10 10

MOV.W @ERs+,Rd W 2 @ERs→Rd16,ERs32+2→@ERd — —

↔

0— 6 6

MOV.W @aa:16,Rd W 4 @aa:16→Rd16 — —

↔

0— 6 6

MOV.W @aa:24,Rd W 6 @aa:24→Rd16 — —

↔

0— 8 8

MOV.W Rs,@ERd W 2 Rs16→@ERd — —

↔

0— 4 4

MOV.W Rs,@(d:16,ERd) W 4 Rs16→@(d:16,ERd) — —

↔

0— 6 6

MOV.W Rs,@(d:24,ERd) W 8 Rs16→@(d:24,ERd) — —

↔

0— 8 10

MOV.W Rs,@–ERd W 2 ERd32-2→ERd32,Rs16→@ERd24 — —

↔

0— 6 6

MOV.W Rs,@aa:16 W 4 Rs16→@aa:16 — —

↔

0— 6 6

MOV.W Rs,@aa:24 W 6 Rs16→@aa:24 — —

↔

0— 8 8

MOV.L #xx:32,ERd L 6 #xx:32→ERd32 — —

↔

0— 8 6

MOV.L ERs,ERd L 2 ERs32→ERd32 — —

↔

0— 2 2

MOV.L @ERs,ERd L 4 @ERs→ERd32 — —

↔

0— 8 8

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 194 of 258

REJ09B0213-0300

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

MOV MOV.L @(d:16,ERs),ERd L 6 @(d:16,ERs)→ERd32 — —

↔

0 — 10 10

MOV.L @(d:24,ERs),ERd L 10 @(d:24,ERs)→ERd32 — —

↔

0 — 14 14

MOV.L @ERs+,ERd L 4 ERs→ERd32,ERs32+4→@ERs32 — —

↔

0 — 10 10

MOV.L @aa:16,ERd L 6 @aa:16→ERd32 — —

↔

0 — 10 10

MOV.L @aa:24,ERd L 8 @aa:24→ERd32 — —

↔

0 — 12 12

MOV.L ERs,@ERd L 4 ERs32→@ERd24 — —

↔

0— 8 8

MOV.L ERs,@(d:16,ERd) L 6 ERs32→@(d:16,ERd) — —

↔

0 — 10 10

MOV.L ERs,@(d:24,ERd) L 10 ERs32→@(d:24,ERd) — —

↔

0 — 14 14

MOV.L ERs,@–ERd L 4 ERd32-4→ERd32,ERs32→@ERd — —

↔

0 — 10 10

MOV.L ERs,@aa:16 L 6 ERs32→@aa:16 — —

↔

0 — 10 10

MOV.L ERs,@aa:24 L 8 ERs32→@aa:24 — —

↔

0 — 12 12

POP POP.W Rn W 2 @SP→Rn16,SP+2→SP — —

↔

0— 6 6

POP.L ERn L 4 @SP→ERn32,SP+4→SP — —

↔

0— 8 10

PUSH PUSH.W Rn W 2 SP-2→SP,Rn16→@SP — —

↔

0— 6 6

PUSH.L ERn L 4 SP-4→SP,ERn32→@SP — —

↔

0— 8 10

MOVFPE MOVFPE@aa:16,Rd B 4 @aa:16→Rd (synchronized with

E clock) ——

↔

0— (6) (6)

MOVTPE MOVT PE Rs,@aa:16 B 4 Rs→@aa:16 (synchronized with

E clock)R ——

↔

0— (6) (6)

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 195 of 258

REJ09B0213-0300

(2) Arithmetic Operation Instructio ns

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

ADD ADD.B #xx:8,Rd B 2 Rd8+#xx:8→Rd8 —

↔

ADD.B Rs,Rd B 2 Rd8+Rs8→Rd8 —

↔

ADD.W #xx:16,Rd W 4 Rd16+#xx:16→Rd16 — (1)

↔

ADD.W Rs,Rd W 2 Rd16+Rs16→Rd16 — (1)

↔

ADD.L #xx:32,ERd L 6 ERd32+#xx:32→ERd32 — (2)

↔

ADD.L ERs,ERd L 2 ERd32+ERs32→ERd32 — (2)

↔

ADDX ADDX #xx:8,Rd B 2 Rd8+#xx:8+C→Rd8 —

↔

(3)

↔

ADDX Rs,Rd B 2 Rd8+Rs8+C→Rd8 —

↔

(3)

↔

ADDS ADDS.L #1,ERd L 2 ERd32+1→ERd32 —————— 2 2

ADDS.L #2,ERd L 2 ERd32+2→ERd32 —————— 2 2

ADDS.L #4,ERd L 2 ERd32+4→ERd32 —————— 2 2

INC INC.B Rd B 2 Rd8+1→Rd8 — —

↔

—2 2

INC.W #1,Rd W 2 Rd16+1→Rd16 — —

↔

—2 2

INC.W #2,Rd W 2 Rd16+2→Rd16 — —

↔

—2 2

INC.L #1,ERd L 2 ERd32+1→ERd32 — —

↔

—2 2

INC.L #2,ERd L 2 ERd32+2→ERd32 — —

↔

—2 2

DAA DAA Rd B 2 Rd8 decimal adjust →Rd8 — *

↔

SUB SUB.B Rs,Rd B 2 Rd8–Rs8→Rd8 —

↔

SUB.W #xx:16,Rd W 4 Rd16–#xx:16→Rd16 — (1)

↔

SUB.W Rs,Rd W 2 Rd16–Rs16→Rd16 — (1)

↔

SUB.L #xx:32,ERd L 6 ERd32–#xx:32→ERd32 — (2)

↔

SUB.L ERs,ERd L 2 ERd32–ERs32→ERd32 — (2)

↔

SUBX SUBX.B #xx:8,Rd B 2 Rd8–#xx:8–C→Rd8 —

↔

(3)

↔

SUBX.B Rs,Rd B 2 Rd8–Rs8–C→Rd8 —

↔

(3)

↔

SUBS SUBS.L #1,ERd L 2 Erd32–1→ERd32 —————— 2 2

SUBS.L #2,ERd L 2 ERd32–2→ERd32 —————— 2 2

SUBS.L #4,ERd L 2 ERd32–4→ERd32 —————— 2 2

DEC DEC.B Rd B 2 Rd8–1→Rd8 — —

↔

—2 2

DEC.W #1,Rd W 2 Rd16–1→Rd16 — —

↔

—2 2

DEC.W #2,Rd W 2 Rd16–2→Rd16 — —

↔

—2 2

DEC.L #1,ERd L 2 ERd32–1→ERd32 — —

↔

—2 2

DEC.L #2,ERd L 2 ERd32–2→ERd32 — —

↔

—2 2

DAS DAS Rd B 2 Rd8 decimal adjust →Rd8 — *

↔

*—2 2

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 196 of 258

REJ09B0213-0300

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

NEG NEG.B Rd B 2 0–Rd8→Rd8 —

↔

NEG.W Rd W 2 0–Rd16→Rd16 —

↔

NEG.L ERd L 2 0–ERd32-ERd32 —

↔

CMP CMP.B #xx:8,Rd B 2 Rd8–#xx:8 —

↔

CMP.B Rs,Rd B 2 Rd8–Rs8 —

↔

CMP.W #xx:16,Rd W 4 Rd16–#xx:16 — (1)

↔

CMP.W Rs,Rd W 2 Rd16–Rs16 — (1)

↔

CMP.L #xx:32,ERd L 6 ERd32–#xx:32 — (2)

↔

CMP.L ERs,ERd L 2 ERd32–ERs32 — (2)

↔

MULXU MULXU.B Rs,Rd B 2 Rd8 × Rs8→Rd16

(unsigned operation) —————— 14 14

MULXU.W Rs,ERd W 2 Rd16 × Rs16→ERd32

(unsigned operation) —————— 22 22

MULXS MULXS.B Rs,R d B 4 Rd8 × Rs8 → Rd16

(signed operation) ——

↔

— — 16 16

MULXS.W Rs,ERd W 4 Rd16 × Rs16 → ERd32

(signed operation) ——

↔

— — 24 24

DIVXU DIVXU.B Rs,Rd B 2 Rd16 ÷ Rs8 → Rd16 (RdH: remainder,

RdL: quotient) (unsigned operation) — — (6) (7) — — 14 14

DIVXU.W Rs,ERd W 2 ERd32 ÷ Rs16 → ERd32

(Ed: remainder, Rd: quotient) (unsigned

operation)

— — (6) (7) — — 22 22

DIVXS DIVXS.B Rs,Rd B 4 Rd16 ÷ Rs8 → Rd16 (RdH: remainder,

RdL: quotient) (signed operation) — — (8) (7) — — 16 16

DIVXS.W Rs,ERd W 4 ERd32 ÷ Rs16 → ERd32

(Ed: remainder, Rd: quotient) (signed

operation)

— — (8) (7) — — 24 24

EXTU EXTU.W Rd W 2 0 → (<bits 15 to 8> of Rd16) — — 0

↔

0— 2 2

EXTU.L ERd L 2 0 → (<bits 31 to 16> of ERd32) — — 0

↔

0— 2 2

EXTS EXTS.W Rd W 2 (<bit 7> of Rd16) → (<bits 15 to 8> of

Rd16) ——

↔

0— 2 2

EXTS.L ERd L 2 (<bit 15> of ERd32) → (<bits 31 to 16>

of ERd32) ——

↔

0— 2 2

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 197 of 258

REJ09B0213-0300

(3) Logic Operation Instructions

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

AND AND.B #xx:8,Rd B 2 Rd8 ∧ #xx:8→Rd8 — —

↔

0— 2 2

AND.B Rs,Rd B 2 Rd8 ∧ Rs8→Rd8 — —

↔

0— 2 2

AND.W #xx:16,Rd W 4 Rd16 ∧ #xx:16→Rd16 — —

↔

0— 4 4

AND.W Rs,Rd W 2 Rd16 ∧ Rs16→Rd16 — —

↔

0— 2 2

AND.L #xx:32,ERd L 6 ERd32 ∧ #xx:32→ERd32 — —

↔

0— 6 6

AND.L ERs,ERd L 4 ERd32 ∧ ERs32→ERd32 — —

↔

0— 4 4

OR OR.B #xx:8,Rd B 2 Rd8 ∨ #xx:8→Rd8 — —

↔

0— 2 2

OR.B Rs,Rd B 2 Rd8 ∨ Rs8→Rd8 — —

↔

0— 2 2

OR.W #xx:16,Rd W 4 Rd16 ∨ #xx:16→Rd16 — —

↔

0— 4 4

OR.W Rs,Rd W 2 Rd16 ∨ Rs16→Rd16 — —

↔

0— 2 2

OR.L #xx:32,ERd L 6 ERd32 ∨ #xx:32→ERd32 — —

↔

0— 6 6

OR.L ERs,ERd L 4 ERd32 ∨ ERs32→ERd32 — —

↔

0— 4 4

XOR XOR.B #xx:8,Rd B 2 Rd8⊕#xx:8→Rd8 — —

↔

0— 2 2

XOR.B Rs,Rd B 2 Rd8⊕Rs8→Rd8 — —

↔

0— 2 2

XOR.W #xx:16,Rd W 4 Rd16⊕#xx:16→Rd16 — —

↔

0— 4 4

XOR.W Rs,Rd W 2 Rd16⊕Rs16→Rd16 — —

↔

0— 2 2

XOR.L #xx:32,ERd L 6 ERd32⊕#xx:32→ERd32 — —

↔

0— 6 6

XOR.L ERs,ERd L 4 ERd32⊕ERs32→ERd32 — —

↔

0— 4 4

NOT NOT.B Rd B 2 ¬Rd8→Rd8 — —

↔

0— 2 2

NOT.W Rd W 2 ¬Rd16→Rd16 — —

↔

0— 2 2

NOT.L ERd L 2 ¬Rd32→Rd32 — —

↔

0— 2 2

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 198 of 258

REJ09B0213-0300

(4) Shift Instructions

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

SHAL SHAL.B Rd B 2 — —

↔

SHAL.W Rd W 2 — —

↔

SHAL.L ERd L 2

MSB LSB 0

——

↔

SHAR SHAR.B Rd B 2 — —

↔

SHAR.W Rd W 2 — —

↔

SHAR.L ERd L 2

MSB LSB C

——

↔

SHLL SHLL.B Rd B 2 — —

↔

SHLL.W Rd W 2 — —

↔

SHLL.L ERd L 2

MSB LSB 0

——

↔

SHLR SHLR.B Rd B 2 — —

↔

SHLR.W Rd W 2 — —

↔

SHLR.L ERd L 2 MSB LSB C

——

↔

ROTXL.B Rd B 2 — —

↔

ROTXL.W Rd W 2 — —

↔

ROTXL

ROTXL.L ERd L 2

MSB LSBC

——

↔

ROTXR ROTXR.B Rd B 2 — —

↔

ROTXR.W Rd W 2 — —

↔

ROTXR.L ERd L 2

MSB LSB C

——

↔

ROTL ROTL.B Rd B 2 — —

↔

ROTL.W Rd W 2 — —

↔

ROTL.L ERd L 2

MSB LSBC

——

↔

ROTR ROTR.B Rd B 2 — —

↔

ROTR.W Rd W 2 — —

↔

ROTR.L ERd L 2

MSB LSB C

——

↔

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 199 of 258

REJ09B0213-0300

(5) Bit Manipulation Instructions

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

BSET BSET #xx :3,Rd B 2 (#xx:3 of Rd8)←1 —————— 2 2

BSET #xx:3,@ERd B 4 (#xx:3 of @ERd)←1 —————— 8 8

BSET #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)←1 —————— 8 8

BSET Rn,Rd B 2 (Rn8 of Rd8)←1 —————— 2 2

BSET Rn,@ERd B 4 (Rn8 of @ERd)←1 —————— 8 8

BSET Rn,@aa:8 B 4 (Rn8 of @aa:8)←1 —————— 8 8

BCLR BCLR #xx:3,Rd B 2 (#xx:3 of Rd8)←0 —————— 2 2

BCLR #xx:3,@ERd B 4 (#xx:3 of @ERd)←0 —————— 8 8

BCLR #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)←0 —————— 8 8

BCLR Rn,Rd B 2 (Rn8 of Rd8)←0 —————— 2 2

BCLR Rn,@ERd B 4 (Rn8 of @ERd)←0 —————— 8 8

BCLR Rn,@aa:8 B 4 (Rn8 of @aa:8)←0 —————— 8 8

BNOT BNOT #xx:3,Rd B 2 (#xx:3 of Rd8)←¬(#xx:3 of Rd8) —————— 2 2

BNOT #xx:3,@ERd B 4 (#xx:3 of @ERd)←¬(#xx:3 of @ERd) —————— 8 8

BNOT #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)←¬(#xx:3 of @aa:8) —————— 8 8

BNOT Rn,Rd B 2 (Rn8 of Rd8)←¬(Rn8 of Rd8) —————— 2 2

BNOT Rn,@ERd B 4 (Rn8 of @ERd)←¬(Rn8 of @ERd) —————— 8 8

BNOT Rn,@aa:8 B 4 (Rn8 of @aa:8)←¬(Rn8 of @aa:8) —————— 8 8

BTST BTST #xx:3,Rd B 2 (#xx:3 of Rd8)→Z ———

↔

—— 2 2

BTST #xx:3,@ERd B 4 (#xx:3 of @ERd)→Z ———

↔

—— 6 6

BTST #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)→Z ———

↔

—— 6 6

BTST Rn,Rd B 2 (Rn8 of Rd8)→Z ———

↔

—— 2 2

BTST Rn,@ERd B 4 (Rn8 of @ERd)→Z ———

↔

—— 6 6

BTST Rn,@aa:8 B 4 (Rn8 of @aa:8)→Z ———

↔

—— 6 6

BLD BLD #xx:3,Rd B 2 (#xx:3 of Rd8)→C —————

↔

BLD #xx:3,@ERd B 4 (#xx:3 of @ERd)→C —————

↔

BLD #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)→C —————

↔

BILD BILD #xx:3,Rd B 2 ¬(#xx:3 of Rd8)→C —————

↔

BILD #xx:3,@ERd B 4 ¬(#xx:3 of @ERd24)→C —————

↔

BILD #xx:3,@aa:8 B 4 ¬(#xx:3 of @aa:8)→C —————

↔

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 200 of 258

REJ09B0213-0300

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

BST BST #xx:3,Rd B 2 C →(#xx:3 of Rd8) —————— 2 2

BST #xx:3,@ERd B 4 C→(#xx:3 of @ERd24) —————— 8 8

BST #xx:3,@aa:8 B 4 C→(#xx:3 of @aa:8) —————— 8 8

BIST BIST #xx:3,Rd B 2 /C→(#xx:3 of Rd8) —————— 2 2

BIST #xx:3,@ERd B 4 /C→(#xx:3 of @ERd24) —————— 8 8

BIST #xx:3,@aa:8 B 4 /C→(#xx:3 of @aa:8) —————— 8 8

BAND BAND #xx:3,Rd B 2 C∧(#xx:3 of Rd8)→C —————

↔

BAND #xx:3,@ERd B 4 C∧(#xx:3 of @ERd24)→C —————

↔

BAND #xx:3,@aa:8 B 4 C∧(#xx:3 of @aa:8)→C —————

↔

BIAND BIAND #xx:3,Rd B 2 C∧¬(/#xx:3 of Rd8)→C —————

↔

BIAND #xx:3,@ERd B 4 C∧¬(/#xx:3 of @ERd24)→C —————

↔

BIAND #xx:3,@aa:8 B 4 C∧¬(/#xx:3 of @aa:8)→C —————

↔

BOR BOR #xx:3,Rd B 2 C ∨ (#xx:3 of Rd8)→C —————

↔

BOR #xx:3,@ERd B 4 C ∨ (#xx:3 of @ERd24)→C —————

↔

BOR #xx:3,@aa:8 B 4 C ∨ (#xx:3 of @aa:8)→C —————

↔

BIOR BIOR #xx:3,Rd B 2 C ∨ ~(#xx:3 of Rd8)→C —————

↔

BIOR #xx:3,@ERd B 4 C ∨ ~(#xx:3 of @ERd24)→C —————

↔

BIOR #xx:3,@aa:8 B 4 C ∨ ~(#xx:3 of @aa:8)→C —————

↔

BXOR BXOR #xx:3,Rd B 2 C ⊕ (#xx:3 of Rd8)→C —————

↔

BXOR #xx:3,@ERd B 4 C ⊕ (#xx:3 of @ERd24)→C —————

↔

BXOR #xx:3,@aa:8 B 4 C ⊕ (#xx:3 of @aa:8)→C —————

↔

BIXOR BIXOR #xx:3,Rd B 2 C ⊕ ~(#xx:3 of Rd8)→C —————

↔

BIXOR #xx:3,@ERd B 4 C ⊕ ~(#xx:3 of @ERd24)→C —————

↔

BIXOR #xx:3,@aa:8 B 4 C ⊕ ~(#xx:3 of @aa:8)→C —————

↔

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 201 of 258

REJ09B0213-0300

(6) Branch Instructions

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation Branch

condition I H N Z V C Normal Ad-

vanced

Bcc BRA d:8(BTd:8) — 2 Always —————— 4 4

BRA d:16(BTd:16) — 4 —————— 6 6

BRN d:8(BFd:8) — 2

if condition is true then

PC←PC+d

else next; Never —————— 4 4

BRN d:16(BFd:16) — 4 —————— 6 6

BHI d:8 — 2 C ∨ Z = 0 —————— 4 4

BHI d:16 — 4 —————— 6 6

BLS d:8 — 2 C ∨ Z = 1 —————— 4 4

BLS d:16 — 4 —————— 6 6

BCC d:8(BHS d:8) — 2 C = 0 —————— 4 4

BCC d:16(BHS d:16) — 4 —————— 6 6

BCS d:8(BLO d:8) — 2 C = 1 —————— 4 4

BCS d:16(BLO d:16) — 4 —————— 6 6

BNE d:8 — 2 Z = 0 —————— 4 4

BNE d:16 — 4 —————— 6 6

BEQ d:8 — 2 Z = 1 —————— 4 4

BEQ d:16 — 4 —————— 6 6

BVC d:8 — 2 V = 0 —————— 4 4

BVC d:16 — 4 —————— 6 6

BVS d:8 — 2 V = 1 —————— 4 4

BVS d:16 — 4 —————— 6 6

BPL d:8 — 2 N = 0 —————— 4 4

BPL d:16 — 4 —————— 6 6

BMI d:8 — 2 N = 1 —————— 4 4

BMI d:16 — 4 —————— 6 6

BGE d:8 — 2 N ⊕ V = 0 —————— 4 4

BGE d:16 — 4 —————— 6 6

BLT d:8 — 2 N ⊕ V = 1 —————— 4 4

BLT d:16 — 4 —————— 6 6

BGT d:8 — 2 Z ∨ (N ⊕ V) = 0 —————— 4 4

BGT d:16 — 4 —————— 6 6

BLE d:8 — 2 Z ∨ (N ⊕ V) = 1 —————— 4 4

BLE d:16 — 4 —————— 6 6

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 202 of 258

REJ09B0213-0300

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation Branch

condition I H N Z V C Normal Ad-

vanced

JMP JMP @ERn — 2 PC←ERn —————— 4 4

JMP @aa:24 — 4 PC←aa:24 —————— 6 6

JMP @@aa:8 — 2 PC←@aa:8 —————— 8 10

BSR BSR d:8 — 2 PC→@-SP,

PC←PC+d:8 —————— 6 8

BSR d:16 — 4 PC→@-SP,

PC←PC+d:16 —————— 8 10

JSR JSR @ERn — 2 PC→@-SP,

PC←ERn —————— 6 8

JSR @aa:24 — 4 PC→@-SP,

PC←aa:24 —————— 8 10

JSR @@aa:8 — 2 PC→@-SP,

PC←@aa:8 —————— 8 12

RTS RTS — 2 PC←@SP+ —————— 8 10

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(7) System Control Instructions

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

TRAPA TRAPA #x:2 — 2 PC→ @–SP, CCR→@–SP,

<vector> → PC (1)————— 14 14

RTE RTE — CCR←@SP+,PC←@SP+

↔

10 10

SLEEP SLEEP — Transition to power-down state —————— 2 2

LDC LDC #xx:8,CCR B 2 #xx:8→CCR

↔

LDC Rs,CCR B 2 Rs8→CCR

↔

LDC @ERs,CCR W 4 @ERs→CCR

↔

LDC @(d:16,ERs),CCR W 6 @(d:16,ERs)→CCR

↔

LDC @(d:16,ERs),CCR W 10 @(d:24,ERs)→CCR

↔

12 12

LDC @ERs+,CCR W 4 @ERs→CCR,ERs32+2→ERs32

↔

LDC @aa:16,CCR W 6 @aa:16→CCR

↔

LDC @aa:24,CCR W 8 @aa:24→CCR

↔

10 10

STC STC CCR,Rd B 2 CCR→Rd8 —————— 2 2

STC CCR,@ERd W 4 CCR→@ERd —————— 6 6

STC CCR,@(d:16,ERs) W 6 CCR→@(d:16,ERs24) —————— 8 8

STC CCR,@(d:24,ERs) W 10 CCR→@(d:24,ERs24) —————— 12 12

STC CCR,@–ERs W 4 ERd32-2→ERd24,CCR→@ERd24 —————— 8 8

STC CCR,@aa:1 6 W 6 CCR→@aa:16 —————— 8 8

STC CCR,@aa:2 4 W 8 CCR→@aa:24 —————— 10 10

ANDC ANDC #xx:8,CCR B 2 CCR ∧#xx:8→CCR

↔

ORC ORC # xx:8,CCR B 2 CCR V#xx:8→CCR

↔

XORC XORC #xx:8,CCR B 2 CCR⊕#xx:8→CCR

↔

NOP NOP — 2 PC←PC+2 —

↔

———— 2 2

Section 2 Instruction Descriptions

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(8) Block Transfer Instructions

Addressing Mode and

Instruction Length (bytes) Condition Code No. of States

Mnemonic

Size

#xx

@ERn

@(d,ERn)

@ERn+/@–ERn

@aa

@(d,PC)

@@aa

—

Operation I H N Z V C Normal Ad-

vanced

EEPMOV EEPMOV.B — 4 if R4L ≠ 0

Repeat @R5→@R6

R5+1→R5

R6+1→R6

R4L–1→R4L

Until R4L = 0

else next;

——————8+4n

*28+4n*2

EEPMOV.W — 4 if R4 ≠ 0

Repeat @R5→@R6

R5+1→R5

R6+1→R6

R4L–1→R4L

Until R4 = 0

else next;

——————8+4n

*28+4n*2

Notes: 1. The number of states is the number of states required for execution when the i nst ruct i on and its

operands are located in on-chi p memory. For other cases see section 2.6, Number of States

Required for Exec ution.

2. n is the value set in register R4L or R4.

(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.

(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.

(3) Retai ns its previous value when the result is zero; otherwise cleared to 0.

(4) S et to 1 when the adjustm ent produc es a carry; otherwi se retains its previous val ue.

(5) The num ber of states required for execution of an instruction t hat transfers data in synchronization

with the E clock is variable.

(6) Set to 1 when the divisor is negative; otherwise cleared to 0.

(7) Set to 1 when the divisor is zero; otherwise cleared to 0.

(8) Set to 1 when the quotient is negative; otherwise cleared to 0.

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2.4 Instruction Codes

Table 2.3 Instruction Codes

Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

ADD B

—

ADD.B #xx:8,Rd B 8 rd IMM

ADD.B Rs,Rd 0 8 rs rd

ADD.W #xx:16,Rd W 7 9 1 rd IMM

ADD.W Rs,Rd 0 9 rs rd

ADD.L #xx:32,ERd L 7 A 1 0 erd IMM

ADD.L ERs,ERd L 0 A 1 ers 0 erd

ADDS ADDS #1,ERd L 0 B 0 0 erd

ADDS #2,ERd L 0 B 8 0 erd

ADDS #4,ERd L 0 B 9 0 erd

ADDX ADDX #xx:8,Rd B 9 rd IMM

ADDX Rs,Rd 0 E rs rd

AND AND.B #xx:8,Rd B E rd IMM

AND.B Rs,Rd 1 6 rs rd

AND.W #xx:16,Rd W 7 9 6 rd IMM

AND.W Rs,Rd 6 6 rs rd

AND.L #xx:32,ERd L 7 A 6 0 erd IMM

AND.L ERs,ERd L 0 1 F 0 6 6 0 ers 0 erd

ANDC ANDC #xx:8,CCR B 0 6 IMM

BAND BAND #xx:3,Rd B 7 6 0 IMM rd

BAND #xx:3,@ERd B 7 C 0 erd 0 7 6 0 IMM 0

BAND #xx:3,@aa:8 B 7 E abs 7 6 0 IMM 0

Bcc BRA d:8 (BT d:8) — 4 0 disp

BRA d:16 (BT d:16) — 5 8 0 0 disp

BRN d:8 (BF d:8) — 4 1 disp

BRN d:16 (BF d:16) — 5 8 1 0 disp

BHI d:8 4 2 disp

BHI d:16 — 5 8 2 0 disp

BLS d:8 4 3 disp

BLS d:16 — 5 8 3 0 disp

BCC d:8 (BHS d:8) — 4 4 disp

BCC d:16 (BHS d:16) — 5 8 4 0 disp

BCS d:8 (BLO d:8) — 4 5 disp

Instruction Mnemonic Size

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Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Bcc —

—

BCS d:16 (BLO d:16) — 585 0 disp

BNE d:8 4 6 disp

BNE d:16 — 586 0 disp

BEQ d:8 4 7 disp

BEQ d:16 — 587 0 disp

BVC d:8 4 8 disp

BVC d:16 — 588 0 disp

BVS d:8 4 9 disp

BVS d:16 — 589 0 disp

BPL d:8 4 A disp

BPL d:16 — 58A 0 disp

BMI d:8 4 B disp

BMI d:16 — 58B 0 disp

BGE d:8 4 C disp

BGE d:16 — 58C 0 disp

BLT d:8 4 D disp

BLT d:16 —58D 0 disp

BGT d:8 4 E disp

BGT d:16 — 58E 0 disp

BLE d:8 4 F disp

BLE d:16 — 58F 0 disp

BCLR BCLR #xx:3,Rd B 7 2 0 IMM rd

BCLR #xx:3,@ERd B 7 D 0 erd 0 7 2 0 IMM 0

BCLR #xx:3,@aa:8 B 7 F abs 7 2 0 IMM 0

BCLR Rn,Rd B 6 2 rn rd

BCLR Rn,@ERd B 7 D 0 erd 0 6 2 rn 0

BCLR Rn,@aa:8 B 7 F abs 6 2 rn 0

BIAND BIAND #xx:3,Rd B 7 6 1 IMM rd

BIAND #xx:3,@ERd B 7 C 0 erd 0 7 6 1 IMM 0

BIAND #xx:3,@aa:8 B 7 E abs 7 6 1 IMM 0

BILD BILD #xx:3,Rd B 7 7 1 IMM rd

BILD #xx:3,@ERd B 7 C 0 erd 0 7 7 1 IMM 0

BILD #xx:3,@aa:8 B 7 E abs 7 7 1 IMM 0

Instruction Mnemonic Size

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Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

BIOR

—

BIOR #xx:3,Rd 7 4 1 IMM rd

BIOR #xx:3,@ERd B 7 C 0 erd 0 7 4 1 IMM 0

BIOR #xx:3,@aa:8 B 7 E abs 7 4 1 IMM 0

BIST BIST #xx:3,Rd B 6 7 1 IMM rd

BIST #xx:3,@ERd B 7 D 0 erd 0 6 7 1 IMM 0

BIST #xx:3,@aa:8 B 7 F abs 6 7 1 IMM 0

BIXOR BIXOR #xx:3,Rd B 7 5 1 IMM rd

BIXOR #xx:3,@ERd B 7 C 0 erd 0 7 5 1 IMM 0

BIXOR #xx:3,@aa:8 B 7 E abs 7 5 1 IMM 0

BLD BLD #xx:3,Rd 7 7 0 IMM rd

BLD #xx:3,@ERd B 7 C 0 erd 0 7 7 0 IMM 0

BLD #xx:3,@aa:8 B 7 E abs 7 7 0 IMM 0

BNOT BNOT #xx:3,Rd B 7 1 0 IMM rd

BNOT #xx:3,@ERd B 7 D 0 erd 0 7 1 0 IMM 0

BNOT #xx:3,@aa:8 B 7 F abs 7 1 0 IMM 0

BNOT Rn,Rd B 6 1 rn rd

BNOT Rn,@ERd B 7 D 0 erd 0 6 1 rn 0

BNOT Rn,@aa:8 B 7 F abs 6 1 rn 0

BOR BOR #xx:3,Rd B 7 4 0 IMM rd

BOR #xx:3,@ERd B 7 C 0 erd 0 7 4 0 IMM 0

BOR #xx:3,@aa:8 B 7 E abs 7 4 0 IMM 0

BSET BSET #xx:3,Rd B 7 0 0 IMM rd

BSET #xx:3,@ERd B 7 D 0 erd 0 7 0 0 IMM 0

BSET #xx:3,@aa:8 B 7 F abs 7 0 0 IMM 0

BSET Rn,Rd B 6 0 rn rd

BSET Rn,@ERd B 7 D 0 erd 0 6 0 rn 0

BSET Rn,@aa:8 B 7 F abs 6 0 rn 0

BSR BSR d:8 5 5 disp

BSR d:16 — 5C0 0 disp

BST BST #xx:3,Rd 6 7 0 IMM rd

BST #xx:3,@ERd B 7 D 0 erd 0 6 7 0 IMM 0

BST #xx:3,@aa:8 B 7 F abs 6 7 0 IMM 0

Instruction Mnemonic Size

Section 2 Instruction Descriptions

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Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

BTST

BTST #xx:3,Rd 7 3 0 IMM rd

BTST #xx:3,@ERd B 7 C 0 erd 0 7 3 0 IMM 0

BTST #xx:3,@aa:8 B 7 E abs 7 3 0 IMM 0

BTST Rn,Rd 6 3 rn rd

BTST Rn,@ERd B 7 C 0 erd 0 6 3 rn 0

BTST Rn,@aa:8 B 7 E abs 6 3 rn 0

BXOR BXOR #xx:3,Rd B 7 5 0 IMM rd

BXOR #xx:3,@ERd B 7 C 0 erd 0 7 5 0 IMM 0

BXOR #xx:3,@aa:8 B 7 E abs 7 5 0 IMM 0

CMP CMP.B #xx:8,Rd B A rd IMM

CMP.B Rs,Rd 1 C rs rd

CMP.W #xx:16,Rd W 7 9 2 rd IMM

CMP.W Rs,Rd W 1 D rs rd

CMP.L #xx:32,ERd L 7 A 2 0 erd IMM

CMP.L ERs,ERd L 1 F 1 ers 0 erd

DAA DAA Rd B 0 F 0 rd

DAS DAS Rd B 1 F 0 rd

DEC DEC.B Rd B 1 A 0 rd

DEC.W #1,Rd 1 B 5 rd

DEC.W #2,Rd 1 B D rd

DEC.L #1,ERd 1 B 7 0 erd

DEC.L #2,ERd 1 B F 0 erd

DIVXS DIVXS.B Rs,Rd B 0 1 D 0 5 1 rs rd

DIVXS.W Rs,ERd W 0 1 D 0 5 3 rs 0 erd

DIVXU DIVXU.B Rs,Rd B 5 1 rs rd

DIVXU.W Rs,ERd W 5 3 rs 0 erd

EEPMOV EEPMOV.B — 7B5 C 59 8 F

EEPMOV.W — 7BD 4 59 8 F

EXTS EXTS.W Rd W 1 7 D rd

EXTS.L ERd L 1 7 F 0 erd

EXTU EXTU.W Rd W 1 7 5 rd

EXTU.L ERd L 1 7 7 0 erd

INC INC.B Rd B 0 A 0 rd

INC.W #1,Rd W 0 B 5 rd

INC.W #2,Rd W 0 B D rd

Instruction Mnemonic Size

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 209 of 258

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Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

—

C INC.L #1,ERd L 0 B 7 0 erd

INC.L #2,ERd L 0 B F 0 erd

JMP JMP @ERn — 5 9 0 ern 0

JMP @aa:24 — 5 A abs

JMP @@aa:8 — 5 B abs

JSR JSR @ERn — 5 D 0 ern 0

JSR @aa:24 — 5 E abs

JSR @@aa:8 5 F abs

LDC LDC #xx:8,CCR B 0 7 IMM

LDC Rs,CCR B 0 3 0 rs

LDC @ERs,CCR W 0 1 4 0 6 9 0 ers 0

LDC @(d:16,ERs),CCR W 0 1 4 0 6 F 0 ers 0 disp

LDC @(d:24,ERs),CCR W 0 1 4 0 7 8 0 ers 0 6 B 2 0 0 0 disp

LDC @ERs+,CCR W 0 1 4 0 6 D 0 ers 0

LDC @aa:16,CCR W 0 1 4 0 6 B 0 0 abs

LDC @aa:24,CCR W 0 1 4 0 6 B 2 0 0 0 abs

MOV MOV.B #xx:8,Rd B F rd IMM

MOV.B Rs,Rd 0 C rs rd

MOV.B @ERs,Rd B 6 8 0 ers rd

MOV.B @(d:16,ERs),Rd B 6 E 0 ers rd disp

MOV.B @(d:24,ERs),Rd B 7 8 0 ers 0 6 A 2 rd 0 0 disp

MOV.B @ERs+,Rd B 6 C 0 ers rd

MOV.B @aa:8,Rd B 2 rd abs

MOV.B @aa:16,Rd B 6 A 0 rd abs

MOV.B @aa:24,Rd B 6 A 2 rd 0 0 abs

MOV.B Rs,@ERd B 6 8 1 erd rs

MOV.B Rs,@(d:16,ERd) B 6 E 1 erd rs disp

MOV.B Rs,@(d:24,ERd) B 7 8 0 erd 0 6 A A rs 0 0 disp

MOV.B Rs,@–ERd B 6 C 1 erd rs

MOV.B Rs,@aa:8 B 3 rs abs

MOV.B Rs,@aa:16 B 6 A 8 rs abs

MOV.B Rs,@aa:24 B 6 A A rs 0 0 abs

MOV.W #xx:16,Rd W 7 9 0 rd IMM

MOV.W Rs,Rd W 0 D rs rd

MOV.W @ERs,Rd W 6 9 0 ers rd

Instruction Mnemonic Size

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 210 of 258

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Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

MOV MOV.W @(d:16,ERs),Rd W 6 F 0 ers rd disp

MOV.W @(d:24,ERs),Rd W 7 8 0 ers 0 6 B 2 rd 0 0 disp

MOV.W @ERs+,Rd W 6 D 0 ers rd

MOV.W @aa:16,Rd W 6 B 0 rd abs

MOV.W @aa:24,Rd W 6 B 2 rd 0 0 abs

MOV.W Rs,@ERd W 6 9 1 erd rs

MOV.W Rs,@(d:16,ERd) W 6 F 1 erd rs disp

MOV.W Rs,@(d:24,ERd) W 7 8 1 erd 0 6 B A rs 0 0 disp

MOV.W Rs,@–ERd W 6 D 1 erd rs

MOV.W Rs,@aa:16 W 6 B 8 rs abs

MOV.W Rs,@aa:24 W 6 B A rs 0 0 abs

MOV.L #xx:32,Rd L 7 A 0 0 erd IMM

MOV.L ERs,ERd L 0 F 1 ers 0 erd

MOV.L @ERs,ERd L 0 1 0 0 6 9 0 ers 0 erd

MOV.L @(d:16,ERs),ERd L 0 1 0 0 6 F 0 ers 0 erd disp

MOV.L @(d:24,ERs),ERd L 0 1 0 0 7 8 0 ers 0 6 B 2 0 erd 0 0 disp

MOV.L @ERs+,ERd L 0 1 0 0 6 D 0 ers 0 erd

MOV.L @aa:16,ERd L 0 1 0 0 6 B 0 0 erd abs

MOV.L @aa:24,ERd L 0 1 0 0 6 B 2 0 erd 0 0 abs

MOV.L ERs,@ERd L 0 1 0 0 6 9 1 erd 0 ers

MOV.L ERs,@(d:16,ERd) L 0 1 0 0 6 F 1 erd 0 ers disp

MOV.L ERs,@(d:24,ERd) L 0 1 0 0 7 8 0 erd 0 6 B A 0 ers 0 0 disp

MOV.L ERs,@–ERd L 0 1 0 0 6 D 1 erd 0 ers

MOV.L ERs,@aa:16 L 0 1 0 0 6 B 8 0 ers abs

MOV.L ERs,@aa:24 L 0 1 0 0 6 B A 0 ers 0 0 abs

MOVFPE MOVFPE @aa:16,Rd B 6 A 4 rd abs

MOVTPE MOVTPE Rs,@aa:16 B 6 A C rs abs

MULXS MULXS.B Rs,Rd B 0 1 C 0 5 0 rs rd

MULXS.W Rs,ERd W 0 1 C 0 5 2 rs 0 erd

MULXU MULXU.B Rs,Rd B 5 0 rs rd

MULXU.W Rs,ERd W 5 2 rs 0 erd

NEG NEG.B Rd B 1 7 8 rd

NEG.W Rd W 1 7 9 rd

NEG.L ERd L 1 7 B 0 erd

NOP NOP — 000 0

Instruction Mnemonic Size

Section 2 Instruction Descriptions

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Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

NOT

NOT.B Rd B 1 7 0 rd

NOT.W Rd W 1 7 1 rd

NOT.L ERd L 1 7 3 0 erd

OR OR.B #xx:8,Rd B C rd IMM

OR.B Rs,Rd B 1 4 rs rd

OR.W #xx:16,Rd W 7 9 4 rd IMM

OR.W Rs,Rd 6 4 rs rd

OR.L #xx:32,ERd L 7 A 4 0 erd IMM

OR.L ERs,ERd L 0 1 F 0 6 4 0 ers 0 ers

ORC ORC #xx:8,CCR B 0 4 IMM

POP POP.W Rn W 6 D 7 rn

POP.L ERn L 0 1 0 0 6 D 7 0 ern

PUSH PUSH.W Rn W 6 D F rn

PUSH.L ERn L 0 1 0 0 6 D F 0 ern

ROTL ROTL.B Rd B 1 2 8 rd

ROTL.W Rd W 1 2 9 rd

ROTL.L ERd L 1 2 B 0 erd

ROTR ROTR.B Rd B 1 3 8 rd

ROTR.W Rd W 1 3 9 rd

ROTR.L ERd L 1 3 B 0 erd

ROTXL ROTXL.B Rd B 1 2 0 rd

ROTXL.W Rd W 1 2 1 rd

ROTXL.L ERd L 1 2 3 0 erd

ROTXR ROTXR.B Rd B 1 3 0 rd

ROTXR.W Rd W 1 3 1 rd

ROTXR.L ERd L 1 3 3 0 erd

RTE RTE —567 0

RTS RTS —547 0

SHAL SHAL.B Rd B 1 0 8 rd

SHAL.W Rd W 1 0 9 rd

SHAL.L ERd L 1 0 B 0 erd

SHAR SHAR.B Rd B 1 1 8 rd

SHAR.W Rd W 1 1 9 rd

SHAR.L ERd L 1 1 B 0 erd

Instruction Mnemonic Size

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 212 of 258

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Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

—

SHLL.B Rd B 1 0 0 rd

SHLL.W Rd W 1 0 1 rd

SHLL.L ERd L 1 0 3 0 erd

SHLR

SHLL

SHLR.B Rd B 1 1 0 rd

SHLR.W Rd W 1 1 1 rd

SHLR.L ERd L 1 1 3 0 erd

SLEEP SLEEP — 018 0

STC STC CCR,Rd B 0 2 0 rd

STC CCR,@ERd W 0 1 4 0 6 9 1 erd 0

STC CCR,@(d:16,ERd) W 0 1 4 0 6 F 1 erd 0 disp

STC CCR,@(d:24,ERd) W 0 1 4 0 7 8 0 erd 0 6 B A 0 0 0 disp

STC CCR,@–ERd W 0 1 4 0 6 D 1 erd 0

STC CCR,@aa:16 W 0 1 4 0 6 B 8 0 abs

STC CCR,@aa:24R W 0 1 4 0 6 B A 0 0 0 abs

SUB SUB.B Rs,Rd 1 8 rs rd

SUB.W #xx:16,Rd W 7 9 3 rd IMM

SUB.W Rs,Rd 1 9 rs rd

SUB.L #xx:32,ERd L 7 A 3 0 erd IMM

SUB.L ERs,ERd L 1 A 1 ers 0 erd

SUBS SUBS #1,ERd L 1 B 0 0 erd

SUBS #2,ERd L 1 B 8 0 erd

SUBS #4,ERd L 1 B 9 0 erd

SUBX SUBX #xx:8,Rd B B rd IMM

SUBX Rs,Rd 1 E rs rd

TRAPA TRAPA #x:2 5 7 00 IMM 0

XOR XOR.B #xx:8,Rd B D rd IMM

XOR.B Rs,Rd 1 5 rs rd

XOR.W #xx:16,Rd W 7 9 5 rd IMM

XOR.W Rs,Rd 6 5 rs rd

XOR.L #xx:32,ERd L 7 A 4 0 erd IMM

XOR.L ERs,ERd L 0 1 F 0 6 5 0 ers 0 erd

XORC XORC #xx:8,CCR B 0 5 IMM

Instruction Mnemonic Size

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Legend:

IMM: Immediate data (2 , 3, 8, 16, or 32 bits)

abs: Absolute address (8, 16, or 24 bits)

disp: Displacement (8, 16, or 24 bits)

rs, rd, rn: Register field (4 bits specifying an 8-bit or 16-bit register. rs corresponds to operand

symbols such as Rs, rd corresponds to operand sy mbols such as Rd, and rn

corresponds to the operand symbol Rn.)

ers, erd, ern: Register field (3 bits specifying a 32-bit register. ers corresponds to operand symbols

such as ERs, erd corresponds to opera nd sym bo ls suc h as ERd, and ern

corresponds to the operand symbol ERn.)

The register fields specify general registers as follows.

Address Register

32-bit Register 16-bit Register 8-bit Register

Field General

000

001

111

ER0

ER1

ER7

0000

0001

0111

1000

1001

1111

0000

0001

0111

1000

1001

1111

R0H

R1H

R7H

R0L

R1L

R7L

2.5 Operation Code Map

Tables 2.4 to 2.6 show an operation code map.

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NOP

Table 2.5

BRA

MULXU

BSET

Table 2.5

BRN

DIVXU

BNOT

STC

Table 2.5

BHI

MULXU

BCLR

LDC

Table 2.5

BLS

DIVXU

BTST

ORG

OR.B

BCC

RTS

OR.W

XORG

XOR.B

BCS

BSR

XOR.W

ANDC

AND.B

BNE

RTE

AND.W

LDC

Table 2.5

BEQ

TRAPA

SUB.B

BVC

Table 2.5

MOV

SUB.W

BVS

Table 2.5

BPL

JMP

Table 2.5

BMI

EEPMOV

MOV

CMP

BGE

BSR

MOV

BLT

ADDX

SUBX

BGT

JSR

Table 2.5

BLE

BOR BIOR BXOR

BIXOR BAND

BIAND

BST BIST

BLD BILD Table 2.6

ADD

ADDX

CMP

SUBX

XOR

AND

MOV

Operation Code:

Table 2.4 Operation Code Map (1)

1st byte 2nd byte

AH AL BH BL

Instruction when most significant bit of BH is 0.

Instruction when most significant bit of BH is 1.

AH AL

ADD

MOV.B

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ADDS

BVS

Operation Code: 1st byte 2nd byte

AH AL BH BL

AH AL BH 0

MOV

INC

ADDS

DAA

DEC

SUBS

DAS

BRA

MOV

BRN

ADD

BHI

CMP

SHLL

SHLR

ROTXL

ROTXR

NOT

BLS

SUB

BCC

INC

EXTU

DEC

BCS

XOR

BNE

AND

INC

EXTU

DEC

BEQ

SLEEP

ADDS

BVC

BPL

SHAL

SHAR

ROTL

ROTR

NEG

BMI

Table 2.6

BGE

Table 2.6

INC

EXTS

DEC

BLT

BGT

Table 2.6

INC

EXTS

DEC

BLE

ADD

MOV

SUB

CMP

SHLL

SHLR

ROTXL

ROTXR

NOT

LDC STC

SHAL

SHAR

ROTL

ROTR

NEG

SUB

Table 2.5 Operation Code Map (2)

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Operation Code: 1st byte 2nd byte

AH AL BH BL

3rd byte 4th byte

CH CL DH DL

01C05

01D05

01F06

7Cr06

7Cr07

7Dr06

7Dr07

7Eaa6

7Eaa7

7Faa6

7Faa7

AHALBHBLCH

CL 0

MULXS

BSET

DIVXS

BNOT

MULXS

BCLR

DIVXS

BTST

XOR

AND

789ABCDEF

BORBIOR BXOR

BIXOR BAND

BIAND BID BILD

BST BIST

BORBIOR BXOR

BIXOR BAND

BIAND BID BILD

BST BIST

r is a register field.

aa is an absolute address field.

Instruction when most significant bit of DH is 0.

Instruction when most significant bit of DH is 1.

Notes: 1.

Table 2.6 Operation Code Map (3)

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2.6 Number of States Required for Instruction Execution

The tables in this section can be used to calculate the number of states required for instruction

execution by the H8/300H CPU. Table 2.8 indicates the number of in struction fetch, data

read/write, and other cycles occurring in each instruction. Table 2.7 indicates the number of states

required for each size. The number of states required for execution of an instruction can be

calculated from these two tables as follows:

Execution states = I × SI + J × SJ + K × SK + L × SK + M × SM + N × SN

Examples: Advanced mode, stack located in external memory, on-chip supporting modules

accessed with 8-bit bus width, ex ternal devices accessed in three states with one wait state and 16-

bit bus width.

1. BSET #0, @FFFFC7:8

From table 2.8:

I = L = 2, J = K = M = N= 0

From table 2.7:

SI = 4, SL = 3

Number of states required for execution = 2 × 4 + 2 × 3 = 14

2. JSR @@30

From table 2.8:

I = J = K = 2, L = M = N = 0

From table 2.7:

SI = SJ = SK = 4

Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24

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Table 2.7 Number of States per Cycle

Access Conditions

On-Chip Supporting

Module 8-Bit Bus 16-Bit Bus

Cycle On-Chip

Memory 8-Bit

Bus 16-Bit

Bus 2-State

Access 3-State

Access 2-State

Access 3-State

Access

Instruction fetch SI2 6 3 4 6 + 2 m 2 3 + m*

Branch address read SJ

Stack operati on S K

Byte data access SL323 + m

Word data access SM6 4 6 + 2 m

Internal operat i on SN1111111

Note: * For the MOVFPE and MOVTPE instructions, refer to the relevant microcontroller

hardware manual.

Legend:

m: Number of wait states inserted into external device access

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Table 2.8 Number of Cycles in Instruction Execution

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

ADD ADD.B #xx:8,Rd 1

ADD.B Rs,Rd 1

ADD.W #xx:16,Rd 2

ADD.W Rs,Rd 1

ADD.L #xx:32,ERd 3

ADD.L ERs,ERd 1

ADDS ADDS #1/2/4,ERd 1

ADDX ADDX #xx:8,Rd 1

ADDX Rs,Rd 1

AND AND.B #xx:8,Rd 1

AND.B Rs,Rd 1

AND.W #xx:16,Rd 2

AND.W Rs,Rd 1

AND.L #xx:32,ERd 3

AND.L ERs,ERd 2

ANDC ANDC #xx:8,CCR 1

BAND BAND #xx:3,Rd 1

BAND #xx:3,@ERd 2 1

BAND #xx:3,@aa:8 2 1

Bcc BRA d:8 (BT d:8) 2

BRN d:8 (BF d:8) 2

BHI d:8 2

BLS d:8 2

BCC d:8 (BHS d:8) 2

BCS d:8 (BLO d:8) 2

BNE d:8 2

BEQ d:8 2

BVC d:8 2

BVS d:8 2

BPL d:8 2

BMI d:8 2

BGE d:8 2

BLT d:8 2

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

Bcc BGT d:8 2

BLE d:8 2

BRA d:16 (BT d:16) 2 2

BRN d:16 (BF d:16) 2 2

BHI d:16 2 2

BLS d:16 2 2

BCC d:16 (BHS d:16) 2 2

BCS d:16 (BLO d:16) 2 2

BNE d:16 2 2

BEQ d:16 2 2

BVC d:16 2 2

BVS d:16 2 2

BPL d:16 2 2

BMI d:16 2 2

BGE d:16 2 2

BLT d:16 2 2

BGT d:16 2 2

BLE d:16 2 2

BCLR BCLR #xx:3,Rd 1

BCLR #xx:3,@ERd 2 2

BCLR #xx:3,@aa:8 2 2

BCLR Rn,Rd 1

BCLR Rn,@ERd 2 2

BCLR Rn,@aa:8 2 2

BIAND BIAND #xx:3,Rd 1

BIAND #xx:3,@ERd 2 1

BIAND #xx:3,@aa:8 2 1

BILD BILD #xx:3,Rd 1

BILD #xx:3,@ERd 2 1

BILD #xx:3,@aa:8 2 1

BIOR BIOR #xx:8,Rd 1

BIOR #xx:8,@ERd 2 1

BIOR #xx:8,@aa:8 2 1

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

BIST BIST #xx:3,Rd 1

BIST #xx:3,@ERd 2 2

BIST #xx:3,@aa:8 2 2

BIXOR BIXOR #xx:3,Rd 1

BIXOR #xx:3,@ERd 2 1

BIXOR #xx:3,@aa:8 2 1

BLD BLD #xx:3,Rd 1

BLD #xx:3,@ERd 2 1

BLD #xx:3,@aa:8 2 1

BNOT BNOT #xx:3,Rd 1

BNOT #xx:3,@ER d 2 2

BNOT #xx:3,@aa:8 2 2

BNOT Rn,Rd 1

BNOT Rn,@ERd 2 2

BNOT Rn,@aa:8 2 2

BOR BOR #xx:3,Rd 1

BOR #xx:3,@ERd 2 1

BOR #xx:3,@aa:8 2 1

BSET BSET #xx:3,Rd 1

BSET #xx:3, @ERd 2 2

BSET #xx:3,@aa:8 2 2

BSET Rn,Rd 1

BSET Rn,@ERd 2 2

BSET Rn,@aa:8 2 2

BSR BSR d:8 Advanced 2 2

Normal 2 1

BSR d:16 Advanced 2 2 2

Normal 2 1 2

BST BST #xx:3,Rd 1

BST #xx:3,@ERd 2 2

BST #xx:3,@aa:8 2 2

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

BTST BTST #xx:3,Rd 1

BTST #xx:3,@ERd 2 1

BTST #xx:3,@ aa: 8 2 1

BTST Rn,Rd 1

BTST Rn,@ERd 2 1

BTST Rn,@aa:8 2 1

BXOR BXOR #xx:3,Rd 1

BXOR #xx:3,@ERd 2 1

BXOR #xx:3,@aa:8 2 1

CMP CMP.B #xx:8,Rd 1

CMP.B Rs,Rd 1

CMP.W #xx:16,Rd 2

CMP.W Rs,Rd 1

CMP.L #xx:32 ,E Rd 3

CMP.L ERs,ERd 1

DAA DAA Rd 1

DAS DAS Rd 1

DEC DEC.B Rd 1

DEC.W #1/2,Rd 1

DEC.L #1/2,ERd 1

DIVXS DIVXS.B Rs,Rd 2 12

DIVXS.W Rs,ERd 2 20

DIVXU DIVXU.B Rs,Rd 1 12

DIVXU.W Rs,ERd 1 20

EEPMOV EEPMOV.B 2 2n + 2*1

EEPMOV.W 2 2n + 2*1

EXTS EXTS.W Rd 1

EXTS.L ERd 1

EXTU EXTU.W Rd 1

EXTU.L ERd 1

INC INC.B Rd 1

INC.W #1/2,Rd 1

INC.L #1/2,E R d 1

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

JMP JMP @ERn 2

JMP @aa:24 2 2

JMP @@aa:8 Advanced 2 2 2

Normal 2 1 2

JSR JSR @ERn Advanced 2 2

Normal 2 1

JSR @aa:24 Advanced 2 2 2

Normal 2 1 2

JSR @@aa:8 Advanced 2 2 2

Normal 2 1 1

LDC LDC #xx:8,CCR 1

LDC Rs,CCR 1

LDC @ERs,CCR 2 1

LDC @(d:16,ERs),CCR 3 1

LDC @(d:24,ERs),CCR 5 1

LDC @ERs+,CCR 2 1 2

LDC @aa:16,CCR 3 1

LDC @aa:24,CCR 4 1

MOV MOV.B #xx:8,Rd 1

MOV.B Rs,Rd 1

MOV.B @ERs,Rd 1 1

MOV.B @(d:16,ERs),Rd 2 1

MOV.B @(d:24,ERs),Rd 4 1

MOV.B @ERs+,Rd 1 1 2

MOV.B @aa:8,Rd 1 1

MOV.B @aa:16,Rd 2 1

MOV.B @aa:24,Rd 3 1

MOV.B Rs,@ERd 1 1

MOV.B Rs,@(d:16,ERd) 2 1

MOV.B Rs,@(d:24,ERd) 4 1

MOV.B Rs,@– ERd 1 1 2

MOV.B Rs,@aa: 8 1 1

MOV.B Rs,@aa: 16 2 1

MOV.B Rs,@aa: 24 3 1

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

MOV MOV.W #xx:16, Rd 2

MOV.W Rs,Rd 1

MOV.W @ERs ,R d 1 1

MOV.W @(d:16,ERs),Rd 2 1

MOV.W @(d:24,ERs),Rd 4 1

MOV.W @ERs+,Rd 1 1 2

MOV.W @aa:16,Rd 2 1

MOV.W @aa:24,Rd 3 1

MOV.W Rs,@ERd 1 1

MOV.W Rs,@(d:16,E R d) 2 1

MOV.W Rs,@(d:24,E R d) 4 1

MOV.W Rs,@–ERd 1 1 2

MOV.W Rs,@aa:16 2 1

MOV.W Rs,@aa:24 3 1

MOV.L #xx:32,ERd 3

MOV.L ERs,ERd 1

MOV.L @ERs,ERd 2 2

MOV.L @(d:16,ERs),ERd 3 2

MOV.L @(d:24,ERs),ERd 5 2

MOV.L @ERs+,ERd 2 2 2

MOV.L @aa:16,ERd 3 2

MOV.L @aa:24,ERd 4 2

MOV.L ERs,@ERd 2 2

MOV.L ERs,@(d:16,ERd) 3 2

MOV.L ERs,@(d:24,ERd) 5 2

MOV.L ERs,@–ERd 2 2 2

MOV.L ERs,@aa:16 3 2

MOV.L ERs,@aa:24 4 2

MOVFPE MOVFPE @:aa:16,Rd 2 1*2

MOVTPE MOVTPE Rs,@:aa:16 2 1*2

MULXS MULXS.B Rs,Rd 2 12

MULXS.W Rs,ERd 2 20

MULXU MULXU.B Rs,Rd 1 12

MULXU.W Rs,ERd 1 20

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

NEG NEG.B Rd 1

NEG.W Rd 1

NEG.L ERd 1

NOP NOP 1

NOT NOT.B Rd 1

NOT.W Rd 1

NOT.L ERd 1

OR OR.B #xx:8,Rd 1

OR.B Rs,Rd 1

OR.W #xx:16,Rd 2

OR.W Rs,Rd 1

OR.L #xx:32,ER d 3

OR.L ERs,ERd 2

ORC ORC #xx:8,CCR 1

POP POP.W Rn 1 1 2

POP.L ERn 2 2 2

PUSH PUSH.W Rn 1 1 2

PUSH.L ERn 1 2 2

ROTL ROTL.B Rd 1

ROTL.W Rd 1

ROTL.L ERd 1

ROTR ROTR.B Rd 1

ROTR.W Rd 1

ROTR.L ERd 1

ROTXL ROTXL.B Rd 1

ROTXL.W Rd 1

ROTXL.L ERd 1

ROTXR ROTXR.B Rd 1

ROTXR.W Rd 1

ROTXR.L ERd 1

RTE RTE 2 2 2

RTS RTS Advanced 2 2 2

Normal 2 1 2

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

SHAL SHAL.B Rd 1

SHAL.W Rd 1

SHAL.L ERd 1

SHAR SHAR.B Rd 1

SHAR.W Rd 1

SHAR.L ERd 1

SHLL SHLL.B Rd 1

SHLL.W Rd 1

SHLL.L ERd 1

SHLR SHLR.B Rd 1

SHLR.W Rd 1

SHLR.L ERd 1

SLEEP SLEEP 1

STC STC CCR,Rd 1

STC CCR,@ERd 2 1

STC CCR,@(d:16,ERd) 3 1

STC CCR,@(d:24,ERd) 5 1

STC CCR,@–ERd 2 1 2

STC CCR,@aa:16 3 1

STC CCR,@aa:24 4 1

SUB SUB.B Rs,Rd 1

SUB.W #xx:16,Rd 2

SUB.W Rs,Rd 1

SUB.L #xx:32,ERd 3

SUB.L ERs,ERd 1

SUBS SUBS #1/2/4,ERd 1

SUBX SUBX #xx:8,Rd 1

SUBX Rs,Rd 1

TRAPA TRAPA #x:2 Advanced 2 2 2 4

Normal 2 1 2 4

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

XOR XOR.B #xx:8,Rd 1

XOR.B Rs,Rd 1

XOR.W #xx:16,Rd 2

XOR.W Rs,Rd 1

XOR.L #xx:32,E R d 3

XOR.L ERs,ERd 2

XORC XORC #xx:8,CCR 1

Notes: 1. When n bytes of data are transferred.

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2.7 Condition Code Modification

This section ind icates th e effect of each CPU instruction on the condition code. The notation used

in the table is def ined below.

m 31 for longword operands, 15 for word operands, 7 for byte operands

SiThe i-th bit of the source operand

DiThe i-th bit of the destination operand

RiThe i-th bit of the result

DnThe specified bit in the destination operand

— Not affected

↔

Modified according to the result of the instruction (see definition)

0 Always cleared to 0

1 Always set to 1

* Undetermined (no guaranteed value)

Z' Z flag before instruction execution

C' C flag before instruction execution

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Table 2.9 Condition Co de Modification

Instruction H N Z V C Definition

ADD

↔

H = S m – 4 · D m – 4 + D m – 4 · / R m – 4 + S m – 4 · / R m – 4

N = R m

Z = / R m · / R m – 1 · ... · / R 0

V = S m · D m · / R m + / S m · / D m · R m

C = S m · D m + D m · / R m + S m · / R m

ADDS —————

ADDX

↔

H = S m – 4 · D m – 4 + D m – 4 · / R m – 4 + S m – 4 · / R m – 4

N = R m

Z = Z ' · / R m · ... · / R 0

V = S m · D m · / R m + / S m · / D m · R m

C = S m · D m + D m · / R m + S m · / R m

AND —

↔

O — N = R m

Z = / R m · / R m – 1 · ... · / R 0

ANDC

↔

Stores the corresponding bits of the result

BAND — — — —

↔

C = C ' · D n

Bcc —————

BCLR —————

BIAND — — — —

↔

C = C ' · / D n

BILD ————

↔

C = / D n

BIOR ————

↔

C = C ' + / D n

BIST —————

BIXOR — — — —

↔

C = C ' · / D n + / C ' · / D n

BLD — — — —

↔

C = D n

BNOT —————

BOR — — — —

↔

C = C ' + D n

BSET —————

BSR —————

BST —————

BTST — —

↔

——Z = / D n

BXOR — — — —

↔

C = C ' · / D n + / C ' · D n

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Instruction H N Z V C Definition

CMP

↔

H = S m – 4 · / D m – 4 + / D m – 4 · R m – 4 + S m – 4 · R m – 4

N = R m

Z = / R m · / R m – 1 · ... · / R 0

V = / S m · D m · / R m + S m · / D m · R m

C = S m · / D m + / D m · R m + S m · R m

DAA *

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

C: decimal arit hm etic carry

DAS *

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

C: decimal arit hm etic borrow

DEC —

↔

—N = R m

Z = / R m· / R m – 1 · ... · / R 0

V = D m · / R m

DIVXS —

↔

— — N = S m · / D m + / S m · D m

Z = / S m · / S m – 1 · ... · / S 0

DIVXU —

↔

——N = S m

Z = / S m · / S m – 1 · ... · / S 0

EEPMOV —————

EXTS —

↔

O — N = R m

Z = / R m · / R m – 1 · ... · / R 0

EXTU — O

↔

O — Z = / R m · / R m – 1 · ... · / R 0

INC —

↔

—N = R m

Z = / R m · / R m – 1 · ... · / R 0

V = D m · / R m

JMP —————

JSR —————

LDC

↔

Stores the corresponding bits of the result

MOV —

↔

O — N = R m

Z = / R m · / R m – 1 · ... · / R 0

MOVFPE —

↔

O — N = R m

Z = / R m · / R m – 1 · ... · / R 0

MOVTPE —

↔

O — N = R m

Z = / R m · / R m – 1 · ... · / R 0

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Instruction H N Z V C Definition

MULXS —

↔

— — N = R 2 m

Z = R 2 m · R 2 m – 1 · ... · / R 0

MULXU —————

NEG

↔

H = D m – 4 + R m – 4

N = R m

Z = / R m · / R m – 1 · ... · R 0

V = D m · R m

C = D m + R m

NOP —————

NOT —

↔

O — N = R m

Z = / R m · / R m – 1 · ... · / R 0

OR —

↔

O — N = R m

Z = / R m · / R m – 1 · .... · / R 0

ORC

↔

Stores the corresponding bits of the result

POP —

↔

O — N = R m

Z = / R m · / R m – 1 · ... · / R 0

PUSH —

↔

O — N = R m

Z = / R m · / R m – 1 · ... · / R 0

ROTL —

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

C = D m

ROTR —

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

C = D 0

ROTXL —

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

C = D m

ROTXR —

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

C = D 0

RTS —————

RTE

↔

Stores the corresponding bits of the result

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Instruction H N Z V C Definition

SHAL —

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

V = D m · / D m – 1 + / D m · D m – 1

C = D m

SHAR —

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

C = D 0

SHLL —

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

C = D m

SHLR —

↔

N = R m

Z = / R m · / R m – 1 · ... · / R 0

C = D 0

SLEEP —————

STC —————

SUB

↔

H = S m – 4 · / D m – 4 + / D m – 4 · R m – 4 + S m – 4 · R m – 4

N = R m

Z = / R m · / R m – 1 · ... · / R 0

V = / S m · D m · / R m + S m · / D m · R m

C = S m · / D m + / D m · R m + S m · R m

SUBS —————

SUBX

↔

H = S m – 4 · / D m – 4 + / D m – 4 · R m – 4 + S m – 4 · R m – 4

N = R m

Z = Z ' · / R m · ... · / R 0

V = / S m · D m · / R m + S m · / D m · R m

C = S m · / D m + / D m · R m + S m · R m

TRAPA —————

XOR —

↔

O — N = R m

Z = / R m · / R m – 1 · ... · / R 0

XORC

↔

Stores the corresponding bits of the result

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 233 of 258

REJ09B0213-0300

2.8 Bus Cycles During Instruction Execution

Table 2.10 indicates the bus cycles during instruction ex ecution by the H8/300H CPU. For the

number of states per bus cycle, see table 2.7, Number of States per Cycle.

How to read the table:

Internal operation

(2 states)

Order of bus cycles

End of instruction

Read effective address (word-size read)

No read or write

Instruction 1 2 3 4 5 6 7 8

JMP @aa:24 R:W 2nd R:W EA

Read 2nd word of current instruction

(word-size read)

Legend

R:B Byte-size re ad

R:W Word-size read

W:B Byte-size wri te

W:W Word-size write

2nd Address of 2nd word (3rd and 4th bytes)

3rd Address of 3rd word (5th and 6th bytes)

4th Address of 4th word (7th and 8th bytes)

5th Address of 5th word (9th and 10th bytes)

NEXT Address of next instruction

EA Effective address

VEC Vector address

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 234 of 258

REJ09B0213-0300

Figure 2.1 shows timing waveforms for the address bus and the RD and WR (HWR or LWR)

signals during execution of the above instruction with an 8-bit bus, using 3-state access with no

wait states.

Address bus

(HWR or LWR)High level

Internal

operation

Fetching

3rd byte

of instruction

Fetching

4th byte

of instruction

Fetching

1st byte of

jump address

Fetching

2nd byte of

jump address

R:W EAR:W 2nd

Figure 2.1 Address Bus, RD

RDRD

RD, and WR

WRWR

WR ( HWR

HWRHWR

HWR or LWR

LWRLWR

LWR) Timing

(8-bit bus, 3-st ate ac cess, no wa it states)

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 235 of 258

REJ09B0213-0300

Instruction 8

1234567

ADD.B #xx:8,Rd R:W NEXT

ADD.B Rs,Rd R:W NEXT

ADD.W #xx:16,Rd R:W 2nd R:W NEXT

ADD.W Rs,Rd R:W NEXT

ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

ADD.L ERs,ERd R:W NEXT

ADDS #1/2/4,ERd R:W NEXT

ADDX #xx:8,Rd R:W NEXT

ADDX Rs,Rd R:W NEXT

AND.B #xx:8,Rd R:W NEXT

AND.B Rs,Rd R:W NEXT

AND.W #xx:16,Rd R:W 2nd R:W NEXT

AND.W Rs,Rd R:W NEXT

AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

AND.L ERs,ERd R:W 2nd R:W NEXT

ANDC #xx:8,CCR R:W NEXT

BAND #xx:3,Rd R:W NEXT

BAND #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BRA d:8 (BT d;8) R:W NEXT R:W EA

BRN d:8 (BF d;8) R:W NEXT R:W EA

BHI d:8 R:W EA

BLS d:

R:W NEXT

8 R:W EA

BCC d:8 (BHS d;8) R:W EA

BCS d:8 (BLO d;8) R:W EA

BNE d:8 R:W EA

BEQ d:8 R:W EA

BVC d:8 R:W EA

BVS d:8 R:W EA

BPL d:8 R:W EA

BMI d:8 R:W EA

Table 2.10 Bus States

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 236 of 258

REJ09B0213-0300

Instruction 8

1234567

BGE d: R:W NEXT

R:W NEXT

8 R:W EA

BLT d:8 R:W EA

BGT d:8 R:W EA

BLE d:8 R:W EA

BRA d:16 (BT d;16) R:W 2nd Internal operation, R:W EA

2 states

BRN d:16 (BF d;16) R:W 2nd Internal operation, R:W EA

2 states

BHI d:16 R:W 2nd Internal operation, R:W EA

2 states

BLS d:16 R:W 2nd Internal operation, R:W EA

2 states

BCC d:16 (BHS d;16) R:W 2nd Internal operation, R:W EA

2 states

BCS d:16 (BLO d;16) R:W 2nd Internal operation, R:W EA

2 states

BNE d:16 R:W 2nd Internal operation, R:W EA

2 states

BEQ d:16 R:W 2nd Internal operation, R:W EA

2 states

BVC d:16 R:W 2nd Internal operation, R:W EA

2 states

BVS d:16 R:W 2nd Internal operation, R:W EA

2 states

BPL d:16 R:W 2nd Internal operation, R:W EA

2 states

BMI d:16 R:W 2nd Internal operation, R:W EA

2 states

BGE d:16 R:W 2nd Internal operation, R:W EA

2 states

BLT d:16 R:W 2nd Internal operation, R:W EA

2 states

BGT d:16 R:W 2nd Internal operation, R:W EA

2 states

BLE d:16 R:W 2nd Internal operation, R:W EA

2 states

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 237 of 258

REJ09B0213-0300

Instruction 8

1234567

BCLR #xx:3,Rd R:W NEXT

BCLR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BCLR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BCLR Rn,Rd R:W NEXT

BCLR Rn,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BCLR Rn,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BIAND #xx:3,Rd R:W NEXT

BIAND #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BIAND #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BILD #xx:3,Rd R:W NEXT

BILD #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BIOR #xx:8,Rd R:W NEXT

BIOR #xx:8,@ERd R:W 2nd R:B EA R:W NEXT

BIOR #xx:8,@aa:8 R:W 2nd R:B EA R:W NEXT

BIST #xx:3,Rd R:W NEXT

BIST #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BIST #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BIXOR #xx:3,Rd R:W NEXT

BIXOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BIXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BLD #xx:3,Rd R:W NEXT

BLD #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BNOT #xx:3,Rd R:W NEXT

BNOT #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BNOT #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BNOT Rn,Rd R:W NEXT

BNOT Rn,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BNOT Rn,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BOR #xx:3,Rd R:W NEXT

BOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BSET #xx:3,Rd R:W NEXT

BSET #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BSET #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 238 of 258

REJ09B0213-0300

Instruction 8

1234567

BSET Rn,Rd R:W NEXT

BSET Rn,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BSET Rn,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BRS d:8 Normal R:W NEXT R:W EA W:W Stack

Advanced R:W NEXT R:W EA W:W Stack (H) W:W Stack (L)

BRS d:16 Normal R:W 2nd R:W EA W:W Stack

Advanced R:W 2nd R:W EA W:W Stack (H) W:W Stack (L)

BST #xx:3,Rd R:W NEXT

BST #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BST #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BTST #xx:3,Rd R:W NEXT

BTST #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BTST Rn,Rd R:W NEXT

BTST Rn,@ERd R:W 2nd R:B EA R:W NEXT

BTST Rn,@aa:8 R:W 2nd R:B EA R:W NEXT

BXOR #xx:3,Rd R:W NEXT

BXOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

CMP.B #xx:8,Rd R:W NEXT

CMP.B Rs,Rd R:W NEXT

CMP.W #xx:16,Rd R:W 2nd R:W NEXT

CMP.W Rs,Rd R:W NEXT

CMP.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

CMP.L ERs,ERd R:W NEXT

DAA Rd R:W NEXT

DAS Rd R:W NEXT

DEC.B Rd R:W NEXT

DEC.W #1/2,Rd R:W NEXT

DEC.L #1/2,ERd R:W NEXT

DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 12 states

DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 20 states

DIVXU.B Rs,Rd R:W NEXT Internal operation, 12 states

DIVXU.W Rs,ERd R:W NEXT Internal operation, 20 states

EEPMOV.B R:W 2nd R:B EAs *1R:B EAd *1R:B EAs *2W:B EAd *2R:W NEXT

EEPMOV.W R:W 2nd R:B EAs *1R:B EAd *1R:B EAs *2W:B EAd *2R:W NEXT

Internal operation, 2 states

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 239 of 258

REJ09B0213-0300

Instruction 8

1234567

EXTS.W Rd R:W NEXT

EXTS.L ERd R:W NEXT

EXTU.W Rd R:W NEXT

EXTU.L ERd R:W NEXT

INC.B Rd R:W NEXT

INC.W #1/2,Rd R:W NEXT

INC.L #1/2,ERd R:W NEXT

JMP @ERn R:W NEXT R:W EA

JMP @aa:24 R:W 2nd Internal operation, R:W EA

2 states

JMP @@aa:8 Normal R:W NEXT R:W aa:8 Internal operation, R:W EA

2 states

Advanced R:W NEXT R:W aa:8 R:W aa:8 Internal operation, R:W EA

2 states

JSR @ERn Normal R:W NEXT R:W EA W:W Stack

Advanced R:W NEXT R:W EA W:W Stack (H) W:W Stack (L)

JSR @aa:24 Normal R:W 2nd Internal operation, R:W EA W:W Stack

2 states

Advanced R:W 2nd Internal operation, R:W EA W:W Stack (H) W:W Stack (L)

2 states

JSR @@aa:8 Normal R:W NEXT R:W aa:8 W:W Stack R:W EA

Advanced R:W NEXT R:W aa:8 R:W aa:8 W:W Stack (H) W:W Stack (L) R:W EA

LDC #xx:8,CCR R:W NEXT

LDC Rs,CCR R:W NEXT

LDC @ERs,CCR R:W 2nd R:W NEXT R:W EA

LDC @(d:16,ERs),CCR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @(d:24,ERs),CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA

LDC @ERs+,CCR R:W 2nd R:W NEXT Internal operation, R:W EA

2 states

LDC @aa:16,CCR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @aa:24,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA

MOV.B #xx:8,Rd R:W NEXT

MOV.B Rs,Rd R:W NEXT

MOV.B @ERs,Rd R:W NEXT R:B EA

MOV.B @(d:16,ERs),Rd R:W 2nd R:W NEXT R:B EA

MOV.B @(d:24,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:B EA

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 240 of 258

REJ09B0213-0300

Instruction 81234567

MOV.B @ERs+,Rd R:W NEXT Internal operation, R:B EA

2 states

MOV.B @aa:8,Rd R:W NEXT R:B EA

MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA

MOV.B @aa:24,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA

MOV.B Rs,@ERd R:W NEXT W:B EA

MOV.B Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:B EA

MOV.B Rs,@(d:24,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:B EA

MOV.B Rs,@–ERd R:W NEXT Internal operation, W:B EA

2 states

MOV.B Rs,@aa:8 R:W NEXT W:B EA

MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W:B EA

MOV.B Rs,@aa:24 R:W 2nd R:W 3rd R:W NEXT W:B EA

MOV.W #xx:16,Rd R:W 2nd R:W NEXT

MOV.W Rs,Rd R:W NEXT

MOV.W @ERs,Rd R:W NEXT R:W EA

MOV.W @(d:16,ERs),Rd R:W 2nd R:W NEXT R:W EA

MOV.W @(d:24,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA

MOV.W @ERs+,Rd R:W NEXT Internal operation, R:W EA

2 states

MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA

MOV.W @aa:24,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA

MOV.W Rs,@ERd R:W NEXT W:W EA

MOV.W Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:W EA

MOV.W Rs,@(d:24,ERd) R:W 2nd R:W 3rd R:E 4th R:W NEXT W:W EA

MOV.W Rs,@–ERd R:W NEXT Internal operation, W:W EA

2 states

MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA

MOV.W Rs,@aa:24 R:W 2nd R:W 3rd R:W NEXT W:W EA

MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

MOV.L ERs,ERd R:W NEXT

MOV.L @ERs,ERd R:W 2nd R:W NEXT R:W EA R:W EA+2

MOV.L @(d:16,ERs),ERd R:W 2nd R:W 3rd R:W NEXT R:W EA R:W EA+2

MOV.L @(d:24,ERs),ERd R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA R:W EA+2

MOV.L @ERs+,ERd R:W 2nd R:W NEXT Internal operation, R:W EA R:W EA+2

2 states

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 241 of 258

REJ09B0213-0300

Instruction 8

1234567

MOV.L @aa:16,ERd R:W 2nd R:W 3rd R:W NEXT R:W EA R:W EA+2

MOV.L @aa:24,ERd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA R:W EA+2

MOV.L ERs,@ERd R:W 2nd R:W NEXT W:W EA W:W EA+2

MOV.L ERs,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA W:W EA+2

MOV.L ERs,@(d:24,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA W:W EA+2

MOV.L ERs,@–ERd R:W 2nd R:W NEXT Internal operation, W:W EA W:W EA+2

2 states

MOV.L ERs,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA W:W EA+2

MOV.L ERs,@aa:24 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA W:W EA+2

MOVFPE @aa:16,Rd R:W 2nd Internal operation, R:W

2 states

MOVTPE Rs,@aa:16 R:W 2nd Internal operation, W:B

2 states

MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 12 states

MULXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 20 states

MULXU.B Rs,Rd R:W NEXT Internal operation, 12 states

MULXU.W Rs,ERd R:W NEXT Internal operation, 20 states

NEG.B Rd R:W NEXT

NEG.W Rd R:W NEXT

NEG.L ERd R:W NEXT

NOP R:W NEXT

NOT.B Rd R:W NEXT

NOT.W Rd R:W NEXT

NOT.L ERd R:W NEXT

OR.B #xx:8,Rd R:W NEXT

OR.B Rs,Rd R:W NEXT

OR.W #xx:16,Rd R:W 2nd R:W NEXT

OR.W Rs,Rd R:W NEXT

OR.L #xx:32,ERd R:W 2nd R:W rd R:W NEXT

OR.L ERs,ERd R:W 2nd R:W NEXT

ORC #xx:8,CCR R:W NEXT

POP.W Rn R:W NEXT Internal operation, R:W Stack

2 states

POP.L ERn R:W 2nd R:W NEXT Internal operation, R:W Stack (H) R:W Stack (L)

2 states

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 242 of 258

REJ09B0213-0300

Instruction 8

1234567

PUSH.W Rn R:W NEXT Internal operation, W:W Stack

2 states

PUSH.L ERn R:W 2nd R:W NEXT Internal operation, W:W Stack (L) W:W Stack (H)

2 states

ROTL.B Rd R:W NEXT

ROTL.W Rd R:W NEXT

ROTL.L ERd R:W NEXT

ROTR.B Rd R:W NEXT

ROTR.W Rd R:W NEXT

ROTR.L ERd R:W NEXT

ROTXL.B Rd R:W NEXT

ROTXL.W Rd R:W NEXT

ROTXL.L ERd R:W NEXT

ROTXR.B Rd R:W NEXT

ROTXR.W Rd R:W NEXT

ROTXR.L ERd R:W NEXT

RT R:W NEXTE R:W Stack (H) R:W Stack (L) Internal operation, R:W (*4)

2 states

RTS Normal R:W NEXT R:W Stack Internal operation, R:W (*4)

2 states

Advanced R:W NEXT R:W Stack (H) R:W Stack (L) Internal operation, R:W (*4)

2 states

SHAL.B Rd R:W NEXT

SHAL.W Rd R:W NEXT

SHAL.L ERd R:W NEXT

SHAR.B Rd R:W NEXT

SHAR.W Rd R:W NEXT

SHAR.L ERd R:W NEXT

SHLL.B Rd R:W NEXT

SHLL.W Rd R:W NEXT

SHLL.L ERd R:W NEXT

SHLR.B Rd R:W NEXT

SHLR.W Rd R:W NEXT

SHLR.L ERd R:W NEXT

SLEEP R:W NEXT

STC CCR,Rd R:W NEXT

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 243 of 258

REJ09B0213-0300

Instruction 8

1234567

STC CCR,@ERd R:W 2nd R:W NEXT W:W EA

STC CCR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA

STC CCR,@(d:24,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA

STC CCR,@–ERd R:W 2nd R:W NEXT Internal operation, W:W EA

2 states

STC CCR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA

STC CCR,@aa:24 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA

SUB.B Rs,Rd R:W NEXT

SUB.W #xx:16,Rd R:W 2nd R:W NEXT

SUB.W Rs,Rd R:W NEXT

SUB.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

SUB.L ERs,ERd R:W NEXT

SUBS #1/2/4,ERd R:W NEXT

SUBX #xx:8,Rd R:W NEXT

SUBX Rs,Rd R:W NEXT

TRAPA #x:2 Normal R:W NEXT Internal operation, W:W Stack (L) W:W Stack (H) R:W VEC Internal operation, R:W (*7)

2 states 2 states

Advanced R:W NEXT Internal operation, W:W Stack (L) W:W Stack (H) R:W VEC R:W VEC+2 Internal operation, R:W (*7)

2 states 2 states

XOR.B #xx8,Rd R:W NEXT

XOR.B Rs,Rd R:W NEXT

XOR.W #xx:16,Rd R:W 2nd R:W NEXT

XOR.W Rs,Rd R:W NEXT

XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

XOR.L ERs,ERd R:W 2nd R:W NEXT

XORC #xx:8,CCR R:W NEXT

Reset exception Normal R:W VEC Internal operation, R:W (*5)

handlin 2 states

2 states

Advanced R:W VEC R:W VEC+2 Internal operation, R:W (*5)

2 states

Interrupt exception Normal R:W (*6) Internal operation, W:W stack (L) W:W stack (H) R:W VEC Internal operation, R:W (*7)

handling 2 states

Advanced R:W (*6) Internal operation, W:W stack (L) W:W stack (H) R:W VEC R:W VEC+2 Internal operation, R:W (*7)

2 states 2 states

Section 2 Instruction Descriptions

Rev. 3.00 Dec 13, 2004 page 244 of 258

REJ09B0213-0300

Notes: 1. EAs is the contents of ER5. EAd is the contents of R6.

2. EAs is the contents of ER5. EAd is the contents of R6. Both registers are incremented

by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these

bus cycles are not executed.

3. The number of states required for byte read or write varies from 9 to 16.

4. Starting address after return.

5. Starting address of the program.

6. Prefetch address, equal to two plus the PC value pushed on the stack. In recovery from

sleep mode or software standby mode the read operation is replaced by an internal

operation.

7. Starting address of the interrupt-handling routine.

8. NEXT: Next address after the current instruction.

2nd: Address of the second word of the current instruction.

3rd: Address of the third word of the current instruction.

4th: Address of the fourth word of the current instruction.

5th: Address of the fifth word of the current instruction.

EA: Effective address.

VEC: Vector address.

Section 3 Proc essing States

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REJ09B0213-0300

Section 3 Processing States

3.1 Overview

The CPU has five main processing states: the program execution state, exception handling state,

power-down state, reset state, and bus-released state. The power-down state includes sleep mode,

software standby mode, and hardware standby mode. Figure 3.1 shows a diagram of the

processing states. Figure 3.2 indicates the state transitions. For details, refer to the relevant

microcontroller hardware manual.

Program execution

state

The CPU executes program instructions in sequence.

Exception-handling

state

A transient state in which the CPU executes a hardware

sequence (saving the program counter and condition-code

interrupt, or other exception.

Bus-released state

The external bus has been released in response to an external

or internal bus request signal.

Reset state

The CPU and all on-chip supporting modules have been

initialized and are stopped.

Power-down state

Some or all clock signals are

stopped to conserve power.

Sleep mode

Software standby

mode

Hardware standby

mode

Processing

states

Figure 3.1 Processing States

Section 3 Proc essing States

Rev. 3.00 Dec 13, 2004 page 246 of 258

REJ09B0213-0300

End of bus-released state

Bus request

Program execution

state

End of bus-

released state

Bus request

Bus-released state

End of exception handling

Request for exception handling

Interrupt request

Sleep mode

Exception-handling state External interrupt Software standby mode

RES high

Bus request

completion

Bus

request

Reset state STBY high, RES low Hardware standby mode

Power-down state

SLEEP instruction with SSBY = 1

SLEEP

instruction with

SSBY = 0

Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES

goes low.

2. From any state, a transition to hardware standby mode occurs when STBY goes low.

Figure 3.2 State Transitions

3.2 Program Execution State

In this state the CPU executes program instructions in normal sequence.

3.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

program flow due to a reset, interrup t, or trap instruction. The CPU fetches a starting address from

the exception vector table and branches to that address. In interrupt exception handling the CPU

references the stack pointer (ER7) and saves the program counter and condition-code register.

Section 3 Proc essing States

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3.3.1 Types of Exception Handling and Their Priority

Exception handling is performed for resets, interrupts, and trap instructions. Table 3.1 indicates

the types o f excep tion handling and their prio rity.

Table 3.1 Exceptio n Handling Types and Pr iority

Priority Type of Exception Detection Timing Start of Exception Handling

High Reset Synchronized with

clock Exception handling starts

immediately when RES changes

from low to high

Interrupt End of instruction

execution (see note) When an interrupt is requested,

exception handling starts at the end

of the current instruct ion or current

exception-handling sequence

Low Trap instruction When TRAPA

instruct ion is exe cuted Exception handling starts when a

trap (TRAPA) instruction is executed

Note: I nterrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or

immediately after reset exception handling.

Figure 3.3 classifies the exception sources. For further details about exception sources, vector

numbers, and vector addresses refer to the relevant microcontroller hardware manual.

Exception sources

Reset

Interrupt

Trap instruction

External interrupts

Internal interrupts (from on-chip supporting modules)

Figure 3.3 Classification of Exception Sources

Section 3 Proc essing States

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3.3.2 Exception-Handling Sequences

Reset Exception Handling: Reset exception handling has the highest priority. The reset state is

entered when the RES signal goes low. Then, if RES goes high again, reset exception handling

starts when the r eset condition is satisf ied. Refer to the re levan t m icroco ntroller hardware manual

for details about the reset con dition. When reset exception handling starts th e CPU f e tches a start

address from the exception vector table and starts program execution from that address. All

interrupts, including NMI, are disabled during the reset exception-handling sequence and

immediately after it ends.

Interrupt Exception Handling and Trap Instruction Exception Handling: When these exception-

handling sequences begin, the CPU references the stack pointer (ER7) and pushes the program

counter and condition-code register on the stack. Next, if the UE bit in the system control register

(SYSCR) is set to 1, the CPU sets the I bit in the condition- code register to 1. If the UE bit is

cleared to 0, the CPU sets bo th the I bit and the UI bit in th e condition-code register to 1 . Then the

CPU fetches a start address from the exception vector table and execution branches to that

address.

The program-counter value pushed on the stack and the start address fetched from the vector table

are 16 bits long in normal mode and 24 bits long in advanced mode. Figure 3.4 shows the stack

after the exception-handling sequence.

Section 3 Proc essing States

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REJ09B0213-0300

Even address

SP (ER7)

SP + 1

SP + 2

SP + 3

SP + 4

SP – 4

SP – 3

SP – 2

SP – 1

SP (ER7)

Before exception

handling starts After exception

handling ends

(a) Stack structure in normal mode

Even address

SP (ER7)

SP + 1

SP + 2

SP + 3

SP + 4

SP – 4

SP – 3

SP – 2

SP – 1

SP (ER7)

Before exception

handling starts After exception

handling ends

(b) Stack structure in advanced mode

Pushed on stack

Legend:

Program counter (PC) bits 23 to 16

Program counter (PC) bits 15 to 8

Program counter (PC) bits 7 to 0

Condition code register

Stack pointer

PCE:

PCH:

PCL:

CCR:

SP:

Ignored at return.

1. PC is the address of the first instruction executed after the return from the exception-handling

routine.

2. Registers must be saved and restored by word access or longword access, starting at

an even address.

Notes:

Stack area

CCR

PCL

CCR

PCE

PCH

PCL

Figure 3.4 Stack Structure after Exception Handling

Section 3 Proc essing States

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3.4 Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master

other than the CPU. Wh ile the bus is released, the CPU halts except for internal operations. For

further details, refer to th e relevant microcontroller hardware manual.

For further details, refer to the relevant microcontroller hardware manu al.

3.5 Reset State

When the RES input goes low all current processing stops and the CPU enters the reset state. The I

bit in the condition-code register is set to 1 by a reset. All inter rup ts ar e masked in the reset state.

Reset exception handling starts when the RES signal changes from low to high.

3.6 Power-Down State

In the power-down state the CPU stops operating to conserve power. There are three modes: sleep

mode, software standby mode, and hardware standby mode. For details, refer to the relevant

microcontroller hardware manual.

3.6.1 Sleep Mode

A transition to sleep mode is made if the SLEEP instruction is executed while the software

standby bit (SSBY) is cleared to 0.

CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU

registers are retained.

3.6.2 Software St andby Mode

A transition to software standby mode is made if the SLEEP instruction is executed while the

SSBY bit is set to 1.

The CPU and clock halt and all on-chip supporting modules stop operating. The on-chip

supporting modules are reset, but as long as a specified voltage is supplied the contents of CPU

registers and on-chip RAM are retained. The I/O ports also remain in their existing states.

Section 3 Proc essing States

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3.6.3 Hardware Standby Mode

A transition to hardware standby mode is made when the STBY input goes low.

As in software standby mode, the CPU and clock halt and the on-chip supporting modules are

reset, but as long as a specified voltage is supplied, on -chip RAM contents are retained.

Section 3 Proc essing States

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Section 4 Basic Timing

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Section 4 Basic Timing

4.1 Overview

The CPU is driven by a clock, denoted by the symbol φ. One cycle of the clock is referred to as a

“state.” The memory cycle or bus cycle consists of two or three states. Different methods are used

to access on-chip memory, on-chip supporting modules, and external devices. Refer to the relevant

microcontroller hardware manual for details.

4.2 On-Chip Memory (RAM, ROM)

For high-speed processing, on-ch ip memory is accessed in two states. The data bus is 16 bits wide,

permitting both byte and word access. Fig ure 4.1 shows the on-chip memory access cy cle. Figure

4.2 shows the pin states.

Internal address bus

Internal read signal

Internal data bus

(read access)

Internal write signal

Internal data bus

(write access)

Bus cycle

state T

state

Address

Read data

Write data

Figure 4.1 On-Chip Memory Access Cycle

Section 4 Basic Timing

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Bus cycle

state T

state

AddressAddress bus

High

WR (HWR or LWR)

High

Data bus

high-impedance state

Figure 4.2 Pin States during On-Chip Memory Access

Section 4 Basic Timing

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4.3 On-Chip Supporting Modules

The on-chip supporting modules are accessed in three states. The data bus is 8 bits or 16 bits wide.

Figure 4.3 shows the access timing for the on-chip supporting modules. Figure 4.4 shows the pin

states.

Bus cycle

T1 state T2 state

Address

Read data

Write data

T3 state

Internal address

bus

Internal read

signal

Internal data bus

(read access)

Internal write

signal

Internal data bus

(write access)

Figure 4.3 On-Chip Supporting Mo dule Access Cycle

Section 4 Basic Timing

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Bus cycle

state T

state

Address

Address bus

High

WR (HWR or LWR)

High

Data bus

high-impedance

state

Figure 4.4 Pin States during O n-Chip Supporting Module Access

4.4 External Data Bus

The external data bus is accessed with 8-bit or 16-bit bus width in two or three states. Figure 4.5

shows the read timing for two-state or three-state access. Figure 4.6 shows the write timing for

two-state or three-state access. In three-state access, wait states can be inserted by the wait-state

controller or other means. For further details refer to the relevant microcontro ller hardware

manual.

Section 4 Basic Timing

Rev. 3.00 Dec 13, 2004 page 257 of 258

REJ09B0213-0300

Read cycle

state T

state

Address

Read data

(two-state access)

Address bus

Data bus

Read cycle

state T

state

Address

Read data

(three-state access)

state

Address bus

Data bus

Figure 4.5 External Device Access Timing (1) Read Timing

Section 4 Basic Timing

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Write cycle

T1 state T2 state

Address

(a) Two-state access

Address bus

(HWR or LWR)

Data bus

Write data

Write cycle

T1 state T2 state

Address

Write data

(b) Three-state access

T3 state

Address bus

(HWR or LWR)

Data bus

Figure 4.6 External Device Access Timing (2) Write Timing

Renesas 16-Bit Single-Chip Microcomputer

Software Manual

H8/300H Series

Publication Date: 1st Edition, August 1993

Rev.3.00, Dece mber 13, 200 4

Published by: Sales Strategic Planning Div.

Renesas Technology Corp.

Edited by: Technical Documentation & Information Department

Renesas Kod aira Semico nductor Co., Ltd.

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REJ09B0213-0300

Software Manual