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FEATURES DESCRIPTION
APPLICATIONS
Timer
LVDT Device
Only
(One of Four Shown)
200
250
300
350
400
450
500
-60 -40 -20 0 20 40 60 80 100
Data Transfer Rate - Mxfr/s
DATA TRANSFER RATE
vs
FREE-AIR TEMPERATURE
TA - Free-Air Temperature - °C
215 -1 prbs NRZ, VID = 0.4 V
VIC = 1.2 V, CL = 5.5 pF, 40% Open Eye
4 Receivers Switching, Input Jitter < 45 ps
550
SN65LVDS352PW
SN65LVDS348PW
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
QUAD HIGH-SPEED DIFFERENTIAL RECEIVERS
•Meets or Exceeds the Requirements of ANSI
The SN65LVDS348, SN65LVDT348,TIA/EIA-644A Standard
SN65LVDS352, and SN65LVDT352 are high-speed,quadruple differential receivers with a wide•Single-Channel Signaling Rates up to
common-mode input voltage range. This allows560 Mbps
receipt of TIA/EIA-644 signals with up to 3-V of•-4 V to 5 V Common-Mode Input Voltage
ground noise or a variety of differential andRange
single-ended logic levels. The '348 is in a 16-pin•Flow-Through Architecture
package to match the industry-standard footprint ofthe DS90LV048. The '352 adds two additional V
CC•Active Failsafe Assures a High-level Output
and GND pins in a 24-pin package to provide higherWhen an Input Signal Is not Present
data transfer rates with multiple receivers in•SN65LVDS348 Provides a Wide Common-
operation. All offer a flow-through architecture with allMode Range Replacement for the
inputs on one side and outputs on the other to easeSN65LVDS048A or the DS90LV048A
board layout and reduce crosstalk betweenreceivers. LVDT versions of both integrate a 110- Ωline termination resistor.•Logic Level Translator
These receivers also provide 3x the standard's•Point-to-Point Baseband Data Transmission
minimum common-mode noise voltage tolerance.Over 100- ΩMedia
The -4 V to 5 V common-mode range allows usagein harsh operating environments or accepts LVPECL,•ECL/PECL-to-LVTTL Conversion
PECL, LVECL, ECL, CMOS, and LVCMOS levels•Wireless Base Stations
without level shifting circuitry. See the Application•Central Office or PABX Switches
Information Section for more details on theECL/PECL to LVDS interface.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RIN1–
RIN1+
RIN2+
RIN2–
RIN3–
RIN3+
RIN4+
RIN4–
EN
ROUT1
ROUT2
VCC
GND
ROUT3
ROUT4
EN
SN65LVDS348, SN65LVDT348
D or PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1A
1B
2A
2B
EN 1,2
VCCA
AGND
EN 3,4
3A
3B
4A
4B
NC
1Y
DGND1
VCCD1
2Y
NC
NC
3Y
VCCD2
DGND2
4Y
NC
SN65LVDS352, SN65LVDT352
PW PACKAGE
(TOP VIEW)
NC – No internal connection
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltagehysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the fullinput common-mode voltage range.
The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage.This provides reliability in cabled and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent-pending) failsafe circuit that provides a high-level output approximately 600ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines,or powered-down transmitters. This prevents noise from being received as valid data under these faultconditions. This feature may also be used for Wired-Or bus signaling.
The SN65LVDT348 and SN65LVDT352 include an integrated termination resistor. This reduces board spacerequirements and parts count by eliminating the need for a separate termination resistor. This can also improvesignal integrity at the receiver by reducing the stub length from the line termination to the receiver.
The intended application of these devices and signaling technique is for point-to-point baseband datatransmission over controlled impedance media of approximately 100 Ω. The transmission media may beprinted-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependentupon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS348, SN65LVDT348, SN65LVDS352 and SN65LVDT352 are characterized for operation from-40°C to 85°C.
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FUNCTIONAL BLOCK DIAGRAMS (one of four receivers shown)
Timer
EN
EN
RIN+
RIN–
SN65LVDT348
Only
Window Comparator
ROUT1
Timer
A
B
SN65LVDT352
Only
Window Comparator
Y
EN
To Three Other Receivers To One Other Receiver
348 Devices 352 Devices
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
AVAILABLE OPTIONS
PART NUMBER
(1)
INTEGRATED TERMINATION PACKAGE TYPE PACKAGE MARKING
SN65LVDS348D SOIC LVDS348SN65LVDT348D √SOIC LVDT348SN65LVDS348PW TSSOP DL348SN65LVDT348PW √TSSOP DE348SN65LVDS352PW TSSOP DL352SN65LVDT352PW √TSSOP DE352
(1) Add the R suffix to the device type (e.g., SN65LVDS348DR) for taped and reeled carrier.
FUNCTION TABLES
348 DEVICES
INPUTS OUTPUTS
V
ID
= V
RIN+
- V
RIN-
EN EN R
OUT
V
ID
≥-32 mV H L or OPEN H100 mV < V
ID
< -32 mV H L or OPEN ?V
ID
≤-100 mV H L or OPEN LOpen H L or OPEN HL or OPEN X ZX
X H Z
352 DEVICES
INPUTS OUTPUTS
V
ID
= V
IA
- V
IB
EN YV
ID
≥-32 mV H H100 mV < V
ID
< -32 mV H ?V
ID
≤-100 mV H LX L or OPEN ZOpen H H
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
1 pF
200 kΩ
60 kΩ
250 kΩ
3 pF
VCC
6.5 kΩ6.5 kΩ
Attenuation
Network Attenuation
Network
7 V
7 V
7 V
7 V
110 Ω
’LVDT Only
VCC
RIN+, A RIN–, B
300 kΩ
100 Ω
7 V
VCC
EN, EN
7 V
37 Ω
VCC
ROUT, Y
Attenuation
Network
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage range
(2)
, V
CC
,V
CCA
,V
CCD1
, and V
CCD2
-0.5 V TO 4 VEnables, R
OUT
, or Y -0.5 V to 6 VVoltage range Differential input magnitude MV
ID
M (LVDT only) 1 VR
IN+
, R
IN-
, A or B -5 V to 6 VHuman body model
(3)
A, B, R
IN+
, R
IN-
and GND ±15 kVElectrostatic discharge All pins ±7 kVCharged-device model
(4)
All pins ±500 VContinuous power dissipation See Dissipation Rating TableStorage temperature range -65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal (GND, AGND).(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
T
A
≤25°C OPERATING FACTOR
(1)
T
A
= 85°CPACKAGE
POWER RATING ABOVE T
A
= 25°C POWER RATING
D16 950 mW 7.6 mW/°C 494 mWPW16 774 mW 6.2 mW/°C 402 mWPW24 1087 mW 8.7 mW/°C 565 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow.
MIN NOM MAX UNIT
V
CC
,V
CCA
,V
CCD1
,
Supply voltage 3 3.3 3.6 Vand V
CCD2
V
IH
High-level input voltage Enables 2 5 VV
IL
Low-level input voltage Enables 0 0.8 V|V
ID
| (LVDT348, 352) 0.1 0.8Magnitude of differential
Vinput voltage
|V
ID
| (LVDS348, 352) 0.1 3Input voltage (any combination of common mode or input signals) -4 5 VT
A
Operating free-air temperature -40 85 °C
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ELECTRICAL CHARACTERISTICS
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Positive-going differential input voltageV
ITH1
50threshold
See Figure 1 and Figure 2 mVNegative-going differential input voltageV
ITH2
-50threshold
V
ITH3
Differential input failsafe voltage threshold See Figure 1 and Table 1 -32 -100 mVV
ID(HY
Differential input voltage hysteresis,
50 mVS)
V
ITH1
- V
ITH2
V
OH
High-level output voltage I
OH
= -4 mA 2.4 VV
OL
Low-level output voltage I
OL
= 4 mA 0.4 VEnabled, EN at V
CC
, EN at 0 V, No load 16 20LVDS348,
mALVDT348
Disabled, EN at 0 or EN at V
CC
1.1 4I
CC
Supply current
Enabled, EN at V
CC
, No load 16 20LVDS352,
mALVDT352
Disabled, EN at 0 1.1 4V
I
= -4 V, Other input open -75 0LVDS348,
0 V ≤V
I
≤2.4 V, Other input 1.2 V -20 0 µALVDS352
V
I
= 5 V, Other input open 0 40Input current (RIN+, RIN-, A or BI
I
inputs)
V
I
= -4 V, Other input open -150 0LVDT348,
0 V ≤V
I
≤2.4 V, Other input open -40 0 µALVDT352
V
I
= 5 V, Other input open 0 80V
CC
= 1.5 V, V
I
= -4 V or 5 V, Other input open -50 50LVDS348,
µAV
CC
= 1.5 V, 0 V ≤V
I
≤2.4 V, Other inputLVDS352
-20 20at 1.2 VPower-off input current (RIN+,I
I(OFF)
RIN-, A or B inputs)
V
CC
= 1.5 V, V
I
= -4 V or 5 V, Other input open -100 100LVDT348,
µAV
CC
= 1.5 V, V
I
= 0 V or 2.4 V, Other inputLVDT352
-40 40openDifferential input current LVDS348,I
ID
V
ID
= 100 mV, V
IC
= -3.9 V or 4.9 V -4 4 µA(I
RIN+
- I
RIN-
, or I
IA
- I
IB
) LVDS352
LVDT348,R
T
Differential input resistance V
CC
= 0 V, V
ID
= 250 mV, V
I
= 0 V or 2.4 V 90 111 132 ΩLVDT352I
IH
High-level input current Enables V
IH
= 2 V 0 10 µAI
IL
Low-level input current Enables V
IL
= 0.8 V 0 10 µAI
OZ
High-impedance output current V
O
= 0 V -10 10 µAInput capacitance, R
IN+
, R
IN-
input to GND or AC
IN
V
I
= 0.4 sin (4E6 πft) + 0.5 V 5 pFor B input to AGND
(1) All typical values are at 25°C and with a 3.3-V supply.
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SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
VID
B or RIN–
VIB or VRIN–
VIA or VRIN+
VIC
(VIA + VIB)/2 or
(VRIN+ + VRIN–)/2 VOY or VROUT
IOY or IROUT
Y or ROUT
A or RIN+
IIA or IRIN+
IIB or IRIN–
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 2.5 4 6 nst
PHL
Propagation delay time, high-to-low-level output 2.5 4 6 nst
d1
Delay time, failsafe disable time 12 nst
d2
Delay time, failsafe enable time 0.3 1.5 µst
sk(p)
Pulse skew (|t
pHL1
- t
pLH1
|) C
L
= 10 pF, See Figure 3 200 pst
sk(o)
Output skew
(2)
150 pst
sk(pp)
Part-to-part skew
(3)
1 nst
r
Output signal rise time 1.2 nst
f
Output signal fall time 1 nst
r
Output signal rise time 650 psC
L
= 1 pF, See Figure 3t
f
Output signal fall time 400 pst
PHZ
Propagation delay time, high-level-to-high-impedance output 5 9 nst
PLZ
Propagation delay time, low-level-to-high-impedance output 5 9 nsSee Figure 4 and Figure 5t
PZH
Propagation delay time, high-impedance-to-high-level output 8 12 nst
PZL
Propagation delay time, high-impedance-to-low-level output 8 12 ns
(1) All typical values are at 25°C and with a 3.3-V supply.(2) t
sk(o)
is the magnitude of the time difference between the t
PHL
or t
PLH
of all receivers of a single device with all of their inputs connectedtogether.
(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Figure 1. Voltage and Current Definitions
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VITH1
VID
0 V
–100 mV
100 mV
0 V
VITH2
VO
VID
VO
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
A. Remove for testing LVDT device.B. Input signal of 3 MHz, duty cycle of 50±0.2%, and transition time of < 1ns.C. Fixture capacitance ±20%.D. Resistors are metal film, 1% tolerance, and surface mount
Figure 2. V
ITH1
and V
ITH2
, Input Voltage Threshold Test Circuit and Definitions
Table 1. Receiver Minimum and Maximum Failsafe Input Voltage
FAILSAFE THRESHOLD TEST VOLTAGES
APPLIED VOLTAGES
(1)
RESULTANT INPUTS
OutputV
IA
(mV) V
IB
(mV) V
ID
(mV) V
IC
(mV)
-4000 -3900 -100 -3950 L-4000 -3968 -32 -3984 H4900 5000 -100 4950 L4968 5000 -32 4984 H
(1) Voltage applied for greater than 1.5 µs.
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VID
VOY or VROUT
Y or ROUT
A or RIN+
B or RIN–
VIB or VRIN–
VIA or VRIN+
A or VRIN+
B or VRIN–
VID
tPHL tPLH td1 td2
tftr
1.4 V
1 V
0.4 V
0 V
–0.4 V
VOH
VCC/2
VOL
–0.2 V
>1.5 µs
VOY or VROUT
CL
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, signaling rate = 250kHz, duty cycle = 50 ±2%, C
L
includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is±20%.
Figure 3. Timing Test Circuit and Waveforms
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_
+
VROUT
10 pF
500 Ω
ROUT
RIN–
RIN+
1.2 V
EN
EN
Inputs VTEST
VTEST
VRIN+
EN
EN
VROUT
VTEST
VRIN+
EN
EN
VROUT
tPZL tPLZ
tPZL tPLZ
tPZH tPHZ
tPZH tPHZ
2.5 V
1 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
2.5 V
1.4 V
VOL +0.5 V
VOL
0 V
1.4 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
VOH –0.5 V
VOH
1.4 V
0 V
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, signaling rate = 500kHz, duty cycle = 50 ±2%, C
L
includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is±20%.
Figure 4. 348 Enable/Disable Time Test Circuit and Waveforms
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_
+
VO
10 pF
500 Ω
Y
B
A
1.2 V
EN
Inputs VTEST
tPZL
tPZH tPHZ
2 V
1.4 V
0.8 V
1 V
2.5 V
2.5 V
1.4 V
VOL +0.5 V
VOL
0 V
1.4 V
2 V
1.4 V
0.8 V
VOH
VOH –0.5 V
1.4 V
0 V
VTEST
A
EN
VO
VTEST
A
EN
VO
tPLZ
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, signaling rate = 500kHz, duty cycle = 50 ±2 %, C
L
includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is±20%.
Figure 5. 352 Enable/Disable Time Test Circuit and Waveforms
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TYPICAL CHARACTERISTICS
3
3.5
4
4.5
5
-50 0 50 100
See NO TAG
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
- Low-to-High Propagation Delay - ns
tPLH
TA - Free-Air Temperature - °C
3
3.5
4
4.5
5
-50 0 50 100
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
- High-to-Low Propagation Delay - ns
tPHL
TA - Free-Air Temperature - °C
See NO TAG
-40
-30
-20
-10
0
0 1 2 3 4
TA = 25°C,
VCC = 3.3 V
- High-Level Output Current - mA
IOH
VOH - High-Level Output Voltage - V
0
10
20
30
40
0 1 2 3 4
- Low-Level Output Current - mAIOL
VOL - Low-Level Output Voltage - V
TA = 25°C,
VCC = 3.3 V
5
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
LOW-TO-HIGH PROPAGATION DELAY HIGH-TO-LOWPROPAGATION DELAYvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 6. Figure 7.
LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENTvs vsLOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
Figure 8. Figure 9.
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10
30
50
70
90
110
0 50 100 150 200 250 300
4 Receivers Switching,
50% Duty Cycle,
CL = 5.5 pF,
TA = 25°C
VCC = 3.3 V
VCC = 3.6 V
VCC = 3 V
- RMS Supply Current - mA
f - Switching Frequency - MHz
ICC
200
250
300
350
400
450
500
-60 -40 -20 0 20 40 60 80 100
Maximum Transfer Rate - Mxfr/s
TA - Free-Air Temperature - °C
215 -1 prbs NRZ,
VIC = 1.2 V,
CL = 5.5 pF,
40% Open Eye,
4 Receivers Switching,
VCC = 3.3 V,
SN65LVDS348PW VID = 0.4 V
VID = 0.2 V
VID = 0.1 V
223 -1 prbs NRZ, TA = 25°C, CL = 5.5 pF,
4 Receivers Switching, VCC = 3.3 V
223 -1 prbs NRZ, TA = 25°C, CL = 5.5 pF,
4 Receivers Switching, VCC = 3.3 V
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
TYPICAL CHARACTERISTICS (continued)
DATA TRANSFER RATE RMS SUPPLY CURRENTvs vsFREE-AIR TEMPERATURE SWITCHING FREQUENCY
Figure 10. Figure 11.
Figure 12. SN65LVDS348 Eye Figure 13. SN65LVDS352 EyePattern Running at 200 Mxfr/s Pattern Running at 200 Mxfr/s
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APPLICATION INFORMATION
IMPEDANCE MATCHING AND REFLECTIONS
0.1
0.05
00 5 10 15
Voltage - V
0.15
0.2
t - Time - ns
TIME DOMAIN RESPONSE
0.25
20 25
ZS = 0 Ω
ZO = 100 Ω
ZT = 132 Ω
VI
V at Load
0.1
0.05
00 5 10 15
Voltage - V
0.15
0.2
t - Time - ns
TIME DOMAIN RESPONSE
0.25
20 25
ZS = 0 Ω
ZO = 100 Ω
ZT = 90 Ω
VIV at Load
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
A termination mismatch can result in reflections that degrade the signal at the load. A low source impedancecauses the signal to alternate polarity at the load (oscillates) as shown in Figure 14 . High source impedanceresults in the signal accumulating monotonically to the final value (stair step) as shown in Figure 15 . Both ofthese modes result in a delay in valid signal and reduce the opening in the eye pattern. A 10% terminationmismatch results in a 5% reflection (r = Z
L
- Z
O
/Z
L
+ Z
O
), even a 1:3 mismatch absorbs half of the incomingsignal. This shows that termination is important in the more critical cases, however, in a general sense, a ratherlarge termination mismatch is not as critical when the differential output signal is much greater than the receiversensitivity.
Figure 14. Low-Source Impedance Figure 15. High-Source Impedance
For example a 200-mV drive signal into a 100- Ωlossless transmission media with a termination resistor of 90 Ωto 132 Ωresults in ~227 mV to 189 mV into the receiver. This would typically be more than enough signal into areceiver with a sensitivity of ±50 mV assuming no other disturbance or attenuation on the line. The other factors,which reduce the signal margin, do affect this and therefore it is important to match the impedance as closely aspossible to allow more noise immunity at the receiver.
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ACTIVE FAILSAFE FEATURE
_
+
Main Receiver
_
+
_
+
A > B + 80 mV
B > A + 80 mV
Failsafe
Timer
Failsafe
Output
Buffer
Reset
Window Comparator
A
BR
ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
APPLICATION INFORMATION (continued)
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. CurrentLVDS failsafe solutions require either external components with subsequent reductions in signal quality orintegrated solutions with limited application. This family of receivers has a new integrated failsafe that solves thelimitations seen in present solutions. A detailed theory of operation is presented in application note The ActiveFail-Safe in TI's LVDS Receivers, literature number SLLA082B.
The following figure shows one receiver channel with active failsafe. It consists of a main receiver that canrespond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers thatform a window comparator. The window comparator has a much slower response than the main receiver and itdetects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparatoroutputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Figure 16. Receiver With Active Failsafe
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer ofchoice for system designers. Designers know that established technology is capable of high-speed datatransmission. In the past, system requirements often forced the selection of ECL. Now technologies like LVDSprovide designers with another alternative. While the total exchange of ECL for LVDS may not be a designoption, designers have been able to take advantage of LVDS by implementing a small resistor divider network atthe input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver(no divider network required) which can be connected directly to an ECL driver with only the termination biasvoltage required for ECL termination (V
CC
- 2 V).
Figure 17 shows the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received by TI's widecommon-mode receiver and the resulting eye-pattern. The values for R3 are required in order to provide aresistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match thecharacteristic load impedance of 50 Ω. The R2 resistor is a small value intended to minimize common-modereflections.
15Submit Documentation Feedback
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R3 R3
VCCICC
5 Meters
of CAT-5
R1 R1
VEE R2
VCCICC
R3 = 240 Ω
R1 = 50 Ω
R2 = 50 Ω
VB
VBLVDSLV/PECL
DEVICE POWER AND GROUNDING
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
APPLICATION INFORMATION (continued)
Figure 17. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
The SN65LVDS352 device provides separate power and ground pins for the analog input section and the twodigital output sections. All of the power pins and all of the ground pins of the device must be tied together atsome point in the system. Figure 18 shows one recommended scheme for power and ground to the device. Thispoint will be determined by the power and grounding distribution design, which can greatly affect systemperformance.
Key points to remember when routing power and grounds in your system are:•The grounding system must provide a low impedance path back to the power source.•The signal return must be close to the signal path.•Ground noise occurs due to ground loops and common-mode noise pick-up.•Closely spaced power and ground planes reduce inductance and increase capacitance.
A good rule to remember when doing your power distribution and board layout is that the current always flows inthe lowest impedance path. At dc the lowest resistance is the lowest impedance, but at high frequencies thelowest impedance is the lowest inductance path.
16
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VCCD1
DGND1
VCCD2
DGND2
VCCA
AGND
VCC
Bypass
Capacitor†
Bypass
Capacitor†
Bypass
Capacitor†
†Bypass capacitors used for data sheet electrical testing were low ESR ceramic, surface mount, 0.01 µF ±10%. For a more accurate
determination of these values refer to the application note, The Bypass Capacitor in High-Speed Environments, literature number SCBA007A.
SN65LVDS348 , SN65LVDT348SN65LVDS352 , SN65LVDT352
SLLS523E – FEBRUARY 2002 – REVISED MAY 2004
APPLICATION INFORMATION (continued)
Figure 18. Recommended Power and Ground Connection
17Submit Documentation Feedback
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVDS348D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS348DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS348PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS348PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS348PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS348PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS352PW ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS352PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDT348D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT348DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT348DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT348DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT348PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT348PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT348PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT348PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT352PW ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDT352PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDT352PWR ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDT352PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Aug-2009
Addendum-Page 1
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Aug-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS348PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDT348DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDT348PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDT352PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS348PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDT348DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDT348PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDT352PWR TSSOP PW 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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