AY, SGS-THOMSON MICROELECTRONICS MK6116 MK6116, MKI6116, MK6116L, MKI6116L (N/S) - 15/20/25 2K X 8 CMOS STATIC RAM m BYTEWYDE 2K x 8 CMOS STATIC RAM. | m@ +5 VOLT ONLY WRITE/READ. @ 24-PIN 600 MIL PLASTIC DIP, JEDEC PINOUT 28-PIN 330 MIL SOIC. 3 ' @ EQUAL WRITE AND READ CYCLE TIMES. DIP 24 {Plastic Package) @ HIGH PERFORMANCE WITH LOW CMOS TA . STANDBY POWER PIN CONNECTION A7 108 [] 24 Vee Ag 2 1] 23 Ag As 30 [] 22 Ag Ag 40 [121 WwW DESCRIPTION Ax 5 C 2 @ Ao 6 ukette LD 19 Aig The MK6116 is a 16,384-bit CMOS Static RAM, A, 7] [J 18 E organized as 2K x 8 usingSGS- THOMSON Micro- Ap 8 C O17 paz electronics advanced HCMOS process technolo- DO, 9 OI 4416 po gy. This device is directly compatible with the 9 5 6 popular 24-pin, three-wire handshake, 16K static DQ, 10 H 15 Das CMOS RAM. All inputs and outputs are TTL com- DQ2 11 O [1 14 DQ4 patible using a single 5V supply. The MK6116 Vss 12 0 13 Dag provides full static operation, requiring no clocks or 1m DP oe refresh operations, and has equal access and cycle times. Additionally, whenever E (Chip Enable) goes ao 1 Ce Ho 28 Veo high, the device will maintain a reduced power ? qd standby mode until E again goes active low. (Refer Ag 2 H 27 Aa to the MK6116Truth Table.) 45 3 [] 26 NC 44 4C [LJ 25 Ag A3 5C [] 24 WwW PIN NAMES a2 8 7 23 6 No 7 MK6116 [1 22 Aio Ao -Aio ADDRESS INPUTS ne 8 [| [1] 21 NIC A 9 O I] 20 PA = PO DATA I/O Ag 10 CI Ls 19 paz E CHIP ENABLE DQg 11 C 1) 18 Dag G OUTPUT ENABLE a1 12 LH 17 0Qs5 DQ. 13 1 16 DQ, WwW WRITE ENABLE Vss 14 [1] [115 Dag Voc. Vss +5V, GND (8) S SOIC-28 October 1989 1/9 479MK6116, MKI6116, MK6116L, MKI6116L(N/S) - 15/20/25 FIGURE 1: BLOCK DIAGRAM G + CONTROL WwW 4 LOGIC E 4| A x , ROW MEMORY COLUMN (7) ADDRESS MATRIX vo BUFFER BUFFER DECODER 128x16x8 DQ0- DazZ A > x COLUMN Ay *| COLUMN DER (4) ADDRESS DECO BUFFER Ay __ MK6116 TRUTH TABLE E G w MODE ba POWER Vin x xX deselect Hight Z Standby Vit x Vit Write Din Active Vit Vit Vin Read Dout Active Vi Vin Vin Read Hight Z Active READ MODE dress input signal is stable, provided that the E and The MK6116 is in the read mode whenever W (Write Enable) is high and E (Chip Enable) is low, providing a ripple-through access of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Ad- dress Inputs (Ao-A1o) defines which one of 2048 bytes of data is to be accessed. Valid data will be available at the eight Data Outputs Drivers (DQo-DQ7) within tavav after the last ad- 219 i377 SGS-THOMSON JF. MicROELECMISMICS 480 G (Qut-put Enable) access times are satisfied. If E or G access times are not met, data access will be measured from the limiting parameter (teLav or ta_av) rather than address. The state of the eight Data I/O signals is controlled by the E and G input signals. Data Out may be indeterminate between taxax and tavav, but data will always be valid at tavav.MK6116, MKI6116, MK6116L, MKI6116L(N/S) - 15/20/25 AC ELECTRICAL CHARACTERISTIICS (READ CYCLE) {0C < TA< +70C (MK6116/L), -40C < TAs + 105C (MKI6116/L), VCC= 5.0 +/- 10%} I MK6116 - 15 MK6116 - 20 | MK6116 - 25 ALT STD MiI6116 -15 wes -20 |MKI6116 -25 . . 116L-15 6116L-20 | MKL6116-25 SYMBOL | SYMBOL |PARAMETER MKI6116L-15 | MKI6116L-20 MIN | MAX | MIN | MAX| MIN | MAX] UNITS | NOTES trac tavav | Read Cycle Time 150 200 250 ns tan tavov | Address Access Time 150 200 250 ns 1 tcEA teLoy | ChipEnable Access Time 150 200 250 ns 1 tcez teHoz | Chip Enable Data Offfime 35 40 50 ns toEa tetqv | Output Enable Access Time 75 80 90 ns 1 toez teLav | Output Enable Data Off Time 35 40 50 ns toeEL tatax | Out put Enable to Q Low-Z 15 15 15 ns toe teLax | Chip Enable to Q Low-Z 15 15 15 ns tou taxax | Output Hold from Address 15 15 15 ns 1 FIGURE 2: READ CYCLE TIMING READ READ WRITE }*#-_ " avav ) tT avav [*+#_ T avav I Ao NE of A 10 _/ A t 4 _ . teow _J t avav | _, tava A E \, '* ' avwH +| 'eLax 7 G \j'etayv > / t T WHWL L - _ [ SwowH = mH | w "axox | fe / \ stax > 'cHaz No ba oo [maiout XX VALID OUT VALID IN 7 UY DQ 7 S-THOMSO i SG FF. Mice2e user 00 3/9 481MK6116, MKI6116, MK6116L, MKI6116L(N/S) - 15/20/25 WRITE MODE The MK6116 is in the Write Mode of operation whenever W and E are active low (Gis adont care as noted in the Truth Table). The latter occurring falling edge of either W or E will determine the start of the write cycle. Therefore, address setup time and write or chip enable pulse width are referenced to the latter occurring edge of W or E. The write cycle can be terminated by either earlier rising edge of W or E. The addresses must be held valid throughout the cycle. W must return to the high logic state for a minimum write recovery time des- ignated as twHw1 between write cycles. Addresses must remain valid for twHax at the termination of the write cycle. The same principles apply for an E controlled write cycle. If the output bus has been enabled (E and G active low), then W will disable the outputs within twLaz from its falling edge; however, care must be taken to avoid a potential bus contention. Data-In must be valid tovwH or tpven prior to the earlier rising AC ELECTRICAL CHARACTERISTICS (WRITE CYCLE) - {0C < Tas +70C (MK6116/L), -40C< Tas +105C (MKI6116/L), Voc=5.0 + 10%} MK6116-15 |MK6116-20 |MK6116 - 25 ALT. SDT. PARAMETER MKGTIOLA18 MKBI16L-20 MALE 16-28 SYMBOL | SYMBOL MKI6116L-15 | MKI6116L -20 MIN | MAX | MIN | MAX MIN | MAX | UNITS | NOTES two tavay | Write Cycle Time 150 200 250 ns tas tavww. | Address Setup Time W Low 0 0 0 ns tas tave. | Address Setup Time E Low 0 0 0 ns tcew teLeEH | Chip Enable to End of Write 90 120 | 160 ns taw tavwi | Address Valid to End of Write! 120 140 180 as | taw taven | Address Valid to End of Write; 120 140 180 ns twew twiwH =| Write Pulse Width 90 120 160 ns tan twuax |W Hight to address Ghange | 10 10 10 ns tan tenax |E Hight to address Change 10 10 10 ns twa twa W Hight to W Low Next Cy- 10 10 10 ns twez | twiaz |W Data Off Time 50 60 80 ns tcez teHoz | E Data Off Time 50 60 80 ns tos tovwH | Data Setup Time to w Hight | 40 60 100 ns tos toven | Data Setup Time to E Hight | 40 60 100 ns ton twHpx | Data Hold Time W High 0 0 0 ns toy teHox | Data Hold Time E High 0 0 0 ns 4/9 482 k SGS-THOMSON S/ Aarti clen tatesMK6116, MKI6116, MK6116L, MKI6116L(N/S) - 15/20/25 FIGURE 3 : WRITE CYCLE TIMING DQ. - VALID VALID IN pa 7 our [men | WRITE WRITE READ I [*_ tavay 9 >} f*#__ T avav * ' avay Ag TTY I Ayo + f __ tave Venax yf 'avayv = Kt! ave > " WHAaXx me + Ee { COS E 7 fo ELEH > / _/ a 7 _ + Gav G / wr _+. b |. w . / \. / \, FIGURE 4 : OUTPUT LOAD DIAGRAM AC TEST CONDITION | Input Levels:......... 0.6Vt024V Transition Times: ...... 5ns + 5.0V Input and Output Timing : Reference Levels:..... 0.8V or 2.2V 1.8 KQ DEVICE UNDER TEST GND Notes: Including scope and JIG 5/9 483MK6116, MKI6116, MK6116L, MKI6116L(N/S) - 15/20/25 ABOLUTE MAXIMUM RATINGS | - PARAMETER | VALUES UNITS | Voltage on any Pin Relative tro Ground -0.3 to +7.0 Vv Operating Temperature (MK6116L} oo OO 0 to +7 Cc _ | Operatting Temperature (MKI6116/L) 4010 +150 | Cc | | Storage Temperature | -55 to +150 c Power Dissipation | 1 Ww Output Current | + 20 : mA * This is a stress rating only and functional operation of the device at these or any conditions above those indicazted in the operation sec- tion of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ~ Output current absolute maximun rating iS specified for one output at a time. not to exceed a duration of a1 second. RECOMMENDED DC OPERATING CONDITIONS {0C <Ta < +70C (MK6116/L), -40C < Ta < +150C (MKI6116/L), Voc=5.0 4/- 10%} | symBot PARAMETER MIN MAX | UNITS | NOTES Vcc Supply Voltage | 4.5 | 5.5. | Vv 4 Vss_ | Supply Voltage 0 0 vio} 4 - Viq_ | Logic 1 All Inputs , 22 | MetO3 | Vo | 4 | | Vi. | Lagic 1 All Inputs 0.3 0.8 v 45 | DC ELECTRICAL CHARACTERISTICS {OC < TA<+70C (MK6116/L). -40C < Tas +150C (MKI6116/L), Vec=5.0 +/- 10%} SYMBOL [PARAMETER 7 win | max =|suNiTs. | NOTES Average Vcc Power Supply Current , Ico | Ket16 MKI6tt6 7 | ma 6 | ft MK6116L, MKI6116L 70 mA | tsB1 TTL Standby Current (E = Vin) 3 mA | CMOS Standby Current {E > Voc-0.2 V) _| mA tooo M6116. MKI6116 _| 1 MK6116L WA MKI6116L ] 10 A | tu Input Leakage Current -1 | +1 HA 7 ILo Output Leakage Current 5 | +5 HA 7 | Vox | Output Logic 1 Voltage (lox = -1.0 mA) 2.4 Vv Vo. | Output Logic 2 Voltage (lon = 2.1 mA) 0.4 Vv 6/9 484 _ {7 SGS-THOMSON \ / Mister cistsLOW Vcc Data RETENTION CHARACTERISTICS (MK6116L, MKI6G116L) MK6116, MKI6116, MK6116L, MKI6116L(N/S) - 15/20/25 SYMBOL | PARAMETER MIN MAX UNITS NOTES |, Vor Vcc Data retention 2.0 Vec (max) Data Retention Power Supply Current ' WA IccDR_ | MK6116L 8 MKI6116L 3 ; nA | tcpr Chip Deselection to Data Retention Time 0 ns tr Operation Recovery Time tavav ] * tAVAV = Read Cycle Time FIGURE 5 . LOW Vcc DATA RETENTION TIMING . ___ DATA RETENTION MODE > 20 'R <+_____+ ; , 5 NTN SS * i o\ > Vv -o2v PNP NN / pr | NO | * 2Ov rn! | | 7 NOTES: 5. Negative spikes of -1.0 volts allowed for up to 10 ns once per 1. Measured with load as shown in Figure 4. cycle. / 2. Effective capacitance calculated fram the equation: 6. ICC) measured with output open C= IAW AV, with AV = 3 volts and power supply at nominal level 7. Measured with GND V < Voc and outputs deselected. 3. Output is deselected. 8. Voc = 2.0 Volts. 4 All voltages referenced to GND CAPACITANCE (TA = 25C) SYMBOL |PARAMETER MAX UNITS NOTES | Ci Capacitance on all pins (except DQ) 7.0 pF | 2 | r | | pq | Capacitance on DQ pins 10.0 | pF 2,3 | SGS-THOMSON 719 bE 3GS-THOMSO! MISE DE LECTR: OSS 485MK6116, MKI6116, MK6116L, MKI6116L(N/S) - 15/20/25 FIGURE 6. 24-PIN PLASTIC DIP (N) mm inches iin | Typ | Mex | Min | Typ | Max : 0.63 0024 04 0017 023 031 | 0.009 6012 127 0.050 3220 1267 1820 16 68 | 0598 0.656 254 010 27 94 1100 1410 0555 45 vusy = Y hy 330 0129 i FIGURE 7 . 28-PIN SOIC (S) a 2a LD tf Di Inches Min. Max. A 120 e i Al .002 014 A2 092 106 B 014 .020 9 . t Bt 014 024 RT [006 [ora 1 D 697 728 E 324 350 e 050 Basic +| 81 | c H 453 500 I j | aa T o L 016 050 + = A e > TA oo it 0 a amd teb aa J L l 8/9 k SGS-THOMSON SK MicROELECTROMICS 486MK6116, MKI6116, MK6116L, MKI6116L(N/S) - 15/20/25 ORDERING INFORMATION ; PART NO. ACCESS TIME CYCLE TIME PACKAGE TYPE TEMPERATURE MK6116 (N/S)-15 150 ns 150 ns Plastic DIP/SOIC C to 70C MK6116 (N)-20 200 ns 200 ns Plastic DIP 0C to 70C MK6116 (N) -25 250 ns 250 ns Plastic DIP OC ta 70C MKI6116 (N/S) -15 150 ns 150 ns Plastic DIP/SOIC -40C to 105C MKI6116 (N) -20 200 ns 200 ns Plastic DIP -40C to 105C MK16116 (N} - 25 250 ns 250 ns Plastic DIP -40C to 105C MK6116 L(N/S} -15 150 ns 150 ns Plastic DIP/SOIC OC to 70C IMKe116 L(N} - 20 200 ns 200 ns Plastic DIP 0C to 70C MK6116 L(N) - 25 250 ns 250 ns Plastic DIP 0C to 70C | MKI6116 L(N/S) - 15 150 ns 150 ns Plastic DIP/SOIC -40C to 105C MKI6116L (N) - 20 200 ns 200 ns Plastic DIP -40C to 105C MK Commercial Temperature Range (0C to +70C) MKI Industrial Temperature Range (-40C to +85C) 6116 Device Family and Identification Number L Low Power Plastic Dip Package Ss SOIC Package 15/20/25 Speed Grade BYTEWYDE is a Trademark of SGS-THOMSON Microelectronics i SGS-THOMSON MICROELECTIOMICS 9/9 487