THCV215-216_Rev.2.70_E THCV215 and THCV216 V-by-One(R) HS High-speed Video Data Transmitter and Receiver General Description Features THCV215 and THCV216 are designed to support video data transmission between the host and display. The chipset can transmit 39bit video data and 3bit sync data via only a single differential cable at an LVDS clock frequency from 20MHz to 100MHz. The chipset, which has two high-speed data lanes, can transmit the video data up to 1080p/10b/60Hz, 1080p/12b/60Hz. The maximum serial data rate is 3.75Gbps/lane. Color Depth 6bit 8bit 10bit 12bit Link LVDS Clock Frequency 20MHz to 100MHz 20MHz to 100MHz 20MHz to 85MHz 20MHz to 75MHz Single/Dual Single/Dual Single/Dual Single/Dual Color depth selectable: 6/8/10/12 bit Single/Dual Link selectable AC coupling LVDS Input internal termination CORE 1.8V, LVDS 3.3V Package: 64 pin TSSOP Wide frequency range CDR requires no external frequency reference Supports Spread Spectrum Clocking: Up to 30kHz/0.5%(center spread) V-by-One(R) HS standard Version1.4 compliant Block Diagram Color depth (6/8/10/12) Single/Dual Pre-emphasis Controls HTPDN LOCKN PDN LVDS Serializer LVDS Serializer RLA0+/ RLF0+/RLCLK0+/RLA1+/ RLF1+/RLCLK1+/- PLL Deserializer Deskew & Formatter TX1+ RX1+ TX1- RX1- Deserializer TX0+ RX0+ TX0- RX0- CDR Serializer Serializer THCV216 PLL Formatter TLA1+/ TLF1+/TLCLK1+/- LVDS Deserializer TLA0+/ TLF0+/TLCLK0+/- LVDS Deserializer THCV215 Controls Color depth (6/8/10/12) Single/Dual RS PDN Copyright(C)2016 THine Electronics, Inc. 1/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Contents Page General Description ................................................................................................................................................. 1 Features .................................................................................................................................................................... 1 Block Diagram ......................................................................................................................................................... 1 Pin Diagram ............................................................................................................................................................. 3 Pin Description......................................................................................................................................................... 4 Functional Description ............................................................................................................................................ 5 Absolute Maximum Ratings0F ............................................................................................................................. 13 Operating Conditions ............................................................................................................................................ 13 Electrical Specifications ........................................................................................................................................ 14 AC Timing Diagrams and Test Circuits ............................................................................................................... 17 Package ................................................................................................................................................................... 24 Notices and Requests ............................................................................................................................................. 25 Copyright(C)2016 THine Electronics, Inc. 2/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Pin Diagram LAGND LAVDH TLA0TLA0+ TLB0TLB0+ TLC0TLC0+ TLCLK0TLCLK0+ TLD0TLD0+ TLE0TLE0+ TLF0TLF0+ TLA1TLA1+ TLB1TLB1+ TLC1TLC1+ TLCLK1TLCLK1+ TLD1TLD1+ TLE1TLE1+ TLF1TLF1+ LAVDH LAGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 THCV215 64pin TSSOP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LPVDL LPGND SDSEL COL1 COL0 RDY PDN HTPDN LOCKN VDL GND CAVDL CAGND TX0TX0+ CAGND TX1TX1+ CAGND CAVDL CPGND CPVDL DRV1 DRV0 PRE1 PRE0 Reserved0 Reserved1 GND VDL LPGND LPVDL LPVDH LPGND SDSEL COL1 COL0 HTPDN LOCKN VDL GND CPVDL0 CPGND0 CAVDL CAGND RX0RX0+ CAGND CAGND RX1RX1+ CAGND CAVDL CPGND1 CPVDL1 GND VDL Reserved1 PDN Reserved2 Reserved3 RS LPGND LPVDH Copyright(C)2016 THine Electronics, Inc. 3/25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 THCV216 64pin TSSOP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LAGND LAVDH RLA0RLA0+ RLB0RLB0+ RLC0RLC0+ RLCLK0RLCLK0+ RLD0RLD0+ RLE0RLE0+ RLF0RLF0+ RLA1RLA1+ RLB1RLB1+ RLC1RLC1+ RLCLK1RLCLK1+ RLD1RLD1+ RLE1RLE1+ RLF1RLF1+ LAVDH LAGND THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Pin Description THCV215 THCV216 Pin Name Pin # TX0 +/50,51 TX1 +/47,48 TLA0+/4,3 TLB0+/6,5 TLC0+/8,7 TLCLK0+/- 10,9 TLD0+/12,11 TLE0+/14,13 TLF0+/16,15 TLA1+/18,17 TLB1+/20,19 TLC1+/22,21 TLCLK1+/- 24,23 TLD1+/26,25 TLE1+/28,27 TLF1+/30,29 LOCKN 56 HTPDN 57 Type* CO CO LI LI LI LI LI LI LI LI LI LI LI LI LI LI I I Description CML Data Output PDN 58 I COL1, COL0 61,60 I SDSEL 62 I LVDS Data Input Lock detect input Hot plug detect input Power down input H: Normal Operation L: Power down (CML output High Fix, other High-Z) Color depth select input L,L: 6bit L,H: 8bit H,L: 10bit H,H: 12bit Single/Dual select input L: Channel0 enable, Channel1 disable H: Channel0, Channel1 enable DRV1 42 I Must be tied to GND DRV0 41 I Must be tied to VDL PRE1, PRE0 40,39 I RDY 59 O Reserved1 Reserved0 37 38 I I VDL 35,55 P GND CAVDL CAGND CPVDL CPGND LPVDL LPGND LAVDH LAGND 36,54 45,53 46,49,52 43 44 33,64 34,63 2,31 1,32 P P P P P P P P P Pin Name Pin # Type* Description RX0 +/15,14 CI RX1 +/19,18 CI CML Data Input RLA0+/61,62 LO RLB0+/59,60 LO RLC0+/57,58 LO RLCLK0+/ 55,56 LO RLD0+/53,54 LO RLE0+/51,52 LO RLF0+/49,50 LO RLA1+/47,48 LO RLB1+/45,46 LO RLC1+/43,44 LO RLCLK1+/ 41,42 LO RLD1+/39,40 LO RLE1+/37,38 LO RLF1+/35,36 LO LVDS Data Output LOCKN 7 O Lock detect output (open drain) HTPDN 6 O Hot plug detect output (open drain) Pre-emphasis level select input L,L: 0% H,L: 100% L,H: not available H,H: not available Link status ready output L: not ready H: ready Field BET mode enable input L: Normal operation (default) H: Field BET mode enabled Must be tied to GND 1.8V power supply pin for digital circuitry Ground pin for digital circuitry 1.8V power supply pin for CML output Ground pin for CML output 1.8V power supply pin for PLL circuitry Ground pin for PLL circuitry 1.8V power supply pin for LVDS PLL Ground pin for LVDS PLL circuitry 3.3V power supply pin for LVDS input Ground pin for LVDS input PDN 27 I COL1, COL0 4,5 I SDSEL 3 I Direction of RS pin depends on Reserved3. LVDS swing range select input IO3 when Reserved3=L H: Normal swing (350mV typ.) L: Reduced swing (200mV typ.) Field BET output when Reserved3=H. Goes LOW when errors detected. RS 30 Reserved 1,2 26,28 I 29 8,25 9,24 12,21 13,16, 17,20 10 11 23 22 1,32 2,31 34,63 33,64 I P P P Reserved3 VDL GND CAVDL Power down input H: Normal Operation L: Power down (High-Z) Color depth select input L,L: 6bit L,H: 8bit H,L: 10bit H,H: 12bit Single/Dual select input L: Channel0 enable, Channel1 disable H: Channel0, Channel1 enable Must be tied to GND Field BET mode enable input L: Normal operation (default) H: Field BET mode enabled 1.8V power supply pin for digital circuitry Ground pin for digital circuitry 1.8V power supply pin for CML input CAGND P Ground pin for CML input CPVDL0 P 1.8V power supply pin for PLL circuitry CPGND0 P Ground pin for PLL circuitry CPVDL1 P 1.8V power supply pin for PLL circuitry CPGND1 P Ground pin for PLL circuitry LPVDH P 3.3V power supply pin for LVDS PLL LPGND P Ground pin for LVDS PLL circuitry LAVDH P 3.3V power supply pin for LVDS output LAGND P Ground pin for LVDS output *type symbol I=1.8V CMOS Input, O=1.8V CMOS Output, IO3=3.3V CMOS I/O LI=LVDS Input, LO= LVDS Output CI=CML Input, CO=CML Output P=Power Note) All CMOS inputs are 1.8V-inputs except for THCV216's RS Copyright(C)2016 THine Electronics, Inc. 4/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Functional Description Functional Overview With V-by-One(R)HS's proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV215 and THCV216 enable transmission of 18/24/30/36bits per pixel video data (Rn/Gn/Bn/CONTn), Hsync (HSYNCn), Vsync (VSYNCn) data and Data Enable (DE) by single/dual differential pair cable with minimal external components. THCV215, the transmitter, inputs LVDS data (including video data, Hsync, Vsync and DE) and serializes video data and Hsync, Vsync data separately, depending on the polarity of DE. DE is a signal which indicates whether video or Hsync, Vsync data are active. When DE is high, it serializes video data inputs into a single differential data stream. And it transmits serialized Hsync, Vsync data when DE is low. THCV216, the receiver, automatically extracts the clock from the incoming data stream and converts the serial data into video data with DE being high or Hsync, Vsync data with DE being low, recognizing which type of serial data is being sent by the transmitter. And it outputs the recovered data in the form of LVDS data. THCV216 can seamlessly operate for a wide range of a serial bit rate from 600Mbps to 3.75Gbps/channel, detecting the frequency of an incoming data stream, and recovering both the clock and data by itself. It does not need any external frequency reference, such as a crystal oscillator. Data Enable Requirement (DE) There are some requirements for DE as described in Figure 2, Figure 3 and Table 15. Dual LVDS input to THCV215 should be synchronized in terms of DE transition. See Figure 2. If DE=Low, Hsync and Vsync data of same cycle are transmitted. Otherwise video data of that are transmitted (DE=High). SYNC data from receiver in DE=High period are previous data of DE transition. See Figure 3. The length of DE being low and high is at least 2 clock cycles long as described in Table 15. Data Enable must be toggled like High -> Low -> High at regular interval. THCV215 Rn/Gn/Bn CONTn HSYNCn VSYNCn THCV216 D[39:0] D[39:0] H Rn/Gn/Bn CONTn H Hsync Vsync Hsync Vsync L L DE HSYNCn VSYNCn DE Figure 1. Conceptual diagram of the basic operation of the chipset Vdiff = (TLCLK0+) - (TLCLK0-) DE DE DE DE DE DE DE DE DE DE DE DE Vdiff = (TLC0+) - (TLC0-) Vdiff = (TLCLK1+) - (TLCLK1-) Vdiff = (TLC1+) - (TLC1-) Figure 2. Service condition of DE input synchronization Copyright(C)2016 THine Electronics, Inc. 5/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E THCV215 1 cycle Input tDEH tDEL DE Low High Low VSYNC HSYNC Valid Data Invalid Valid Data Rn/Gn/Bn CONTn Invalid Valid Data Invalid n=0,1 THCV216 1 cycle Output tDEH tDEL DE Low High Low VSYNCn HSYNCn Valid Data Keep the last data of DE=L period Valid Data Rn/Gn/Bn CONTn Low Valid Data Low n=0,1 Figure 3. Video and sync data transmission timing diagram Single/Dual Link mode function (SDSEL) SDSEL Mode H Single L Dual Table 1. Function Channel 0 active and channel 1 power down Both channel 0 and channel 1 active Single/Dual mode select Color Depth mode function (COL [1:0]) COL[1:0] Color Depth LVDS Clock Frequency Range L,L 6bit 20MHz to 100MHz L,H 8bit 20MHz to 100MHz H,L 10bit 20MHz to 85MHz H,H 12bit 20MHz to 75MHz Table 2. Color depth mode select Copyright(C)2016 THine Electronics, Inc. 6/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E LVDS Mapping LVDS data (video data, Hsync, Vsync, DE) are mapped as Figure 4. TLC0[6] is special bit for DE(data enable), and TLC0[5:4] are for Hsync, Vsync data bits and the other bits are for video data. The number of LVDS channel depends on color depth mode(COL[1:0]). If SDSEL=Low, only channel 0 (Figure 4, n=0) is active. If SDSEL=High, both channel 0/1(Figure 4, n=0/1) are active. (TLC1[6:4] are not available). Depending on color mode, TLD1[6] and TLD0[6] are not available. See Table 3. Vdiff = (TLCLKn +) - (TLCLKn-) Vdiff=0V tTCIP n=0,1 Color depth 12,10, 8, 6 previous cycle current cycle next cycle TLAn +/- TLAn1 TLAn0 TLAn6 TLAn5 TLAn4 TLAn3 TLAn2 TLAn1 TLAn0 TLAn6 TLAn5 TLAn4 TLAn3 TLAn2 TLAn1 TLBn +/- TLBn1 TLBn0 TLBn6 TLBn5 TLBn4 TLBn3 TLBn2 TLBn1 TLBn0 TLBn6 TLBn5 TLBn4 TLBn3 TLBn2 TLBn1 TLCn +/- TLCn1 TLCn0 TLCn6 (DE) TLCn5 (V) TLCn4 (H) TLCn3 TLCn2 TLCn1 TLCn0 TLCn6 (DE) TLCn5 (V) TLCn4 (H) TLCn3 TLCn2 TLCn1 TLDn +/- TLDn1 TLDn0 TLDn6 TLDn5 TLDn4 TLDn3 TLDn2 TLDn1 TLDn0 TLDn6 TLDn5 TLDn4 TLDn3 TLDn2 TLDn1 TLEn +/- TLEn1 TLEn0 TLEn6 TLEn5 TLEn4 TLEn3 TLEn2 TLEn1 TLEn0 TLEn6 TLEn5 TLEn4 TLEn3 TLEn2 TLEn1 TLFn +/- TLFn1 TLFn0 TLFn6 TLFn5 TLFn4 TLFn3 TLFn2 TLFn1 TLFn0 TLFn6 TLFn5 TLFn4 TLFn3 TLFn2 TLFn1 Data Enable Control data bit Figure 4. LVDS mapping timing diagram Copyright(C)2016 THine Electronics, Inc. 7/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Color depth (COL[1:0]) THCV215 THCV216 Symbol defined by (R) L,L (6bit) L,H (8bit) H,L (10bit) H,H (12bit) Input Output V-by-One HS TLAn[0] RLAn[0] Rn[0] Rn[2] Rn[4] Rn[6] D2 TLAn[1] RLAn[1] Rn[1] Rn[3] Rn[5] Rn[7] D3 TLAn[2] RLAn[2] Rn[2] Rn[4] Rn[6] Rn[8] D4 TLAn[3] RLAn[3] Rn[3] Rn[5] Rn[7] Rn[9] D5 TLAn[4] RLAn[4] Rn[4] Rn[6] Rn[8] Rn[10] D6 TLAn[5] RLAn[5] Rn[5] Rn[7] Rn[9] Rn[11] D7 TLAn[6] RLAn[6] Gn[0] Gn[2] Gn[4] Gn[6] D10 TLBn[0] RLBn[0] Gn[1] Gn[3] Gn[5] Gn[7] D11 TLBn[1] RLBn[1] Gn[2] Gn[4] Gn[6] Gn[8] D12 TLBn[2] RLBn[2] Gn[3] Gn[5] Gn[7] Gn[9] D13 TLBn[3] RLBn[3] Gn[4] Gn[6] Gn[8] Gn[10] D14 TLBn[4] RLBn[4] Gn[5] Gn[7] Gn[9] Gn[11] D15 TLBn[5] RLBn[5] Bn[0] Bn[2] Bn[4] Bn[6] D18 TLBn[6] RLBn[6] Bn[1] Bn[3] Bn[5] Bn[7] D19 TLCn[0] RLCn[0] Bn[2] Bn[4] Bn[6] Bn[8] D20 TLCn[1] RLCn[1] Bn[3] Bn[5] Bn[7] Bn[9] D21 TLCn[2] RLCn[2] Bn[4] Bn[6] Bn[8] Bn[10] D22 TLCn[3] RLCn[3] Bn[5] Bn[7] Bn[9] Bn[11] D23 TLCn[4] RLCn[4] HSYNCn HSYNCn HSYNCn HSYNCn Hsync TLCn[5] RLCn[5] VSYNCn VSYNCn VSYNCn VSYNCn Vsync TLCn[6] RLCn[6] DEn(*2) DEn(*2) DEn(*2) DEn(*2) DE TLDn[0] RLDn[0] Rn[0] Rn[2] Rn[4] D0 TLDn[1] RLDn[1] Rn[1] Rn[3] Rn[5] D1 TLDn[2] RLDn[2] Channel Gn[0] Gn[2] Gn[4] D8 TLDn[3] RLDn[3] Power Gn[1] Gn[3] Gn[5] D9 TLDn[4] RLDn[4] Down Bn[0] Bn[2] Bn[4] D16 TLDn[5] RLDn[5] Bn[1] Bn[3] Bn[5] D17 TLDn[6] RLDn[6] N/A(*1) CONTn[1] CONTn[3] D25(*3) TLEn[0] RLEn[0] Rn[0] Rn[2] D30 TLEn[1] RLEn[1] Rn[1] Rn[3] D31 TLEn[2] RLEn[2] Channel Channel Gn[0] Gn[2] D28 TLEn[3] RLEn[3] Power Power Gn[1] Gn[3] D29 TLEn[4] RLEn[4] Down Down Bn[0] Bn[2] D26 TLEn[5] RLEn[5] Bn[1] Bn[3] D27 TLEn[6] RLEn[6] CONTn[2] CONTn[4] D24(*3) TLFn[0] RLFn[0] Channel Rn[0] D38 TLFn[1] RLFn[1] Rn[1] D39 Power TLFn[2] RLFn[2] Channel Channel Gn[0] D36 TLFn[3] RLFn[3] Power Power Gn[1] D37 TLFn[4] RLFn[4] Down Down Bn[0] D34 TLFn[5] RLFn[5] Bn[1] D35 TLFn[6] RLFn[6] CONTn[1] D33 n=0,1 : if SDSEL=L, Channel 1(n=1) is power down *1 N/A: Not available, THCV216 output RLDn[6]=Low. *2 DE must be same polarity(TLC0[6] = TLC1[6]) when SDSEL=H (R) *3 3D information flags defined in the V-by-One HS Standard are assigned to the following bit. V-by-One(R) HS Standard Packer/Unpacker D[24](3DLR) <=> LVDS T/RLEn[6] V-by-One(R) HS Standard Packer/Unpacker D[25](3DEN) <=> LVDS T/RLDn[6] Table 3. LVDS mapping table Copyright(C)2016 THine Electronics, Inc. 8/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E CML Buffer THCV215 CAVDL THCV216 CAVDL 50 50 TXn + C=75 200nF Zdiff=100 C=75 200nF RXn + TXn - RXn - n=0,1 50 50 Vterm ~ 1.3V CAGND CML Transmitter CML Receiver Figure 5. CML buffer scheme Lock detect and Hot-plug function LOCKN and HTPDN are both open drain output from THCV216. Pull-up resistors are needed at THCV215 side to VDL. See Figure 6. If THCV216 is not active (power down mode (PDN=L) or powered off), HTPDN is open. Otherwise, HTPDN is pulled down by THCV216. HTPDN of THCV215 side is High when THCV216 is not active or the receiver board is not connected. Then THCV215 enters into the power down mode. When HTPDN transits from High to Low, THCV215 starts up and transmits training pattern for link training. LOCKN indicates whether THCV216 is in the lock state or not. If THCV216 is in the unlock state, LOCKN is open. Otherwise (in the lock state), it's pulled down by THCV216. THCV215 keeps transmitting training pattern until LOCKN transits to Low. After training done, THCV216 sinks current and LOCKN is Low. Then THCV215 starts transmitting normal video pattern. THCV215 VDL (THCV215 side) THCV216 10k HTPDN VDL (THCV215 side) 10k LOCKN Figure 6. Hot-plug and Lock detect scheme Copyright(C)2016 THine Electronics, Inc. 9/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E No HTPDN connection option HTPDN connection between THCV215 and THCV216 can be omitted as an application option. In this case, HTPDN at the Transmitter side should always be taken ad Low. See Figure 7. THCV215 THCV216 HTPDN HTPDN VDL (THCV215 side) 10k LOCKN Figure 7. HTPDN is not connected scheme Copyright(C)2016 THine Electronics, Inc. 10/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E THCV215 Pre-emphasis function (PRE [1:0]) Pre-emphasis can equalize severe signal degradation caused by long distance or high-speed transmission. Two pins, PRE1 and PRE0, select the strength of pre-emphasis. See Table 4. PRE[1:0] Description L,L w/o Pre-emphasis H,L w/ 100% Pre-emphasis L,H / H,H Not available Table 4. Pre-emphasis function table THCV215 Power Down function (PDN) By setting the PDN pin to low, it results in the power down mode. All the internal circuitry turns off and the both TXn+/- (n=0, 1) outputs turn to VDL. THCV216 Power Down function (PDN) By setting the PDN pin to low, it results in the power down mode. All the internal circuitry turns off and the RLXn+/- (X=A, B, C, D, E, F, CLK, n=0, 1) outputs turn to High-Z. THCV215 Link Ready function (RDY) This is a CMOS output for indicating the link status. RDY=High if link is ready. Copyright(C)2016 THine Electronics, Inc. 11/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Field BET Operation In order to help users to check the validity of high speed serial links (CML lines), THCV215/THCV216 have an operation mode in which they act as the bit error tester (BET). In this mode, THCV215 internally generates a test pattern, which is then serialized onto the CML high speed lines. THCV216 receives the data stream and checks the sampled data for bit errors. This "Field BET" mode is activated by setting Reserved1= H on THCV215 and Reserved3= H on THCV216 (Refer to Table 5). In the Field BET mode, the on-chip pattern generator on THCV215 is enabled and generates the test pattern as long as the LVDS clocks (TLCLK0+/-, TLCLK1+/-) are applied. Other LVDS data inputs may be left open or applied with any pattern. They are ignored by THCV215. The generated data pattern is then 8b/10b encoded, scrambled, and serialized onto the CML channels. As for THCV216, the internal test pattern check circuit gets enabled and the RS pin, which is normally an input, turns into an output for the pattern checker (LVDS output level is internally configured to be "Normal Swing"). The RS pin goes LOW whenever bit errors occur, and it stays HIGH when there is no bit error. Please Refer to Figure 8. Product THCV215 THCV216 Pin Name Reserved1 Reserved3 Normal L L Field BET H H RS 3.3V INPUT H: Normal Swing, L: Reduced Swing 3.3V OUTPUT Goes LOW when bit errors occur. Table 5. Field BET Operation Pin Settings THCV215 THCV216 LVDS data inputs are ignored LVDS clock to TLCLK0, 1 Test Pattern Checker Test Pattern Generator LVDS Swing Select for Normal Operation R S Test Point for Field BET Reserved1=H (Field BET mode) Reserved3=H (Field BET mode) Figure 8. Field BET Configuration Copyright(C)2016 THine Electronics, Inc. 12/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Absolute Maximum Ratings 0F Parameter 1.8V Supply VoltageVDL,CAVDL,CPVDL,LPVDL 3.3V Supply Voltage(LAVDH) 1.8V CMOS Input Voltage 1.8V CMOS Output Voltage LVDS Receiver Input Voltage CML Transmitter Output Voltage Output Current Storage Temperature Junction Temperature Reflow Peak Temperature / Time Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -50 -55 - Typ. - Max. Units +2.1 V +4.0 V VDL+0.3 V VDL+0.3 V LAVDH+0.3 V CAVDL+0.3 V 50 mA +125 C +125 C +260/10sec C Table 6. THCV215 Absolute Maximum Ratings Parameter 1.8V Supply Voltage(VDL,CAVDL,CPVDL0,CPVDL1) 3.3V Supply Voltage(LPVDH,LAVDH) 1.8V CMOS Input Voltage 3.3V CMOS Input Voltage CMOS Output Voltage CML Receiver Input Voltage LVDS Transmitter Output Voltage Output Current Storage Temperature Junction Temperature Reflow Peak Temperature / Time Maximum Power Dissipation @+25 Lead Temperature (Soldering, 10sec) Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -30 -55 - Typ. - Max. Units +2.1 V +4.0 V VDL+0.3 V LAVDH+0.3 +2.1 V CAVDL+0.3 V LAVDH+0.3 V 30 mA +125 C +125 C +260/10sec C 2 W +260 C Table 7. THCV216 Absolute Maximum Ratings Operating Conditions Parameter 1.8V Supply VoltageVDL,CAVDL,CPVDL,LPVDL 3.3V Supply Voltage(LAVDH) Operating Temperature Min. 1.62 3.00 0 Typ. 1.80 3.30 - Max. 1.98 3.60 70 Units V V Min. Typ. Max. Units 1.62 1.80 1.98 V 1.71 3.00 0 1.80 3.30 - 1.89 3.60 70 V V Table 8. THCV215 Operating Conditions Parameter 1.8V Supply Voltage(VDL,CAVDL,CPVDL0,CPVDL1) except for the 12 bit color depth mode 1.8V Supply Voltage(VDL,CAVDL,CPVDL0,CPVDL1) for the 12 bit color depth mode 3.3V Supply Voltage(LPVDH,LAVDH) Operating Temperature Table 9. THCV216 Operating Conditions "Absolute Maximum Ratings" are those values beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Copyright(C)2016 THine Electronics, Inc. 13/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Electrical Specifications 1.8V & 3.3V CMOS DC Specifications Symbol VIH VIL VOH VOL IIH IIL VIH3 VIL3 VOH3 VOL3 IIH3 IIL3 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leak Current High Input Leak Current Low High Level Input Voltage (3.3V inputs) Low Level Input Voltage (3.3V inputs) High Level Output Voltage (3.3V outputs) Low Level Output Voltage (3.3V outputs) Input Leak Current High (3.3V inputs) Input Leak Current Low (3.3V inputs) Conditions IOH=-2mA IOL=2mA VIN=VDL VIN=0V IOH=-4mA IOL=4mA VIN=LAVDH VIN=0V Min. 0.65xVDL 0 VDL-0.45 2.1 0 2.4 - Typ. - Max. VDL 0.35xVDL 0.2 10 10 LAVDH 0.8 0.4 10 10 Units V V V V uA uA V V V V uA uA Table 10. THCV215 and THCV216 1.8V & 3.3V CMOS DC Specifications CML & LVDS DC Specifications Symbol VTTH VTTL Parameter LVDS Differential Input High Threshold LVDS Differential Input Low Threshold ITIH ITIL RTIN LVDS Input Leak Current High LVDS Input Leak Current Low LVDS Differential Input Resistance VTOD CML Differential Mode Output Voltage PRE CML Pre-emphasis Level VTOC ITOH ITOS CML Common Mode Output Voltage CML Output Leak Current High CML Output Short Circuit Current Conditions PDN=L, TLxn+/-=LAVDH TLxn+/-=0V,PDN=L PDN=L DRV[1:0]=L,H PRE[1:0]=L,L PRE[1:0]=L,L PRE[1:0]=H,L PRE[1:0]=L,L PRE[1:0]=H,L PDN=L CAVDL=1.8V Min. -100 Typ. - Max. 100 - Units mV mV 80 100 10 10 120 uA uA W 200 80 300 0 100 CAVDL-VTOD CAVDL-2xVTOD - 400 120 mV % % mV mV uA mA -90 10 - Table 11. THCV215 CML & LVDS DC Specifications Symbol VRTH VRTL Parameter CML Differential Input High Threshold CML Differential Input Low Threshold IRIH IRIL IRRIH IRRIL RRIN VROC IROS CML Input Leak Current High CML Input Leak Current Low CML Input Current High CML Input Current Low CML Differential Input Resistance LVDS Differential Mode Output Voltage (Normal Swing) LVDS Differential Mode Output Voltage (Reduced Swing) Change in VROD between Complementary Output States LVDS Common Mode Output Voltage Change in VROC between Complementary Output States LVDS Output Short Circuit Current IROZ LVDS Output TRI-STATE Current VROD VROD VROC Conditions Min. -50 Typ. - Max. 50 Units mV mV -6 80 100 10 10 2 120 uA uA mA mA W RL=100, RS=H 250 350 450 mV RL=100, RS=L 100 200 300 mV 1.125 1.25 35 1.375 mV V -24 - 35 - mV mA - - 10 uA PDN=L, RXn+/-=CAVDL PDN=L,RXn+/-=0V RXn+/-=CAVDL RXn+/-=0V RL=100 RL=100 RL=100 RLxn+/-=0V PDN=L, RLxn+/-=0V / LAVDH x=A~F,CLK, n=0, 1 Table 12. THCV216 CML & LVDS DC Specifications Copyright(C)2016 THine Electronics, Inc. 14/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Supply Currents Symbol ITCCW Parameter Supply Current for 1.8V Power Supply (Worst Case Pattern) Supply Current for 3.3V Power Supply ITCCW33 (Worst Case Pattern) ITCCS Power Down Supply Current Conditions COL[1:0]=H,H PRE[1:0]=H,L SDSEL=H COL[1:0]=H,H PRE[1:0]=H,L SDSEL=H PDN=L All Inputs =Fixed L or H Min. Typ. Max. Units - - 210 mA - - 90 mA - - 200 uA Min. Typ. Max. Units - - 160 mA - - 190 mA - - 200 uA Table 13. THCV215 Supply Currents Symbol IRCCW Parameter Supply Current for 1.8V Power Supply (Worst Case Pattern) Supply Current for 3.3V Power Supply IRCCW33 (Worst Case Pattern) IRCCS Power Down Supply Current Conditions COL[1:0]=H,H SDSEL=H RS=H COL[1:0]=H,H SDSEL=H RS=H PDN=L All Inputs =Fixed L or H Table 14. THCV216 Supply Currents Vdiff = (TLCLKn +) - (TLCLKn-) Vdiff=0V tTCIP n=0,1 previous cycle current cycle next cycle TLAn +/TLBn +/TLCn +/- H H TLDn +/TLEn +/TLFn +/- Data Enable Control bit Figure 9. Worst Case Pattern Copyright(C)2016 THine Electronics, Inc. 15/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Switching Characteristics Symbol tDEH tDEL Parameter DE=High Duration DE=Low Duration Conditions Min. 2tTCIP 2tTCIP Typ. - Max. - Units sec sec Min. 10 11.76 13.3 2xtTCIP/7 2xtTCIP/7 -440 -390 -330 -tSK tTCIP/7-tSK 2xtTCIP/7-tSK 3xtTCIP/7-tSK 4xtTCIP/7-tSK 5xtTCIP/7-tSK 6xtTCIP/7-tSK -0.3xtTCIP 50 -2 (56/(5xn)+6.1) xtTCIP-5 (1) 0 - Typ. 0 tTCIP/7 2xtTCIP/7 3xtTCIP/7 4xtTCIP/7 5xtTCIP/7 6xtTCIP/7 - Units ns ns ns ns ns ps ps ps ns ns ns ns ns ns ns ns ps UI - Max. 50 50 50 5xtTCIP/7 5xtTCIP/7 440 390 330 +tSK tTCIP/7+tSK 2xtTCIP/7+tSK 3xtTCIP/7+tSK 4xtTCIP/7+tSK 5xtTCIP/7+tSK 6xtTCIP/7+tSK 0.3xtTCIP 150 2 (56/(5xn)+6.1) xtTCIP+5 (1) 10 20 - - 10 ms Table 15. DE requirement Symbol tTCIP tTCIH tTCIL Parameter TLCLK Period LVDS Differential Clock High Time LVDS Differential Clock Low Time tSK tTIP1 tTIP0 tTIP6 tTIP5 tTIP4 tTIP3 tTIP2 tTISK tTRF tTOSK LVDS Receiver Skew Margin LVDS Input Data Position0 LVDS Input Data Position1 LVDS Input Data Position2 LVDS Input Data Position3 LVDS Input Data Position4 LVDS Input Data Position5 LVDS Input Data Position6 Lane0/1 LVDS Input Clock Skew CML Output Rise and Fall Time(20%-80%) CML Lane0/1 Output Inter Pair Skew tTCD tTPD tTPLL0 tTPLL1 Input Clock to Output Data Delay Power On to PDN High Delay PDN High to CML Output Delay PDN Low to CML Output High Fix Delay LOCKN High to Training Pattern Output Delay LOCKN Low to Data Pattern Output Delay tTNP0 tTNP1 Conditions COL[1:0]=L,L | L,H COL[1:0]=H,L COL[1:0]=H,H tTCIP=75MHz tTCIP=85MHz tTCIP=100MHz ns ns ms ns 10 ms (1) n =3, 4, and 5 for 6/8bit, 10bit, and 12bit mode, respectively. Table 16. THCV215 Switching Characteristics Symbol Parameter tRBIT tRISK tRLVT tROP1 tROP0 tROP6 tROP5 tROP4 tROP3 tROP2 tROSK Unit Interval CML Lane0/1 Input Inter Pair Skew Margin LVDS Differential Output Transition Time LVDS Output Data Position0 LVDS Output Data Position1 LVDS Output Data Position2 LVDS Output Data Position3 LVDS Output Data Position4 LVDS Output Data Position5 LVDS Output Data Position6 Lane0/1 LVDS Output Clock Skew tRDC tRPD tRHPD0 tRHPD1 Input Data to Output Clock Delay Power On to PDN High Delay PDN High to HTPDN Low Delay PDN Low to HTPDN High Delay Training Pattern Input to LOCKN Low Delay PDN Low to LOCKN High Delay LOCKN Low to LVDS Output Delay LOCKN High to LVDS High-Z Delay tRPLL0 tRPLL1 tRLCK0 tRLCK1 Conditions COL[1:0]=L,L | L,H COL[1:0]=H,L COL[1:0]=H,H Min. 333 294 266 -0.25 tTCIP/7-0.25 2xtTCIP/7-0.25 3xtTCIP/7-0.25 4xtTCIP/7-0.25 5xtTCIP/7-0.25 6xtTCIP/7-0.25 (178+68xn) xtRBIT-5 (1) 0 - Typ. tTCIP/30 tTCIP/40 tTCIP/50 0.6 0 tTCIP/7 2xtTCIP/7 3xtTCIP/7 4xtTCIP/7 5xtTCIP/7 6xtTCIP/7 - Max. Units 1667 ps 1250 ps 1000 ps 15 UI 1.5 ns 0.25 ns tTCIP/7+0.25 ns 2xtTCIP/7+0.25 ns 3xtTCIP/7+0.25 ns 4xtTCIP/7+0.25 ns 5xtTCIP/7+0.25 ns 6xtTCIP/7+0.25 ns 50 ps (178+68xn) xtRBIT+5 (1) ns ns 1 us 1 us 10 ms 10 us 1 ms 0 ns (1) n =3, 4, and 5 for 6/8bit, 10bit, and 12bit mode, respectively. Table 17. THCV216 Switching Characteristics Copyright(C)2016 THine Electronics, Inc. 16/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E AC Timing Diagrams and Test Circuits THCV215 LVDS Input Switching Characteristics Vdiff = (TLCLKn +) - (TLCLKn-) Vdiff=0V tTCIP x=A,B,C,D,E,F n=0,1 Vdiff = (TLxn +) - (TLxn-) TLxn6 TLxn5 TLxn4 TLxn3 TLxn2 TLxn1 TLxn0 TLxn6 TLxn5 TLxn4 TLxn3 TLxn2 TLxn1 tTIP1 tTIP0 tTIP6 tTIP5 tTIP4 tTIP3 tTIP2 tTCIH Vdiff = (TLCLK0 +) - (TLCLK0-) tTCIL Vdiff=0V Vdiff = (TLCLK1 +) - (TLCLK1-) Vdiff=0V tTISK Figure 10. THCV215 LVDS Input Switching Timing Diagrams Copyright(C)2016 THine Electronics, Inc. 17/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E THCV216 LVDS Output Switching Characteristics tROP2 tROP3 tROP4 tROP5 tROP6 tROP0 tROP1 Vdiff = (RLxn +) - (RLxn-) RLxn6 RLxn5 RLxn4 RLxn3 RLxn2 Vdiff = (RLCLKn +) - (RLCLKn-) RLxn1 RLxn0 RLxn6 RLxn5 RLxn4 RLxn3 RLxn2 RLxn1 Vdiff=0V x=A,B,C,D,E,F n=0,1 tTCIP Vdiff = (RLCLK0 +) - (RLCLK0-) Vdiff=0V Vdiff = (RLCLK1 +) - (RLCLK1-) Vdiff=0V tROSK Figure 11. THCV216 LVDS Output Switching Timing Diagrams RLxn+ 5pF RL=100 RLxnx=A,B,C,D,E,F n=0,1 80% Vdiff = (RLxn +) - (RLxn-) 20% tRLVT tRLVT Figure 12. THCV216 LVDS Output Switching Timing Diagram and Test Circuit. Copyright(C)2016 THine Electronics, Inc. 18/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E THCV215 CML Output Switching Characteristics 75200nF 50 75200nF 50 TXn+ TXn- < 5mm n=0,1 80% Vdiff = (TXn +) - (TXn-) 20% tTRF tTRF Vdiff = (TX0 +) - (TX0-) Vdiff=0V tTOSK Vdiff = (TX1 +) - (TX1-) Vdiff=0V Figure 13. THCV215 CML Output Switching Timing Diagrams and Test Circuit THCV216 CML Input Switching Characteristics Vdiff = (RX0 +) - (RX0-) Vdiff=0V tRISK Vdiff = (RX1 +) - (RX1-) Vdiff=0V Figure 14. THCV216 CML Input Timing Diagrams Copyright(C)2016 THine Electronics, Inc. 19/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E DE period requirement Vdiff = (TLCLK0+) - (TLCLK0-) DE DE DE DE DE DE Vdiff = (TLC0+) - (TLC0-) tDEH tDEL Figure 15. DE period requirement Latency Characteristics Vdiff = (TLCLK0 +) - (TLCLK0-) Vdiff=0V tTCD Vdiff = (TX0 +) - (TX0-) pixel 1st bit pixel 1st bit Vdiff = (RX0 +) - (RX0-) tRDC Vdiff = (RLCLK0 +) - (RLCLK0-) Vdiff=0V Figure 16. THCV215 and THCV216 Latency Copyright(C)2016 THine Electronics, Inc. 20/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Lock and Unlock Sequence VDD18 : 1.8V power supply VDD33 : 3.3V power supply VDD18 VDD33 1.5V Power On TLCLKn LVDS Clock Pattern TLxn+/HTPDN LVDS Data Pattern Low-level tTPD PDN LOCKN tTPLL0 TXn Fix to VDD18 tTNP0 tTNP1 CDR Training ALN Training pattern Pattern Normal pattern tTPLL1 CDR Training pattern Normal pattern x=A,B,C,D,E,F n=0,1 Figure 17. THCV215 Lock/Unlock Sequence VDD18 : 1.8V power supply VDD33 : 3.3V power supply VDD18 VDD33 PDN 1.5V Power On tRPD tRHPD0 tRHPD1 HTPDN CDR Training ALN Training Pattern Pattern RXn Normal pattern tRPLL0 tRPLL1 LOCKN tRLCK1 tRLCK0 RLCLK RLx High-Z LVDS Clock Pattern High-Z LVDS Data Pattern x=A,B,C,D,E,F n=0,1 Figure 18. THCV216 Lock/Unlock Sequence tTPD and tRPD minimum is 0sec; therefore, PDN can be applied at the same time as VDD18 and VDD33. tTPLL0 is the time from "both PDN=High and HTPDN=Low" moment to Training pattern ignition. HTPDN could transit from High to Low under PDN=High condition at THCV215, which is different from what Figure 17 indicates but is natural situation. Copyright(C)2016 THine Electronics, Inc. 21/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Note 1)HTPDN/LOCKN connection between high VDD V-by-One(R) HS transmitter and THCV216 When using THCV216 with high VDD V-by-One(R) HS transmitter, user have to take care of HTPDN/LOCKN connection because THCV216 HTPDN/LOCKN output pins absolute maximum ratings are VDL+0.3V; therefore high VDD pull-up at transmitter side can cause violation of usage. Users are supposed to connect those HTPDN/LOCKN line between two devices with appropriate level-shifter configuration. V-by-One(R)HS Tx side PCB V-by-One(R)HS Rx side PCB 1.8V 3.3V THCV216 G D S 10k 10k HTPDN MOSFET (Vth<1.2V) V-by-One(R)HS Transmitter (Ex. THCV217,THCV233) 1.8V 3.3V 1.8V Tolerant Transistor G D S 10k 10k LOCKN MOSFET (Vth<1.2V) 2)LVDS input pin connection When LVDS line is not drove from the previous device, the line is pulled up to 3.3V internally in THCV215.This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose operating condition is lower voltage power supply than 3.3V. This phenomenon may happen at power on phase of the whole system including THCV215. One solution for this problem is PD=L control during no LVDS input period because pull-up resistors are cut off at power down state. LVDS Tx side PCB LVDS Rx side PCB Low VDD LAVDH THCV215 LVDS Tx or LVDS Tx integrated device LVDS input buffer Internal circuit of THCV215 3)Power On Sequence Don't input TCLK#+/- before power supply to THCV215 is on in order to keep absolute maximum ratings. 4)Unused LVDS input pins First, select appropriate color depth with COL0,COL1 pins. If there are inevitably remained LVDS no input pins which are originally active, tie them to GND. Second, avoid the situation that LVDS input pins in use are open. You can use PDN=L control during no LVDS input period to cut off pulled-up resistors. 5)Cable Connection and Disconnection Don't connect and disconnect CML and LVDS cables, when the power is supplied to the system. 6)GND Connection Connect the each GND of the PCB which Transmitter, Receiver and THCV215 on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. Copyright(C)2016 THine Electronics, Inc. 22/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E 7)Multi Drop Connection Multi drop connection is not recommended. RLCLK0,1THCV216 LVDS Rx RLCLK0,1+ LVDS Rx 8)Multiple counterpart use Multiple counterpart use such as following system is not recommended. p.15 tTISK spec should be kept. CLK IC TLCLK0TLCLK0+ LVDS Tx DATA CLK TLCLK1LVDS Tx DATA THCV215 TLCLK1+ Asynchronous use such as following system is not recommended. RLCLK0RLCLK0+ THCV216 CLK LVDS Rx DATA IC RLCLK1RLCLK1+ LVDS Rx DATA 9)Multiple device connection HTPDN and LOCKN signals are supposed to be connected proper for their purpose like the following figure. HTPDN should be from just one Rx to multiple Tx because its purpose is only ignition of all Tx. LOCKN should be connected so as to indicate that all Rx CDR become ready to receive normal operation data. LOCKN of Tx side can be simply split to multiple Tx. There can be other applicable circuits like `OR gate of LOCKN', `npn transistor with resistors as inverter', etc. Also possible time difference of internal processing time (p.15 THCV215 tTCD and THCV216 tRDC) on multiple data stream must be accommodated and compensated by the following destination device connected to multiple THCV216, which may have internal FIFO. THCV215 THCV216 HTPDN HTPDN LOCKN LOCKN clkin.1 clkout.1 FIFO PDN Source Device Ex. synchronized Time diff. comes up THCV215 Destination Device THCV216 HTPDN HTPDN LOCKN LOCKN FIFO clkin.2 clkout.2 PDN Internal processing time tTCD Internal processing time tRDC Copyright(C)2016 THine Electronics, Inc. 23/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Package 64 Lead Molded Thin Shrink Small Outline Package, JEDEC 6.10 0.10 8.10 0.20 64 1 17. 00 0.10 0. 50 NOM 0.10 0.17~0.27 1. 20 MAX 0. 90 0.10 0. 25 NOM 0~8 0. 10 0.05 0. 60 0.15 1. 00 NOM Detail of Lead End Unit:mm Figure 19. 64 pin TSSOP package physical dimension Copyright(C)2016 THine Electronics, Inc. 24/25 THine Electronics, Inc. Security E THCV215-216_Rev.2.70_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. Product Application 5.1 Application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. This product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this data sheet. THine Electronics, Inc. ("THine") accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user's request, testing of all functions and performance of the product is not necessarily performed. 9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. 10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damage may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. THine Electronics, Inc. sales@thine.co.jp http://www.thine.co.jp/ Copyright(C)2016 THine Electronics, Inc. 25/25 THine Electronics, Inc. Security E