S12
Microcontrollers
freescale.com
MC9S12VR-Family
Reference Manual
MC9S12VRRMV2
Rev. 2.8
October 2, 2012
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 2
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to: http://freescale.com/
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the CPU. For CPU
information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual.
Table 0-1. Revision History
Date Revision
Level Description
27-June-2011 Rev 2.3 • Corrected ADC conditional text settings, ADC resolution is 10 bit
29-July-2011 Rev 2.4 • Corrected ETRIG0/ETRIG1 in pinouts
06-February-2012 Rev 2.5
• Corrected register name in register summary page 585 address 0x024F
• Corrected PartID
• Added Maskset 2N05E
• Updated electricals: Num 5 & 6 Table I-2, Num 2 Table D-2, Num 2 Table J-1,
Table A-12, A-13 & A-14, Num 13 & 14 Table A-8, Table A-4
09-February-2012 Rev 2.6 • Added HVI[3:0] to Table A-4 Num 11
15-May-2012 Rev 2.7
• Correced NVM timing parameter
• Updated stop current values
• Added 1.16 ADC Result Reference
• Added Bandgap Spec Table B-1 Num 15 & 16
• Added Order Info Appendix
02-October-2012 Rev 2.8
• Minor Corrections
• Corrected Table B-1 Num 8 ACLK frequency is typ 20KHz
• Added Max value to Table A-13 Num 5
• Table M-1New NVM timing parameters
• Added Section C.3.2, “ATD Analog Input Parasitics
• See Section Chapter 2, “Port Integration Module (S12VRPIMV2) Revision
History
• See Section Chapter 4, “S12 Clock, Reset and Power Management Unit
(S12CPMU_UHV) Revision History
• Added Table B-2
• Changed Num 2 in Table H-2 inductive load max 450mH
MC9S12VR Family Reference Manual, Rev. 2.8
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Chapter 1 Device Overview MC9S12VR-Family . . . . . . . . . . . . . . . . . . . .21
Chapter 2 Port Integration Module (S12VRPIMV2) . . . . . . . . . . . . . . . . . .49
Chapter 3 S12G Memory Map Controller (S12GMMCV1) . . . . . . . . . . . .105
Chapter 4 Clock, Reset and Power Management (S12CPMU_UHV) . . .119
Chapter 5 Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . .175
Chapter 6 S12S Debug Module (S12SDBGV2) . . . . . . . . . . . . . . . . . . . .199
Chapter 7 Interrupt Module (S12SINTV1). . . . . . . . . . . . . . . . . . . . . . . . .243
Chapter 8 Analog-to-Digital Converter (ADC12B6CV2) . . . . . . . . . . . . .251
Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) . . . . . . . . . . . . . .277
Chapter 10 Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . .307
Chapter 11 Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . .345
Chapter 12 Timer Module (TIM16B8CV3). . . . . . . . . . . . . . . . . . . . . . . . . .371
Chapter 13 High-Side Drivers - HSDRV (S12HSDRV1) . . . . . . . . . . . . . . .399
Chapter 14 Low-Side Drivers - LSDRV (S12LSDRV1). . . . . . . . . . . . . . . .411
Chapter 15 LIN Physical Layer (S12LINPHYV1) . . . . . . . . . . . . . . . . . . . .425
Chapter 16 Supply Voltage Sensor - (BATSV2). . . . . . . . . . . . . . . . . . . . .443
Chapter 17 64 KByte Flash Module (S12FTMRG64K512V1). . . . . . . . . . .457
Appendix A MCU Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . .509
Appendix B VREG Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . .523
Appendix C ATD Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .525
Appendix D HSDRV Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . .531
Appendix E PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .533
Appendix F IRC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .535
Appendix G LINPHY Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .537
Appendix H LSDRV Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . .541
Appendix I BATS Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . .543
Appendix J PIM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .547
Appendix K SPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .549
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4 Freescale Semiconductor
Appendix L XOSCLCP Electrical Specifications . . . . . . . . . . . . . . . . . . . .555
Appendix M FTMRG Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .557
Appendix N Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .565
Appendix O Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . .571
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 5
Chapter 1
Device Overview MC9S12VR-Family
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2.1 MC9S12VR-Family Member Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.1 HCS12 16-Bit Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.2 On-Chip Flash with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.3 On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4.4 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.5 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.6 Internal Phase-Locked Loop (IPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.7 Clock and Power Management Unit (CPMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.8 System Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.9 Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4.10 Pulse Width Modulation Module (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4.11 LIN physical layer transceiver (LINPHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4.13 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4.14 Analog-to-Digital Converter Module (ATD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.15 Supply Voltage Sense (BATS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.16 On-Chip Voltage Regulator system (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.17 Low-side drivers (LSDRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4.18 High-side drivers (HSDRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4.19 Background Debug (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4.20 Debugger (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.6 Family Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.6.1 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7 Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.7.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
1.8 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.8.1 Pinout 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
1.8.2 Pinout 32-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
1.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.9.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.9.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.11.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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6 Freescale Semiconductor
1.12 API external clock output (API_EXTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1.13 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1.14 ADC External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
1.15 ADC Special Conversion Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 2
Port Integration Module (S12VRPIMV2)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.3 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.3.4 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.3.5 Port E, BKGD pin Pull Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.6 ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.7 PIM Miscellaneous Register (PIMMISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.8 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.9 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.10 Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.11 Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.12 Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.13 Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.14 Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.15 Module Routing Register 0 (MODRR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.16 Module Routing Register 1 (MODRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.17 Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.18 Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.19 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.20 Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.21 Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3.22 Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3.23 Module Routing Register 2 (MODRR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.3.24 Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.3.25 Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.3.26 Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.3.27 Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.3.28 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.3.29 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.3.30 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.3.31 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.3.32 Port L Input Register (PTIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.3.33 Port L Digital Input Enable Register (DIENL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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2.3.34 Port L Analog Access Register (PTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.3.35 Port L Input Divider Ratio Selection Register (PIRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.36 Port L Polarity Select Register (PPSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.37 Port L Interrupt Enable Register (PIEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.38 Port L Interrupt Flag Register (PIFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.39 Port AD Data Register (PT1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.40 Port AD Input Register (PTI1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.41 Port AD Data Direction Register (DDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.3.42 Port AD Pull Enable Register (PER1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.3.43 Port AD Polarity Select Register (PPS1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.3.44 Port AD Interrupt Enable Register (PIE1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.3.45 Port AD Interrupt Flag Register (PIF1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.5.2 ADC External Triggers ETRIG1-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.5.3 Over-Current Protection on EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.5.4 Open Input Detection on HVI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Chapter 3
S12G Memory Map Controller (S12GMMCV1)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.4.1 MCU Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.4.3 Unimplemented and Reserved Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.4.4 Prioritization of Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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Chapter 4
Clock, Reset and Power Management (S12CPMU_UHVV1)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.1.3 S12CPMU_UHV Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.2.3 VSUP — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.2.4 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.2.5 VDDX, VSSX— Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.2.6 VSS, VSSC — Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.2.7 API_EXTCLK — API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.2.8 VDD— Internal Regulator Output Supply (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . . 126
4.2.9 VDDF— Internal Regulator Output Supply (NVM Logic) . . . . . . . . . . . . . . . . . . . . . . 126
4.2.10 TEMPSENSE — Internal Temperature Sensor Output Voltage . . . . . . . . . . . . . . . . . . 126
4.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.4.3 Stop Mode using PLLCLK as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.4.4 Full Stop Mode using Oscillator Clock as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.5.3 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.5.4 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.7.1 General Initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Chapter 5
Background Debug Module (S12SBDMV1)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
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5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Chapter 6
S12S Debug Module (S12SDBGV2)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
6.4.1 S12SDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
6.4.3 Match Modes (Forced or Tagged) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
6.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.5.1 State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.5.2 Scenario 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.5.3 Scenario 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.5.4 Scenario 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
6.5.5 Scenario 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
6.5.6 Scenario 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
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6.5.7 Scenario 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.5.8 Scenario 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.5.9 Scenario 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.5.10 Scenario 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.5.11 Scenario 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Chapter 7
Interrupt Module (S12SINTV1)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
7.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
7.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
7.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
7.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
7.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
7.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
7.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.4.1 S12S Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.4.3 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
7.4.4 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
7.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Chapter 8
Analog-to-Digital Converter (ADC12B6CV2)
Block Description
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
8.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
8.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
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Chapter 9
Pulse-Width Modulator (S12PWM8B8CV2)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
9.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
9.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
9.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
9.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
9.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
9.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Chapter 10
Serial Communication Interface (S12SCIV5)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
10.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
10.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
10.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
10.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
10.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
10.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
10.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
10.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
10.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
10.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
10.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
10.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
10.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
10.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
10.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
10.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
10.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
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10.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Chapter 11
Serial Peripheral Interface (S12SPIV5)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
11.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
11.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
11.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
11.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
11.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
11.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
11.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
11.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
11.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
11.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
11.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
11.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
11.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Chapter 12
Timer Module (TIM16B8CV3)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
12.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
12.2.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 375
12.2.2 IOC6 - IOC0 — Input Capture and Output Compare Channel 6-0 . . . . . . . . . . . . . . . . 375
12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
12.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
12.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
12.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
12.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
12.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
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12.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Chapter 13
High-Side Drivers - HSDRV (S12HSDRV1)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
13.2.1 HS0, HS1— High Side Driver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
13.2.2 VSUPHS — High Side Driver Power Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
13.2.3 VSSXHS — High Side Driver Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
13.3.2 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
13.3.3 Port HS Data Register (HSDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
13.3.4 HSDRV Configuration Register (HSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
13.3.5 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
13.3.6 HSDRV Status Register (HSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
13.3.7 HSDRV Interrupt Enable Register (HSIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
13.3.8 HSDRV Interrupt Flag Register (HSIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
13.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
13.4.2 Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
13.4.3 Over-Current Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
13.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
13.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
13.5.1 Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Chapter 14
Low-Side Drivers - LSDRV (S12LSDRV1)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
14.2.1 LS0, LS1— Low Side Driver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
14.2.2 LSGND — Low Side Driver Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
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14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
14.3.2 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
14.3.3 Port LS Data Register (LSDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
14.3.4 LSDRV Configuration Register (LSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
14.3.5 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
14.3.6 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
14.3.7 LSDRV Status Register (LSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
14.3.8 LSDRV Interrupt Enable Register (LSIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
14.3.9 LSDRV Interrupt Flag Register (LSIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
14.4.2 Open-Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
14.4.3 Over-Current Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
14.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
14.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
14.5.1 Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Chapter 15
LIN Physical Layer (S12LINPHYV1)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
15.2.1 LIN — LIN Bus Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
15.2.2 LGND — LIN Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
15.2.3 VSUP — Positive Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
15.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
15.4.2 Slew Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
15.4.3 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
15.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
15.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
15.5.1 Over-current handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
15.5.2 Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Chapter 16
Supply Voltage Sensor - (BATSV2)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
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16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
16.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
16.2.1 VSENSE — Supply (Battery) Voltage Sense Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
16.2.2 VSUP — Voltage Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
16.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
16.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
16.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Chapter 17
64 KByte Flash Module (S12FTMRG64K512V1)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
17.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
17.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
17.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
17.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
17.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
17.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
17.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 490
17.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
17.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
17.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
17.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
17.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
17.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 507
17.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 507
17.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Appendix A
MCU Electrical Specifications
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
A.1.2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
A.1.3 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
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A.1.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
A.1.5 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
A.1.6 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
A.1.7 Power Dissipation and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
A.1.8 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
A.1.9 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Appendix B
VREG Electrical Specifications
Appendix C
ATD Electrical Specifications
C.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
C.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
C.2.1 Port AD Output Drivers Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
C.2.2 Source Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
C.2.3 Source Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
C.2.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
C.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
C.3.1 ATD Accuracy Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Appendix D
HSDRV Electrical Specifications
D.1 Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
D.2 Static Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
D.3 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Appendix E
PLL Electrical Specifications
E.1 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
E.1.1 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Appendix F
IRC Electrical Specifications
Appendix G
LINPHY Electrical Specifications
G.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
G.2 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
G.3 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
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Appendix H
LSDRV Electrical Specifications
H.1 Static Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
H.2 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Appendix I
BATS Electrical Specifications
I.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
I.2 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
I.3 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Appendix J
PIM Electrical Specifications
J.1 High-Voltage Inputs (HVI) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
J.2 Pin Interrupt Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Appendix K
SPI Electrical Specifications
K.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
K.1.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
K.1.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Appendix L
XOSCLCP Electrical Specifications
Appendix M
FTMRG Electrical Specifications
M.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
M.1.1 Erase Verify All Blocks (Blank Check) (FCMD=0x01) . . . . . . . . . . . . . . . . . . . . . . . . 557
M.1.2 Erase Verify Block (Blank Check) (FCMD=0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
M.1.3 Erase Verify P-Flash Section (FCMD=0x03). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
M.1.4 Read Once (FCMD=0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
M.1.5 Program P-Flash (FCMD=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
M.1.6 Program Once (FCMD=0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
M.1.7 Erase All Blocks (FCMD=0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
M.1.8 Erase P-Flash Block (FCMD=0x09). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
M.1.9 Erase P-Flash Sector (FCMD=0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
M.1.10Unsecure Flash (FCMD=0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
M.1.11Verify Backdoor Access Key (FCMD=0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
M.1.12Set User Margin Level (FCMD=0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
M.1.13Set Field Margin Level (FCMD=0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
M.1.14Erase Verify D-Flash Section (FCMD=0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
M.1.15Program D-Flash (FCMD=0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
MC9S12VR Family Reference Manual, Rev. 2.8
18 Freescale Semiconductor
M.1.16Erase D-Flash Sector (FCMD=0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
M.1.17NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Appendix N
Package Information
Appendix O
Detailed Register Address Map
O.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 19
Chapter 1
Device Overview MC9S12VR-Family
Table 1-1. Revision History
1.1 Introduction
The MC9S12VR-Family is an optimized automotive 16-bit microcontroller product line focused on
low-cost, high-performance, and low pin-count. This family integrates an S12 microcontroller with a LIN
Physical interface, a 5V regulator system to supply the microcontroller, and analog blocks to control other
elements of the system which operate at vehicle battery level (e.g. relay drivers, high-side driver outputs,
wake up inputs). The MC9S12VR-Family is targeted at generic automotive applications requiring single
node LIN communications. Typical examples of these applications include window lift modules, seat
modules and sun-roof modules to name a few.
The MC9S12VR-Family uses many of the same features found on the MC9S12G family, including error
correction code (ECC) on flash memory, EEPROM for diagnostic or data storage, a fast analog-to-digital
converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC
performance. The MC9S12VR-Family delivers an optimized solution with the integration of several key
system components into a single device, optimizing system architecture and achieving significant space
savings. The MC9S12VR-Family delivers all the advantages and efficiencies of a 16-bit MCU while
retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed
by users of Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12XS family, the
MC9S12VR-Family will run 16-bit wide accesses without wait states for all peripherals and memories.
Misaligned single cycle 16 bit RAM access is not supported. The MC9S12VR-Family will be available in
32-pin and 48-pin LQFP. In addition to the I/O ports available in each module, further I/O ports are
available with interrupt capability allowing wake-up from stop or wait modes.
The MC9S12VR-Family is a general-purpose family of devices created with relay based motor control in
mind and is suitable for a range of applications, including:
• Window lift modules
• Door modules
• Seat controllers
• Smart actuators
Version
Number
Revision
Date Description of Changes
1.0 26-November-2010 • Added Block Diagram
• Minor Corrections from Shared Review
2.0 11-April-2011 • New Revision for Maskset N05E PartID=$3201
• Added 6 PWM Channels
• Pinout changes for PWM channels
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
20 Freescale Semiconductor
• Sun roof modules
1.2 Features
This section describes the key features of the MC9S12VR-Family.
1.2.1 MC9S12VR-Family Member Comparison
Table 1-2 provides a summary of different members of the MC9S12VR-Family and their features. This
information is intended to provide an understanding of the range of functionality offered by this
microcontroller family.
Table 1-2. MC9S12VR - Family
Feature MC9S12VR48 MC9S12VR64
CPU HCS12
Flash memory (ECC) 48 Kbytes 64 Kbytes
EEPROM (ECC) 512 Bytes
RAM 2 Kbytes
LIN physical layer 1
SPI 1
SCI Up to 2
Timer 4ch x 16-bit
PWM 8ch x 8-bit or
4ch x 16-bit
ADC 6 ch x 10-bit available on external
pins and four internal channels.
see Table 1-13.
Frequency modulated PLL Yes
Internal 1 MHz RC oscillator Yes
Autonomous window watchdog 1
Low-side drivers
(protected for inductive loads)
2
High-side drivers Up to 2
High voltage Inputs 4
General purpose I/Os (5V) Up to 28
Direct battery sense pin Yes
Supply voltage sense Yes
Chip temperature sensor 1 general sensor
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 21
1.3 Chip-Level Features
On-chip modules available within the family include the following features:
• HCS12 CPU core
• 64 or 48 Kbyte on-chip flash with ECC
• 512 byte EEPROM with ECC
• 2 Kbyte on-chip SRAM
• Phase locked loop (IPLL) frequency multiplier with internal filter
• 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range
• 4-16MHz amplitude controlled pierce oscillator
• Internal COP (watchdog) module (with separate clock source)
• Timer module (TIM) supporting input/output channels that provide a range of 16-bit input capture,
output compare and counter (up to 4 channels)
• Pulse width modulation (PWM) module (up to 8 x 8-bit channels)
•10-bit resolution successive approximation analog-to-digital converter (ADC) with up to 6
channels available on external pins
• One serial peripheral interface (SPI) module
• One serial communication interface (SCI) module supporting LIN communications (with RX
connected to a timer channel for internal oscillator calibration purposes, if desired)
• Up to one additional SCI (not connected to LIN physical layer)
• One on-chip LIN physical layer transceiver fully compliant with the LIN 2.1 standard
• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
• Autonomous periodic interrupt (API) (combination with cyclic, watchdog)
• Two protected low-side outputs to drive inductive loads
• Up to two protected high-side outputs
• 4 high-voltage inputs with wake-up capability and readable internally on ADC
• Up to two 10mA high-current outputs
• 20mA high-current output for use as Hall sensor supply
• Battery voltage sense with low battery warning, internally reverse battery protected
• Chip temperature sensor
Supply voltage VSUP = 6V – 18 V (normal
operation)
up to 40V (protected operation)
EVDD output current 20mA @ 5V
Maximum execution speed 25 MHz
Package 32 pins
48 pins
Feature MC9S12VR48 MC9S12VR64
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
22 Freescale Semiconductor
1.4 Module Features
The following sections provide more details of the modules implemented on the MC9S12VR-Family.
1.4.1 HCS12 16-Bit Central Processor Unit (CPU)
The HCS12 CPU is a high-speed, 16-bit processing unit that has a programming model identical to that of
the industry standard M68HC11 central processor unit (CPU).
• Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution
• Supports instructions with odd byte counts, including many single-byte instructions. This allows
much more efficient use of ROM space.
• Extensive set of indexed addressing capabilities, including:
— Using the stack pointer as an indexing register in all indexed operations
— Using the program counter as an indexing register in all but auto increment/decrement mode
— Accumulator offsets using A, B, or D accumulators
— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
1.4.2 On-Chip Flash with ECC
On-chip flash memory on the MC9S12VR features the following:
• 64 or 48 Kbyte of program flash memory
— Automated program and erase algorithm
— Protection scheme to prevent accidental program or erase
• 512 Byte EEPROM
— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
— Erase sector size 4 bytes
— Automated program and erase algorithm
— User margin level setting for reads
1.4.3 On-Chip SRAM
• 2 Kbytes of general-purpose RAM
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 23
1.4.4 Main External Oscillator (XOSCLCP)
• Loop control Pierce oscillator using 4 MHz to 16 MHz crystal
— Current gain control on amplitude output
— Signal with low harmonic distortion
— Low power
— Good noise immunity
— Eliminates need for external current limiting resistor
— Transconductance sized for optimumstart-up margin for typical crystals
— Oscillator pins shared with GPIO functionality
1.4.5 Internal RC Oscillator (IRC)
• Factory trimmed internal reference clock
— Frequency: 1 MHz
— Trimmed accuracy over –40˚C to +105˚C ambient temperature range: ±1.3%
1.4.6 Internal Phase-Locked Loop (IPLL)
• Phase-locked-loop clock frequency multiplier
— No external components required
— Reference divider and multiplier allow large variety of clock rates
— Automatic bandwidth control mode for low-jitter operation
— Automatic frequency lock detector
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
— Reference clock sources:
– Internal 1 MHz RC oscillator (IRC)
1.4.7 Clock and Power Management Unit (CPMU)
• Real time interrupt (RTI)
• Clock monitor (CM)
• System reset generation
1.4.8 System Integrity Support
• Power-on reset (POR)
• Illegal address detection with reset
• Low-voltage detection with interrupt or reset
• Computer operating properly (COP) watchdog with option to run on internal RC oscillator
— Configurable as window COP for enhanced failure detection
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
24 Freescale Semiconductor
— Can be initialized out of reset using option bits located in flash memory
• Clock monitor supervising the correct function of the oscillator
1.4.9 Timer (TIM)
• Up to 4 x 16-bit channels for input capture or output compare
• 16-bit free-running counter with 8-bit precision prescaler
1.4.10 Pulse Width Modulation Module (PWM)
• Up to eight 8-bit channels or reconfigurable four 16-bit channel PWM resolution
— Programmable period and duty cycle per channel
— Center-aligned or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
1.4.11 LIN physical layer transceiver (LINPHY)
• Compliant with LIN physical layer 2.1
• Standby mode with glitch-filtered wake-up.
• Slew rate selection optimized for the baud rates: 10kBit/s, 20kBit/s and Fast Mode (up to
250kBit/s).
• Selectable pull-up of 30kΩ or 330kΩ (in Shutdown Mode, 330kΩonly)
• Current limitation by LIN Bus pin rising and falling edges
• Over-current protection with transmitter shutdown
1.4.12 Serial Peripheral Interface Module (SPI)
• Configurable 8- or 16-bit data size
• Full-duplex or single-wire bidirectional
• Double-buffered transmit and receive
• Master or slave
• MSB-first or LSB-first shifting
• Serial clock phase and polarity options
1.4.13 Serial Communication Interface Module (SCI)
• Full-duplex or single-wire operation
• Standard mark/space non-return-to-zero (NRZ) format
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
• 13-bit baud rate selection
• Programmable character length
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 25
• Programmable polarity for transmitter and receiver
• Active edge receive wake-up
• Break detect and transmit collision detect supporting LIN
• Internal connection to one SCI routable to external pins
1.4.14 Analog-to-Digital Converter Module (ATD)
• Up to 6-channel, 10-bit analog-to-digital converter
— 8-/10-bit resolution
— 3 us, 10-bit single conversion time
— Left or right justified result data
— Internal oscillator for conversion in stop modes
— Wake up from low power modes on analog comparison > or <= match
— Continuous conversion mode
— Multiple channel scans
• Pins can also be used as digital I/O
• Up to 6 pins can be used as keyboard wake-up interrupt (KWI)
• Internal voltages monitored with the ATD module
—V
SUP
,V
SENSE, chip temperature sensor, high voltage inputs, LIN physical temperature sense,
VRH, VRL, VDDF
1.4.15 Supply Voltage Sense (BATS)
• VSENSE & VSUP pin low or a high voltage interrupt
• VSENSE & VSUP pin can be routed via an internal divider to the internal ADC
1.4.16 On-Chip Voltage Regulator system (VREG)
• Voltage regulator
— Linear voltage regulator directly supplied by VSUP (protected VBAT)
— Low-voltage detect with low-voltage interrupt on VSUP
— Capable of supplying both the MCU internally and providing additional external current
(approximately 20mA) to supply other components within the electronic control unit.
— Over-temperature protection and interrupt
• Internal Voltage regulator
— Linear voltage regulator with bandgap reference
— Low-voltage detect with low-voltage interrupt on VDDA
— Power-on reset (POR) circuit
— Low-voltage reset (LVR)
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
26 Freescale Semiconductor
1.4.17 Low-side drivers (LSDRV)
• 2x low-side drivers targeted for up to approximately 150mA current capability.
• Internal timer or PWM channels can be routed to control the low-side drivers
• Open-load detection
• Over-current protection with shutdown and interrupt
• Active clamp (for driving relays)
• Recirculation detection
1.4.18 High-side drivers (HSDRV)
• 2 High-side drivers targeted for up to approximately 44mA current capability
• Internal timer or PWM channels can be routed to control the high-side drivers
• Open load detection
• Over-current protection with shutdown and interrupt
1.4.19 Background Debug (BDM)
• Background debug module (BDM) with single-wire interface
— Non-intrusive memory access commands
— Supports in-circuit programming of on-chip nonvolatile memory
1.4.20 Debugger (DBG)
•Trace buffer with depth of 64 entries
• Three comparators (A, B and C)
— Access address comparisons with optional data comparisons
— Program counter comparisons
— Exact address or address range comparisons
• Two types of comparator matches
— Tagged This matches just before a specific instruction begins execution
— Force This is valid on the first instruction boundary after a match occurs
• Four trace modes
• Four stage state sequencer
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 27
1.5 Block Diagram
Figure 1-1. MC9S12VR Block Diagram
2K bytes RAM
RESET
EXTAL
XTAL
512 bytes EEPROM with ECC
BKGD
VSUP
Real Time Interrupt
Clock Monitor
Single-wire Background
TEST
Debug Module
ADC
Interrupt Module
SCI1 PS0
PS1
PTS
AN[5:0] PAD[5:0]
10-bit 6 channel
16-bit 4 channel
Timer
TIM
Asynchronous Serial IF
8-bit 8 channel
Pulse Width Modulator
PWM
48K & 64K bytes Flash with ECC
CPU12-V1
COP Watchdog
PLL with Frequency
Modulation option
Debug Module
3 comparators
64 Byte Trace Buffer
Reset Generation
and Test Entry
RXD
TXD
Auton. Periodic Int.
PT3
PT0
PT1
PT2
PTT
PP0
PP1
PP2 / EVDD
PTP
IOC3
IOC0
IOC1
IOC2
VDDA
VSSA
VDDX1/VSSX1
VDDX2/VSSX2
HS0
HS1
5V IO Supply Output
VSS
Low Power Pierce
Oscillator
SCI0
Asynchronous Serial IF
RXD
TXD
MOSI
SS
SCK
MISO
SPI0
Synchronous Serial IF
PS2
PS3
PS4
PS5
Voltage Regulator
Input: 6V – 18V
Block Diagram shows the maximum configuration!
HS1
HS0
HSDRV 0 & 1
High Side Driver
LS0
LSDRV 0 & 1
Low Side Driver
Not all pins or all peripherals are available on all devices and packages.
Rerouting options are not shown.
PE0
PTE
PE1
PTAD
Analog-Digital
Converter
Internal RC Oscillator
PWM0
PWM1
PP3
PP4
PP5
PL0
PL1
PL2
PL3
LIN LINPHY
LIN Physical
PTL
LIN
LGND
VSUPHS VSUPHS
LSGND LSGND
LS1
LS0
LS1
VSENSE
BATS VSENSE
Battery Sensor
LGND
PWM2
PWM3
PWM4
PWM5
PWM[7:6] see Pinout
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
28 Freescale Semiconductor
1.6 Family Memory Map
Table 1-3 shows the MC9S12VR-Family register memory map.
Table 1-3. Device Register Memory Map
Address Module Size
(Bytes)
0x0000–0x0009 PIM (port integration module)10
0x000A–0x000B MMC (memory map control) 2
0x000C–0x000D PIM (port integration module) 2
0x000E–0x000F Reserved 2
0x0010–0x0017 MMC (memory map control) 8
0x0018–0x0019 Reserved 2
0x001A–0x001B Device ID register 2
0x001C–0x001F PIM (port integration module) 4
0x0020–0x002F DBG (debug module) 16
0x0030–0x0033 Reserved 4
0x0034–0x003F CPMU (clock and power management) 12
0x0040–0x006F TIM (timer module <= 4channels) 48
0x0070–0x009F ADC (analog to digital converter <= 6 channels) 48
0x00A0–0x00C7 PWM (pulse-width modulator <= 2channels) 40
0x00C8–0x00CF SCI0 (serial communication interface) 8
0x00D0–0x00D7 SCI1 (serial communication interface) 8
0x00D8–0x00DF SPI (serial peripheral interface) 8
0x00E0–0x00FF Reserved 32
0x0100–0x0113 FTMRG control registers 20
0x0114–0x011F Reserved 12
0x0120 INT (interrupt module) 1
0x0121–0x013F Reserved 31
0x0140-0x0147 HSDRV (high-side driver) 8
0x0148-0x014F Reserved 8
0x0150-0x0157 LSDRV (low-side driver) 8
0x0158-0x015F Reserved 8
0x0160-0x0167 LINPHY (LIN physical layer) 8
0x0168-0x016F Reserved 8
0x0170-0x0177 BATS (Supply Voltage Sense) 8
0x0178–0x023F Reserved 200
0x0240–0x027F PIM (port integration module) 64
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 29
NOTE
Reserved register space shown in Table 1-3 is not allocated to any module.
This register space is reserved for future use. Writing to these locations has
no effect. Read access to these locations returns zero.
Figure 1-2 shows MC9S12VR-Family CPU and BDM local address translation to the global memory map
as a graphical representation. The whole 256K global memory space is visible through the P-Flash window
located in the 64k local memory map located at 0x8000 - 0xBFFF using the PPAGE register.
NOTE
Flash space on page 0xC in Figure 1-2 is not available on S12VR48. This is
only available on S12VR64.
0x0280–0x02EF Reserved 112
0x02F0–0x02FF CPMU (clock and power management) 16
0x0300–0x03FF Reserved 256
Address Module Size
(Bytes)
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
30 Freescale Semiconductor
Figure 1-2. MC9S12VR-Family Global Memory Map.
Paging Window
0x3_FFFF
Local CPU and BDM
Memory Map Global Memory Map
0xFFFF
0xC000
0x0_0400
0x0_0000
0x3_C000
0x0000
0x8000
0x0400
0x4000 0x0_4000
Paging Window
RAM
RAM
Unimplemented
Unimplemented
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Register Space
Register Space
Internal
NVM
Resources
Internal
NVM
Resources
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
EEPROM
EEPROM EEPROM
EEPROM
Page 0xF
Page 0xF
Page 0xD
Page 0xD
Register Space
Register Space
Page 0xC
Page 0xC
Page 0xE
Page 0xE
Page 0xF
Page 0xF
Page 0xD
Page 0xD
Page 0xC
Page 0xC
NVMRES=1
Page 0x2
0x3_0000
0x3_4000
0x3_8000
0x0_8000
RAM
RAM
Unimplemented
Unimplemented
0x0600
0x3800
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 31
1.6.1 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip. Table 1-4 shows the assigned part ID
number and mask set number.
1.7 Signal Description and Device Pinouts
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the
individual IP blocks on the device.
1.7.1 Pin Assignment Overview
Table 1-5 provides a summary of which ports are available for 32-pin and 48-pin package option.
Table 1-4. Assigned Part ID Numbers
Device Mask Set Number Part ID
MC9S12VR48 1N05E $3281
MC9S12VR64 1N05E $3281
MC9S12VR48 2N05E1
1The open load detection feature described in Section 13.4.2 Open
Load Detection is not available on mask set 2N05E
$3282
MC9S12VR64 2N05E1$3282
Table 1-5. Port Availability by Package Option
Port 32 LQFP 48 LQFP
Port AD PAD[1:0] PAD[5:0]
Port E PE[1:0] PE[1:0]
Port P PP1,PP2 PP[5:0]
Port S PS[3:2] PS[5:0]
Port T PT[3:0] PT[3:0]
Port L PL[3:0] PL[3:0]
sum of ports 16 28
I/O power pairs VDDX/VSSX 1/1 2/2
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
32 Freescale Semiconductor
NOTE
To avoid current drawn from floating inputs, all non-bonded pins should be
configured as output or configured as input with a pull up or pull down
device enabled
1.7.2 Detailed Signal Descriptions
This section describes the signal properties.
1.7.2.1 RESET — External Reset Signal
The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to
a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has
an internal pull-up device.
1.7.2.2 TEST — Test Pin
This input only pin is reserved for factory test. This pin has an internal pull-down device.
NOTE
The TEST pin must be tied to ground in all applications.
1.7.2.3 BKGD / MODC — Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has an internal pull-up device.
1.7.2.4 PAD[5:0] / KWAD[5:0] — Port AD Input Pins of ADC
PAD[5:0] are general-purpose input or output signals. The signals can be configured on per signal basis as
interrupt inputs with wake-up capability (KWAD[5:0]).These signals can have a pull-up or pull-down
device selected and enabled on per signal basis. Out of reset the pull devices are disabled.
1.7.2.5 PE[1:0] — Port E I/O Signals
PE[1:0] are general-purpose input or output signals. The signals can have pull-down device, enabled by a
single control bit for this signal group. Out of reset the pull-down devices are enabled.
1.7.2.6 PP[5:0] / KWP[5:0] — Port P I/O Signals
PP[5:0] are general-purpose input or output signals. The signals can be configured on per signal basis as
interrupt inputs with wake-up capability (KWP[5:0]). PP[2] has a high current drive strength and an
over-current interrupt feature. They can have a pull-up or pull-down device selected and enabled on per
signal basis. Out of reset the pull devices are disabled.
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 33
1.7.2.7 PS[5:0] — Port S I/O Signals
PS[5:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull-up devices are enabled.
1.7.2.8 PT[3:0] — Port T I/O Signals
PT[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull devices are disabled.
1.7.2.9 PL[3:0] / KWL[3:0] — Port L Input Signals
PL[3:0] are high voltage input ports. The signals can be configured on per signal basis as interrupt inputs
with wake-up capability (KWL[3:0]).
1.7.2.10 LIN — LIN Physical Layer
This pad is connected to the single-wire LIN data bus.
1.7.2.11 HS[1:0] — High-Side Drivers Output Signals
Outputs of the two high-side drivers intended to drive incandescent bulbs or LEDs.
1.7.2.12 LS[1:0] — Low-Side Drivers Output Signals
Outputs of the two low-side drivers intended to drive inductive loads (relays).
1.7.2.13 VSENSE — Voltage Sensor Input
This pin can be connected to the supply (Battery) line for voltage measurements. The voltage present at
this input is scaled down by an internal voltage divider, and can be routed to the internal ADC via an analog
multiplexer. The pin itself is protected against reverse battery connections. To protect the pin from external
fast transients an external resistor is needed.
1.7.2.14 AN[5:0] — ADC Input Signals
AN[5:0] are the analog inputs of the Analog-to-Digital Converter.
1.7.2.15 SPI Signals
1.7.2.15.1 SS Signal
This signal is associated with the slave select SS functionality of the serial peripheral interface SPI.
1.7.2.15.2 SCK Signal
This signal is associated with the serial clock SCK functionality of the serial peripheral interface SPI.
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
34 Freescale Semiconductor
1.7.2.15.3 MISO Signal
This signal is associated with the MISO functionality of the serial peripheral interface SPI. This signal acts
as master input during master mode or as slave output during slave mode.
1.7.2.15.4 MOSI Signal
This signal is associated with the MOSI functionality of the serial peripheral interface SPI. This signal acts
as master output during master mode or as slave input during slave mode
1.7.2.16 LINPHY Signals
1.7.2.16.1 LPTXD Signal
This signal is the LINPHY transmit input. See Figure 2-22
1.7.2.16.2 LPRXD Signal
This signal is the LINPHY receive output. See Figure 2-22
1.7.2.17 SCI Signals
1.7.2.17.1 RXD[1:0] Signals
Those signals are associated with the receive functionality of the serial communication interfaces SCI1-0.
1.7.2.17.2 TXD[1:0] Signals
Those signals are associated with the transmit functionality of the serial communication interfaces SCI1-0.
1.7.2.18 PWM[7:0] Signals
The signals PWM[7:0] are associated with the PWM module outputs.
1.7.2.19 Internal Clock outputs
1.7.2.19.1 ECLK
This signal is associated with the output of the divided bus clock (ECLK).
NOTE
This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.
1.7.2.20 ETRIG[1:0]
These signals are inputs to the Analog-to-Digital Converter. Their purpose is to trigger ADC conversions.
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 35
1.7.2.21 IOC[3:0] Signals
The signals IOC[3:0] are associated with the input capture or output compare functionality of the timer
(TIM) module.
1.7.3 Power Supply Pins
MC9S12VR-Family power and ground pins are described below. Because fast signal transitions place
high, short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible.
NOTE
All ground pins must be connected together in the application.
1.7.3.1 VDDX1, VDDX2, VSSX1,VSSX2 — Power Output Pins and Ground Pins
VDDX1 and VDDX2 are the 5V power supply output for the I/O drivers. This voltage is generated by the
on chip voltage regulator. Bypass requirements on VDDX1 and VDDX2 pins depend on how heavily the
MCU pins are loaded. All VDDX pins are connected together internally. All VSSX pins are connected
together internally.
NOTE
The high side driver ground pin VSSXHS mentioned in Chapter 13,
“High-Side Drivers - HSDRV (S12HSDRV1) is internally connected to
VSSX2 ground pin.
NOTE
Not all power and ground pins are available on all packages. Refer to pinout
section for further details.
1.7.3.2 VDDA, VSSA — Power Supply Pins for ADC
These are the power supply and ground input pins for the analog-to-digital converter and the voltage
regulator.
NOTE
The reference voltages VRH and VRL mentioned in Appendix C, “ATD
Electrical Specifications are internally connected to VDDA and VSSA.
1.7.3.3 VSS — Core Ground Pin
The voltage supply of nominally 1.8V is generated by the internal voltage regulator. The return current
path is through the VSS pin.
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
36 Freescale Semiconductor
1.7.3.4 LGND — LINPHY Ground Pin
LGND is the the ground pin for the LIN physical layer LINPHY.
1.7.3.5 LSGND — Ground Pin for Low-Side Drivers
LSGND is the shared ground pin for the low-side drivers.
1.7.3.6 VSUP — Voltage Supply Pin for Voltage Regulator
VSUP is the 12V/18V shared supply voltage pin for the on chip voltage regulator.
1.7.3.7 VSUPHS — Voltage Supply Pin for High-Side Drivers
VSUPHS is the 12V/18V shared supply voltage pin for the high-side drivers.
1.7.3.8 Power and Ground Connection Summary
Table 1-6. Power and Ground Connection Summary
1.8 Device Pinouts
MC9S12VR-Familyis available in 48-pin package and 32-pin package. Signals in parentheses in
Figure 1-3. and Figure 1-4. denote alternative module routing options.
Mnemonic Nominal Voltage Description
VSS 0V Ground pin for 1.8V core supply voltage generated by on chip voltage regulator
VDDX1 5.0 V 5V power supply output for I/O drivers generated by on chip voltage regulator
VSSX1 0V Ground pin for I/O drivers
VDDX2 5.0 V 5V power supply output for I/O drivers generated by on chip voltage regulator
VSSX2 0V Ground pin for I/O drivers
VDDA 5.0 V External power supply for the analog-to-digital converter and for the reference circuit of the
internal voltage regulator
VSSA 0V Ground pin for VDDA analog supply
LGND 0V Ground pin for LIN physical
LSGND 0V Ground pin for low-side driver
VSUP 12V/18V External power supply for voltage regulator
VSUPHS 12V/18V External power supply for high-side driver
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 37
1.8.1 Pinout 48-pin LQFP
Figure 1-3. MC9S12VR 48-pin LQFP pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
MC9S12VR
48-pin LQFP
Pin out is subject to
change!
PAD4 / KWAD4 / AN4
PAD5 / KWAD5 / AN5
PL3 / HVI3 / KWL3
PL2 / HVI2 / KWL2
PL1 / HVI1 / KWL1
PL0 / HVI0 / KWL0
VSENSE
HS1 / (OC3) / (PWM1) / (PWM4)
VSSX2
HS0 / (OC2) / (PWM3)
VSUPHS
VSUP
TEST
RESET
PWM3 / KWP3 / PP3
PWM4 / (ETRIG0) / KWP4 / PP4
PWM5 / (ETRIG1) / IRQ / KWP5 / PP5
VSS
EXTAL / PE0
XTAL / PE1
VDDX2
PWM0 / KWP0 / PP0
XIRQ / PWM1 / KWP1 / PP1
PWM2 / EVDD / KWP2 / PP2
LGND
LIN
(PWM5) / (PWM6) / (OC0) / LS0
LSGND
(PWM7) / (OC1) / LS1
VSSX1
VDDX1
MISO / (RXD1) / (PWM4) / (ETRIG0) / PS2
ECLK / MOSI / (TXD1) / (PWM5) / (ETRIG1) / PS3
SCK / PS4
SS / PS5
MODC / BKGD
PS1 / (TXD0) / (LPDR1) / TXD1
PS0 / (RXD0) / RXD1
PT3 / IOC3 / (LPTXD) / (SS)
PT2 / IOC2 / (LPRXD) / (SCK)
PT1 / IOC1 / PWM7 / (TXD0) / (LPDR)
PT0 / IOC0 / PWM6 / (RXD0)
PAD0 / KWAD0 / AN0
PAD1 / KWAD1 / AN1
PAD2 / KWAD2 / AN2
PAD3 / KWAD3 / AN3
VDDA
VSSA
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
38 Freescale Semiconductor
1.8.2 Pinout 32-pin LQFP
Figure 1-4. MC9S12VR 32-pin LQFP pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
MC9S12VR
32-pin LQFP
Pin out is
subject to
change!
PL3 / HVI3 / KWL3
PL2 / HVI2 / KWL2
PL1 / HVI1 / KWL1
PL0 / HVI0 / KWL0
VSENSE
VSSX2
HS0 / (OC2) / (PWM3)
VSUP
TEST
RESET
VSS
EXTAL / PE0
XTAL / PE1
VDDX2
XIRQ / PWM1 / KWP1 / PP1
PWM2 / EVDD / KWP2 / PP2
LGND
LIN
(PWM5) / (PWM6) / (OC0) / LS0
LSGND
(PWM3) / (PWM0) / (OC1) / LS1
MISO / (RXD1) / (PWM4) / (ETRIG0) / PS2
ECLK / MOSI / (TXD1) / (PWM5) / (ETRIG1) / PS3
MODC / BKGD
PT3 / IOC3 / (LPTXD) / (SS)
PT2 / IOC2 / (LPRXD) / (SCK)
PT1 / IOC1 / PWM7 / (TXD0) / (LPDR1)
PT0 / IOC0 / PWM6 / (RXD0)
PAD0 / KWAD0 / AN0
PAD1 / KWAD1 / AN1
VDDA
VSSA
32
31
30
29
28
27
26
25
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 39
Table 1-7. Pin Summary
Package Function
Power
Supply
Internal Pull
Resistor
48
LQ
FP
32
LQ
FP
Pin 1th
Func.
2nd
Func.
3rd
Func.
4th
Func.
5th
Func. CTRL Reset
State
1 1 LGND —————— — —
22LIN—————— — —
3 3 LS0 OC01PWM5 PWM6 — — — — —
4 4 LSGND —————— — —
5 5 LS1 OC1 PWM7 — — — — — —
6 — VSSX1 —————— — —
7 — VDDX1 —————V
DDX ——
8 6 PS2 ETRIG0 PWM4 RXD1 MISO — VDDX PERS/PPSS Up
9 7 PS3 ETRIG1 PWM5 TXD1 MOSI ECLK VDDX PERS/PPSS Up
10—PS4SCK————V
DDX PERS/PPSS Up
11 — PS5 SS————V
DDX PERS/PPSS Up
12 8 BKGD MODC ————V
DDX PUCR/BKPUE Up
13 9 TEST —————N.A
RESET pin Down
14 10 RESET —————V
DDX TEST pin Up
15 — PP3 KWP3 PWM3 — — — VDDX PERP/PPSP Disabled
16 — PP4 KWP4 ETRIG0 PWM4 — — VDDX PERP/PPSP Disabled
17 — PP5 KWP5 ETRIG1 PWM5 IRQ — VDDX PERP/PPSP Disabled
18 11 VSS ——————— —
1912PE0EXTAL————V
DDX PUCR/PUPEE Down
2013PE1XTAL————V
DDX PUCR/PUPEE Down
21 14 VDDX2 —————— — —
22 — PP0 KWP0 PWM0 — — — VDDX PERP/PPSP Disabled
23 15 PP1 KWP1 PWM1 XIRQ — — VDDX PERP/PPSP Disabled
24 16 PP2 KWP2 EVDD PWM2 — — VDDX PERP/PPSP Disabled
25 17 VSUP —————— — —
26 — VSUPHS —————— — —
27 18 HS0 OC2 PWM3 — — — VSUPH
S
——
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
40 Freescale Semiconductor
28 19 VSSX2 —————— — —
29 — HS1 OC3 PWM1 PWM4 — — VSUPH
S
——
30 20 VSENSE —————— — —
31 21 PL0 HVI0 KWL0 — — — VDDX ——
32 22 PL1 HVI1 KWL1 — — — VDDX ——
33 23 PL2 HVI2 KWL2 — — — VDDX ——
34 24 PL3 HVI3 KWL3 — — — VDDX ——
35 — PAD5 KWAD5 AN5 — — — VDDA PER1AD/
PPS1AD
Disabled
36 — PAD4 KWAD4 AN4 — — — VDDA PER1AD/
PPS1AD
Disabled
37 25 VSSA —————— — —
3826VDDA—————— — —
39 — PAD3 KWAD3 AN3 — — — VDDA PER1AD/
PPS1AD
Disabled
40 — PAD2 KWAD2 AN2 — — — VDDA PER1AD/
PPS1AD
Disabled
41 27 PAD1 KWAD1 AN1 — — — VDDA PER1AD/
PPS1AD
Disabled
42 28 PAD0 KWAD0 AN0 — — — VDDA PER1AD/
PPS1AD
Disabled
43 29 PT0 IOC0 PWM6 RXD0 — — VDDX PERT/PPST Disabled
44 30 PT1 IOC1 PWM7 TXD0 LPDR1 — VDDX PERT/PPST Disabled
45 31 PT2 IOC2 LPRXD SCK — — VDDX PERT/PPST Disabled
46 32 PT3 IOC3 LPTXD SS — — VDDX PERT/PPST Disabled
47 — PS0 RXD0 RXD1 — — — VDDX PERS/PPSS Up
48 — PS1 TXD0 LPDR1 TXD1 — — VDDX PERS/PPSS Up
1Timer Output Compare Channel
Package Function
Power
Supply
Internal Pull
Resistor
48
LQ
FP
32
LQ
FP
Pin 1th
Func.
2nd
Func.
3rd
Func.
4th
Func.
5th
Func. CTRL Reset
State
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 41
1.9 Modes of Operation
The MCU can operate in different modes. These are described in 1.9.1 Chip Configuration Summary.
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in 1.9.2 Low Power Operation.
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging.
1.9.1 Chip Configuration Summary
The different modes and the security state of the MCU affect the debug features (enabled or disabled).
The operating mode out of reset is determined by the state of the MODC signal during reset (see
Table 1-8). The MODC bit in the MODE register shows the current operating mode and provides limited
mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge
of RESET.
1.9.1.1 Normal Single-Chip Mode
This mode is intended for normal device operation. The opcode from the on-chip memory is being
executed after reset (requires the reset vector to be programmed correctly). The processor program is
executed from internal memory.
1.9.1.2 Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin.
1.9.2 Low Power Operation
The MC9S12VR-Family has two dynamic-power modes (run and wait) and two static low-power modes
stop and pseudo stop). For a detailed description refer to Section Chapter 4 S12 Clock, Reset and Power
Management Unit (S12CPMU_UHV).
• Dynamic power mode: Run
— Run mode is the main full performance operating mode with the entire device clocked. The user
can configure the device operating speed through selection of the clock source and the phase
locked loop (PLL) frequency. To save power, unused peripherals must not be enabled.
Table 1-8. Chip Modes
Chip Modes MODC
Normal single chip 1
Special single chip 0
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
42 Freescale Semiconductor
• Dynamic power mode: Wait
— This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will
not execute instructions. The internal CPU clock is switched off. All peripherals can be active
in system wait mode. For further power consumption the peripherals can individually turn off
their local clocks. Asserting RESET, XIRQ, IRQ, or any other interrupt that is not masked ends
system wait mode.
• Static power mode Pseudo-stop:
— In this mode the system clocks are stopped but the oscillator is still running and the real time
interrupt (RTI) and watchdog (COP), Autonomous Periodic Interrupt (API) and ATD modules
may be enabled. Other peripherals are turned off. This mode consumes more current than
system STOP mode but, as the oscillator continues to run, the full speed wake up time from this
mode is significantly shorter.
• Static power mode: Stop
— The oscillator is stopped in this mode. By default, all clocks are switched off and all counters
and dividers remain frozen. The autonomous periodic interrupt (API), ATD, key wake-up and
the LIN physical layer transceiver modules may be enabled to wake the device.
1.10 Security
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 5.4.1
Security and Section 17.5 Security.
1.11 Resets and Interrupts
Consult the S12 CPU manual and the S12SINT section for information on exception processing.
1.11.1 Resets
Table 1-9. lists all Reset sources and the vector locations. Resets are explained in detail in the Chapter 4,
“S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)”.
Table 1-9. Reset Sources and Vector Locations
Vector Address Reset Source CCR
Mask Local Enable
$FFFE Power-On Reset (POR) None None
$FFFE Low Voltage Reset (LVR) None None
$FFFE External pin RESET None None
$FFFE Illegal Address Reset None None
$FFFC Clock monitor reset None OSCE Bit in CPMUOSC register
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 43
1.11.2 Interrupt Vectors
Table 1-10 lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Chapter 7, “Interrupt Module (S12SINTV1)”) provides an interrupt vector base register (IVBR) to relocate
the vectors.
$FFFA COP watchdog reset None CR[2:0] in CPMUCOP register
Table 1-10. Interrupt Vector Locations (Sheet 1 of 2)
Vector Address1Interrupt Source CCR
Mask Local Enable Wake up
from STOP
Wake up
from WAIT
Vector base + $F8 Unimplemented instruction trap None None - -
Vector base+ $F6 SWI None None - -
Vector base+ $F4 XIRQ X Bit None Yes Yes
Vector base+ $F2 IRQ I bit IRQCR (IRQEN) Yes Yes
Vector base+ $F0 RTI time-out interrupt I bit CPMUINT (RTIE) 4.6 Interrupts
Vector base+ $EE TIM timer channel 0 I bit TIE (C0I) No Yes
Vector base + $EC TIM timer channel 1 I bit TIE (C1I) No Yes
Vector base+ $EA TIM timer channel 2 I bit TIE (C2I) No Yes
Vector base+ $E8 TIM timer channel 3 I bit TIE (C3I) No Yes
Vector base+ $E6
to
Vector base + $E0
Reserved
Vector base+ $DE TIM timer overflow I bit TSCR2(TOF) No Yes
Vector base+ $DC
to
Vector base + $DA
Reserved
Vector base + $D8 SPI I bit SPICR1 (SPIE, SPTIE) No Yes
Vector base+ $D6 SCI0 I bit SCI0CR2
(TIE, TCIE, RIE, ILIE)
Ye s Ye s
Vector base + $D4 SCI1 I bit SCI1CR2
(TIE, TCIE, RIE, ILIE)
Ye s Ye s
Vector base + $D2 ADC I bit ATDCTL2 (ASCIE) No Yes
Vector base + $D0 Reserved
Vector base + $CE Port L I bit PIEL (PIEL3-PIEL0) Yes Yes
Vector Address Reset Source CCR
Mask Local Enable
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
44 Freescale Semiconductor
1.11.3 Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.
Vector base + $CC
to
Vector base + $CA
Reserved
Vector base + $C8 Oscillator status interrupt I bit CPMUINT (OSCIE) No Yes
Vector base + $C6 PLL lock interrupt I bit CPMUINT (LOCKIE) No Yes
Vector base + $C4
to
Vector base + $BC
Reserved
Vector base + $BA FLASH error I bit FERCNFG (SFDIE, DFDIE) No No
Vector base + $B8 FLASH command I bit FCNFG (CCIE) No Yes
Vector base + $B6
to
Vector base + $B0
Reserved
Vector base + $AE HSDRV over-current interrupt I bit HSIE (HSERR) No Ye s
Vector base + $AC LSDRV over-current interrupt I bit LSIE (LSERR) No Yes
Vector base + $AA LINPHY over-current interrupt I bit LPIE (LPERR) Yes Yes
Vector base + $A8 BATS low & high battery voltage
interrupt
I bit BATIE (BVHIE,BVLIE) No Yes
Vector base + $A6
to
Vector base + $90
Reserved
Vector base + $8E Port P interrupt I bit PIEP (PIEP5-PIEP3,
PIEP1-PIEP0)
Ye s Ye s
Vector base+ $8C Port P2 (EVDD Hall Sensor Supply)
over-current interrupt
I bit PIEP (OCIE) No Yes
Vector base + $8A Low-voltage interrupt (LVI) I bit CPMUCTRL (LVIE) No Yes
Vector base + $88 Autonomous periodical interrupt
(API) I bit CPMUAPICTRL (APIE) Ye s Ye s
Vector base + $86 High temperature interrupt I bit CPMUHTCTL(HTIE) Yes Yes
Vector base + $84 ADC compare interrupt I bit ATDCTL2 (ACMPIE) No Yes
Vector base + $82 Port AD interrupt I bit PIE1AD(PIE1AD5-PIE1AD0) Yes Yes
Vector base + $80 Spurious interrupt — None - -
116 bits vector address based
Table 1-10. Interrupt Vector Locations (Sheet 2 of 2)
Vector Address1Interrupt Source CCR
Mask Local Enable Wake up
from STOP
Wake up
from WAIT
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 45
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
1.11.3.1 Flash Configuration Reset Sequence Phase
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module Section 17.1,
“Introduction”.
1.11.3.2 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.11.3.3 I/O Pins
Refer to the PIM section for reset configurations of all peripheral module ports.
1.11.3.4 RAM
The RAM arrays are not initialized out of reset.
1.12 API external clock output (API_EXTCLK)
The API_EXTCLK option which is described 4.3.2.15 Autonomous Periodical Interrupt Control Register
(CPMUAPICTL) is not available on S12VR-Family.
1.13 COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence. See
Table 1-11 and Table 1-12 for coding
Table 1-11. Initial COP Rate Configuration
NV[2:0] in
FOPT Register
CR[2:0] in
COPCTL Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000
Device Overview MC9S12VR-Family
MC9S12VR Family Reference Manual, Rev. 2.8
46 Freescale Semiconductor
1.14 ADC External Trigger Input Connection
The ADC module includes external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external
trigger allows the user to synchronize ADC conversion to external trigger events. ETRIG0 is connected to
PP0 / PWM0 and ETRIG1 is connected to PP1 / PWM1. ETRIG2 and ETRIG3 are not used .ETRIG0 can
be routed to PS2 and ETRIG1 can be routed to PS3.
1.15 ADC Special Conversion Channels
Whenever the ADC’s Special Channel Conversion Bit (SC) in 8.3.2.6 ATD Control Register 5 (ATDCTL5)
is set, it is capable of running conversion on a number of internal channels. Table 1-13 lists the internal
sources which are connected to these special conversion channels.
1.16 ADC Result Reference
MCUs of the MC9S12VR-Fanmily are able to measure the internal bandgap reference voltage VBGwith
the analog digital converter. (see Table 1-13.) VBG is a constant voltage with a narrow distribution over
temperature and external voltage supply. The ADC conversion result of VBG is provided at address
0x0_405A/0x0_405B in the NVM IFR for reference. By measuring the voltage VBG and comparing the
result to the reference value in the IFR it is possible to determine the refrence voltage of the ADC VRH in
the application environment.
Table 1-12. Initial WCOP Configuration
NV[3] in
FOPT Register
WCOP in
COPCTL Register
10
01
Table 1-13. Usage of ADC Special Conversion Channels
ATDCTL5 Register Bits Usage
SC CD CC CB CA ADC Channel
1 0 0 0 1 Internal_7 Bandgap Voltage VBG or Chip temperature
sensor VHT see 4.3.2.13 High Temperature
Control Register (CPMUHTCTL)
1 0 0 1 0 Internal_0 Flash Supply Voltage VDDF
1 0 0 1 1 Internal_1 LINPHY temperature sensor
1 1 0 1 0 Internal_4 VSENSE or VSUP selectable in BATS module
see 16.1.1 Features
1 1 0 1 1 Internal_5 High voltage inputs Port L see 2.3.34 Port L
Analog Access Register (PTAL)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 47
Chapter 2
Port Integration Module (S12VRPIMV2)
Revision History
2.1 Introduction
2.1.1 Overview
The S12VR port integration module (PIM) establishes the interface between the peripheral modules and
the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This section covers:
• 2-pin port E associated with the external oscillator
• 4-pin port T associated with 4 TIM channels and 2 PWM channels
• 6-pin port S associated with 2 SCI and 1 SPI
• 6-pin port P with pin interrupts and wakeup function; associated with
—IRQ, XIRQ interrupt inputs
— Six PWM channels with two of those capable of driving up to 10 mA
— One output with over-current protection and interrupt capable of supplying up to 20 mA to
external devices such as Hall sensors
• 6-pin port AD with pin interrupts and wakeup function; associated with 6 ADC channels
• 4-pin port L with pin interrupts and wakeup function; associated with 4 high-voltage inputs for
digital or analog use with optional voltage divider bypass and open input detection
Most I/O pins can be configured by register bits to select data direction and to enable and select pullup or
pulldown devices.
Rev. No.
(Item No.)
Date
(Submitted By)
Sections
Affected Substantial Change(s)
V02.02 11 Apr 2011 • Added stop mode condition to PTTEL and PTPSL
• Minor corrections after review
V02.03 18 Apr 2011 • Minor corrections after review
V02.04 24 May 2012 • Corrected PTAENL bit value in PTIL bit description
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
48 Freescale Semiconductor
2.1.2 Features
The PIM includes these distinctive registers:
• Data registers and data direction registers for Ports E, T, S, P and AD when used as general-purpose
I/O
• Control registers to enable/disable pull devices and select pullups/pulldowns on Ports T, S, P, AD
on per-pin basis
• Single control register to enable/disable pullups on Port E on per-port basis and on BKGD pin
• Control registers to enable/disable open-drain (wired-or) mode on Port S
• Control register to enable/disable reduced output drive on Port P high-current pins
• Interrupt flag register for pin interrupts on Port P, L and AD
• Control register to configure IRQ pin operation
• Control register to enable ECLK clock output
• Routing registers to support module port relocation and control internal module routings:
— PWM and ETRIG to alternative pins
— SPI SS and SCK to alternative pins
— SCI1 to alternative pins
— HSDRV and LSDRV control selection from PWM, TIM or related register bit
— Various SCI0-LINPHY routing options supporting standalone use and conformance testing
— Optional LINPHY to TIM link
— Optional HVI to ADC link
A standard port pin has the following minimum features:
• Input/output selection
• 5 V output drive
• 5 V digital and analog input
• Input with selectable pullup or pulldown device
Optional features supported on dedicated pins:
• Two selectable output drive strengths
• Open drain for wired-or connections
• Interrupt input with glitch filtering
• High-voltage input
• 10 mA high-current output
• 20 mA high-current output with over-current protection for use as Hall sensor supply
2.2 External Signal Description
This section lists and describes the signals that do connect off-chip.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 49
Table 2-1 shows all the pins and their functions that are controlled by the PIM. Routing options are denoted
in parenthesis.
NOTE
If there is more than one function associated with a pin, the output priority
is indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
Table 2-1. Pin Functions and Priorities
Port Pin Name Pin Function
& Priority1I/O Description Pin Function
after Reset
- BKGD MODC2I MODC input during RESET BKGD
BKGD I/O BDM communication pin
E PE1 XTAL - CPMU OSC signal GPIO
PTE[1] I/O General-purpose
PE0 EXTAL - CPMU OSC signal
PTE[0] I/O General-purpose
T PT3 (SS) I/O SPI slave select GPIO
(LPTXD) I LINPHY transmit pin
IOC3 I/O TIM channel 3
PTT[3] I/O General-purpose
PT2 (SCK) I/O SPI serial clock
(LPRXD) O LINPHY receive pin
IOC2 I/O TIM channel 2
PTT[2] I/O General-purpose
PT1 (LPDR1) O LINPHY register LPDR[LPDR1]
(TXD0) I/O Serial Communication Interface 0 transmit pin
PWM7 O Pulse Width Modulator channel 7
IOC1 I/O TIM channel 1
PTT[1] I/O General-purpose
PT0 (RXD0) I Serial Communication Interface 0 receive pin
PWM6 O Pulse Width Modulator channel 6
IOC0 I/O TIM channel 0
PTT[0] I/O General-purpose
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
50 Freescale Semiconductor
S PS5 SS I/O SPI slave select GPIO
PTS[5] I/O General-purpose
PS4 SCK I/O SPI serial clock
PTS[4] I/O General-purpose
PS3 ECLK O Free running clock
MOSI I/O SPI master out / slave in
(TXD1) I/O Serial Communication Interface 1 transmit pin
(PWM5) O Pulse Width Modulator channel 5
(ETRIG1) I ADC external trigger input
PTS[3] I/O General-purpose
PS2 MISO I/O SPI master in / slave out
(RXD1) I Serial Communication Interface 1 receive pin
(PWM4) O Pulse Width Modulator channel 4
(ETRIG0) I ADC external trigger input
PTS[2] I/O General-purpose
PS1 TXD1 I/O Serial Communication Interface 1 transmit pin
(LPDR1) O LINPHY register LPDR[LPDR1]
(TXD0) I/O Serial Communication Interface 0 transmit pin
PTS[1] I/O General-purpose
PS0 RXD1 I Serial Communication Interface 1 receive pin
(RXD0) I Serial Communication Interface 0 receive pin
PTS[0] I/O General-purpose
Port Pin Name Pin Function
& Priority1I/O Description Pin Function
after Reset
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 51
2.3 Memory Map and Register Definition
This section provides a detailed description of all PIM registers.
P PP5 IRQ I Maskable level- or falling edge-sensitive interrupt GPIO
PWM5 O Pulse Width Modulator channel 5
ETRIG1 I ADC external trigger input
PTP[5]/
KWP[5]
I/O General-purpose; with pin interrupt and wakeup
PP4 PWM4 O Pulse Width Modulator channel 4
ETRIG0 I ADC external trigger input
PTP[4]/
KWP[4]
I/O General-purpose; with pin interrupt and wakeup
PP3 PWM3 O Pulse Width Modulator channel 3
PTP[3]/
KWP[3]
I/O General-purpose; with pin interrupt and wakeup
PP2 PWM2 O Pulse Width Modulator channel 2
PTP[2]/
KWP[2]/
EVDD
I/O General-purpose; with pin interrupt and wakeup;
switchable external power supply output with over-current
interrupt; high-current capable (20 mA)
PP1 XIRQ I Non-maskable level-sensitive interrupt
PWM1 O Pulse Width Modulator channel 1; high-current capable (10 mA)
PTP[1]/
KWP[1]
I/O General-purpose; with interrupt and wakeup; high-current
capable (10 mA)
PP0 PWM0 O Pulse Width Modulator channel 0; high-current capable (10 mA)
PTP[0]/
KWP[0]
I/O General-purpose; with interrupt and wakeup; high-current
capable (10 mA)
L PL3-0 PTL[3:0]/
KWL[3:0]
I General-purpose high-voltage input (HVI); with interrupt and
wakeup; optional ADC link
GPI (HVI)
AD PAD5-0 AN[5:0] I ADC analog GPIO
PTAD[5:0]/
KWAD[5:0]
I/O General-purpose; with interrupt and wakeup
1Signals in parentheses denote alternative module routing pins
2Function active when RESET asserted
Port Pin Name Pin Function
& Priority1I/O Description Pin Function
after Reset
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
52 Freescale Semiconductor
2.3.1 Register Map
Global
Address
Register
Name Bit 7 654321Bit 0
0x0000–
0x0007 Reserved R00000000
W
0x0008 PORTE R000000
PE1 PE0
W
0x0009 DDRE R000000
DDRE1 DDRE0
W
0x000A–
0x000B
Non-PIM
Address Range
RNon-PIM Address Range
W
0x000C PUCR R0 BKPUE 0PDPEE 0000
W
0x000D Reserved R00000000
W
0x000E–
0x001B
Non-PIM
Address Range
RNon-PIM Address Range
W
0x001C ECLKCTL RNECLK 0000000
W
0x001D PIMMISC ROCPE 0000000
W
0x001E IRQCR RIRQE IRQEN 000000
W
0x001F Reserved RReserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
0x0020–
0x023F
Non-PIM
Address Range
RNon-PIM Address Range
W
0x0240 PTT R0000
PTT3 PTT2 PTT1 PTT0
W
0x0241 PTIT R0000PTIT3 PTIT2 PTIT1 PTIT0
W
0x0242 DDRT R0000
DDRT3 DDRT2 DDRT1 DDRT0
W
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 53
0x0243 Reserved R00000000
W
0x0244 PERT R0000
PERT3 PERT2 PERT1 PERT0
W
0x0245 PPST R0000
PPST3 PPST2 PPST1 PPST0
W
0x0246 MODRR0 RMODRR07 MODRR06 MODRR05 MODRR04 MODRR03 MODRR02 MODRR01 MODRR00
W
0x0247 MODRR1 R0 0 MODRR15 MODRR14 0000
W
0x0248 PTS R0 0 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
W
0x0249 PTIS R 0 0 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
W
0x024A DDRS R0 0 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
W
0x024B Reserved R00000000
W
0x024C PERS R0 0 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
W
0x024D PPSS R0 0 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
W
0x024E WOMS R0 0 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
W
0x024F MODRR2 RMODRR27 0MODRR25 MODRR24 MODRR23 MODRR22 MODRR21 MODRR20
W
0x0250–
0x0257 Reserved R00000000
W
0x0258 PTP R0 0 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
0x0259 PTIP R 0 0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
W
Global
Address
Register
Name Bit 7 654321Bit 0
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
54 Freescale Semiconductor
0x025A DDRP R0 0 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
W
0x025B RDRP R00000
RDRP2 RDRP1 RDRP0
W
0x025C PERP R0 0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
W
0x025D PPSP R0 0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
W
0x025E PIEP ROCIE 0PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
W
0x025F PIFP ROCIF 0PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
0x0260–
0x0268 Reserved R00000000
W
0x0269 PTIL R0000PTIL3 PTIL2 PTIL1 PTIL0
W
0x026A DIENL R0000
DIENL3 DIENL2 DIENL1 DIENL0
W
0x026B PTAL RPTTEL PTPSL PTABYPL PTADIRL PTAENL 0PTAL1 PTAL0
W
0x026C PIRL R0000
PIRL3 PIRL2 PIRL1 PIRL0
W
0x026D PPSL R0000
PPSL3 PPSL2 PPSL1 PPSL0
W
0x026E PIEL R0000
PIEL3 PIEL2 PIEL1 PIEL0
W
0x026F PIFL
R0000
PIFL3 PIFL2 PIFL1 PIFL0
W
0x0270 Reserved R00000000
W
0x0271 PT1AD R0 0 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0
W
Global
Address
Register
Name Bit 7 654321Bit 0
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 55
2.3.2 Register Descriptions
The following table summarizes the effect of the various configuration bits, that is data direction (DDR),
output level (PORT/PT), pull enable (PER), pull select (PPS), interrupt enable (PIE) on the pin function,
pull device and interrupt activity.
The configuration bit PPS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
0x0272 Reserved R00000000
W
0x0273 PTI1AD R0 0 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0
W
0x0274 Reserved R00000000
W
0x0275 DDR1AD R0 0 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0
W
0x0276–
0x0278 Reserved R00000000
W
0x0279 PER1AD R0 0 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0
W
0x027A Reserved R00000000
W
0x027B PPS1AD R0 0 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0
W
0x027C Reserved R00000000
W
0x027D PIE1AD R0 0 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0
W
0x027E Reserved R00000000
W
0x027F PIF1AD R0 0 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0
W
= Unimplemented
Global
Address
Register
Name Bit 7 654321Bit 0
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
56 Freescale Semiconductor
2. Select either a pullup or pulldown device if PER is active.
Table 2-2. Pin Configuration Summary1
NOTE
• All register bits in this module are completely synchronous to internal
clocks during a register read.
• Figure of port data registers also display the alternative functions if
applicable on the related pin as defined in Table 2-1. Names in
parentheses denote the availability of the function when using a specific
routing option.
• Figures of module routing registers also display the module instance or
module channel associated with the related routing bit.
DDR PORT
PT PER PPS1
1Always “0” on Port E
PIE2
2Applicable only on Port P and AD
Function Pull Device Interrupt
0 x 0 x 0 Input Disabled Disabled
0 x 1 0 0 Input Pullup Disabled
0 x 1 1 0 Input Pulldown Disabled
0 x 0 0 1 Input Disabled Falling edge
0 x 0 1 1 Input Disabled Rising edge
0 x 1 0 1 Input Pullup Falling edge
0 x 1 1 1 Input Pulldown Rising edge
1 0 x x 0 Output, drive to 0 Disabled Disabled
1 1 x x 0 Output, drive to 1 Disabled Disabled
1 0 x 0 1 Output, drive to 0 Disabled Falling edge
1 1 x 1 1 Output, drive to 1 Disabled Rising edge
1. Not applicable for Port L. Refer to register descriptions.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 57
2.3.3 Port E Data Register (PORTE)
2.3.4 Port E Data Direction Register (DDRE)
Address 0x0008 Access: User read/write1
1Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R000000
PE1 PE0
W
Altern.
Function ——————XTAL EXTAL
Reset 00000000
Figure 2-1. Port E Data Register (PORTE)
Table 2-3. PORTE Register Field Descriptions
Field Description
1
PE
PorT data register port E — General-purpose input/output data, CPMU OSC XTAL signal
If the CPMU OSC function is active this pin is used as XTAL signal and the pulldown device is
disabled. When not used with the alternative function, this pin can be used as general-purpose I/O.
In general-purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
synchronized pin input state is read.
• The CPMU OSC function takes precedence over the general purpose I/O function if enabled.
0
PE
PorT data register port E — General-purpose input/output data, CPMU OSC EXTAL signal
If the CPMU OSC function is active this pin is used as EXTAL signal and the pulldown device is
disabled. When not used with the alternative function, this pin can be used as general-purpose I/O.
In general-purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
synchronized pin input state is read.
• The CPMU OSC function takes precedence over the general purpose I/O function if enabled.
Address 0x0009 Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R000000
DDRE1 DDRE0
W
Reset 00000000
Figure 2-2. Port E Data Direction Register (DDRE)
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
58 Freescale Semiconductor
2.3.5 Port E, BKGD pin Pull Control Register (PUCR)
2.3.6 ECLK Control Register (ECLKCTL)
Table 2-4. DDRE Register Field Descriptions
Field Description
1-0
DDRE
Data Direction Register port E —
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
Address 0x000C Access: User read/write1
1Read:Anytime
Write:Anytime, except BKPUE, which is writable in special mode only
76543210
R0
BKPUE
0
PDPEE
0000
W
Reset 01010000
Figure 2-3. Port E, BKGD pin Pull Control Register (PUCR)
Table 2-5. PUCR Register Field Descriptions
Field Description
6
BKPUE
BKGD pin Pullup Enable — Activate pullup device on pin
This bit configures whether a pullup device is activated, if the pin is used as input. If a pin is used as output this bit
has no effect.
1 Pullup device enabled
0 Pullup device disabled
4
PDPEE
Pull-Down Port E Enable — Activate pulldown devices on all port input pins
This bit configures whether a pulldown device is activated on all associated port input pins. If a pin is used as output
or used with the CPMU OSC function this bit has no effect. Out of reset the pulldown devices are enabled.
1 Pulldown devices enabled
0 Pulldown devices disabled
Address 0x001C Access: User read/write1
76543210
R
NECLK
0000000
W
Reset 10000000
Figure 2-4. ECLK Control Register (ECLKCTL)
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 59
2.3.7 PIM Miscellaneous Register (PIMMISC)
2.3.8 IRQ Control Register (IRQCR)
1Read: Anytime
Write: Anytime
Table 2-6. ECLKCTL Register Field Descriptions
Field Description
7
NECLK
No ECLK — Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
Address 0x001D Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R
OCPE
0000000
W
Reset 00000000
Figure 2-5. PIM Miscellaneous Register (PIMMISC)
Table 2-7. PIMMISC Register Field Descriptions
Field Description
7
OCPE
Over-Current Protection Enable— Activate over-current detector on PP2
Refer to Section 2.5.3, “Over-Current Protection on EVDD”
1 PP2 over-current detector enabled
0 PP2 over-current detector disabled
Address 0x001E Access: User read/write1
76543210
R
IRQE IRQEN
000000
W
Reset 00000000
Figure 2-6. IRQ Control Register (IRQCR)
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
60 Freescale Semiconductor
2.3.9 Reserved Register
NOTE
These reserved registers are designed for factory test purposes only and are
not intended for general user access. Writing to these registers when in
special modes can alter the module’s functionality.
1Read: Anytime
Write:
IRQE: Once in normal mode, anytime in special mode
IRQEN: Anytime
Table 2-8. IRQCR Register Field Descriptions
Field Description
7
IRQE
IRQ select Edge sensitive only —
1IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE=1
and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0IRQ pin configured for low level recognition
6
IRQEN
IRQ ENable —
1IRQ pin is connected to interrupt logic
0IRQ pin is disconnected from interrupt logic
Address 0x001F Access: User read/write1
1Read: Anytime
Write: Only in special mode
76543210
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
Reset xxxxxxxx
Figure 2-7. Reserved Register
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 61
2.3.10 Port T Data Register (PTT)
Address 0x0240 Access: User read/write1
1Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R0000
PTT3 PTT2 PTT1 PTT0
W
Altern.
Function
————(SS) (SCK) PWM72
2PWM function available on this pin only if not used with a routed HSDRV or LSDRV function. Refer to Section 2.3.15, “Module
Routing Register 0 (MODRR0)”
PWM62
————(LPTXD) (LPRXD) (TXD0) (RXD0)
——————(LPDR1) —
————IOC33
3TIM output compare function available on this pin only if not used with routed HSDRV. Refer to Section 2.3.15, “Module Routing
Register 0 (MODRR0)”. TIM input capture function available on this pin only if not used with LPRXD. Refer to Section 2.3.23,
“Module Routing Register 2 (MODRR2)”.
IOC24
4TIM output compare function available on this pin only if not used with routed HSDRV. Refer to Section 2.3.15, “Module Routing
Register 0 (MODRR0)”
IOC15
5TIM output compare function available on this pin only if not used with routed LSDRV. Refer to Section 2.3.15, “Module Routing
Register 0 (MODRR0)”
IOC05
Reset 00000000
Figure 2-8. Port T Data Register (PTT)
Table 2-9. PTT Register Field Descriptions
Field Description
3-2
PTT
PorT data register port T — General-purpose input/output data, SPI SS and SCK, TIM input/output, routed LINPHY
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The routed SPI takes precedence over the routed LINPHY function, TIM output function and the general-purpose
I/O function if enabled.
• The routed LINPHY function takes precedence over the TIM output function and the general-purpose I/O function
if the related channel is enabled.
• The TIM function takes precedence over the general-purpose I/O function.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
62 Freescale Semiconductor
2.3.11 Port T Input Register (PTIT)
1
PTT
PorT data register port T — General-purpose input/output data, TIM input/output, routed SCI0, LPDR[LPDR1]
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The routed SCI0 or LPDR[LPDR1] takes precedence over the TIM output function and the general-purpose I/O
function if enabled.
• The TIM function takes precedence over the general-purpose I/O function if enabled.
0
PTT
PorT data register port T — General-purpose input/output data, TIM input/output, routed SCI0
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The routed SCI0 takes precedence over the TIM output function and the general-purpose I/O function if enabled.
• The TIM function takes precedence over the general-purpose I/O function if enabled.
Address 0x0241 Access: User read only1
1Read: Anytime
Write:Never
76543210
R0000PTIT3 PTIT2 PTIT1 PTIT0
W
Reset 00000000
Figure 2-9. Port T Input Register (PTIT)
Table 2-10. PTIT Register Field Descriptions
Field Description
3-0
PTIT
PorT Input data register port T —
A read always returns the synchronized input state of the associated pin. It can be used to detect overload or short
circuit conditions on output pins.
Table 2-9. PTT Register Field Descriptions (continued)
Field Description
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 63
2.3.12 Port T Data Direction Register (DDRT)
Address 0x0242 Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0000
DDRT3 DDRT2 DDRT1 DDRT0
W
Reset 00000000
Figure 2-10. Port T Data Direction Register (DDRT)
Table 2-11. DDRT Register Field Descriptions
Field Description
3
DDRT
Data Direction Register port T —
This bit determines whether the pin is an input or output
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. The enabled
routed LINPHY forces the I/O state to be an input (LPTXD). Else the TIM forces the I/O state to be an output for a
TIM port associated with an enabled TIM output compare. In these cases the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
2
DDRT
Data Direction Register port T —
This bit determines whether the pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. The enabled
routed LINPHY forces the I/O state to be an output (LPRXD). Else the TIM forces the I/O state to be an output for a
TIM port associated with an enabled TIM output compare. In these cases the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
1-0
DDRT
Data Direction Register port T —
This bit determines whether the pin is an input or output.
Depending on the configuration of the enabled routed SCI0 the I/O state will be forced to be input or output. The
enabled routed LINPHY forces the I/O state to be an output (LPDR[LPDR1]). Else the TIM forces the I/O state to be
an output for a TIM port associated with an enabled TIM output compare. In these cases the data direction bit will
not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
64 Freescale Semiconductor
2.3.13 Port T Pull Device Enable Register (PERT)
2.3.14 Port T Polarity Select Register (PPST)
Address 0x0244 Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0000
PERT3 PERT2 PERT1 PERT0
W
Reset 00000000
Figure 2-11. Port T Pull Device Enable Register (PERT)
Table 2-12. PERT Register Field Descriptions
Field Description
3-0
PERT
Pull device Enable Register port T — Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Address 0x0245 Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0000
PPST3 PPST2 PPST1 PPST0
W
Reset 00000000
Figure 2-12. Port T Polarity Select Register (PPST)
Table 2-13. PPST Register Field Descriptions
Field Description
3-0
PPST
Pull device Polarity Select register port T — Configure pull device polarity on input pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
1 A pulldown device is selected
0 A pullup device is selected
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 65
2.3.15 Module Routing Register 0 (MODRR0)
Address 0x0246 Access: User read/write1
1Read: Anytime
Write: Once in normal, anytime in special mode
76543210
R
MODRR07 MODRR06 MODRR05 MODRR04 MODRR03 MODRR02 MODRR01 MODRR00
W
Routing
Option HS1 HS0 LS1 LS0
Reset 00000000
Figure 2-13. Module Routing Register 0 (MODRR0)
Table 2-14. Module Routing Register 0 Field Descriptions
Field Description
7-6
MODRR0
MODule Routing Register 0 — HS1
This register controls the routing of PWM and TIM channels to pin HS1 of HSDRV module. By default the pin is
controlled by the related HSDRV port register bit.
11 PWM channel 1 routed to HS1 if enabled
10 PWM channel 4 routed to HS1 if enabled
01 TIM output compare channel 3 routed to HS1 if enabled
00 HS1 controlled by register bit HSDR[HSDR1]. Refer to HSDRV section.
5-4
MODRR0
MODule Routing Register 0 — HS0
This register controls the routing of PWM and TIM channels to pin HS0 of HSDRV module. By default the pin is
controlled by the related HSDRV port register bit.
11 PWM channel 3 routed to HS0 if enabled
10 PWM channel 3 routed to HS0 if enabled
01 TIM output compare channel 2 routed to HS0 if enabled
00 HS0 controlled by register bit HSDR[HSDR0]. Refer to HSDRV section.
3-2
MODRR0
MODule Routing Register 0 — LS1
This register controls the routing of PWM and TIM channels to pin LS1 of LSDRV module. By default the pin is
controlled by the related LSDRV port register bit.
11 PWM channel 7 routed to LS1 if enabled
10 PWM channel 7 routed to LS1 if enabled
01 TIM output compare channel 1 routed to LS1 if enabled
00 LS1 controlled by register bit LSDR[LSDR1]. Refer to LSDRV section.
1-0
MODRR0
MODule Routing Register 0 — LS0
This register controls the routing of PWM and TIM channels to pin LS0 of LSDRV module. By default the pin is
controlled by the related LSDRV port register bit.
11 PWM channel 5 routed to LS0 if enabled
10 PWM channel 6 routed to LS0 if enabled
01 TIM output compare channel 0 routed to LS0 if enabled
00 LS0 controlled by register bit LSDR[LSDR0]. Refer to LSDRV section.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
66 Freescale Semiconductor
2.3.16 Module Routing Register 1 (MODRR1)
2.3.17 Port S Data Register (PTS)
Address 0x0247 Access: User read/write1
1Read: Anytime
Write: Once in normal, anytime in special mode
76543210
R0 0
MODRR15 MODRR14
0000
W
Routing
Option ——
PWM5
ETRIG1
PWM4
ETRIG0 ————
Reset 00000000
Figure 2-14. Module Routing Register 1 (MODRR1)
Table 2-15. Module Routing Register 1 Field Descriptions
Field Description
5
MODRR1
MODule Routing Register 1 —PWM5, ETRIG1
1 PWM channel 5 on PS3; ETRIG1 on PS3
0 PWM channel 5 on PP5; ETRIG1 on PP5
4
MODRR1
MODule Routing Register 1 —PWM4, ETRIG0
1 PWM channel 4 on PS2; ETRIG0 on PS2
0 PWM channel 4 on PP4; ETRIG0 on PP4
Address 0x0248 Access: User read/write1
1Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R0 0
PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
W
Altern.
Function
————ECLK — — —
——
SS SCK MOSI MISO — —
————(TXD1) (RXD1) TXD1 RXD1
————(PWM52)
2PWM function available on this pin only if not used with a routed HSDRV or LSDRV function. Refer to Section 2.3.15, “Module
Routing Register 0 (MODRR0)”
(PWM42) (LPDR1) —
————(ETRIG1) (ETRIG0) (TXD0) (RXD0)
Reset 00000000
Figure 2-15. Port S Data Register (PTS)
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 67
Table 2-16. PTS Register Field Descriptions
Field Description
5
PTS
PorT data register port S — General-purpose input/output data, SPI SS
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The SPI function takes precedence over the general-purpose I/O function if enabled.
4
PTS
PorT data register port S — General-purpose input/output data, SPI SCK
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The SPI function takes precedence over the general-purpose I/O function if enabled.
3
PTS
PorT data register port S — General-purpose input/output data, ECLK, SPI MOSI, routed SCI1, routed PWM,
routed ETRIG
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The ECLK output function takes precedence over the SPI, routed SCI1 and PWM and the general purpose I/O
function if enabled.
• The SPI function takes precedence over the routed SCI1, routed PWM and the general purpose I/O function if
enabled.
• The routed SCI1 function takes precedence over the PWM and general-purpose I/O function if enabled.
• The routed PWM function takes precedence over the general-purpose I/O function if enabled.
2
PTS
PorT data register port S — General-purpose input/output data, SPI MISO, routed SCI1, routed PWM, routed
ETRIG
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The SPI function takes precedence over the routed SCI1, routed PWM and the general purpose I/O function if
enabled.
• The routed SCI1 function takes precedence over the routed PWM and the general-purpose I/O function if enabled.
• The routed PWM function takes precedence over the general-purpose I/O function if enabled.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
68 Freescale Semiconductor
2.3.18 Port S Input Register (PTIS)
1
PTS
PorT data register port S — General-purpose input/output data, SCI1, routed SCI0 or LPDR[LPDR1]
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The SCI1 function takes precedence over the routed SCI0 or LPDR[LPDR1] function and the general-purpose I/O
function if enabled.
• The routed SCI0 or LPDR[LPDR1] function takes precedence over the general-purpose I/O function if enabled.
0
PTS
PorT data register port S — General-purpose input/output data, SCI1, routed SCI0
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The SCI1 function takes precedence over the routed SCI0 function and the general-purpose I/O function if
enabled.
• The routed SCI0 function takes precedence over the general-purpose I/O function if enabled.
Address 0x0249 Access: User read only1
1Read: Anytime
Write:Never
76543210
R 0 0 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
W
Reset 00000000
Figure 2-16. Port S Input Register (PTIS)
Table 2-17. PTIS Register Field Descriptions
Field Description
5-0
PTIS
PorT Input data register port S —
A read always returns the synchronized input state of the associated pin. It can be used to detect overload or short
circuit conditions on output pins.
Table 2-16. PTS Register Field Descriptions (continued)
Field Description
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 69
2.3.19 Port S Data Direction Register (DDRS)
Address 0x024A Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
W
Reset 00000000
Figure 2-17. Port S Data Direction Register (DDRS)
Table 2-18. DDRS Register Field Descriptions
Field Description
5
DDRS
Data Direction Register port S —
This bit determines whether the associated pin is an input or output. Depending on the configuration of the enabled
SPI the I/O state will be forced to be input or output. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
4
DDRS
Data Direction Register port S —
This bit determines whether the associated pin is an input or output. Depending on the configuration of the enabled
SPI the I/O state will be forced to be input or output. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
3
DDRS
Data Direction Register port S —
This bit determines whether the associated pin is an input or output. The ECLK output function, routed SCI1 and
routed PWM function forces the I/O state to output if enabled. Depending on the configuration of the enabled SPI
the I/O state will be forced to be input or output. In these cases the data direction bit will not change. The routed
ETRIG function has no effect on the I/O state.
1 Associated pin is configured as output
0 Associated pin is configured as input
2
DDRS
Data Direction Register port S —
This bit determines whether the associated pin is an input or output. Depending on the configuration of the enabled
SPI the I/O state will be forced to be input or output. The routed SCI1 function forces the I/O state to input if enabled.
The routed PWM function forces the I/O state to output if enabled. In these cases the data direction bit will not
change. The routed ETRIG function has no effect on the I/O state.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
70 Freescale Semiconductor
2.3.20 Port S Pull Device Enable Register (PERS)
1
DDRS
Data Direction Register port S —
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. The enabled
routed LINPHY forces the I/O state to be an output (LPDR[LPDR1]). In these cases the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
0
DDRS
Data Direction Register port S —
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Address 0x024C Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
W
Reset 00111111
Figure 2-18. Port S Pull Device Enable Register (PERS)
Table 2-19. PERS Register Field Descriptions
Field Description
5-0
PERS
Pull device Enable Register port S — Enable pull device on input pin or wired-or output pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Table 2-18. DDRS Register Field Descriptions (continued)
Field Description
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 71
2.3.21 Port S Polarity Select Register (PPSS)
2.3.22 Port S Wired-Or Mode Register (WOMS)
Address 0x024D Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
W
Reset 00000000
Figure 2-19. Port S Polarity Select Register (PPSS)
Table 2-20. PPSS Register Field Descriptions
Field Description
5-0
PPSS
Pull device Polarity Select register port S — Configure pull device polarity on input pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
1 A pulldown device is selected
0 A pullup device is selected
Address 0x024E Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
W
Reset 00000000
Figure 2-20. Port S Wired-Or Mode Register (WOMS)
Table 2-21. WOMS Register Field Descriptions
Field Description
5-0
WOMS
Wired-Or Mode register port S — Enable open-drain functionality on output pin
This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven
active-low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit
has no influence on pins used as input.
1 Output buffer operates as open-drain output
0 Output buffer operates as push-pull output
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
72 Freescale Semiconductor
2.3.23 Module Routing Register 2 (MODRR2)
Address 0x024F Access: User read/write1
1Read: Anytime
Write: Once in normal, anytime in special mode
76543210
R
MODRR27
0
MODRR25 MODRR24 MODRR23 MODRR22 MODRR21 MODRR20
W
Routing
Option
LPRXD to
TIM —SPI
SS and SCK SCI1 SCI0-to-LINPHY interface
Reset 00000000
Figure 2-21. Module Routing Register 2 (MODRR2)
Table 2-22. Module Routing Register 2 Field Descriptions
Field Description
7
MODRR2
MODule Routing Register 2 — TIM routing
1 TIM input capture channel 3 is connected to LPRXD
0 TIM input capture channel 3 is connected to PT3
5
MODRR2
MODule Routing Register 2 — SPI SS and SCK routing
1SS on PT3; SCK on PT2
0SS on PS5; SCK on PS4
4
MODRR2
MODule Routing Register 2 — SCI1 routing
1 TXD1 on PS3; RXD1 on PS2
0 TXD1 on PS1; RXD1 on PS0
3-0
MODRR2
MODule Routing Register 2 — SCI0-to-LINPHY routing
Selection of SCI0-to-LINPHY interface routing options to support probing and conformance testing. Refer to
Figure 2-22 for an illustration and Table 2-23 for preferred settings. SCI0 must be enabled for TXD0 routing to take
effect on pins. LINPHY must be enabled for LPRXD and LPDR[LPDR1] routings to take effect on pins.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 73
Figure 2-22. SCI0-to-LINPHY Routing Options Illustration
Table 2-23. Preferred Interface Configurations
MODRR2[3:0] Signal Routing Description
0000 Default setting:
SCI0 connects to LINPHY, interface internal only
0001 Direct control setting:
LPDR[LPDR1] register bit controls LPTXD, interface internal only
MODRR27
IOC3
PT2 / LPRXD
PT3 / LPTXD
PT1 / TXD0 / LPDR1
PT0 / RXD0
0
1
0
1
0
1
1
0
1
0
1
0
TIM input
capture
channel 3
MODRR22MODRR21MODRR20
SCI0 LINPHY
TXD0
RXD0
LPTXD
LPRXD
1
0
1
0
MODRR23
PS0 / RXD0
PS1 / TXD0 / LPDR1
LPDR1
LIN
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
74 Freescale Semiconductor
NOTE
For standalone usage of SCI0 on external pins set MODRR2[3:0]=0b1110
and disable the LINPHY (LPCR[LPE]=0). This releases PT2 and PT3 to
other associated functions and maintains TXD0 and RXD0 signals on PT1
and PT0, respectively, if no other function with higher priority takes
precedence.
2.3.24 Port P Data Register (PTP)
1100 Probe setting:
SCI0 connects to LINPHY, interface accessible on 2 external pins
1110 Conformance test setting:
Interface opened and all 4 signals routed externally
Address 0x0258 Access: User read/write1
1Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R0 0
PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
Altern.
Function
— — PWM523
2PWM function available on this pin only if not used with a routed HSDRV or LSDRV function. Refer to Section 2.3.15, “Module
Routing Register 0 (MODRR0)”
3PWM function available on this pin only if not routed to port S. Refer to Section 2.3.16, “Module Routing Register 1 (MODRR1)”
PWM423 PWM32PWM2 PWM12PWM0
——IRQ — — EVDD XIRQ —
— — ETRIG1 ETRIG0 — — — —
Reset 00000000
Figure 2-23. Port P Data Register (PTP)
MODRR2[3:0] Signal Routing Description
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 75
Table 2-24. PTP Register Field Descriptions
Field Description
5
PTP
PorT data register port P — General-purpose input/output data, PWM output, ETRIG input, pin interrupt
input/output, IRQ input
The IRQ signal is mapped to this pin when used with the IRQ interrupt function. If enabled
(IRQCR[IRQEN]=1) the I/O state of the pin is forced to be an input.
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The IRQ function takes precedence over the PWM and the general-purpose I/O function if enabled.
• The PWM function takes precedence over the general-purpose I/O function if the related channel is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
• The ETRIG function has no effect on the I/O state.
4
PTP
PorT data register port P — General-purpose input/output data, PWM output, ETRIG input, pin interrupt
input/output
The associated pin can be used as general-purpose I/O. In general-purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The PWM function takes precedence over the general-purpose I/O function if the related channel is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
• The ETRIG function has no effect on the I/O state.
3
PTP
PorT data register port P — General-purpose input/output data, PWM output, pin interrupt input/output
The associated pin can be used as general-purpose I/O. In general-purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The PWM function takes precedence over the general-purpose I/O function if the related channel is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
2
PTP
PorT data register port P — General-purpose input/output data, PWM output, switchable high-current capable
external supply with over-current protection (EVDD)
The associated pin can be used as general-purpose I/O or as a supply for external devices such as Hall sensors
(see Section 2.5.3, “Over-Current Protection on EVDD”. In output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The PWM function takes precedence over the general-purpose I/O function if the related channel is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
• An over-current interrupt can be generated if enabled. Refer to Section 2.4.4.3, “Over-Current Interrupt”
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
76 Freescale Semiconductor
2.3.25 Port P Input Register (PTIP)
1
PTP
PorT data register port P — General-purpose input/output data, PWM output, pin interrupt input/output, XIRQ input
The XIRQ signal is mapped to this pin when used with the XIRQ interrupt function. The
interrupt is enabled by clearing the X mask bit in the CPU Condition Code register. The I/O state of the
pin is forced to input level upon the first clearing of the X bit and held in this state even if the bit is set
again. A stop or wait recovery with the X bit set (refer to CPU12/CPU12X Reference Manual) is not
available.
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The XIRQ function takes precedence over the PWM and the general-purpose I/O function if enabled.
• The PWM function takes precedence over the general-purpose I/O function if the related channel is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
0
PTP
PorT data register port P — General-purpose input/output data, PWM output, pin interrupt input/output
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the
synchronized pin input state is read.
• The PWM function takes precedence over the general-purpose I/O function if the related channel is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
Address 0x0259 Access: User read only1
1Read: Anytime
Write:Never
76543210
R 0 0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
W
Reset 0 0000000
Figure 2-24. Port P Input Register (PTIP)
Table 2-25. PTIP Register Field Descriptions
Field Description
5-0
PTIP
PorT Input data register port P —
A read always returns the synchronized input state of the associated pin. It can be used to detect overload or short
circuit conditions on output pins.
Table 2-24. PTP Register Field Descriptions (continued)
Field Description
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 77
2.3.26 Port P Data Direction Register (DDRP)
Address 0x025A Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
W
Reset 00000000
Figure 2-25. Port P Data Direction Register (DDRP)
Table 2-26. DDRP Register Field Descriptions
Field Description
5
DDRP
Data Direction Register port P —
This bit determines whether the associated pin is an input or output.
The enabled IRQ function forces the I/O state to be an input if enabled. In this case the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
4-2
DDRP
Data Direction Register port P —
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
1
DDRP
Data Direction Register port P —
This bit determines whether the associated pin is an input or output.
The I/O state of the pin is forced to input level upon the first clearing of the X bit and held in this state even if the bit
is set again. The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit
will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
0
DDRP
Data Direction Register port P —
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
78 Freescale Semiconductor
2.3.27 Port P Reduced Drive Register (RDRP)
2.3.28 Port P Pull Device Enable Register (PERP)
Address 0x025B Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R00000
RDRP2 RDRP1 RDRP0
W
Reset 00000000
Figure 2-26. Port P Reduced Drive Register (RDRP)
Table 2-27. RDRP Register Field Descriptions
Field Description
2
RDRP
Reduced Drive Register port P — Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/10 of the full drive strength)
0 Full drive strength enabled
1-0
RDRP
Reduced Drive Register port P — Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Address 0x025C Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
W
Reset 00000000
Figure 2-27. Port P Pull Device Enable Register (PERP)
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 79
2.3.29 Port P Polarity Select Register (PPSP)
2.3.30 Port P Interrupt Enable Register (PIEP)
Read: Anytime.
Table 2-28. PERP Register Field Descriptions
Field Description
5-0
PERP
Pull device Enable Register port P — Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Address 0x025D Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
W
Reset 00000000
Figure 2-28. Port P Polarity Select Register (PPSP)
Table 2-29. PPSP Register Field Descriptions
Field Description
5-0
PPSP
Pull device Polarity Select register port P — Configure pull device polarity and pin interrupt edge polarity on input
pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pulldown device is selected; rising edge selected
0 A pullup device is selected; falling edge selected
Address 0x025E Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R
OCIE
0
PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
W
Reset 00000000
Figure 2-29. Port P Interrupt Enable Register (PIEP)
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
80 Freescale Semiconductor
2.3.31 Port P Interrupt Flag Register (PIFP)
Table 2-30. PIEP Register Field Descriptions
Field Description
7
OCIE
Over-Current Interrupt Enable register port P —
This bit enables or disables the over-current interrupt on PP2.
1 PP2 over-current interrupt enabled
0 PP2 over-current interrupt disabled (interrupt flag masked)
5-0
PIEP
Pin Interrupt Enable register port P —
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
Address 0x025F Access: User read/write1
1Read: Anytime
Write: Anytime, write 1 to clear
76543210
R
OCIF
0
PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
Reset 00000000
Figure 2-30. Port P Interrupt Flag Register (PIFP)
Table 2-31. PIFP Register Field Descriptions
Field Description
7
OCIF
Over-Current Interrupt Flag register port P —
This flag asserts if an over-current condition is detected on PP2 (Section 2.4.4.3, “Over-Current Interrupt”).
1 PP2 Over-current event occurred
0 No PP2 over-current event occurred
5-0
PIFP
Pin Interrupt Flag register port P —
This flag asserts after a valid active edge was detected on the related pin (Section 2.4.4, “Interrupts”). This can be
a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated
interrupt enable bit is set.
1 Active edge on the associated bit has occurred
0 No active edge occurred
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 81
2.3.32 Port L Input Register (PTIL)
2.3.33 Port L Digital Input Enable Register (DIENL)
Address 0x0269 Access: User read only1
1Read: Anytime
Write: No Write
76543210
R0000PTIL3 PTIL2 PTIL1 PTIL0
W
Reset 00000000
Figure 2-31. Port L Input Register (PTIL)
Table 2-32. PTIL - Register Field Descriptions
Field Description
3-0
PTIL
PorT Input data register port L —
A read returns the synchronized input state if the associated pin is used in digital mode, that is the related
DIENL bit is set to 1 and the pin is not used in analog mode (PTAL[PTAENL]=0). See Section 2.3.34, “Port L
Analog Access Register (PTAL)”. A one is read in any other case1.
1Refer to PTTEL bit description in Section 2.3.34, “Port L Analog Access Register (PTAL) for an override condition.
Address 0x26A Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0000
DIENL3 DIENL2 DIENL1 DIENL0
W
Reset 00000000
Figure 2-32. Port L Digital Input Enable Register (DIENL)
Table 2-33. DIENL Register Field Descriptions
Field Description
3-0
DIENL
Digital Input ENable port L — Input buffer control
This bit controls the HVI digital input function. If set to 1 the input buffers are enabled and the pin can be used with
the digital function. If the analog input function is enabled (PTAL[PTAENL]=1) the input buffer of the selected HVI pin
is forced off1 in run mode and is released to be active in stop mode only if DIENL=1.
1 Associated pin digital input is enabled if not used as analog input in run mode1
0 Associated pin digital input is disabled1
1Refer to PTTEL bit description in Section 2.3.34, “Port L Analog Access Register (PTAL) for an override condition.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
82 Freescale Semiconductor
2.3.34 Port L Analog Access Register (PTAL)
Address 0x026B Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R
PTTEL PTPSL PTABYPL PTADIRL PTAENL
0
PTAL1 PTAL0
W
Reset 00000000
Figure 2-33. Port L Analog Access Register (PTAL)
Table 2-34. PTAL Register Field Descriptions
Field Description
7
PTTEL
PorT Test Enable port L —
This bit forces the input buffer of the selected HVI pin (PTAL[1:0]) to be active while using the analog function to
support open input detection in run mode. Refer to Section 2.5.4, “Open Input Detection on HVI Pins”). In stop mode
this bit has no effect.
Note: In direct input connection (PTAL[PTADIRL]=1) the digital input buffer is not enabled.
1 Input buffer enabled when used with analog function and not in direct mode (PTAL[PTADIRL]=0)
0 Input buffer disabled when used with analog function
6
PTPSL
PorT Pull Select port L —
This bit selects a pull device on the selected HVI pin (PTAL[1:0]) in analog mode for open input detection. By default
a pulldown device is active as part of the input voltage divider. If set to 1 and PTTEL=1 and not in stop mode a pullup
to a level close to VDDX takes effect and overrides the weak pulldown device. Refer to Section 2.5.4, “Open Input
Detection on HVI Pins”).
1 Pullup enabled
0 Pulldown enabled
5
PTABYPL
PorT ADC connection BYPass port L —
This bit bypasses and powers down the impedance converter stage in the signal path from the analog input pin to
the ADC channel input. This bit takes effect only if using direct input connection to the ADC channel (PTADIRL=1).
1 Bypass impedance converter in ADC channel signal path
0 Use impedance converter in ADC channel signal path
4
PTADIRL
PorT ADC DIRect connection port L —
This bit connects the selected analog input signal (PTAL[1:0]) directly to the ADC channel bypassing the voltage
divider. This bit takes effect only in analog mode (PTAENL=1).
1 Input pin directly connected to ADC channel
0 Input voltage divider active on analog input to ADC channel
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 83
NOTE
When enabling the resistor paths to ground by setting PTAL[PTAENL]=1
or by changing PTAL[PTAL1:PTAL0], a settling time of tUNC_HVI + two
bus cycles must be considered to let internal nodes be loaded with correct
values.
3
PTAENL
PorT ADC connection ENable port L —
This bit enables the analog signal link of an HVI pin selected by PTAL[1:0] to an ADC channel. If set to 1 the analog
input function takes precedence over the digital input in run mode by forcing off the input buffers if not overridden by
PTTEL=1.
1 Selected pin by PTAL[1:0] is connected to ADC channel
0 No Port L pin is connected to ADC
1-0
PTAL
PorT ADC connection selector port L —
These selector bits choose the HVI pin connecting to an ADC channel if enabled (PTAENL=1). Refer to Table 2-35
for details.
Table 2-35. HVI pin connected to ADC channel
PTAL[PTAL1] PTAL[PTAL0] HVI pin connected
to ADC1
1Refer to device overview section for channel assignment
0 0 HVI0
0 1 HVI1
1 0 HVI2
1 1 HVI3
Table 2-34. PTAL Register Field Descriptions (continued)
Field Description
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
84 Freescale Semiconductor
2.3.35 Port L Input Divider Ratio Selection Register (PIRL)
2.3.36 Port L Polarity Select Register (PPSL)
Address 0x026C Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0000
PIRL3 PIRL2 PIRL1 PIRL0
W
Reset 00000000
Figure 2-34. Port L Input Divider Ratio Selection Register (PIRL)
Table 2-36. PIRL Register Field Descriptions
Field Description
3-0
PIRL
Port L Input Divider Ratio Select —
This bit selects one of two voltage divider ratios for the associated high-voltage input pin in analog mode.
1 RatioL_HVI selected
0 RatioH_HVI selected
Address 0x026D Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0000
PPSL3 PPSL2 PPSL1 PPSL0
W
Reset 00000000
Figure 2-35. Port L Polarity Select Register (PPSL)
Table 2-37. PPSL Register Field Descriptions
Field Description
3-0
PPSL
Pin interrupt Polarity Select register port L —
This bit selects the polarity of the active pin interrupt edge.
1 Rising edge selected
0 Falling edge selected
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 85
2.3.37 Port L Interrupt Enable Register (PIEL)
2.3.38 Port L Interrupt Flag Register (PIFL)
2.3.39 Port AD Data Register (PT1AD)
Address 0x026E Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0000
PIEL3 PIEL2 PIEL1 PIEL0
W
Reset 00000000
Figure 2-36. Port L Interrupt Enable Register (PIEL)
Table 2-38. PIEL Register Field Descriptions
Field Description
3-0
PIEL
Pin Interrupt Enable register port L —
This bit enables or disables the edge sensitive pin interrupt on the associated pin. For wakeup from stop mode
this bit must be set.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
Address 0x026F Access: User read/write1
1Read: Anytime
Write: Anytime, write 1 to clear
76543210
R0000
PIFL3 PIFL2 PIFL1 PIFL0
W
Reset 00000000
Figure 2-37. Port L Interrupt Flag Register (PIFL)
Table 2-39. PIFL Register Field Descriptions
Field Description
3-0
PIFL
Pin Interrupt Flag register port L —
This flag asserts after a valid active edge was detected on the related pin (Section 2.4.4, “Interrupts”). This
can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the
associated interrupt enable bit is set.
1 Active edge on the associated bit has occurred
0 No active edge occurred
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
86 Freescale Semiconductor
2.3.40 Port AD Input Register (PTI1AD)
Address 0x0271 Access: User read/write1
1Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R0 0
PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0
W
Altern.
Function — — AN5 AN4 AN3 AN2 AN1 AN0
Reset 00000000
Figure 2-38. Port AD Data Register (PT1AD)
Table 2-40. PT1AD Register Field Descriptions
Field Description
5-0
PT1AD
PorT data register 1 port AD — General-purpose input/output data, ADC AN analog input
When not used with the alternative function, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the register bit value is driven to the pin.
If the associated data direction bit set to 1, a read returns the value of the port register bit. If the data direction bit is
set to 0 and the ADC Digital Input Enable Register (ATDDIEN) is set to 1 the synchronized pin input state is read.
Address 0x0273 Access: User read only1
1Read: Anytime
Write:Never
76543210
R 0 0 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0
W
Reset 00000000
u = Unaffected by reset
Figure 2-39. Port P Input Register (PTI1AD)
Table 2-41. PTI1AD Register Field Descriptions
Field Description
5-0
PTI1AD
PorT Input data register 1 port AD —
A read always returns the synchronized input state of the associated pin if the ADC Digital Input Enable Register
(ATDDIEN) is set to 1. Else a logic 1 is read. It can be used to detect overload or short circuit conditions on output
pins.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 87
2.3.41 Port AD Data Direction Register (DDR1AD)
Address 0x0275 Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0
W
Reset 00000000
Figure 2-40. Port AD Data Direction Register (DDR1AD)
Table 2-42. DDR1AD Register Field Descriptions
Field Description
5-0
DDR1AD
Data Direction Register 1 port AD —
This bit determines whether the associated pin is an input or output.
To use the digital input function the ADC Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
88 Freescale Semiconductor
2.3.42 Port AD Pull Enable Register (PER1AD)
2.3.43 Port AD Polarity Select Register (PPS1AD)
Address 0x0279 Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0
W
Reset 00000000
Figure 2-41. Port AD Pullup Enable Register (PER1AD)
Table 2-43. PER1AD Register Field Descriptions
Field Description
5-0
PER1AD
Pull device Enable Register 1 port AD — Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Address 0x027B Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0
W
Reset 00000000
Figure 2-42. Port AD Polarity Select Register (PPS1AD)
Table 2-44. PPS1AD Register Field Descriptions
Field Description
5-0
PPS1AD
Pull device Polarity Select register 1 port AD — Configure pull device polarity and pin interrupt edge polarity on
input pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pulldown device is selected; rising edge selected
0 A pullup device is selected; falling edge selected
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 89
2.3.44 Port AD Interrupt Enable Register (PIE1AD)
Read: Anytime.
2.3.45 Port AD Interrupt Flag Register (PIF1AD)
Address 0x027D Access: User read/write1
1Read: Anytime
Write: Anytime
76543210
R0 0
PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0
W
Reset 00000000
Figure 2-43. Port AD Interrupt Enable Register (PIE1AD)
Table 2-45. PIE1AD Register Field Descriptions
Field Description
5-0
PIE1AD
Pin Interrupt Enable register 1 port AD —
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
For wakeup from stop mode this bit must be set to allow activating the RC oscillator.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
Address 0x027F Access: User read/write1
1Read: Anytime
Write: Anytime, write 1 to clear
76543210
R0 0
PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0
W
Reset 00000000
Figure 2-44. Port AD Interrupt Flag Register (PIF1AD)
Table 2-46. PIF1AD Register Field Descriptions
Field Description
5-0
PIF1AD
Pin Interrupt Flag register 1 port AD —
This flag asserts after a valid active edge was detected on the related pin (Section 2.4.4, “Interrupts”). This can be
a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated
interrupt enable bit is set.
1 Active edge on the associated bit has occurred
0 No active edge occurred
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
90 Freescale Semiconductor
2.4 Functional Description
2.4.1 General
Each pin except BKGD and port L pins can act as general-purpose I/O. In addition each pin can act as an
output or input of a peripheral module.
2.4.2 Registers
Table 2-47 lists the configuration registers which are available on each port. These registers except the pin
input and routing registers can be written at any time, however a specific configuration might not become
active.
For example selecting a pullup device: This device does not become active while the port is used as a
push-pull output.
2.4.2.1 Data register (PTx)
This register holds the value driven out to the pin if the pin is used as a general-purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general-purpose output. When
reading this address, the synchronized state of the pin is returned if the associated data direction register
bit is set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration (Figure 2-45).
2.4.2.2 Input register (PTIx)
This register is read-only and always returns the synchronized state of the pin (Figure 2-45).
2.4.2.3 Data direction register (DDRx)
This register defines whether the pin is used as an general-purpose input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-45).
Port Data Input Data
Direction
Reduced
Drive
Pull
Enable
Polarity
Select
Wired-
Or Mode
Interrupt
Enable
Interrupt
Flag Routing
Eyes-yes-yes-----
T yes yes yes - yes yes - - - yes
S yes yes yes - yes yes yes - - yes
P yes yes yes yes yes yes - yes yes -
L- yesyes
1
1Input buffer control only
- - yes - yes yes -
AD yes yes yes - yes yes - yes yes -
Table 2-47. Register availability per port (each cell represents one register with individual configuration bit)
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 91
Independent of the pin usage with a peripheral module this register determines the source of data when
reading the associated data register address (2.4.2.1/2-90).
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on port data or port input registers, when
changing the data direction register.
Figure 2-45. Illustration of I/O pin functionality
2.4.2.4 Reduced drive register (RDRx)
If the pin is used as an output this register allows the configuration of the drive strength independent of the
use with a peripheral module.
2.4.2.5 Pull device enable register (PERx)
This register turns on a pullup or pulldown device on the related pins determined by the associated polarity
select register (2.4.2.6/2-91).
The pull device becomes active only if the pin is used as an input or as a wired-or output. Some peripheral
module only allow certain configurations of pull devices to become active. Refer to the respective bit
descriptions.
2.4.2.6 Polarity select register (PPSx)
This register selects either a pullup or pulldown device if enabled.
PT
DDR
output enable
module enable
1
0
1
1
0
0
PIN
PTI
data out
Module
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
92 Freescale Semiconductor
It becomes only active if the pin is used as an input. A pullup device can be activated if the pin is used as
a wired-or output.
2.4.2.7 Wired-or mode register (WOMx)
If the pin is used as an output this register turns off the active-high drive. This allows wired-or type
connections of outputs.
2.4.2.8 Interrupt enable register (PIEx)
If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable
the interrupt.
2.4.2.9 Interrupt flag register (PIFx)
If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event.
2.4.2.10 Module routing register (MODRRx)
Routing registers allow software re-configuration of specific peripheral inputs and outputs:
• MODRR0 selects the driving source of the HSDRV and LSDRV pins
• MODRR1 selects optional pins for PWM channels and ETRIG inputs
• MODRR2 supports options to test the internal SCI-LINPHY interface signals
2.4.3 Pins and Ports
NOTE
Please refer to the device pinout section to determine the pin availability in
the different package options.
2.4.3.1 BKGD pin
The BKGD pin is associated with the BDM module.
During reset, the BKGD pin is used as MODC input.
2.4.3.2 Port E
This port is associated with the CPMU OSC.
Port E pins PE1-0 can be used for general-purpose or with the CPMU OSC module.
2.4.3.3 Port T
This port is associated with TIM, routed SCI-LINPHY interface and routed SPI.
Port T pins can be used for either general-purpose I/O or with the channels of the standard TIM, SPI, or
SCI and LINPHY subsystems.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 93
2.4.3.4 Port S
This port is associated with the ECLK, SPI, SCI1, routed SCI0, routed PWM channels and ETRIG inputs.
Port S pins can be used either for general-purpose I/O, or with the ECLK, SPI, SCI, and PWM subsystems.
2.4.3.5 Port P
Port P pins can be used for either general-purpose I/O, IRQ and XIRQ or with the PWM subsystem. All
pins feature pin interrupt functionality.
PP2 has an increased current capability to drive up to 20 mA to supply external devices for external Hall
sensors. An over-current protection is available.
PP1 and PP0 have an increased current capability to drive up to 10 mA.
PP4 and PP5 support ETRIG functionality.
PP5 can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ interrupt
input. IRQ will be enabled by setting the IRQCR[IRQEN] configuration bit (2.3.8/2-59) and clearing the
I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially configured as a simple
input with a pullup.
PP0 can be used for either general-purpose input or as the level-sensitive XIRQ interrupt input. XIRQ can
be enabled by clearing the X-bit in the CPU condition code register. It is inhibited at reset so this pin is
initially configured as a high-impedance input with a pullup.
2.4.3.6 Port L
Port L provides four high-voltage inputs (HVI) with the following features:
• Input voltage proof up to VHVIx
• Digital input function with pin interrupt and wakeup from stop capability
• Analog input function with selectable divider ratio routable to ADC channel. Optional direct input
bypassing voltage divider and impedance converter. Capable to wakeup from stop (pin interrupts
in run mode not available). Open input detection.
Figure 2-46 shows a block diagram of the HVI.
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
94 Freescale Semiconductor
Figure 2-46. HVI Block Diagram
Voltages up to VHVIx can be applied to all HVI pins. Internal voltage dividers scale the input signals down
to logic level. There are two modes, digital and analog, where these signals can be processed.
2.4.3.6.1 Digital Mode Operation
In digital mode the input buffers are enabled (DIENL[x]=1 & PTAL[PTAENL]=0). The synchronized pin
input state determined at threshold level VTH_HVI can be read in register PTIL. Interrupt flags (PIFL) are
set on input transitions if enabled (PIEL[x]=1) and configured for the related edge polarity (PPSL).
Wakeup from stop mode is supported.
2.4.3.6.2 Analog Mode Operation
In analog mode (PTAL[PTAENL]=1) the voltage applied to a selectable pin (PTAL[PTAL1:PTAL0]) can
be measured on an internal ADC channel (refer to device overview section for channel assignment). One
of two input divider ratios (RatioH_HVI, RatioL_HVI) can be chosen on each analog input (PIRL[x]) or the
HVIx
PTIL[x]
PIRL[x]
ADC
REXT_HVI
ANALOG[x]
VHVI
(DIENL[x] & (ANALOG[x] | STOP))
Input Buffer
Impedance
Converter
PTAENL
&STOP & PTADIRL
ANALOG[x]
& STOP & PTADIRL
VDDX
& STOP
ANALOG[x]
| (ANALOG[x] & PTADIRL & PTTEL & STOP)
40K
500K
110K
440K
ANALOG[x] = PTAENL & PTAL[1:0]
ANALOG[x]
& PTTEL
& PTPSL
& PTADIRL
& PTABYPL
(other inputs)
10K
& PTADIRL
&STOP
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 95
voltage divider can be bypassed (PTAL[PTADIRL]=1). Additionally in latter case the impedance
converter in the ADC signal path can be configured to be used or bypassed in direct input mode
(PTAL[PTABYPL]).
In run mode the digital input buffer of the selected pin is disabled to avoid shoot-through current. Thus pin
interrupts cannot be generated.
In stop mode the digital input buffer is enabled only if DIENL[x]=1 to support wakeup functionality.
Table 2-48 shows the HVI input configuration depending on register bits and operation mode.
NOTE
An external resistor REXT_HVI must always be connected to the
high-voltage inputs to protect the device pins from fast transients and to
achieve the specified pin input divider ratios when using the HVI in analog
mode.
2.4.3.7 Port AD
This port is associated with the ADC.
Port AD pins can be used for either general-purpose I/O, or with the ADC subsystem.
2.4.4 Interrupts
This section describes the interrupts generated by the PIM and their individual sources. Vector addresses
and interrupt priorities are defined at MCU level.
Table 2-48. HVI Input Configurations
Mode DIENL PTAENL Digital Input Analog Input Resulting Function
Run 0 0 off off Input disabled (Reset)
0 1 off1enabled Analog input, interrupt not supported
1 0 enabled off Digital input, interrupt supported
1 1 off1
1Enabled if (PTAL[PTTEL]=1 & PTAL[PTADIRL]=0)
enabled Analog input, interrupt not supported
Stop 0 0 off off Input disabled, wakeup from stop not
supported
0 1 off off
1 0 enabled off Digital input, wakeup from stop supported
1 1 enabled off
Table 2-49. PIM Interrupt Sources
Module Interrupt Sources Local Enable
XIRQ None
IRQ IRQCR[IRQEN]
Port P pin interrupt PIEP[PIEP5-PIEP0]
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
96 Freescale Semiconductor
2.4.4.1 XIRQ, IRQ Interrupts
The XIRQ pin allows requesting non-maskable interrupts after reset initialization. During reset, the X bit
in the condition code register is set and any interrupts are masked until software enables them.
The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To
enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register.
The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN]
is cleared while an interrupt is pending, the request will deassert.
Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not
provided on these pins.
2.4.4.2 Pin Interrupts and Wakeup
Ports P, L and AD offer pin interrupt capability. The related interrupt enable (PIE) as well as the sensitivity
to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share
the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag (PIF) and its corresponding port interrupt
enable (PIE) are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop
or wait mode.
A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is
detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active
level. Else the sampling logic is restarted.
In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of tPULSE
<n
P_MASK/fbus are assuredly filtered out while pulses with a duration of tPULSE >n
P_PASS/fbus guarantee
a pin interrupt.
In stop mode the clock is generated by an RC-oscillator. The minimum pulse length varies over process
conditions, temperature and voltage (Figure 2-47). Pulses with a duration of tPULSE < tP_MASK are
assuredly filtered out while pulses with a duration of tPULSE > tP_PASS guarantee a wakeup event.
Please refer to the appendix table “Pin Interrupt Characteristics” for pulse length limits.
To maximize current saving the RC oscillator is active only if the following condition is true on any
individual pin:
Sample count <= 4 (at active or passive level) and interrupt enabled (PIE[x]=1) and interrupt flag not set
(PIF[x]=0).
Port L pin interrupt PIEL[PIEL3-PIEL0]
Port AD pin interrupt PIE1AD[PIE1AD5-PIE1AD0]
Port P over-current PIEP[OCIE]
Table 2-49. PIM Interrupt Sources
Module Interrupt Sources Local Enable
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 97
Figure 2-47. Interrupt Glitch Filter (here: active low level selected)
2.4.4.3 Over-Current Interrupt
In case of an over-current condition on PP2 (see Section 2.5.3, “Over-Current Protection on EVDD”) the
over-current interrupt flag PIFP[OCIF] asserts. This flag generates an interrupt if the enable bit
PIEP[OCIE] is set.
An asserted flag immediately forces the output pin low to protect the device. The flag must be cleared to
re-enable the driver.
2.5 Initialization and Application Information
2.5.1 Port Data and Data Direction Register writes
It is not recommended to write PORT[x]/PT[x] and DDR[x] in a word access. When changing the register
pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port
data register before enabling the outputs.
2.5.2 ADC External Triggers ETRIG1-0
The ADC external trigger inputs ETRIG1-0 allow the synchronization of conversions to external trigger
events if selected as trigger source (for details refer to ATDCTL1[ETRIGSEL] and ATDCTL1[ETRIGCH]
configuration bits in ADC section). These signals are related to PWM channels 5-4 to support periodic
trigger applications with the ADC. Other pin functions can also be used as triggers.
If a PWM channel is routed to an alternative pin, the ETRIG input function will follow the relocation
accordingly.
If the related PWM channel is enabled and not routed for internal use, the PWM signal as seen on the pin
will drive the ETRIG input. Else the ETRIG function will be triggered by other functions on the pin
including general-purpose input.
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set uncertain
tPULSE(min) tPULSE(max)
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
98 Freescale Semiconductor
2.5.3 Over-Current Protection on EVDD
Pin PP2 can be used as general-purpose I/O or due to its increased current capability in output mode as a
switchable external power supply pin (EVDD) for external devices like Hall sensors. An over-current
monitor is implemented to protect the controller from short circuits or excess currents on the output which
can only arise if the pin is configured for full drive. Although the full drive current is available on the high
and low side, the protection is only available if the pin is driven high (PTP[PTP2]=1). This is also true if
using the pin with the PWM.
To power up the over-current monitor set PIMMISC[OCPE]=1.
In stop mode the over-current monitor is disabled for power saving. The increased current capability
cannot be maintained to supply the external device. Therefore when using the pin as power supply the
external load must be powered down prior to entering stop mode by setting PTP[PTP2]=0.
An over-current condition is detected if the output current level exceeds the threshold IOCD in run mode.
The output driver is immediately forced low and the over-current interrupt flag PIFP[OCIF] asserts. Refer
to Section 2.4.4.3, “Over-Current Interrupt”.
2.5.4 Open Input Detection on HVI Pins
The connection of an external pull device on any port L high-voltage input can be validated by using the
built-in pull functionality of the HVI pins. Depending on the application type an external pulldown circuit
can be detected with the internal pullup device whereas an external pullup circuit can be detected with the
internal pulldown device which is part of the input voltage divider.
Note that the following procedures make use of a function that overrides the automatic disable mechanism
of the digital input buffers when using the inputs in analog mode. Make sure to switch off the override
function when using an input in analog mode after the check has been completed.
External pulldown device (Figure 2-48):
1. Enable analog function on HVIx in non-direct mode (PTAL[PTAENL]=1, PTAL[PTADIRL]=0,
PTAL[PTAL1:PTAL0]=x, where x is 0, 1, 2, or 3)
2. Select internal pullup device on selected HVI (PTAL[PTPSL]=1)
3. Enable function to force input buffer active on selected HVI in analog mode (PTAL[PTTEL]=1)
4. Verify PTILx=0 for a connected external pulldown device; read PTILx=1 for an open input
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 99
Figure 2-48. Digital Input Read with Pullup Enabled
External pullup device (Figure 2-49):
1. Enable analog function on HVIx in non-direct mode (PTAL[PTAENL]=1, PTAL[PTADIRL]=0,
PTAL[PTAL1:PTAL0]=x, where x is 0, 1, 2, or 3)
2. Select internal pulldown device on selected HVI (PTAL[PTPSL]=0)
3. Enable function to force input buffer active on selected HVI in analog mode (PTAL[PTTEL]=1)
4. Verify PTILx=1 for a connected external pullup device; read PTILx=0 for an open input
Figure 2-49. Digital Input Read with Pulldown Enabled
HVIx
40K
500K
VDDX
Digital in
110K / 550K
min. 1/10 * V
DDX
10K
PIRL=0 / PIRL=1
HV Supply
HVIx
40K
610K / 1050K
Digital in
max. 10/11 * V
HVI
(PIRL=0)
PIRL=0 / PIRL=1
max. 21/22 * V
HVI
(PIRL=1)
10K
HV Supply
Port Integration Module (S12VRPIMV2)
MC9S12VR Family Reference Manual, Rev. 2.8
100 Freescale Semiconductor
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 103
Chapter 3
S12G Memory Map Controller (S12GMMCV1)
Table 3-1. Revision History Table
3.1 Introduction
The S12GMMC module controls the access to all internal memories and peripherals for the CPU12 and
S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip
ressources. Figure 3-1 shows a block diagram of the S12GMMC module.
3.1.1 Glossary
3.1.2 Overview
The S12GMMC connects the CPU12’s and the S12SBDM’s bus interfaces to the MCU’s on-chip resources
(memories and peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps.
Furthermore, the S12GMMC is responsible for constraining memory accesses on secured devices and for
selecting the MCU’s functional mode.
Rev. No.
(Item No.)
Date
(Submitted By)
Sections
Affected Substantial Change(s)
01.00 2-Jun 2009 Changed the RAM size of the S12GN32 from 1K to 2K
01.01 3-Aug 2009 Changed the RAM size of the S12GN16 from 0.5K to 1K
01.02 20-May 2010 Updates for S12VR48 and S12VR64
Table 3-2. Glossary Of Terms
Term Definition
Local Addresses Address within the CPU12’s Local Address Map (Figure 3-11)
Global Address Address within the Global Address Map (Figure 3-11)
Aligned Bus Access Bus access to an even address.
Misaligned Bus Access Bus access to an odd address.
NS Normal Single-Chip Mode
SS Special Single-Chip Mode
Unimplemented Address Ranges Address ranges which are not mapped to any on-chip resource.
NVM Non-volatile Memory; Flash or EEPROM
IFR NVM Information Row. Refer to FTMRG Block Guide
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
104 Freescale Semiconductor
3.1.3 Features
The main features of this block are:
• Paging capability to support a global 256 KByte memory address space
• Bus arbitration between the masters CPU12, S12SBDM to different resources.
• MCU operation mode control
• MCU security control
• Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address
which does not belong to any of the on-chip modules) in single-chip modes
3.1.4 Modes of Operation
The S12GMMC selects the MCU’s functional mode. It also determines the devices behavior in secured
and unsecured state.
3.1.4.1 Functional Modes
Two functional modes are implemented on devices of the S12VR product family:
• Normal Single Chip (NS)
The mode used for running applications.
• Special Single Chip Mode (SS)
A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals
may also provide special debug features in this mode.
3.1.4.2 Security
S12VR devices can be secured to prohibit external access to the on-chip flash. The S12GMMC module
determines the access permissions to the on-chip memories in secured and unsecured state.
3.1.5 Block Diagram
Figure 3-1 shows a block diagram of the S12GMMC.
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 105
Figure 3-1. S12GMMC Block Diagram
3.2 External Signal Description
The S12GMMC uses two external pins to determine the devices operating mode: RESET and MODC
(Figure 3-3) See Device User Guide (DUG) for the mapping of these signals to device pins.
3.3 Memory Map and Registers
3.3.1 Module Memory Map
A summary of the registers associated with the S12GMMC block is shown in Figure 3-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Table 3-3. External System Pins Associated With S12GMMC
Pin Name Pin Functions Description
RESET
(See Section
Device Overview)
RESET
The RESET pin is used the select the MCU’s operating mode.
MODC
(See Section
Device Overview)
MODC The MODC pin is captured at the rising edge of the RESET pin. The captured
value determines the MCU’s operating mode.
CPU
BDM
Target Bus Controller
DBG
MMC
Address Decoder & Priority
Peripherals
FlashEEPROM RAM
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
106 Freescale Semiconductor
3.3.2 Register Descriptions
This section consists of the S12GMMC control register descriptions in address order.
3.3.2.1 Mode Register (MODE)
Address Register
Name Bit 7 65432 1Bit 0
0x000A Reserved R 000000 0 0
W
0x000B MODE R MODC 00000 0 0
W
0x0010 Reserved R 000000 0 0
W
0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8
W
0x0012 Reserved R 000000 0 0
W
0x0013 MMCCTL1 R 000000 0
NVMRES
W
0x0014 Reserved R 000000 0 0
W
0x0015 PPAGE R 0000
PIX3 PIX2 PIX1 PIX0
W
0x0016-
0x0017
Reserved R 000000 0 0
W
= Unimplemented or Reserved
Figure 3-2. MMC Register Summary
Address: 0x000B
76543210
RMODC 0000000
W
Reset MODC10000000
1. External signal (see Table 3-3).
= Unimplemented or Reserved
Figure 3-3. Mode Register (MODE)
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 107
Read: Anytime.
Write: Only if a transition is allowed (see Figure 3-4).
The MODC bit of the MODE register is used to select the MCU’s operating mode.
Figure 3-4. Mode Transition Diagram when MCU is Unsecured
3.3.2.2 Direct Page Register (DIRECT)
Read: Anytime
Write: anytime in special SS, write-once in NS.
This register determines the position of the 256 Byte direct page within the memory map.It is valid for both
global and local mapping scheme.
Table 3-4. MODE Field Descriptions
Field Description
7
MODC
Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external
mode pin MODC determines the operating mode during RESET low (active). The state of the pin is registered
into the respective register bit after the RESET signal goes inactive (see Figure 3-4).
Write restrictions exist to disallow transitions between certain modes. Figure 3-4 illustrates all allowed mode
changes. Attempting non authorized transitions will not change the MODE bit, but it will block further writes to
the register bit except in special modes.
Write accesses to the MODE register are blocked when the device is secured.
Address: 0x0011
76543210
RDP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8
W
Reset 00000000
Figure 3-5. Direct Register (DIRECT)
Normal
Single-Chip
1
Special
Single-Chip
0
(SS)
RESET
(NS)
1
01
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
108 Freescale Semiconductor
Figure 3-6. DIRECT Address Mapping
Example 3-1. This example demonstrates usage of the Direct Addressing Mode
MOVB #$04,DIRECT ;Set DIRECT register to 0x04. From this point on, all memory
;accesses using direct addressing mode will be in the local
;address range from 0x0400 to 0x04FF.
LDY <$12 ;Load the Y index register from 0x0412 (direct access).
3.3.2.3 MMC Control Register (MMCCTL1)
Read: Anytime.
Write: Anytime.
The NVMRES bit maps 16k of internal NVM resources (see Section FTMRG) to the global address space
0x04000 to 0x07FFF.
Table 3-5. DIRECT Field Descriptions
Field Description
7–0
DP[15:8]
Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct
addressing mode. These register bits form bits [15:8] of the local address (see Figure 3-6).
Address: 0x0013
76543210
R0000000
NVMRES
W
Reset 00000000
= Unimplemented or Reserved
Figure 3-7. MMC Control Register (MMCCTL1)
Table 3-6. MODE Field Descriptions
Field Description
0
NVMRES
Map internal NVM resources into the global memory map
Write: Anytime
This bit maps internal NVM resources into the global address space.
0 Program flash is mapped to the global address range from 0x04000 to 0x07FFF.
1 NVM resources are mapped to the global address range from 0x04000 to 0x07FFF.
Bit15 Bit0
Bit7
CPU Address [15:0]
Bit8
DP [15:8]
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 109
3.3.2.4 Program Page Index Register (PPAGE)
Read: Anytime
Write: Anytime
The four index bits of the PPAGE register select a 16K page in the global memory map (Figure 3-11). The
selected 16K page is mapped into the paging window ranging from local address 0x8000 to 0xBFFF.
Figure 3-9 illustrates the translation from local to global addresses for accesses to the paging window. The
CPU has special access to read and write this register directly during execution of CALL and RTC
instructions.
Figure 3-9. PPAGE Address Mapping
NOTE
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
The fixed 16KB page from 0x0000 to 0x3FFF is the page number 0xC. Parts of this page are covered by
Registers, EEPROM and RAM space. See SoC Guide for details.
The fixed 16KB page from 0x4000–0x7FFF is the page number 0xD.
Address: 0x0015
76543210
R0000
PIX3 PIX2 PIX1 PIX0
W
Reset 00001110
Figure 3-8. Program Page Index Register (PPAGE)
Table 3-7. PPAGE Field Descriptions
Field Description
3–0
PIX[3:0]
Program Page Index Bits 3–0 — These page index bits are used to select which of the 256 flash array pages
is to be accessed in the Program Page Window.
Bit14 Bit0
Address [13:0]
PPAGE Register [3:0]
Global Address [17:0]
Bit13
Bit17
Address: CPU Local Address
or BDM Local Address
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
110 Freescale Semiconductor
The reset value of 0xE ensures that there is linear Flash space available between addresses 0x0000 and
0xFFFF out of reset.
The fixed 16KB page from 0xC000-0xFFFF is the page number 0xF.
3.4 Functional Description
The S12GMMC block performs several basic functions of the S12VR sub-system operation: MCU
operation modes, priority control, address mapping, select signal generation and access limitations for the
system. Each aspect is described in the following subsections.
3.4.1 MCU Operating Modes
• Normal single chip mode
This is the operation mode for running application code. There is no external bus in this mode.
• Special single chip mode
This mode is generally used for debugging operation, boot-strapping or security related operations.
The active background debug mode is in control of the CPU code execution and the BDM firmware
is waiting for serial commands sent through the BKGD pin.
3.4.2 Memory Map Scheme
3.4.2.1 CPU and BDM Memory Map Scheme
The BDM firmware lookup tables and BDM register memory locations share addresses with other
modules; however they are not visible in the memory map during user’s code execution. The BDM
memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish
between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block
Guide for further details).
When the MCU enters active BDM mode, the BDM firmware lookup tables and the BDM registers
become visible in the local memory map in the range 0xFF00-0xFFFF (global address 0x3_FF00 -
0x3_FFFF) and the CPU begins execution of firmware commands or the BDM begins execution of
hardware commands. The resources which share memory space with the BDM module will not be visible
in the memory map during active BDM mode.
Please note that after the MCU enters active BDM mode the BDM firmware lookup tables and the BDM
registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value
of 0x0F.
3.4.2.1.1 Expansion of the Local Address Map
Expansion of the CPU Local Address Map
The program page index register in S12GMMC allows accessing up to 256KB of address space in the
global memory map by using the four index bits (PPAGE[3:0]) to page 16x16 KB blocks into the program
page window located from address 0x8000 to address 0xBFFF in the local CPU memory map.
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 111
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE
register can be read or written by normal memory accesses as well as by the CALL and RTC instructions.
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the
64KB local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is
certain that the PPAGE register will be set to the appropriate value when the service routine is called.
However an interrupt service routine can call other routines that are in paged memory. The upper 16KB
block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that all reset and
interrupt vectors point to locations in this area or to the other unmapped pages sections of the local CPU
memory map.
Expansion of the BDM Local Address Map
PPAGE and BDMPPR register is also used for the expansion of the BDM local address to the global
address. These registers can be read and written by the BDM.
The BDM expansion scheme is the same as the CPU expansion scheme.
The four BDMPPR Program Page index bits allow access to the full 256KB address map that can be
accessed with 18 address bits.
The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and,
in the case the CPU is executing a firmware command which uses CPU instructions, or by a BDM
hardware commands. See the BDM Block Guide for further details. (see Figure 3-10).
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
112 Freescale Semiconductor
Figure 3-10. Expansion of BDM local address map
BDM HARDWARE COMMAND
BDM FIRMWARE COMMAND
Bit14 Bit0
BDM Local Address [13:0]
BDMPPR Register [3:0]
Global Address [17:0]
Bit13
Bit17
Bit14 Bit0
CPU Local Address [13:0]
BDMPPR Register [3:0]
Global Address [17:0]
Bit13
Bit17
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 113
Figure 3-11. Local to Global Address Mapping
Paging Window
0x3_FFFF
Local CPU and BDM
Memory Map Global Memory Map
0xFFFF
0xC000
0x0_0400
0x0_0000
0x3_C000
0x0000
0x8000
0x0400
0x4000 0x0_4000
Paging Window
Flash
Space
Flash
Space
RAM
RAM
Unimplemented
Unimplemented
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Register Space
Register Space
Internal
NVM
Resources
Internal
NVM
Resources
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
Flash Space
EEPROM
EEPROM EEPROM
EEPROM
Page 0x1
Page 0x1
Page 0xF
Page 0xF
Page 0xD
Page 0xD
Register Space
Register Space
Page 0xC
Page 0xC
Page 0xE
Page 0xE
Page 0xF
Page 0xF
Page 0xD
Page 0xD
Page 0xC
Page 0xC
NVMRES=0
NVMRES=0 NVMRES=1
NVMRES=1
Flash Space
Flash Space
Page 0x2
Page 0x2
0x3_0000
0x3_4000
0x3_8000
0x0_8000
RAM
RAM
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
114 Freescale Semiconductor
3.4.3 Unimplemented and Reserved Address Ranges
The S12GMMC is capable of mapping up 64K of flash, 512 bytes of EEPROM and 2K of RAM into the
global memory map{statement}. Smaller devices of theS12VR-family do not utilize all of the available
address space. Address ranges which are not associated with one of the on-chip memories fall into two
categories: Unimplemented addresses and reserved addresses.
Unimplemented addresses are not mapped to any of the on-chip memories. The S12GMMC is aware that
accesses to these address location have no destination and triggers a system reset (illegal address reset)
whenever they are attempted by the CPU. The BDM is not able to trigger illegal address resets.
Reserved addresses are associated with a memory block on the device, even though the memory block does
not contain the resources to fill the address space. The S12GMMC is not aware that the associated memory
does not physically exist. It does not trigger an illegal address reset when accesses to reserved locations
are attempted.
Table 3-9 shows the global address ranges of all members of the S12VR-family.
3.4.4 Prioritization of Memory Accesses
On S12VR devices, the CPU and the BDM are not able to access the memory in parallel. An arbitration
occurs whenever both modules attempt a memory access at the same time. CPU accesses are handled with
Table 3-9. Global Address Ranges
S12VR48 S12VR64
0x00000-
0x003FF
Register Space
0x00400-
0x005FF
0.5k
EEPROM
0x00800-
0x037FF
Unimplemented
0x03800-
0x03FFF
RAM
2k
0x04000-
0x07FFF
(NVMRES
=1)
Internal NVM Resources
0x04000-
0x07FFF
(NVMRES
=0)
Unimplemented
0x08000-
0x30000
0x30000-
0x33FFF
Reserved Flash
0x34000-
0x3FFFF 48k 64k
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 115
higher priority than BDM accesses unless the BDM module has been stalled for more then 128 bus cycles.
In this case the pending BDM access will be processed immediately.
3.4.5 Interrupts
The S12GMMC does not generate any interrupts.
S12G Memory Map Controller (S12GMMCV1)
MC9S12VR Family Reference Manual, Rev. 2.8
116 Freescale Semiconductor
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 117
Chapter 4
S12 Clock, Reset and Power Management Unit
(S12CPMU_UHV)
Revision History
4.1 Introduction
This specification describes the function of the Clock, Reset and Power Management Unit
(S12CPMU_UHV).
• The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock
source. It is designed for optimal start-up margin with typical crystal oscillators.
• The Voltage regulator (VREGAUTO) operates from the range 6V to 18V. It provides all the
required chip internal voltages and voltage monitors.
• The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
• The Internal Reference Clock (IRC1M) provides a 1MHz internal clock.
Rev. No.
(Item No)
Date
(Submitted By) Sections Affected Substantial Change(s)
V01.00 22.Dec 10 Initial Version.
V02.00 08. Apr 11
4.1.2.3/4-121
4.1.2.4/4-122
4.1.3/4-123
4.3.1/4-127
4.3.2.6/4-134
4.3.2.18/4-153
4.4.3/4-164
4.4.4/4-165
4.5.2.2/4-170
4.7.2/4-174
Table 4-5
Table 4-14
Table 4-31
Figure 4-1
Figure 4-3
Figure 4-9
Added bit CSAD (COP in Stop Mode ACLK Disable) in register
CPMUCLKS. This bit allows halting the COP in Stop Mode (Full or
Pseudo) when ACLK is the COP clock source. Description of Stop
Modes, Block Diagram, CPMUCLKS register and COP Watchdog
feature are updated.
V02.01 21.June 12 Improved signal descriptions of VSUP, VDDA/VSSA, VDDX/VSSX
concerning recommended decoupling capacitors.
V02.02 30.July 12 Figure “Startup of clock system after Reset”: Corrected PLL clock
frequencies to 12.5Mhz and 25MHz (instead of 16MHz and
32Mhz before)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
118 Freescale Semiconductor
4.1.1 Features
The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
• Supports crystals or resonators from 4MHz to 16MHz.
• High noise immunity due to input hysteresis and spike filtering.
• Low RF emissions with peak-to-peak swing limited dynamically
• Transconductance (gm) sized for optimum start-up margin for typical crystals
• Dynamic gain control eliminates the need for external current limiting resistor
• Integrated resistor eliminates the need for external bias resistor
• Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits
power
The Voltage Regulator (VREGAUTO) has the following features:
• Input voltage range from 6 to 18V
• Low-voltage detect (LVD) with low-voltage interrupt (LVI)
• Power-on reset (POR)
• Low-voltage reset (LVR)
• On Chip Temperature Sensor and Bandgap Voltage measurement via internal ATD channel.
• Voltage Regulator providing Full Performance Mode (FPM) and Reduced Performance Mode
(RPM)
The Phase Locked Loop (PLL) has the following features:
• highly accurate and phase locked frequency multiplier
• Configurable internal filter for best stability and lock time
• Frequency modulation for defined jitter and reduced emission
• Automatic frequency lock detector
• Interrupt request on entry or exit from locked condition
• Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based.
• PLL stability is sufficient for LIN communication in slave mode, even if using IRC1M as reference
clock
The Internal Reference Clock (IRC1M) has the following features:
• Frequency trimming
(A factory trim value for 1MHz is loaded from Flash Memory into the IRCTRIM register after
reset, which can be overwritten by application if required)
• Temperature Coefficient (TC) trimming.
(A factory trim value is loaded from Flash Memory into the IRCTRIM register to turn off TC
trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM
register).
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 119
Other features of the S12CPMU_UHV include
• Clock monitor to detect loss of crystal
• Autonomous periodical interrupt (API)
• Bus Clock Generator
— Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock
— PLLCLK divider to adjust system speed
• System Reset generation from the following possible sources:
— Power-on reset (POR)
— Low-voltage reset (LVR)
— Illegal address access
— COP time-out
— Loss of oscillation (clock monitor fail)
— External pin RESET
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
120 Freescale Semiconductor
4.1.2 Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12CPMU_UHV.
4.1.2.1 Run Mode
The voltage regulator is in Full Performance Mode (FPM).
NOTE
The voltage regulator is active, providing the nominal supply voltages with
full current sourcing capability (see also Appendix for VREG electrical
parameters). The features ACLK clock source, Low Voltage Interrupt (LVI),
Low Voltage Reset (LVR) and Power-On Reset (POR) are available.
The Phase Locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
The API is available.
• PLL Engaged Internal (PEI)
— This is the default mode after System Reset and Power-On Reset.
— The Bus Clock is based on the PLLCLK.
— After reset the PLL is configured for 50MHz VCOCLK operation
Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 12.5MHz and Bus Clock is
6.25MHz.
The PLL can be re-configured for other bus frequencies.
— The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M
• PLL Engaged External (PEE)
— The Bus Clock is based on the PLLCLK.
— This mode can be entered from default mode PEI by performing the following steps:
– Configure the PLL for desired bus frequency.
– Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if
necessary.
– Enable the external oscillator (OSCE bit)
– Wait for oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1)
• PLL Bypassed External (PBE)
— The Bus Clock is based on the Oscillator Clock (OSCCLK).
— The PLLCLK is always on to qualify the external oscillator clock. Therefore it is necessary to
make sure a valid PLL configuration is used for the selected oscillator frequency.
— This mode can be entered from default mode PEI by performing the following steps:
– Make sure the PLL configuration is valid for the selected oscillator frequency.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 121
– Enable the external oscillator (OSCE bit)
– Wait for oscillator to start up (UPOSC=1)
– Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0).
— The PLLCLK is on and used to qualify the external oscillator clock.
4.1.2.2 Wait Mode
For S12CPMU_UHV Wait Mode is the same as Run Mode.
4.1.2.3 Stop Mode
This mode is entered by executing the CPU STOP instruction.
The voltage regulator is in Reduced Performance Mode (RPM).
NOTE
The voltage regulator output voltage may degrade to a lower value than in
Full Performance Mode (FPM), additionally the current sourcing capability
is substantially reduced (see also Appendix for VREG electrical
parameters). Only clock source ACLK is available and the Power On Reset
(POR) circuitry is functional. The Low Voltage Interrupt (LVI) and Low
Voltage Reset (LVR) are disabled.
The API is available.
The Phase Locked Loop (PLL) is off.
The Internal Reference Clock (IRC1M) is off.
Core Clock, Bus Clock and BDM Clock are stopped.
Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full
Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1). In addition, the
behavior of the COP in each mode will change based on the clocking method selected by
COPOSCSEL[1:0].
•Full Stop Mode (PSTP = 0 or OSCE=0)
External oscillator (XOSCLCP) is disabled.
— If COPOSCSEL1=0:
The COP and RTI counters halt during Full Stop Mode.
After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK
(PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0).
— If COPOSCSEL1=1:
The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During
Full Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active)
depending on the setting of bit CSAD. When bit CSAD is set the ACLK clock source for the
COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
122 Freescale Semiconductor
Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time occurs when
entering or exiting (Full, Pseudo) Stop Mode. When bit CSAD is clear the ACLK clock source
is on for the COP during Full Stop Mode and COP is operating.
During Full Stop Mode the RTI counter halts.
After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK
(PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0,
RTIOSCSEL=0).
•Pseudo Stop Mode (PSTP = 1 and OSCE=1)
External oscillator (XOSCLCP) continues to run.
— If COPOSCSEL1=0:
If the respective enable bits are set (PCE=1 and PRE=1) the COP and RTI will continue to run
with a clock derived from the oscillator clock.
The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.
— If COPOSCSEL1=1:
If the respective enable bit for the RTI is set (PRE=1) the RTI will continue to run with a clock
derived from the oscillator clock.
The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During
Pseudo Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active)
depending on the setting of bit CSAD. When bit CSAD is set the ACLK for the COP is stopped
during Pseudo Stop Mode and COP continues to operate after exit from Pseudo Stop Mode.
For this COP configuration (ACLK clock source, CSAD set) a latency time occurs when
entering or exiting (Pseudo, Full) Stop Mode. When bit CSAD is clear the ACLK clock source
is on for the COP during Pseudo Stop Mode and COP is operating.
The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.
NOTE
When starting up the external oscillator (either by programming OSCE bit
to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software
must wait for a minimum time equivalent to the startup-time of the external
oscillator tUPOSC before entering Pseudo Stop Mode.
4.1.2.4 Freeze Mode (BDM active)
For S12CPMU_UHV Freeze Mode is the same as Run Mode except for RTI and COP which can be
stopped in Active BDM Mode with the RSBCK bit in the CPMUCOP register. Additionally the COP can
be forced to the maximum time-out period in Active BDM Mode. For details please see also the RSBCK
and CR[2:0] bit description field of Table 4-12 in Section 4.3.2.9, “S12CPMU_UHV COP Control
Register (CPMUCOP)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 123
4.1.3 S12CPMU_UHV Block Diagram
Figure 4-1. Block diagram of S12CPMU_UHV
S12CPMU_UHV
EXTAL
XTAL
System Reset
Power-On Detect
PLL Lock Interrupt
MMC
Illegal Address Access
Loop
Reference
Divider
Voltage
VSUP
Internal
Reset
Generator
Divide by
Phase
Post
Divider
1,2,.32
VCOCLK
LOCKIE
IRCTRIM[9:0]
SYNDIV[5:0]
LOCK
REFDIV[3:0]
2*(SYNDIV+1)
Pierce
Oscillator
4MHz-16MHz
OSCE
ILAF
PORF
divide
by 2
ECLK
POSTDIV[4:0]
Power-On Reset
Controlled
locked
Loop with
internal
Filter (PLL)
REFCLK
FBCLK
REFFRQ[1:0]
VCOFRQ[1:0]
Lock
detect
Regulator
6V to 18V
Autonomous
Periodic
Interrupt (API)
API Interrupt
VSS
PLLSEL
VSSX
VDDA
VDDX
Low Voltage Detect VDDX
LVRF
PLLCLK
Reference
divide
by 8
BDM Clock
Clock
(IRC1M)
Clock
Monitor
monitor fail
Real Time
Interrupt (RTI)
RTI Interrupt
PSTP
CPMURTI
Oscillator status Interrupt
(XOSCLCP)
High
Temperature
Sense
HT Interrupt
Low Voltage Interrupt
APICLK
RTICLK
IRCCLK
OSCCLK
RTIOSCSEL
COP time-out
PRE
UPOSC=0 sets PLLSEL bit
API_EXTCLK
RC
Osc.
VDD, VDDF
(core supplies)
UPOSC
RESET OSCIE
APIE
RTIE
HTDS HTIE
LVDS LVIE
Low Voltage Detect VDDA
OSCCLK
divide
by 4
Bus Clock
VSSA
ADC
vsup
monitor
(VREGAUTO)
ECLK2X
(Core Clock)
(Bus Clock)
COP time-out
COP
Watchdog
CPMUCOP
COPCLK
IRCCLK
OSCCLK
COPOSCSEL0
to Reset
Generator
PCE
UPOSC
UPOSC=0 clears
ACLK
COPOSCSEL1
OSCCLK_LCP
CSAD
divide
by 2
ACLK
divide
by 2
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
124 Freescale Semiconductor
Figure 4-2 shows a block diagram of the XOSCLCP.
Figure 4-2. XOSCLCP Block Diagram
EXTAL XTAL
Gain Control
VDD = 1.8 V
Rf
OSCCLK_LCP
Peak
Detector
VSS
VSS VSS
C1 C2
Quartz Crystals
Ceramic Resonators
or
Clock
Monitor
monitor fail
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 125
4.2 Signal Description
This section lists and describes the signals that connect off chip as well as internal supply nodes and special
signals.
4.2.1 RESET
Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
4.2.2 EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is
the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. If
XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If
OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 kΩ and the XTAL
pin is pulled down by an internal resistor of approximately 700 kΩ.
NOTE
Freescale recommends an evaluation of the application board and chosen
resonator or crystal by the resonator or crystal supplier.
The loop controlled circuit (XOSCLCP) is not suited for overtone
resonators and crystals.
4.2.3 VSUP — Regulator Power Input Pin
Pin VSUP is the power input of VREGAUTO. All currents sourced into the regulator loads flow through
this pin.
An appropriate reverse battery protection network consisting of a diode and capacitors is recommended.
4.2.4 VDDA, VSSA — Regulator Reference Supply Pins
Pins VDDA and VSSA,are used to supply the analog parts of the regulator.
Internal precision reference circuits are supplied from these signals.
A local decoupling capacitor between VDDA and VSSA according to the electrical specification is
required. Additionally a bigger tank capacitor is required on the 5 Volt supply network as well to ensure
Voltage regulator stability.
VDDA has to be connected externally to VDDX.
4.2.5 VDDX, VSSX— Pad Supply Pins
This supply domain is monitored by the Low Voltage Reset circuit.
A local decoupling capacitor between VDDX and VSSX according to the electrical specification is
required.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
126 Freescale Semiconductor
VDDX has to be connected externally to VDDA.
4.2.6 VSS— Ground Pin
VSS is the ground pin for the core logic. On the board VSSX, VSSA and VSS need to be connected
together to the application ground.
4.2.7 API_EXTCLK — API external clock output pin
This pin provides the signal selected via APIES and is enabled with APIEA bit. See the device
specification if this clock output is available on this device and to which pin it might be connects.
4.2.8 VDD— Internal Regulator Output Supply (Core Logic)
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for
the core logic.
This supply domain is monitored by the Low Voltage Reset circuit.
4.2.9 VDDF— Internal Regulator Output Supply (NVM Logic)
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for
the NVM logic.
This supply domain is monitored by the Low Voltage Reset circuit.
4.2.10 TEMPSENSE — Internal Temperature Sensor Output Voltage
Depending on the VSEL setting either the voltage level generated by the temperature sensor or the VREG
bandgap voltage is driven to a special channel input of the ATD Converter. See device level specification
for connectivity of ATD special channels.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 127
4.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU_UHV.
4.3.1 Module Memory Map
The S12CPMU_UHV registers are shown in Figure 4-3.
Addres
sName Bit 7 6 5 4 3 2 1 Bit 0
0x0034 CPMU
SYNR
RVCOFRQ[1:0] SYNDIV[5:0]
W
0x0035 CPMU
REFDIV
RREFFRQ[1:0] 00 REFDIV[3:0]
W
0x0036 CPMU
POSTDIV
R0 0 0 POSTDIV[4:0]
W
0x0037 CPMUFLG RRTIF PORF LVRF LOCKIF LOCK ILAF OSCIF UPOSC
W
0x0038 CPMUINT RRTIE 00
LOCKIE 00
OSCIE 0
W
0x0039 CPMUCLKS RPLLSEL PSTP CSAD COP
OSCSEL1 PRE PCE RTI
OSCSEL
COP
OSCSEL0
W
0x003A CPMUPLL R0 0 FM1 FM0 00 0 0
W
0x003B CPMURTI RRTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
0x003C CPMUCOP RWCOP RSBCK 000
CR2 CR1 CR0
W WRTMASK
0x003D RESERVED
CPMUTEST0
R0 0 0 000 0 0
W
0x003E RESERVED
CPMUTEST1
R0 0 0 000 0 0
W
0x003F CPMU
ARMCOP
R0 0 0 000 0 0
W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x02F0 CPMU
HTCTL
R0 0 VSEL 0HTE HTDS HTIE HTIF
W
0x02F1 CPMU
LVCTL
R 0 0 0 0 0 LVDS LVIE LVIF
W
0x02F2 CPMU
APICTL
RAPICLK 00
APIES APIEA APIFE APIE APIF
W
= Unimplemented or Reserved
Figure 4-3. CPMU Register Summary
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
128 Freescale Semiconductor
0x02F3 CPMUACLKTR RACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 00
W
0x02F4 CPMUAPIRH RAPIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8
W
0x02F5 CPMUAPIRL RAPIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0
W
0x02F6 RESERVED
CPMUTEST3
R0 0 0 000 0 0
W
0x02F7 CPMUHTTR RHTOE 000
HTTR3 HTTR2 HTTR1 HTTR0
W
0x02F8 CPMU
IRCTRIMH
RTCTRIM[4:0] 0IRCTRIM[9:8]
W
0x02F9 CPMU
IRCTRIML
RIRCTRIM[7:0]
W
0x02FA CPMUOSC ROSCE Reserved 0Reserved
W
0x02FB CPMUPROT R0 0 0 000 0
PROT
W
0x02FC RESERVED
CPMUTEST2
R0 0 0 000 0 0
W
Addres
sName Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 4-3. CPMU Register Summary
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 129
4.3.2 Register Descriptions
This section describes all the S12CPMU_UHV registers and their individual bits.
Address order is as listed in Figure 4-3
4.3.2.1 S12CPMU_UHV Synthesizer Register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency
range.
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Writing to this register clears the LOCK and UPOSC status bits.
NOTE
fVCO must be within the specified VCO frequency lock range. Bus
frequency fbus must not exceed the specified maximum.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct
PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 4-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional
PLL (no locking and/or insufficient stability).
0x0034
76543210
R
VCOFRQ[1:0] SYNDIV[5:0]
W
Reset 01011000
Figure 4-4. S12CPMU_UHV Synthesizer Register (CPMUSYNR)
Table 4-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges VCOFRQ[1:0]
32MHz <= fVCO<= 48MHz 00
48MHz < fVCO<= 50MHz 01
Reserved 10
Reserved 11
fVCO 2f
REF
×SYNDIV 1+()×=
If PLL has locked (LOCK=1)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
130 Freescale Semiconductor
4.3.2.2 S12CPMU_UHV Reference Divider Register (CPMUREFDIV)
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external oscillator as reference.
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Table 4-2.
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= fREF <=
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
0x0035
76543210
R
REFFRQ[1:0]
00
REFDIV[3:0]
W
Reset 00001111
Figure 4-5. S12CPMU_UHV Reference Divider Register (CPMUREFDIV)
Table 4-2. Reference Clock Frequency Selection if OSC_LCP is enabled
REFCLK Frequency Ranges
(OSCE=1) REFFRQ[1:0]
1MHz <= fREF <= 2MHz 00
2MHz < fREF <= 6MHz 01
6MHz < fREF <= 12MHz 10
fREF >12MHz 11
fREF
fOSC
REFDIV 1+()
------------------------------------
=
If XOSCLCP is enabled (OSCE=1)
If XOSCLCP is disabled (OSCE=0) fREF fIRC1M
=
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 131
4.3.2.3 S12CPMU_UHV Post Divider Register (CPMUPOSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Read: Anytime
Write: If PLLSEL=1 write anytime, else write has no effect
4.3.2.4 S12CPMU_UHV Flags Register (CPMUFLG)
This register provides S12CPMU_UHV status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
0x0036
76543210
R000
POSTDIV[4:0]
W
Reset 00000011
= Unimplemented or Reserved
Figure 4-6. S12CPMU_UHV Post Divider Register (CPMUPOSTDIV)
0x0037
76543210
R
RTIF PORF LVRF LOCKIF
LOCK
ILAF OSCIF
UPOSC
W
Reset 0 Note 1 Note 2 0 0 Note 3 0 0
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
= Unimplemented or Reserved
Figure 4-7. S12CPMU_UHV Flags Register (CPMUFLG)
fPLL
fVCO
POSTDIV 1+()
-----------------------------------------
=
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0) fPLL
fVCO
4
---------------
=
fbus
fPLL
2
-------------
=
If PLL is selected (PLLSEL=1)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
132 Freescale Semiconductor
Table 4-3. CPMUFLG Field Descriptions
Field Description
7
RTIF
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
6
PORF
Power on Reset Flag —PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
5
LVRF
Low Voltage Reset Flag —LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
4
LOCKIF
PLL Lock Interrupt Flag —LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
3
LOCK
Lock Status Bit —LOCK reflects the current state of PLL lock condition. Writes have no effect.While PLL is
unlocked (LOCK=0) fPLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL
stabilization time tlock.
0 VCOCLK is not within the desired tolerance of the target frequency.
fPLL = fVCO/4.
1 VCOCLK is within the desired tolerance of the target frequency.
fPLL = fVCO/(POSTDIV+1).
2
ILAF
Illegal Address Reset Flag —ILAF is set to 1 when an illegal address reset occurs.Refer to MMC chapter for
details.This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
1
OSCIF
Oscillator Interrupt Flag —OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (OSCIE=1), OSCIF causes an interrupt request.
0 No change in UPOSC bit.
1 UPOSC bit has changed.
0
UPOSC
Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. Entering Full Stop
Mode UPOSC is cleared.
0 The oscillator is off or oscillation is not qualified by the PLL.
1 The oscillator is qualified by the PLL.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 133
4.3.2.5 S12CPMU_UHV Interrupt Enable Register (CPMUINT)
This register enables S12CPMU_UHV interrupt requests.
Read: Anytime
Write: Anytime
0x0038
76543210
R
RTIE
00
LOCKIE
00
OSCIE
0
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-8. S12CPMU_UHV Interrupt Enable Register (CPMUINT)
Table 4-4. CPMUINT Field Descriptions
Field Description
7
RTIE
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
4
LOCKIE
PLL Lock Interrupt Enable Bit
0 PLL LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
1
OSCIE
Oscillator Corrupt Interrupt Enable Bit
0 Oscillator Corrupt interrupt requests are disabled.
1 Interrupt will be requested whenever OSCIF is set.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
134 Freescale Semiconductor
4.3.2.6 S12CPMU_UHV Clock Select Register (CPMUCLKS)
This register controls S12CPMU_UHV clock selection.
Read: Anytime
Write:
5. Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
6. All bits in Special Mode (if PROT=0).
7. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
8. CSAD: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
9. COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1 or
insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
10. COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with
COPOSCSEL1=1 or insufficient OSCCLK quality if OSCCLK is used as clock source for
other clock domains: for instance core clock etc.).
NOTE
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL and COPOSCSEL was successful.
0x0039
76543210
R
PLLSEL PSTP CSAD COP
OSCSEL1 PRE PCE RTI
OSCSEL
COP
OSCSEL0
W
Reset 10000000
= Unimplemented or Reserved
Figure 4-9. S12CPMU_UHV Clock Select Register (CPMUCLKS)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 135
Table 4-5. CPMUCLKS Descriptions
Field Description
7
PLLSEL
PLL Select Bit
This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock).
PLLSEL can only be set to 0, if UPOSC=1.
UPOSC= 0 sets the PLLSEL bit.
Entering Full Stop Mode sets the PLLSEL bit.
0 System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, fbus = fosc / 2).
1 System clocks are derived from PLLCLK, fbus = fPLL / 2.
6
PSTP
Pseudo Stop Bit
This bit controls the functionality of the oscillator during Stop Mode.
0 Oscillator is disabled in Stop Mode (Full Stop Mode).
1 Oscillator continues to run in Stop Mode (Pseudo Stop Mode), option to run RTI and COP.
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator tUPOSC before entering Pseudo Stop Mode.
4
CSAD
COP in Stop Mode ACLK Disable — This bit disables the ACLK for the COP in Stop Mode. Hence the COP is
static while in Stop Mode and continues to operate after exit from Stop Mode.
Due to clock domain crossing synchronization there is a latency time to enter and exit Stop Mode if COP clock
source is ACLK and this clock is stopped in Stop Mode. This maximum latency time is 4 ACLK cycles which must
be added to the Stop Mode recovery time tSTP_REC from exit of current Stop Mode to entry of next Stop Mode.
This latency time occurs no matter which Stop Mode (Full, Pseudo) is currently exited or entered next. After exit
from Stop Mode (Pseudo, Full) for 2 ACLK cycles no Stop Mode request (STOP instruction) should be generated
to make sure the COP counter increments at each Stop Mode exit.
This bit does not influence the ACLK for the API.
0 COP running in Stop Mode (ACLK for COP enabled in Stop Mode).
1 COP stopped in Stop Mode (ACLK for COP disabled in Stop Mode)
4
COP
OSCSEL1
COP Clock Select 1 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP
(see also Table 4-6).
If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit
does not re-start the COP time-out period.
COPOSCSEL1 selects the clock source to the COP to be either ACLK (derived from trimmable internal
RC-Oscillator) or clock selected via COPOSCSEL0 (IRCCLK or OSCCLK).
Changing the COPOSCSEL1 bit re-starts the COP time-out period.
COPOSCSEL1 can be set independent from value of UPOSC.
UPOSC= 0 does not clear the COPOSCSEL1 bit.
0 COP clock source defined by COPOSCSEL0
1 COP clock source is ACLK derived from a trimmable internal RC-Oscillator
3
PRE
RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode.
0 RTI stops running during Pseudo Stop Mode.
1 RTI continues running during Pseudo Stop Mode if RTIOSCSEL=1.
Note: If PRE=0 or RTIOSCSEL=0 then the RTI will go static while Stop Mode is active. The RTI counter will not
be reset.
2
PCE
COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.
0 COP stops running during Pseudo Stop Mode
1 COP continues running during Pseudo Stop Mode if COPOSCSEL=1
Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will
not be reset.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
136 Freescale Semiconductor
Table 4-6. COPOSCSEL1, COPOSCSEL0 clock source select description
1
RTIOSCSEL
RTI Clock Select— RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the
RTIOSCSEL bit re-starts the RTI time-out period.
RTIOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the RTIOSCSEL bit.
0 RTI clock source is IRCCLK.
1 RTI clock source is OSCCLK.
0
COP
OSCSEL0
COP Clock Select 0 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP
(see also Table 4-6)
If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit
does not re-start the COP time-out period.
When COPOSCSEL1=0,COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK.
Changing the COPOSCSEL0 bit re-starts the COP time-out period.
COPOSCSEL0 can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the COPOSCSEL0 bit.
0 COP clock source is IRCCLK.
1 COP clock source is OSCCLK
COPOSCSEL1 COPOSCSEL0 COP clock source
0 0 IRCCLK
0 1 OSCCLK
1 x ACLK
Table 4-5. CPMUCLKS Descriptions (continued)
Field Description
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 137
4.3.2.7 S12CPMU_UHV PLL Control Register (CPMUPLL)
This register controls the PLL functionality.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
NOTE
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
0x003A
76543210
R0 0
FM1 FM0
0000
W
Reset 00000000
Figure 4-10. S12CPMU_UHV PLL Control Register (CPMUPLL)
Table 4-7. CPMUPLL Field Descriptions
Field Description
5, 4
FM1, FM0
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
is to reduce noise emission. The modulation frequency is fref divided by 16. See Table 4-8 for coding.
Table 4-8. FM Amplitude selection
FM1 FM0 FM Amplitude /
fVCO Variation
0 0 FM off
01 ±1%
10 ±2%
11 ±4%
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
138 Freescale Semiconductor
4.3.2.8 S12CPMU_UHV RTI Control Register (CPMURTI)
This register selects the time-out period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else
the RTI counter halts in Stop Mode.
Read: Anytime
Write: Anytime
NOTE
A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
0x003B
76543210
R
RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
Reset 00000000
Figure 4-11. S12CPMU_UHV RTI Control Register (CPMURTI)
Table 4-9. CPMURTI Field Descriptions
Field Description
7
RTDEC
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 4-10
1 Decimal based divider value. See Table 4-11
6–4
RTR[6:4]
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI.See Table 4-10
and Table 4-11.
3–0
RTR[3:0]
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 4-10 and Table 4-11 show all possible divide values selectable by the
CPMURTI register.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 139
Table 4-10. RTI Frequency Divide Rates for RTDEC = 0
RTR[3:0]
RTR[6:4] =
000
(OFF)
001
(210)
010
(211)
011
(212)
100
(213)
101
(214)
110
(215)
111
(216)
0000 (÷1) OFF1
1Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
210 211 212 213 214 215 216
0001 (÷2) OFF 2x210 2x211 2x212 2x213 2x214 2x215 2x216
0010 (÷3) OFF 3x210 3x211 3x212 3x213 3x214 3x215 3x216
0011 (÷4) OFF 4x210 4x211 4x212 4x213 4x214 4x215 4x216
0100 (÷5) OFF 5x210 5x211 5x212 5x213 5x214 5x215 5x216
0101 (÷6) OFF 6x210 6x211 6x212 6x213 6x214 6x215 6x216
0110 (÷7) OFF 7x210 7x211 7x212 7x213 7x214 7x215 7x216
0111 (÷8) OFF 8x210 8x211 8x212 8x213 8x214 8x215 8x216
1000 (÷9) OFF 9x210 9x211 9x212 9x213 9x214 9x215 9x216
1001 (÷10) OFF 10x210 10x211 10x212 10x213 10x214 10x215 10x216
1010 (÷11) OFF 11x210 11x211 11x212 11x213 11x214 11x215 11x216
1011 (÷12) OFF 12x210 12x211 12x212 12x213 12x214 12x215 12x216
1100 (÷13) OFF 13x210 13x211 13x212 13x213 13x214 13x215 13x216
1101 (÷14) OFF 14x210 14x211 14x212 14x213 14x214 14x215 14x216
1110 (÷15) OFF 15x210 15x211 15x212 15x213 15x214 15x215 15x216
1111 (÷16) OFF 16x210 16x211 16x212 16x213 16x214 16x215 16x216
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
140 Freescale Semiconductor
Table 4-11. RTI Frequency Divide Rates for RTDEC=1
RTR[3:0]
RTR[6:4] =
000
(1x103)
001
(2x103)
010
(5x103)
011
(10x103)
100
(20x103)
101
(50x103)
110
(100x103)
111
(200x103)
0000 (÷1) 1x1032x1035x10310x10320x10350x103100x103200x103
0001 (÷2) 2x1034x10310x10320x10340x103100x103200x103400x103
0010 (÷3) 3x1036x10315x10330x10360x103150x103300x103600x103
0011 (÷4) 4x1038x10320x10340x10380x103200x103400x103800x103
0100 (÷5) 5x10310x10325x10350x103100x103250x103500x1031x106
0101 (÷6) 6x10312x10330x10360x103120x103300x103600x1031.2x106
0110 (÷7) 7x10314x10335x10370x103140x103350x103700x1031.4x106
0111 (÷8) 8x10316x10340x10380x103160x103400x103800x1031.6x106
1000 (÷9) 9x10318x10345x10390x103180x103450x103900x1031.8x106
1001 (÷10) 10 x10320x10350x103100x103200x103500x1031x1062x106
1010 (÷11) 11 x10322x10355x103110x103220x103550x1031.1x1062.2x106
1011 (÷12) 12x10324x10360x103120x103240x103600x1031.2x1062.4x106
1100 (÷13) 13x10326x10365x103130x103260x103650x1031.3x1062.6x106
1101 (÷14) 14x10328x10370x103140x103280x103700x1031.4x1062.8x106
1110 (÷15) 15x10330x10375x103150x103300x103750x1031.5x1063x106
1111 (÷16) 16x10332x10380x103160x103320x103800x1031.6x1063.2x106
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 141
4.3.2.9 S12CPMU_UHV COP Control Register (CPMUCOP)
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit (see also Table 4-6).
In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the
COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0.
In Full Stop Mode and Pseudo Stop Mode with COPOSCSEL1=1 the COP continues to run.
Read: Anytime
Write:
1. RSBCK: Anytime in Special Mode; write to “1” but not to “0” in Normal Mode
2. WCOP, CR2, CR1, CR0:
— Anytime in Special Mode, when WRTMASK is 0, otherwise it has no effect
— Write once in Normal Mode, when WRTMASK is 0, otherwise it has no effect.
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL0 or COPOSCSEL1 bit (writing a different value) or loosing UPOSC status
while COPOSCSEL1 is clear and COPOSCSEL0 is set, re-starts the COP time-out period.
In Normal Mode the COP time-out period is restarted if either of these conditions is true:
1. Writing a non-zero value to CR[2:0] (anytime in special mode, once in normal mode) with
WRTMASK = 0.
2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0.
3. Changing RSBCK bit from “0” to “1”.
In Special Mode, any write access to CPMUCOP register restarts the COP time-out period.
0x003C
76543210
R
WCOP RSBCK
000
CR2 CR1 CR0
W WRTMASK
Reset F 0 0 0 0 F F F
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
details.
= Unimplemented or Reserved
Figure 4-12. S12CPMU_UHV COP Control Register (CPMUCOP)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
142 Freescale Semiconductor
Table 4-12. CPMUCOP Field Descriptions
Field Description
7
WCOP
Window COP Mode Bit — When set, a write to the CPMUARMCOP register must occur in the last 25% of the
selected period.A write during the first 75% of the selected period generates a COP reset.As long as all writes
occur during this window, $55 can be written as often as desired.Once $AA is written after the $55, the time-out
logic restarts and the user must wait until the next window before writing to CPMUARMCOP. Table 4-13 shows
the duration of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
6
RSBCK
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
5
WRTMASK
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
while writing the CPMUCOP register. It is intended for BDM writing the RSBCK without changing the content of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of CPMUCOP
1 Write of WCOP and CR[2:0] has no effect with this write of CPMUCOP.
(Does not count for “write once”.)
2–0
CR[2:0]
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 4-13 and Table 4-14).
Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period.A COP counter
time-out causes a System Reset.This can be avoided by periodically (before time-out) initializing the COP
counter via the CPMUARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (224 cycles) in normal COP mode (Window COP mode disabled):
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in Special Mode
Table 4-13. COP Watchdog Rates if COPOSCSEL1=0.
(default out of reset)
CR2 CR1 CR0
COPCLK
Cycles to time-out
(COPCLK is either IRCCLK or
OSCCLK depending on the
COPOSCSEL0 bit)
0 0 0 COP disabled
001 2
14
010 2
16
011 2
18
100 2
20
101 2
22
110 2
23
111 2
24
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 143
Table 4-14. COP Watchdog Rates if COPOSCSEL1=1.
CR2 CR1 CR0
COPCLK
Cycles to time-out
(COPCLK is ACLK divided by 2)
0 0 0 COP disabled
001 2
7
010 2
9
011 2
11
100 2
13
101 2
15
110 2
16
111 2
17
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
144 Freescale Semiconductor
4.3.2.10 Reserved Register CPMUTEST0
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in Special
Mode can alter the S12CPMU_UHV’s functionality.
Read: Anytime
Write: Only in Special Mode
4.3.2.11 Reserved Register CPMUTEST1
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in Special
Mode can alter the S12CPMU_UHV’s functionality.
Read: Anytime
Write: Only in Special Mode
0x003D
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-13. Reserved Register (CPMUTEST0)
0x003E
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-14. Reserved Register (CPMUTEST1)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 145
4.3.2.12 S12CPMU_UHV COP Timer Arm/Reset Register (CPMUARMCOP)
This register is used to restart the COP time-out period.
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the
sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.
Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done
in the last 25% of the selected time-out period; writing any value in the first 75% of the selected
period will cause a COP reset.
4.3.2.13 High Temperature Control Register (CPMUHTCTL)
The CPMUHTCTL register configures the temperature sense features.
Read: Anytime
Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only
0x003F
76543210
R00000000
W ARMCOP-Bit
7
ARMCOP-Bit
6
ARMCOP-Bit
5
ARMCOP-Bit
4
ARMCOP-Bit
3
ARMCOP-Bit
2
ARMCOP-Bit
1
ARMCOP-Bit
0
Reset 00000000
Figure 4-15. S12CPMU_UHV CPMUARMCOP Register
0x02F0
76543210
R0 0 VSEL 0HTE HTDS HTIE HTIF
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-16. High Temperature Control Register (CPMUHTCTL)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
146 Freescale Semiconductor
Figure 4-17. Voltage Access Select
Table 4-15. CPMUHTCTL Field Descriptions
Field Description
5
VSEL
Voltage Access Select Bit — If set, the bandgap reference voltage VBG can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). If not set, the die temperature proportional
voltage VHT of the temperature sensor can be accessed internally.See device level specification for connectivity.
For any of these access the HTE bit must be set.
0 An internal temperature proportional voltage VHT can be accessed internally.
1 Bandgap reference voltage VBG can be accessed internally.
3
HTE
High Temperature Sensor/Bandgap Voltage Enable Bit — This bit enables the high temperature sensor and
bandgap voltage amplifier.
0 The temperature sensor and bandgap voltage amplifier is disabled.
1 The temperature sensor and bandgap voltage amplifier is enabled.
2
HTDS
High Temperature Detect Status Bit — This read-only status bit reflects the temperature status.Writes have
no effect.
0 Junction Temperature is below level THTID or RPM.
1 Junction Temperature is above level THTIA and FPM.
1
HTIE
High Temperature Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
0
HTIF
High Temperature Interrupt Flag — HTIF — High Temperature Interrupt Flag
HTIF is set to 1 when HTDS status bit changes.This flag can only be cleared by writing a 1.
Writing a 0 has no effect. If enabled (HTIE=1), HTIF causes an interrupt request.
0 No change in HTDS bit.
1 HTDS bit has changed.
C
HTD
VBG
ATD
Ref
Channel
VSEL TEMPSENSE
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 147
4.3.2.14 Low Voltage Control Register (CPMULVCTL)
The CPMULVCTL register allows the configuration of the low-voltage detect features.
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
0x02F1
76543210
R00000LVDS
LVIE LVIF
W
Reset 00000U0U
The Reset state of LVDS and LVIF depends on the external supplied VDDA level
= Unimplemented or Reserved
Figure 4-18. Low Voltage Control Register (CPMULVCTL)
Table 4-16. CPMULVCTL Field Descriptions
Field Description
2
LVDS
Low-Voltage Detect Status Bit — This read-only status bit reflects the voltage level on VDDA.Writes have no
effect.
0 Input voltage VDDA is above level VLVID or RPM.
1 Input voltage VDDA is below level VLVIA and FPM.
1
LVIE
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
0
LVIF
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1.Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
148 Freescale Semiconductor
4.3.2.15 Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features.
Read: Anytime
Write: Anytime
0x02F2
76543210
RAPICLK 00
APIES APIEA APIFE APIE APIF
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-19. Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
Table 4-17. CPMUAPICTL Field Descriptions
Field Description
7
APICLK
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0. APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous Clock (ACLK) used as source.
1 Bus Clock used as source.
4
APIES
Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin
API_EXTCLK as shown in Figure 4-20. See device level specification for connectivity of API_EXTCLK pin.
0 If APIEA and APIFE are set, at the external pin API_EXTCLK periodic high pulses are visible at the end of
every selected period with the size of half of the minimum period (APIR=0x0000 in Table 4-21).
1 If APIEA and APIFE are set, at the external pin API_EXTCLK a clock is visible with 2 times the selected API
Period.
3
APIEA
Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES
can be accessed externally. See device level specification for connectivity.
0 Waveform selected by APIES can not be accessed externally.
1 Waveform selected by APIES can be accessed externally, if APIFE is set.
2
APIFE
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
1
APIE
Autonomous Periodical Interrupt Enable Bit
0 API interrupt request is disabled.
1 API interrupt will be requested whenever APIF is set.
0
APIF
Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API configured time has elapsed.
This flag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an
interrupt request.
0 API time-out has not yet occurred.
1 API time-out has occurred.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 149
Figure 4-20. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1)
APIES=0
APIES=1
API period
API min. period / 2
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
150 Freescale Semiconductor
4.3.2.16 Autonomous Clock Trimming Register (CPMUACLKTR)
The CPMUACLKTR register configures the trimming of the Autonomous Clock (ACLK - trimmable
internal RC-Oscillator) which can be selected as clock source for some CPMU features.
Read: Anytime
Write: Anytime
0x02F3
76543210
RACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 00
W
Reset F F F F F F 0 0
After de-assert of System Reset a value is automatically loaded from the Flash memory.
Figure 4-21. Autonomous Clock Trimming Register (CPMUACLKTR)
Table 4-18. CPMUACLKTR Field Descriptions
Field Description
7–2
ACLKTR[5:0]
Autonomous Clock Period Trimming Bits — See Table 4-19 for trimming effects. The ACLKTR[5:0] value
represents a signed number influencing the ACLK period time.
Table 4-19. Trimming Effect of ACLKTR
Bit Trimming Effect
ACLKTR[5] Increases period
ACLKTR[4] Decreases period less than ACLKTR[5] increased it
ACLKTR[3] Decreases period less than ACLKTR[4]
ACLKTR[2] Decreases period less than ACLKTR[3]
ACLKTR[1] Decreases period less than ACLKTR[2]
ACLKTR[0] Decreases period less than ACLKTR[1]
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 151
4.3.2.17 Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate.
Read: Anytime
Write: Anytime if APIFE=0, Else writes have no effect.
The period can be calculated as follows depending on logical value of the APICLK bit:
APICLK=0: Period = 2*(APIR[15:0] + 1) * (ACLK Clock Period * 2)
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock Period
NOTE
For APICLK bit clear the first time-out period of the API will show a latency
time between two to three fACLK cycles due to synchronous clock gate
release when the API feature gets enabled (APIFE bit set).
0x02F4
76543210
RAPIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-22. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
0x02F5
76543210
RAPIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0
W
Reset 00000000
Figure 4-23. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
Table 4-20. CPMUAPIRH / CPMUAPIRL Field Descriptions
Field Description
15-0
APIR[15:0]
Autonomous Periodical Interrupt Rate Bits — These bits define the time-out period of the API. See
Table 4-21 for details of the effect of the autonomous periodical interrupt rate bits.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
152 Freescale Semiconductor
Table 4-21. Selectable Autonomous Periodical Interrupt Periods
APICLK APIR[15:0] Selected Period
0 0000 0.2 ms1
1When fACLK is trimmed to 20kHz.
0 0001 0.4 ms1
0 0002 0.6 ms1
0 0003 0.8 ms1
0 0004 1.0 ms1
0 0005 1.2 ms1
0 ..... .....
0 FFFD 13106.8 ms1
0 FFFE 13107.0 ms1
0 FFFF 13107.2 ms1
1 0000 2 * Bus Clock period
1 0001 4 * Bus Clock period
1 0002 6 * Bus Clock period
1 0003 8 * Bus Clock period
1 0004 10 * Bus Clock period
1 0005 12 * Bus Clock period
1 ..... .....
1 FFFD 131068 * Bus Clock period
1 FFFE 131070 * Bus Clock period
1 FFFF 131072 * Bus Clock period
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 153
4.3.2.18 Reserved Register CPMUTEST3
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in Special
Mode can alter the S12CPMU_UHV’s functionality.
Read: Anytime
Write: Only in Special Mode
0x02F6
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-24. Reserved Register (CPMUTEST3)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
154 Freescale Semiconductor
4.3.2.19 High Temperature Trimming Register (CPMUHTTR)
The CPMUHTTR register configures the trimming of the S12CPMU_UHV temperature sense.
Read: Anytime
Write: Anytime
0x02F7
76543210
RHTOE 000
HTTR3 HTTR2 HTTR1 HTTR0
W
Reset 0000FFFF
After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for
details.
= Unimplemented or Reserved
Figure 4-25. High Temperature Trimming Register (CPMUHTTR)
Table 4-23. CPMUHTTR Field Descriptions
Field Description
7
HTOE
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled.
0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care.
1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
3–0
HTTR[3:0]
High Temperature Trimming Bits — See Table 4-24 for trimming effects.
Table 4-24. Trimming Effect of HTTR
Bit Trimming Effect
HTTR[3] Increases VHT twice of HTTR[2]
HTTR[2] Increases VHT twice of HTTR[1]
HTTR[1] Increases VHT twice of HTTR[0]
HTTR[0] Increases VHT (to compensate Temperature Offset)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 155
4.3.2.20 S12CPMU_UHV IRC1M Trim Registers (CPMUIRCTRIMH /
CPMUIRCTRIML)
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register). Else write has no effect
NOTE
Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC
status bits.
0x02F8
15 14 13 12 11 10 9 8
R
TCTRIM[4:0]
0
IRCTRIM[9:8]
W
Reset F F F F F 0 F F
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency fIRC1M_TRIM.
Figure 4-26. S12CPMU_UHV IRC1M Trim High Register (CPMUIRCTRIMH)
0x02F9
76543210
R
IRCTRIM[7:0]
W
Reset F F F FFFFF
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency fIRC1M_TRIM.
Figure 4-27. S12CPMU_UHV IRC1M Trim Low Register (CPMUIRCTRIML)
Table 4-25. CPMUIRCTRIMH/L Field Descriptions
Field Description
15-11
TCTRIM[4:0]
IRC1M temperature coefficient Trim Bits
Trim bits for the Temperature Coefficient (TC) of the IRC1M frequency.
Table 4-26 shows the influence of the bits TCTRIM[4:0] on the relationship between frequency and temperature.
Figure 4-29 shows an approximate TC variation, relative to the nominal TC of the IRC1M (i.e. for
TCTRIM[4:0]=0x00000 or 0x10000).
9-0
IRCTRIM[9:0]
IRC1M Frequency Trim Bits — Trim bits for Internal Reference Clock
After System Reset the factory programmed trim value is automatically loaded into these registers, resulting in a
Internal Reference Frequency fIRC1M_TRIM.See device electrical characteristics for value of fIRC1M_TRIM.
The frequency trimming consists of two different trimming methods:
A rough trimming controlled by bits IRCTRIM[9:6] can be done with frequency leaps of about 6% in average.
A fine trimming controlled by bits IRCTRIM[5:0] can be done with frequency leaps of about 0.3% (this trimming
determines the precision of the frequency setting of 0.15%, i.e. 0.3% is the distance between two trimming
values).
Figure 4-28 shows the relationship between the trim bits and the resulting IRC1M frequency.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
156 Freescale Semiconductor
Figure 4-28. IRC1M Frequency Trimming Diagram
IRCTRIM[9:0]
$000
IRCTRIM[9:6]
IRCTRIM[5:0]
IRC1M frequency (IRCCLK)
600KHz
1.5MHz
1MHz
$3FF
{
......
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 157
Figure 4-29. Influence of TCTRIM[4:0] on the Temperature Coefficient
NOTE
The frequency is not necessarily linear with the temperature (in most cases
it will not be). The above diagram is meant only to give the direction
(positive or negative) of the variation of the TC, relative to the nominal TC.
Setting TCTRIM[4:0] at 0x00000 or 0x10000 does not mean that the
temperature coefficient will be zero. These two combinations basically
switch off the TC compensation module, which results in the nominal TC of
the IRC1M.
frequency
temperature
TCTRIM[4:0] = 0x11111
TCTRIM[4:0] = 0x01111
- 40C 150C
TCTRIM[4:0] = 0x10000 or 0x00000 (nominal TC)
0x00001
0x00010
0x00011
0x00100
0x00101
...
0x01111
0x11111
...
0x10101
0x10100
0x10011
0x10010
0x10001
TC increases
TC decreases
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
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158 Freescale Semiconductor
Table 4-26. TC trimming of the frequency of the IRC1M at ambient temperature
NOTE
Since the IRC1M frequency is not a linear function of the temperature, but
more like a parabola, the above relative variation is only an indication and
should be considered with care.
TCTRIM[4:0] IRC1M Indicative
relative TC variation
IRC1M indicative frequency drift for
relative TC variation
00000 0 (nominal TC of the IRC) 0%
00001 -0.27% -0.5%
00010 -0.54% -0.9%
00011 -0.81% -1.3%
00100 -1.08% -1.7%
00101 -1.35% -2.0%
00110 -1.63% -2.2%
00111 -1.9% -2.5%
01000 -2.20% -3.0%
01001 -2.47% -3.4%
01010 -2.77% -3.9%
01011 -3.04 -4.3%
01100 -3.33% -4.7%
01101 -3.6% -5.1%
01110 -3.91% -5.6%
01111 -4.18% -5.9%
10000 0 (nominal TC of the IRC) 0%
10001 +0.27% +0.5%
10010 +0.54% +0.9%
10011 +0.81% +1.3%
10100 +1.07% +1.7%
10101 +1.34% +2.0%
10110 +1.59% +2.2%
10111 +1.86% +2.5%
11000 +2.11% +3.0%
11001 +2.38% +3.4%
11010 +2.62% +3.9%
11011 +2.89% +4.3%
11100 +3.12% +4.7%
11101 +3.39% +5.1%
11110 +3.62% +5.6%
11111 +3.89% +5.9%
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 159
Be aware that the output frequency varies with the TC trimming. A
frequency trimming correction is therefore necessary. The values provided
in Table 4-26 are typical values at ambient temperature which can vary from
device to device.
4.3.2.21 S12CPMU_UHV Oscillator Register (CPMUOSC)
This register configures the external oscillator (XOSCLCP).
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
NOTE.
Write to this register clears the LOCK and UPOSC status bits.
0x02FA
76543210
R
OSCE Reserved
0
Reserved
W
Reset 00000000
Figure 4-30. S12CPMU_UHV Oscillator Register (CPMUOSC)
Table 4-27. CPMUOSC Field Descriptions
Field Description
7
OSCE
Oscillator Enable Bit — This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the
CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as Bus Clock or source
of the COP or RTI.A loss of oscillation will lead to a clock monitor reset.This
0 External oscillator is disabled.
REFCLK for PLL is IRCCLK.
1 External oscillator is enabled. Clock monitor is enabled. External oscillator is qualified by PLLCLK
REFCLK for PLL is the external oscillator clock divided by REFDIV.
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator tUPOSC before entering Pseudo Stop Mode.
6
Reserved
Do not alter this bit from its reset value.It is for Manufacturer use only and can change the PLL behavior.
4-0
Reserved
Do not alter these bits from their reset value. These are for Manufacturer use only and can change the PLL
behavior.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
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160 Freescale Semiconductor
4.3.2.22 S12CPMU_UHV Protection Register (CPMUPROT)
This register protects the clock configuration registers from accidental overwrite:
CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L and CPMUOSC
Read: Anytime
Write: Anytime
0x02FB
76543210
R0000000
PROT
W
Reset 00000000
Figure 4-31. S12CPMU_UHV Protection Register (CPMUPROT)
Field Description
PROT Clock Configuration Registers Protection Bit — This bit protects the clock configuration registers from
accidental overwrite (see list of protected registers above): Writing 0x26 to the CPMUPROT register clears the
PROT bit, other write accesses set the PROT bit.
0 Protection of clock configuration registers is disabled.
1 Protection of clock configuration registers is enabled. (see list of protected registers above).
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 161
4.3.2.23 Reserved Register CPMUTEST2
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in Special
Mode can alter the S12CPMU_UHV’s functionality.
Read: Anytime
Write: Only in Special Mode
0x02FC
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-32. Reserved Register CPMUTEST2
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
162 Freescale Semiconductor
4.4 Functional Description
4.4.1 Phase Locked Loop with Internal Filter (PLL)
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK.
The REFCLK is by default the IRCCLK which is trimmed to fIRC1M_TRIM=1MHz.
If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK
can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0]
bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock
by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,
3, 4, 5, 6,... to 32 to generate the PLLCLK.
.
NOTE
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
fVCO 2f
REF
×SYNDIV 1+()×=
fREF
fOSC
REFDIV 1+()
------------------------------------
=
If oscillator is enabled (OSCE=1)
If oscillator is disabled (OSCE=0) fREF fIRC1M
=
fPLL
fVCO
POSTDIV 1+()
-----------------------------------------
=
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0) fPLL
fVCO
4
---------------
=
fbus
fPLL
2
-------------
=
If PLL is selected (PLLSEL=1)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 163
Several examples of PLL divider settings are shown in Table 4-28. The following rules help to achieve
optimum stability and shortest lock time:
• Use lowest possible fVCO / fREF ratio (SYNDIV value).
• Use highest possible REFCLK frequency fREF.
The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1)) with
the reference clock (REFCLK = (IRC1M or OSCCLK)/(REFDIV+1)). Correction pulses are generated
based on the phase difference between the two signals. The loop filter alters the DC voltage on the internal
filter capacitor, based on the width and direction of the correction pulse which leads to a higher or lower
VCO frequency.
The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the
VCOCLK frequency (VCOFRQ[1:0] bits) to ensure that the correct PLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance
check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously
(during PLL start-up) or at periodic intervals. In either case, only when the LOCK bit is set, the VCOCLK
will have stabilized to the programmed frequency.
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within the tolerance, ∆Lock, and is cleared when
the VCO frequency is out of the tolerance, ∆unl.
• Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
Table 4-28. Examples of PLL Divider Settings
fosc REFDIV[3:0] fREF REFFRQ[1:0] SYNDIV[5:0] fVCO VCOFRQ[1:0] POSTDIV[4:0] fPLL fbus
off $00 1MHz 00 $18 50MHz 01 $03 12.5MHz 6.25MHz
off $00 1MHz 00 $18 50MHz 01 $00 50MHz 25MHz
4MHz $00 4MHz 01 $05 48MHz 00 $00 48MHz 24MHz
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
164 Freescale Semiconductor
4.4.2 Startup from Reset
An example for startup of the clock system from Reset is given in Figure 4-33.
Figure 4-33. Startup of clock system after Reset
4.4.3 Stop Mode using PLLCLK as Bus Clock
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in
Figure 4-34. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode.
Figure 4-34. Stop Mode using PLLCLK as Bus Clock
Depending on the COP configuration there might be an additional significant latency time until COP is
active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time
of 2 ACLK cycles occurs if COP clock source is ACLK and the CSAD bit is set and must be added to the
device Stop Mode recovery time tSTP_REC. After exit from Stop Mode (Pseudo, Full) for this latency time
System
PLLCLK
Reset
fPLLRST
CPU reset state vector fetch, program execution
LOCK
POSTDIV $03 (default target fPLL=fVCO/4 = 12.5MHz)
fPLL increasing fPLL=12.5MHz
tlock
SYNDIV $18 (default target fVCO=50MHz)
$01
fPLL=25MHz
example change
of POSTDIV
768 cycles
) (
PLLCLK
CPU
LOCK tlock
STOP instructionexecution interrupt continue execution
wakeup
tSTP_REC
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 165
of 2 ACLK cycles no Stop Mode request (STOP instruction) should be generated to make sure the COP
counter can increment at each Stop Mode exit.
4.4.4 Full Stop Mode using Oscillator Clock as Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is
shown in Figure 4-35.
Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going
into Full Stop Mode.
Figure 4-35. Full Stop Mode using Oscillator Clock as Bus Clock
Depending on the COP configuration there might be a significant latency time until COP is active again
after exit from Stop Mode due to clock domain crossing synchronization. This latency time of 2 ACLK
cycles occurs if COP clock source is ACLK and the CSAD bit is set and must be added to the device Stop
Mode recovery time tSTP_REC. After exit from Stop Mode (Pseudo, Full) for this latency time of 2 ACLK
cycles no Stop Mode request (STOP instruction) should be generated to make sure the COP counter can
increment at each Stop Mode exit.
CPU
UPOSC
tlock
STOP instruction
execution interrupt continue execution
wakeup
tSTP_REC
Core
Clock
select OSCCLK as Core/Bus Clock by writing PLLSEL to “0”
PLLSEL
automatically set when going into Full Stop Mode
OSCCLK
PLLCLK
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
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166 Freescale Semiconductor
4.4.5 External Oscillator
4.4.5.1 Enabling the External Oscillator
An example of how to use the oscillator as Bus Clock is shown in Figure 4-36.
Figure 4-36. Enabling the external oscillator
PLLSEL
OSCE
EXTAL
OSCCLK
Core
enable external oscillator by writing OSCE bit to one.
crystal/resonator starts oscillating
UPOSC
UPOSC flag is set upon successful start of oscillation
select OSCCLK as Core/Bus Clock by writing PLLSEL to zero
Clock
based on PLL Clock based on OSCCLK
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 167
4.4.6 System Clock Configurations
4.4.6.1 PLL Engaged Internal Mode (PEI)
This mode is the default mode after System Reset or Power-On Reset.
The Bus Clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M).
The PLL is configured to 50 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results
in a PLLCLK of 12.5 MHz and a Bus Clock of 6.25 MHz. The PLL can be re-configured to other bus
frequencies.
The clock sources for COP and RTI can be based on the internal reference clock generator (IRC1M) or the
RC-Oscillator (ACLK).
4.4.6.2 PLL Engaged External Mode (PEE)
In this mode, the Bus Clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL
is based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps:
1. Configure the PLL for desired bus frequency.
2. Enable the external Oscillator (OSCE bit).
3. Wait for oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1).
4. Clear all flags in the CPMUFLG register to be able to detect any future status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PEE mode is as follows:
• The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
168 Freescale Semiconductor
4.4.6.3 PLL Bypassed External Mode (PBE)
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is
based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps:
1. Make sure the PLL configuration is valid.
2. Enable the external Oscillator (OSCE bit)
3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1)
4. Clear all flags in the CPMUFLG register to be able to detect any status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
6. Select the Oscillator clock as Bus clock (PLLSEL=0)
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows:
• PLLSEL is set automatically and the Bus clock is switched back to the PLL clock.
• The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
4.5 Resets
4.5.1 General
All reset sources are listed in Table 4-29. Refer to MCU specification for related vector addresses and
priorities.
4.5.2 Description of Reset Operation
Upon detection of any reset of Table 4-29, an internal circuit drives the RESET pin low for 512 PLLCLK
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU_UHV
Table 4-29. Reset Summary
Reset Source Local Enable
Power-On Reset (POR) None
Low Voltage Reset (LVR) None
External pin RESET None
Illegal Address Reset None
Clock Monitor Reset OSCE Bit in CPMUOSC register
COP Reset CR[2:0] in CPMUCOP register
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 169
waits for additional 256PLLCLK cycles and then samples the RESET pin to determine the originating
source. Table 4-30 shows which vector will be fetched.
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
fVCORST.
The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK
cycles long reset sequence. In case the RESET pin is externally driven low for more than these 768
PLLCLK cycles (External Reset), the internal reset remains asserted longer.
Figure 4-37. RESET Timing
4.5.2.1 Clock Monitor Reset
If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is
below the failure assert frequency fCMFA (see device electrical characteristics for values), the
Table 4-30. Reset Vector Selection
Sampled RESET Pin
(256 cycles after
release)
Oscillator monitor
fail pending
COP
time-out
pending
Vector Fetch
1 0 0 POR
LVR
Illegal Address Reset
External pin RESET
1 1 X Clock Monitor Reset
1 0 1 COP Reset
0 X X POR
LVR
Illegal Address Reset
External pin RESET
)
(
)
PLLCLK
512 cycles 256 cycles
S12_CPMU drives
possibly
RESET
driven low
externally
)
(
(
RESET
S12_CPMU releases
fVCORST
RESET pin low RESET pin
fVCORST
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
170 Freescale Semiconductor
S12CPMU_UHV generates a Clock Monitor Reset. In Full Stop Mode the external oscillator and the clock
monitor are disabled.
4.5.2.2 Computer Operating Properly Watchdog (COP) Reset
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus COP reset is generated.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit.
Due to clock domain crossing synchronization there is a latency time to enter and exit Stop Mode if the
COP clock source is ACLK and this clock is stopped in Stop Mode. This maximum total latency time is 4
ACLK cycles (2 ACLK cycles for Stop Mode entry and exit each) which must be added to the Stop Mode
recovery time tSTP_REC from exit of current Stop Mode to entry of next Stop Mode. This latency time
occurs no matter which Stop Mode (Full, Pseudo) is currently exited or entered next.
After exit from Stop Mode (Pseudo, Full) for this latency time of 2 ACLK cycles no Stop Mode request
(STOP instruction) should be generated to make sure the COP counter can increment at each Stop Mode
exit.
Table 4-31 gives an overview of the COP condition (run, static) in Stop Mode depending on legal
configuration and status bit settings:
Table 4-31. COP condition (run, static) in Stop Mode
COPOSCSEL1 CSAD PSTP PCE COPOSCSEL0 OSCE UPOSC COP counter behavior in Stop Mode
(clock source)
1 0 x x x x x Run (ACLK)
1 1 x x x x x Static (ACLK)
0 x 1 1 1 1 1 Run (OSCCLK)
0 x 1 1 0 0 x Static (IRCCLK)
0 x 1 1 0 1 x Static (IRCCLK)
0 x 1 0 0 x x Static (IRCCLK)
0 x 1 0 1 1 1 Static (OSCCLK)
0 x 0 1 1 1 1 Static (OSCCLK)
0 x 0 1 0 1 x Static (IRCCLK)
0 x 0 1 0 0 0 Static (IRCCLK)
0 x 0 0 1 1 1 Satic (OSCCLK)
0 x 0 0 0 1 1 Static (IRCCLK)
0 x 0 0 0 1 0 Static (IRCCLK)
0 x 0 0 0 0 0 Static (IRCCLK)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 171
Three control bits in the CPMUCOP register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP
register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the
program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55
or $AA is written, a COP reset is generated.
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to
the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out
period. A premature write will immediately reset the part.
In MCU Normal Mode the COP time-out period (CR[2:0]) and COP window (WCOP) setting can be
automatically pre-loaded at reset release from NVM memory (if values are defined in the NVM by the
application). By default the COP is off and no window COP feature is enabled after reset release via NVM
memory. The COP control register CPMUCOP can be written once in an application in MCU Normal
Mode to update the COP time-out period (CR[2:0]) and COP window (WCOP) setting loaded from NVM
memory at reset release. Any value for the new COP time-out period and COP window setting is allowed
except COP off value if the COP was enabled during pre-load via NVM memory.
The COP clock source select bits can not be pre-loaded via NVM memory at reset release. The IRC clock
is the default COP clock source out of reset.
The COP clock source select bits (COPOSCSEL0/1) and ACLK clock control bit in Stop Mode (CSAD)
can be modified until the CPMUCOP register write once has taken place. Therefore these control bits
should be modified before the final COP time-out period and window COP setting is written.
The CPMUCOP register access to modify the COP time-out period and window COP setting in MCU
Normal Mode after reset release must be done with the WRTMASK bit cleared otherwise the update is
ignored and this access does not count as the write once.
4.5.3 Power-On Reset (POR)
The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage
level. The POR is deasserted, if the internal supply VDD exceeds an appropriate voltage level (voltage
levels not specified in this document because this internal supply is not visible on device pins).
4.5.4 Low-Voltage Reset (LVR)
The on-chip LVR circuitry detects when one of the supply voltages VDD, VDDX and VDDF drops below
an appropriate voltage level. If LVR is deasserted the MCU is fully operational at the specified maximum
speed. The LVR assert and deassert levels for the supply voltage VDDX are VLVRXA and VLVRXD and are
specified in the device Reference Manual.
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
172 Freescale Semiconductor
4.6 Interrupts
The interrupt/reset vectors requested by the S12CPMU_UHV are listed in Table 4-32. Refer to MCU
specification for related vector addresses and priorities.
4.6.1 Description of Interrupt Operation
4.6.1.1 Real Time Interrupt (RTI)
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), RTIOSCSEL=1 and PRE=1 the RTI continues to
run, else the RTI counter halts in Stop Mode.
The RTI can be used to generate hardware interrupts at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the CPMURTI register. At the end of the RTI
time-out period the RTIF flag is set to one and a new RTI time-out period starts immediately.
A write to the CPMURTI register restarts the RTI time-out period.
4.6.1.2 PLL Lock Interrupt
The S12CPMU_UHV generates a PLL Lock interrupt when the lock condition (LOCK status bit) of the
PLL changes, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally
disabled by setting the LOCKIE bit to zero. The PLL Lock interrupt flag (LOCKIF) is set to1 when the
lock condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
4.6.1.3 Oscillator Status Interrupt
When the OSCE bit is 0, then UPOSC stays 0. When OSCE=1 the UPOSC bit is set after the LOCK bit is
set.
Table 4-32. S12CPMU_UHV Interrupt Vectors
Interrupt Source CCR
Mask Local Enable
RTI time-out interrupt I bit CPMUINT (RTIE)
PLL lock interrupt I bit CPMUINT (LOCKIE)
Oscillator status
interrupt I bit CPMUINT (OSCIE)
Low voltage interrupt I bit CPMULVCTL (LVIE)
High temperature
interrupt I bit CPMUHTCTL (HTIE)
Autonomous
Periodical Interrupt I bit CPMUAPICTL (APIE)
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 173
Upon detection of a status change (UPOSC) the OSCIF flag is set. Going into Full Stop Mode or disabling
the oscillator can also cause a status change of UPOSC.
Any change in PLL configuration or any other event which causes the PLL lock status to be cleared leads
to a loss of the oscillator status information as well (UPOSC=0).
Oscillator status change interrupts are locally enabled with the OSCIE bit.
NOTE
Loosing the oscillator status (UPOSC=0) affects the clock configuration of
the system1. This needs to be dealt with in application software.
4.6.1.4 Low-Voltage Interrupt (LVI)
In FPM the input voltage VDDA is monitored. Whenever VDDA drops below level VLVIA, the status bit
LVDS is set to 1. When VDDA rises above level VLVID the status bit LVDS is cleared to 0. An interrupt,
indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE
= 1.
4.6.1.5 HTI - High Temperature Interrupt
In FPM the junction temperature TJis monitored. Whenever TJ exceeds level THTIA the status bit HTDS
is set to 1. Vice versa, HTDS is reset to 0 when TJ get below level THTID. An interrupt, indicated by flag
HTIF = 1, is triggered by any change of the status bit HTDS, if interrupt enable bit HTIE = 1.
4.6.1.6 Autonomous Periodical Interrupt (API)
The API sub-block can generate periodical interrupts independent of the clock source of the MCU. To
enable the timer, the bit APIFE needs to be set.
The API timer is either clocked by the Autonomous Clock (ACLK - trimmable internal RC oscillator) or
the Bus Clock. Timer operation will freeze when MCU clock source is selected and Bus Clock is turned
off. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is not
set.
The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is
cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When
the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered
if interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF.
The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or
APIR[15:0], and afterwards set APIFE.
The API Trimming bits ACLKTR[5:0] must be set so the minimum period equals 0.2 ms if stable
frequency is desired.
See Table 4-19 for the trimming effect of ACLKTR.
1. For details please refer to “4.4.6 System Clock Configurations”
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
MC9S12VR Family Reference Manual, Rev. 2.8
174 Freescale Semiconductor
NOTE
The first period after enabling the counter by APIFE might be reduced by
API start up delay tsdel.
It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and
enabling the external access with setting APIEA.
4.7 Initialization/Application Information
4.7.1 General Initialization information
Usually applications run in MCU Normal Mode.
It is recommended to write the CPMUCOP register in any case from the application program initialization
routine after reset no matter if the COP is used in the application or not, even if a configuration is loaded
via the flash memory after reset. By doing a “controlled” write access in MCU Normal Mode (with the
right value for the application) the write once for the COP configuration bits (WCOP,CR[2:0]) takes place
which protects these bits from further accidental change. In case of a program sequencing issue (code
runaway) the COP configuration can not be accidentally modified anymore.
4.7.2 Application information for COP and API usage
In many applications the COP is used to check that the program is running and sequencing properly. Often
the COP is kept running during Stop Mode and periodic wake-up events are needed to service the COP on
time and maybe to check the system status.
For such an application it is recommended to use the ACLK as clock source for both COP and API. This
guarantees lowest possible IDD current during Stop Mode.Additionally it eases software implementation
using the same clock source for both, COP and API.
The Interrupt Service Routine (ISR) of the Autonomous Periodic Interrupt API should contain the write
instruction to the CPMUARMCOP register. The value (byte) written is derived from the “main routine”
(alternating sequence of $55 and $AA) of the application software.
Using this method, then in the case of a runtime or program sequencing issue the application “main
routine” is not executed properly anymore and the alternating values are not provided properly. Hence the
COP is written at the correct time (due to independent API interrupt request) but the wrong value is written
(alternating sequence of $55 and $AA is no longer maintained) which causes a COP reset.
If the COP is stopped during any Stop Mode it is recommended to service the COP shortly before Stop
Mode is entered.
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 175
Chapter 5
Background Debug Module (S12SBDMV1)
Table 5-1. Revision History
5.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S
core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
• TAGGO command not supported by S12SBDM
• External instruction tagging feature is part of the DBG module
• S12SBDM register map and register content modified
• Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
• Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)
5.1.1 Features
The BDM includes these distinctive features:
• Single-wire communication with host development system
• Enhanced capability for allowing more flexibility in clock rates
• SYNC command to determine communication rate
• GO_UNTIL command
• Hardware handshake protocol to increase the performance of the serial communication
Revision Number Date Summary of Changes
1.03 14.May.2009 Internal Conditional text only
1.04 30.Nov.2009 Internal Conditional text only
1.05 07.Dec.2010 Standardized format of revision history table header.
Background Debug Module (S12SBDMV1)
MC9S12VR Family Reference Manual, Rev. 2.8
176 Freescale Semiconductor
• Active out of reset in special single chip mode
• Nine hardware commands using free cycles, if available, for minimal CPU intervention
• Hardware commands not requiring active BDM
• 14 firmware commands execute from the standard BDM firmware lookup table
• Software control of BDM operation during wait mode
• When secured, hardware commands are allowed to access the register space in special single chip
mode, if the Flash erase tests fail.
• Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
• BDM hardware commands are operational until system stop mode is entered
5.1.2 Modes of Operation
BDM is available in all operating modes but must be enabled before firmware commands are executed.
Some systems may have a control bit that allows suspending the function during background debug mode.
5.1.2.1 Regular Run Modes
All of these operations refer to the part in run mode and not being secured. The BDM does not provide
controls to conserve power during run mode.
• Normal modes
General operation of the BDM is available and operates the same in all normal modes.
• Special single chip mode
In special single chip mode, background operation is enabled and active out of reset. This allows
programming a system with blank memory.
5.1.2.2 Secure Mode Operation
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run
mode operation. Secure operation prevents access to Flash other than allowing erasure. For more
information please see Section 5.4.1, “Security”.
5.1.2.3 Low-Power Modes
The BDM can be used until stop mode is entered. When CPU is in wait mode all BDM firmware
commands as well as the hardware BACKGROUND command cannot be used and are ignored. In this case
the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also
the CPU can not enter a low power mode (stop or wait) during BDM active mode.
In stop mode the BDM clocks are stopped. When BDM clocks are disabled and stop mode is exited, the
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in
progress and disable the ACK function). The BDM is now ready to receive a new command.
Background Debug Module (S12SBDMV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 177
5.1.3 Block Diagram
A block diagram of the BDM is shown in Figure 5-1.
Figure 5-1. BDM Block Diagram
5.2 External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode. The communication rate of this pin is based on the settings for the VCO clock
(CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8. After reset the
BDM clock is based on the reset values of the CPMUSYNR register (4 MHz). When modifying the VCO
clock please make sure that the communication rate is adapted accordingly and a communication time-out
(BDM soft reset) has occurred.
5.3 Memory Map and Register Definition
5.3.1 Module Memory Map
Table 5-2 shows the BDM memory map when BDM is active.
16-Bit Shift Register
BKGD
Host
System Serial
Interface Data
Control
Register Block
Register
BDMSTS
Instruction Code
and
Execution
Standard BDM Firmware
LOOKUP TABLE
Secured BDM Firmware
LOOKUP TABLE
Bus Interface
and
Control Logic
Address
Data
Control
Clocks
BDMACT
TRACE
ENBDM
SDV
UNSEC
Background Debug Module (S12SBDMV1)
MC9S12VR Family Reference Manual, Rev. 2.8
178 Freescale Semiconductor
5.3.2 Register Descriptions
A summary of the registers associated with the BDM is shown in Figure 5-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Table 5-2. BDM Memory Map
Global Address Module Size
(Bytes)
0x3_FF00–0x3_FF0B BDM registers 12
0x3_FF0C–0x3_FF0E BDM firmware ROM 3
0x3_FF0F Family ID (part of BDM firmware ROM) 1
0x3_FF10–0x3_FFFF BDM firmware ROM 240
Global
Address
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
0x3_FF00 Reserved R X X X X X X 0 0
W
0x3_FF01 BDMSTS R ENBDM BDMACT 0 SDV TRACE 0 UNSEC 0
W
0x3_FF02 Reserved R X X X X X X X X
W
0x3_FF03 Reserved R X X X X X X X X
W
0x3_FF04 Reserved R X X X X X X X X
W
0x3_FF05 Reserved R X X X X X X X X
W
0x3_FF06 BDMCCR R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
W
0x3_FF07 Reserved R 0 0 0 0 0 0 0 0
W
= Unimplemented, Reserved = Implemented (do not alter)
X = Indeterminate 0 = Always read zero
Figure 5-2. BDM Register Summary
Background Debug Module (S12SBDMV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 179
5.3.2.1 BDM Status Register (BDMSTS)
Figure 5-3. BDM Status Register (BDMSTS)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
— ENBDM should only be set via a BDM hardware command if the BDM firmware commands
are needed. (This does not apply in special single chip mode).
— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by
the standard BDM firmware lookup table upon exit from BDM active mode.
0x3_FF08 BDMPPR R BPAE 000
BPP3 BPP2 BPP1 BPP0
W
0x3_FF09 Reserved R 0 0 0 0 0 0 0 0
W
0x3_FF0A Reserved R 0 0 0 0 0 0 0 0
W
0x3_FF0B Reserved R 0 0 0 0 0 0 0 0
W
Register Global Address 0x3_FF01
7 6 543 2 1 0
RENBDM BDMACT 0SDVTRACE 0 UNSEC 0
W
Reset
Special Single-Chip Mode 01
1ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (Flash). This is because the ENBDM bit is set by the standard BDM firmware before a BDM command can be fully
transmitted and executed.
1000 0 02
2UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
0
All Other Modes 0 0 000 0 0 0
= Unimplemented, Reserved = Implemented (do not alter)
0 = Always read zero
Global
Address
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented, Reserved = Implemented (do not alter)
X = Indeterminate 0 = Always read zero
Figure 5-2. BDM Register Summary (continued)
Background Debug Module (S12SBDMV1)
MC9S12VR Family Reference Manual, Rev. 2.8
180 Freescale Semiconductor
— All other bits, while writable via BDM hardware or standard BDM firmware write commands,
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
Table 5-3. BDMSTS Field Descriptions
Field Description
7
ENBDM
Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made
active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM
hardware commands are still allowed.
0 BDM disabled
1 BDM enabled
Note: ENBDM is set out of reset in special single chip mode. In special single chip mode with the device
secured, this bit will not be set until after the Flash erase verify tests are complete.
6
BDMACT
BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is
then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the
standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from
the map.
0 BDM not active
1 BDM active
4
SDV
Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as
part of a BDM firmware or hardware read command or after data has been received as part of a BDM firmware
or hardware write command. It is cleared when the next BDM command has been received or BDM is exited.
SDV is used by the standard BDM firmware to control program flow execution.
0 Data phase of command not complete
1 Data phase of command is complete
3
TRACE
TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 firmware
command is first recognized. It will stay set until BDM firmware is exited by one of the following BDM commands:
GO or GO_UNTIL.
0 TRACE1 command is not being executed
1 TRACE1 command is being executed
1
UNSEC
Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure
firmware. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled
and put into the memory map overlapping the standard BDM firmware lookup table.
The secure BDM firmware lookup table verifies that the on-chip Flash is erased. This being the case, the UNSEC
bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure
BDM firmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted.
0 System is in a secured mode.
1 System is in a unsecured mode.
Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip
Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the
system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect
when the security byte in the Flash EEPROM is configured for unsecure mode.
Background Debug Module (S12SBDMV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 181
Figure 5-4. BDM CCR Holding Register (BDMCCR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
NOTE
When BDM is made active, the CPU stores the content of its CCR register
in the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR
register in this CPU mode. Out of reset in all other modes the BDMCCR
register is read zero.
When entering background debug mode, the BDM CCR holding register is used to save the condition code
register of the user’s program. It is also used for temporary storage in the standard BDM firmware mode.
The BDM CCR holding register can be written to modify the CCR value.
5.3.2.2 BDM Program Page Index Register (BDMPPR)
Figure 5-5. BDM Program Page Register (BDMPPR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
Register Global Address 0x3_FF06
7 6 5 4 3 2 1 0
RCCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
W
Reset
Special Single-Chip Mode 1 1 0 0 1 0 0 0
All Other Modes 0 0 0 0 0 0 0 0
Register Global Address 0x3_FF08
7 6 5 4 3 2 1 0
RBPAE 0 0 0 BPP3 BPP2 BPP1 BPP0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented, Reserved
Table 5-4. BDMPPR Field Descriptions
Field Description
7
BPAE
BDM Program Page Access Enable Bit — BPAE enables program page access for BDM hardware and
firmware read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD
and WRITE_BD) can not be used for global accesses even if the BGAE bit is set.
0 BDM Program Paging disabled
1 BDM Program Paging enabled
3–0
BPP[3:0]
BDM Program Page Index Bits 3–0 — These bits define the selected program page. For more detailed
information regarding the program page window scheme, please refer to the S12S_MMC Block Guide.
Background Debug Module (S12SBDMV1)
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182 Freescale Semiconductor
5.3.3 Family ID Assignment
The family ID is an 8-bit value located in the BDM ROM in active BDM (at global address: 0x3_FF0F).
The read-only value is a unique family ID which is 0xC2 for devices with an HCS12S core.
5.4 Functional Description
The BDM receives and executes commands from a host via a single wire serial interface. There are two
types of BDM commands: hardware and firmware commands.
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode, see Section 5.4.3, “BDM Hardware Commands”. Target system memory
includes all memory that is accessible by the CPU.
Firmware commands are used to read and write CPU resources and to exit from active background debug
mode, see Section 5.4.4, “Standard BDM Firmware Commands”. The CPU resources referred to are the
accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).
Hardware commands can be executed at any time and in any mode excluding a few exceptions as
highlighted (see Section 5.4.3, “BDM Hardware Commands”) and in secure mode (see Section 5.4.1,
“Security”). BDM firmware commands can only be executed when the system is not secure and is in active
background debug mode (BDM).
5.4.1 Security
If the user resets into special single chip mode with the system secured, a secured mode BDM firmware
lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table.
The secure BDM firmware verifies that the on-chip Flash EEPROM are erased. This being the case, the
UNSEC and ENBDM bit will get set. The BDM program jumps to the start of the standard BDM firmware
and the secured mode BDM firmware is turned off and all BDM commands are allowed. If the Flash does
not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware
enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the
firmware commands. This allows the BDM hardware to be used to erase the Flash.
BDM operation is not possible in any other mode than special single chip mode when the device is secured.
The device can only be unsecured via BDM serial interface in special single chip mode. For more
information regarding security, please see the S12S_9SEC Block Guide.
5.4.2 Enabling and Activating BDM
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated
only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS)
register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire
interface, using a hardware command such as WRITE_BD_BYTE.
After being enabled, BDM is activated by one of the following1:
1. BDM is enabled and active immediately out of special single-chip reset.
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• Hardware BACKGROUND command
• CPU BGND instruction
• Breakpoint force or tag mechanism1
When BDM is activated, the CPU finishes executing the current instruction and then begins executing the
firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type
of breakpoint used determines if BDM becomes active before or after execution of the next instruction.
NOTE
If an attempt is made to activate BDM before being enabled, the CPU
resumes normal instruction execution after a brief delay. If BDM is not
enabled, any hardware BACKGROUND commands issued are ignored by
the BDM and the CPU is not delayed.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses
0x3_FF00 to 0x3_FFFF. BDM registers are mapped to addresses 0x3_FF00 to 0x3_FF0B. The BDM uses
these registers which are readable anytime by the BDM. However, these registers are not readable by user
programs.
When BDM is activated while CPU executes code overlapping with BDM firmware space the saved
program counter (PC) will be auto incremented by one from the BDM firmware, no matter what caused
the entry into BDM active mode (BGND instruction, BACKGROUND command or breakpoints). In such
a case the PC must be set to the next valid address via a WRITE_PC command before executing the GO
command.
5.4.3 BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode. Target system memory includes all memory that is accessible by the CPU such
as on-chip RAM, Flash, I/O and control registers.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to
be in active BDM for execution, although, they can still be executed in this mode. When executing a
hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not
disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is
momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation
does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,
if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the
BDM found a free cycle.
The BDM hardware commands are listed in Table 5-5.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations
are not normally in the system memory map but share addresses with the application in memory. To
distinguish between physical memory locations that share the same address, BDM memory resources are
1. This method is provided by the S12S_DBG module.
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enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM
locations unobtrusively, even if the addresses conflict with the application memory map.
5.4.4 Standard BDM Firmware Commands
BDM firmware commands are used to access and manipulate CPU resources. The system must be in active
BDM to execute standard BDM firmware commands, see Section 5.4.2, “Enabling and Activating BDM”.
Normal instruction execution is suspended while the CPU executes the firmware located in the standard
BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM.
As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become
visible in the on-chip memory map at 0x3_FF00–0x3_FFFF, and the CPU begins executing the standard
BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are
received.
The firmware commands are shown in Table 5-6.
Table 5-5. Hardware Commands
Command Opcode
(hex) Data Description
BACKGROUND 90 None Enter background mode if BDM is enabled. If enabled, an ACK will be issued
when the part enters active background mode.
ACK_ENABLE D5 None Enable Handshake. Issues an ACK pulse after the command is executed.
ACK_DISABLE D6 None Disable Handshake. This command does not issue an ACK pulse.
READ_BD_BYTE E4 16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
READ_BD_WORD EC 16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table in map.
Must be aligned access.
READ_BYTE E0 16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
READ_WORD E8 16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table out of map.
Must be aligned access.
WRITE_BD_BYTE C4 16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
WRITE_BD_WORD CC 16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table in map.
Must be aligned access.
WRITE_BYTE C0 16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
WRITE_WORD C8 16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table out of map.
Must be aligned access.
NOTE:
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is
complete for all BDM WRITE commands.
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5.4.5 BDM Command Structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a
16-bit data word, depending on the command. All the read commands return 16 bits of data despite the
byte or word implication in the command name.
8-bit reads return 16-bits of data, only one byte of which contains valid data.
If reading an even address, the valid data will appear in the MSB. If reading
an odd address, the valid data will appear in the LSB.
Table 5-6. Firmware Commands
Command1
1If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is
complete for all BDM WRITE commands.
Opcode
(hex) Data Description
READ_NEXT2
2When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources
are accessed rather than user code. Writing BDM firmware is not possible.
62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to.
READ_PC 63 16-bit data out Read program counter.
READ_D 64 16-bit data out Read D accumulator.
READ_X 65 16-bit data out Read X index register.
READ_Y 66 16-bit data out Read Y index register.
READ_SP 67 16-bit data out Read stack pointer.
WRITE_NEXT242 16-bit data in Increment X index register by 2 (X = X + 2), then write word to location
pointed to by X.
WRITE_PC 43 16-bit data in Write program counter.
WRITE_D 44 16-bit data in Write D accumulator.
WRITE_X 45 16-bit data in Write X index register.
WRITE_Y 46 16-bit data in Write Y index register.
WRITE_SP 47 16-bit data in Write stack pointer.
GO 08 none Go to user program. If enabled, ACK will occur when leaving active
background mode.
GO_UNTIL3
3System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode).
The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the “UNTIL”
condition (BDM active again) is reached (see Section 5.4.7, “Serial Interface Hardware Handshake Protocol” last note).
0C none Go to user program. If enabled, ACK will occur upon returning to active
background mode.
TRACE1 10 none Execute one user instruction then return to active BDM. If enabled,
ACK will occur upon returning to active background mode.
TAGGO -> GO 18 none (Previous enable tagging and go to user program.)
This command will be deprecated and should not be used anymore.
Opcode will be executed as a GO command.
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16-bit misaligned reads and writes are generally not allowed. If attempted
by BDM hardware command, the BDM ignores the least significant bit of
the address and assumes an even address from the remaining bits.
For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending
the address before attempting to obtain the read data. This is to be certain that valid data is available in the
BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait
150 bus clock cycles after sending the data to be written before attempting to send a new command. This
is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle
delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a
free cycle before stealing a cycle.
For BDM firmware read commands, the external host should wait at least 48 bus clock cycles after sending
the command opcode and before attempting to obtain the read data. The 48 cycle wait allows enough time
for the requested data to be made available in the BDM shift register, ready to be shifted out.
For BDM firmware write commands, the external host must wait 36 bus clock cycles after sending the data
to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register
before the write has been completed.
The external host should wait for at least for 76 bus clock cycles after a TRACE1 or GO command before
starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM
firmware lookup table and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM firmware lookup table.
NOTE
If the bus rate of the target processor is unknown or could be changing, it is
recommended that the ACK (acknowledge function) is used to indicate
when an operation is complete. When using ACK, the delay times are
automated.
Figure 5-6 represents the BDM command structure. The command blocks illustrate a series of eight bit
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.1
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 5.4.6, “BDM Serial Interface”
and Section 5.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected.
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Figure 5-6. BDM Command Structure
5.4.6 BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed based on the VCO clock (please refer to the CPMU Block Guide for
more details), which gets divided by 8. This clock will be referred to as the target clock in the following
explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
The timing for host-to-target is shown in Figure 5-7 and that of target-to-host in Figure 5-8 and
Figure 5-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since
the host and target are operating from separate clocks, it can take the target system up to one full clock
cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the
host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle
Hardware
Hardware
Firmware
Firmware
GO,
48-BC
BC = Bus Clock Cycles
Command Address
150-BC
Delay
Next
DELAY
8 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
Command Address Data Next
Data
Read
Write
Read
Write
TRACE
Command Next
Command Data
76-BC
Delay
Next
Command
150-BC
Delay
36-BC
DELAY
Command
Command
Command
Command
Data
Next
Command
TC = Target Clock Cycles
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earlier. Synchronization between the host and target is established in this manner at the start of every bit
time.
Figure 5-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven
signals.
Figure 5-7. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 5-8 shows the host receiving a logic 1 from the target
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
Target Senses Bit
10 Cycles
Synchronization
Uncertainty
BDM Clock
(Target MCU)
Host
Transmit 1
Host
Transmit 0
Perceived
Start of Bit Time Earliest
Start of
Next Bit
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Figure 5-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 5-9 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target,
there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit
time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives
it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting
the bit time.
Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
High-Impedance
Earliest
Start of
Next Bit
R-C Rise
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Perceived
Start of Bit Time
BKGD Pin
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
Target System
Speedup
Pulse
High-Impedance
High-Impedance
Earliest
Start of
Next Bit
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
BKGD Pin
Perceived
Start of Bit Time
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Target System
Drive and
Speedup Pulse
Speedup Pulse
High-Impedance
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5.4.7 Serial Interface Hardware Handshake Protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM
clock source can be modified when changing the settings for the VCO frequency (CPMUSYNR), it is very
helpful to provide a handshake protocol in which the host could determine when an issued command is
executed by the CPU. The BDM clock frequency is always VCO frequency divided by 8. The alternative
is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate
the clock could be running. This sub-section will describe the hardware handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully
executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a
brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued
by the host, has been successfully executed (see Figure 5-10). This pulse is referred to as the ACK pulse.
After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read
command, or start a new command if the last command was a write command or a control command
(BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock
cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick
of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also
that, there is no upper limit for the delay between the command and the related ACK pulse, since the
command execution depends upon the CPU bus, which in some cases could be very slow due to long
accesses taking place.This protocol allows a great flexibility for the POD designers, since it does not rely
on any accurate time measurement or short response time to any event in the serial communication.
Figure 5-10. Target Acknowledge Pulse (ACK)
NOTE
If the ACK pulse was issued by the target, the host assumes the previous
command was executed. If the CPU enters wait or stop prior to executing a
hardware command, the ACK pulse will not be issued meaning that the
BDM command was not executed. After entering wait or stop mode, the
BDM command is no longer pending.
16 Cycles
BDM Clock
(Target MCU)
Target
Transmits
ACK Pulse
High-Impedance
BKGD Pin
Minimum Delay
From the BDM Command
32 Cycles
Earliest
Start of
Next Bit
Speedup Pulse
16th Tick of the
Last Command Bit
High-Impedance
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Figure 5-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE
instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the
address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed
(free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the
BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved.
After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form
of a word and the host needs to determine which is the appropriate byte based on whether the address was
odd or even.
Figure 5-11. Handshake Protocol at Command Level
Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK
handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware
handshake protocol in Figure 5-10 specifies the timing when the BKGD pin is being driven, so the host
should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin.
NOTE
The only place the BKGD pin can have an electrical conflict is when one
side is driving low and the other side is issuing a speedup pulse (high). Other
“highs” are pulled rather than driven. However, at low rates the time of the
speedup pulse can become lengthy and so the potential conflict time
becomes longer as well.
The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not
acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to
issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command
(e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected.
Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be
issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any
possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol
provides a mechanism in which a command, and its corresponding ACK, can be aborted.
READ_BYTE
BDM Issues the
BKGD Pin Byte Address
BDM Executes the
READ_BYTE Command
Host Target
HostTarget
BDM Decodes
the Command
ACK Pulse (out of scale)
Host Target
(2) Bytes are
Retrieved
New BDM
Command
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NOTE
The ACK pulse does not provide a time out. This means for the GO_UNTIL
command that it can not be distinguished if a stop or wait has been executed
(command discarded and ACK not issued) or if the “UNTIL” condition
(BDM active) is just not reached yet. Hence in any case where the ACK
pulse of a command is not issued the possible pending command should be
aborted before issuing a new command. See the handshake abort procedure
described in Section 5.4.8, “Hardware Handshake Abort Procedure”.
5.4.8 Hardware Handshake Abort Procedure
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued
the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving
it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a
speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol,
see Section 5.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command
and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been
completed the host is free to issue new BDM commands. For BDM firmware READ or WRITE commands
it can not be guaranteed that the pending command is aborted when issuing a SYNC before the
corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins
until it is finished and the corresponding ACK pulse is issued. The latency time depends on the firmware
READ or WRITE command that is issued and on the selected bus clock rate. When the SYNC command
starts during this latency time the READ or WRITE command will not be aborted, but the corresponding
ACK pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL command can not be aborted. Only
the corresponding ACK pulse can be aborted by the SYNC command.
Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in
the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command.
The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short
abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative
edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending
command will be aborted along with the ACK pulse. The potential problem with this abort procedure is
when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not
perceive the abort pulse. The worst case is when the pending command is a read command (i.e.,
READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new
command after the abort pulse was issued, while the target expects the host to retrieve the accessed
memory byte. In this case, host and target will run out of synchronism. However, if the command to be
aborted is not a read command the short abort pulse could be used. After a command is aborted the target
assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command.
NOTE
The details about the short abort pulse are being provided only as a reference
for the reader to better understand the BDM internal behavior. It is not
recommended that this procedure be used in a real application.
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Since the host knows the target serial clock frequency, the SYNC command (used to abort a command)
does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC
very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to
assure the SYNC pulse will not be misinterpreted by the target. See Section 5.4.9, “SYNC — Request
Timed Reference Pulse”.
Figure 5-12 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE
command. Note that, after the command is aborted a new command could be issued by the host computer.
Figure 5-12. ACK Abort Procedure at the Command Level
NOTE
Figure 5-12 does not represent the signals in a true timing scale
Figure 5-13 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not
a probable situation, the protocol does not prevent this conflict from happening.
Figure 5-13. ACK Pulse and SYNC Request Conflict
READ_BYTE READ_STATUSBKGD Pin Memory Address New BDM Command
New BDM Command
Host Target Host Target Host Target
SYNC Response
From the Target
(Out of Scale)
BDM Decode
and Starts to Execute
the READ_BYTE Command
READ_BYTE CMD is Aborted
by the SYNC Request
(Out of Scale)
BDM Clock
(Target MCU)
Target MCU
Drives to
BKGD Pin
BKGD Pin
16 Cycles
Speedup Pulse
High-Impedance
Host
Drives SYNC
To BKGD Pin
ACK Pulse
Host SYNC Request Pulse
At Least 128 Cycles
Electrical Conflict
Host and
Target Drive
to BKGD Pin
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NOTE
This information is being provided so that the MCU integrator will be aware
that such a conflict could occur.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDM commands. This provides backwards compatibility with the existing POD devices which are not
able to execute the hardware handshake protocol. It also allows for new POD devices, that support the
hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
The commands are described as follows:
• ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse
when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the
ACK pulse as a response.
• ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst
case delay time at the appropriate places in the protocol.
The default state of the BDM after reset is hardware handshake protocol disabled.
All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then
ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data
has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See
Section 5.4.3, “BDM Hardware Commands” and Section 5.4.4, “Standard BDM Firmware Commands”
for more information on the BDM commands.
The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be
used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is
issued in response to this command, the host knows that the target supports the hardware handshake
protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In
this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid
command.
The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to
background mode. The ACK pulse related to this command could be aborted using the SYNC command.
The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse
related to this command could be aborted using the SYNC command.
The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this
case, is issued when the CPU enters into background mode. This command is an alternative to the GO
command and should be used when the host wants to trace if a breakpoint match occurs and causes the
CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which
could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related
to this command could be aborted using the SYNC command.
The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode
after one instruction of the application program is executed. The ACK pulse related to this command could
be aborted using the SYNC command.
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5.4.9 SYNC — Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the
correct communication speed to use for BDM communications until after it has analyzed the response to
the SYNC command. To issue a SYNC command, the host should perform the following steps:
1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication
frequency (The lowest serial communication frequency is determined by the settings for the VCO
clock (CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8.)
2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically
one cycle of the host clock.)
3. Remove all drive to the BKGD pin so it reverts to high impedance.
4. Listen to the BKGD pin for the sync response pulse.
Upon detecting the SYNC request from the host, the target performs the following steps:
1. Discards any incomplete command received or bit retrieved.
2. Waits for BKGD to return to a logic one.
3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.
4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.
5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.
6. Removes all drive to the BKGD pin so it reverts to high impedance.
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed
for subsequent BDM communications. Typically, the host can determine the correct communication speed
within a few percent of the actual target speed and the communication protocol can easily tolerate speed
errors of several percent.
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is
discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the
SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new
BDM command or the start of new SYNC request.
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the
same as in a regular SYNC command. Note that one of the possible causes for a command to not be
acknowledged by the target is a host-target synchronization problem. In this case, the command may not
have been understood by the target and so an ACK response pulse will not be issued.
5.4.10 Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM
firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to
return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the
TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or
tracing through the user code one instruction at a time.
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If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but
no user instruction is executed. Once back in standard BDM firmware execution, the program counter
points to the first instruction in the interrupt service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step but
all peripherals are free running. Hence possible timing relations between CPU code execution and
occurrence of events of other peripherals no longer exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will
result in a return address pointing to BDM firmware address space.
When tracing through user code which contains stop or wait instructions the following will happen when
the stop or wait instruction is traced:
The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving
the low power mode. This is the case because BDM active mode can not be entered after CPU
executed the stop instruction. However all BDM hardware commands except the BACKGROUND
command are operational after tracing a stop or wait instruction and still being in stop or wait
mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is
operational.
As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value
points to the entry of the corresponding interrupt service routine.
In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command
will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM
active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode.
All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or
wait mode will have an ACK pulse. The handshake feature becomes disabled only when system
stop mode has been reached. Hence after a system stop mode the handshake feature must be
enabled again by sending the ACK_ENABLE command.
5.4.11 Serial Communication Time Out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If
BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command
was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the
SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any
time-out limit.
Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as
a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge
marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock
cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting
memory or the operating mode of the MCU. This is referred to as a soft-reset.
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will
occur causing the command to be disregarded. The data is not available for retrieval after the time-out has
occurred. This is the expected behavior if the handshake protocol is not enabled. In order to allow the data
to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware
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handshake protocol is enabled, the time out between a read command and the data retrieval is disabled.
Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data
from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the time-out
feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host
needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued.
After that period, the read command is discarded and the data is no longer available for retrieval. Any
negative edge in the BKGD pin after the time-out period is considered to be a new command or a SYNC
request.
Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the
serial communication is active. This means that if a time frame higher than 512 serial clock cycles is
observed between two consecutive negative edges and the command being issued or data being retrieved
is not complete, a soft-reset will occur causing the partially received command or data retrieved to be
disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the
target as the start of a new BDM command, or the start of a SYNC request pulse.
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Chapter 6
S12S Debug Module (S12SDBGV2)
Table 6-1. Revision History
6.1 Introduction
The S12SDBG module provides an on-chip trace buffer with flexible triggering capability to allow
non-intrusive debug of application software. The S12SDBG module is optimized for S12SCPU
debugging.
Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user
configures the S12SDBG module for a debugging session over the BDM interface. Once configured the
S12SDBG module is armed and the device leaves BDM returning control to the user program, which is
then monitored by the S12SDBG module. Alternatively the S12SDBG module can be configured over a
serial interface using SWI routines.
6.1.1 Glossary Of Terms
COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt.
BDM: Background Debug Mode
S12SBDM: Background Debug Module
DUG: Device User Guide, describing the features of the device into which the DBG is integrated.
WORD: 16 bit data entity
Data Line: 20 bit data entity
CPU: S12SCPU module
DBG: S12SDBG module
POR: Power On Reset
Revision Number Revision
Date
Sections
Affected Summary of Changes
02.07 13.DEC.2007
Section 6.5,
“Application
Information
Added application information
02.08 09.MAY.2008 General Spelling corrections. Revision history format changed.
02.09 29.MAY.2008 6.4.5.4 Added note for end aligned, PurePC, rollover case.
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Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches
the execution stage a tag hit occurs.
6.1.2 Overview
The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer
transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated.
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can
be triggered immediately by writing to the TRIG control bit.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
6.1.3 Features
• Three comparators (A, B and C)
— Comparators A compares the full address bus and full 16-bit data bus
— Comparator A features a data bus mask register
— Comparators B and C compare the full address bus only
— Each comparator features selection of read or write access cycles
— Comparator B allows selection of byte or word access cycles
— Comparator matches can initiate state sequencer transitions
• Three comparator modes
— Simple address/data comparator match mode
— Inside address range mode, Addmin ≤ Address ≤Addmax
— Outside address range match mode, Address <Addmin or Address > Addmax
• Two types of matches
— Tagged — This matches just before a specific instruction begins execution
— Force — This is valid on the first instruction boundary after a match occurs
• Two types of breakpoints
— CPU breakpoint entering BDM on breakpoint (BDM)
— CPU breakpoint executing SWI on breakpoint (SWI)
• Trigger mode independent of comparators
— TRIG Immediate software trigger
• Four trace modes
— Normal: change of flow (COF) PC information is stored (see Section 6.4.5.2.1, “Normal Mode)
for change of flow definition.
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Compressed Pure PC: all program counter addresses are stored
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• 4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin and End alignment of tracing to trigger
6.1.4 Modes of Operation
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When
the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already
armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
6.1.5 Block Diagram
Figure 6-1. Debug Module Block Diagram
Table 6-2. Mode Dependent Restriction Summary
BDM
Enable
BDM
Active
MCU
Secure
Comparator
Matches Enabled
Breakpoints
Possible
Tagging
Possible
Tracing
Possible
x x 1 Yes Yes Yes No
0 0 0 Yes Only SWI Yes Yes
0 1 0 Active BDM not possible when not enabled
1 0 0 Yes Yes Yes Yes
110 No No No No
CPU BUS
TRACE BUFFER
BUS INTERFACE
TRANSITION
MATCH0
STATE
COMPARATOR B
COMPARATOR C
COMPARATOR A
STATE SEQUENCER
MATCH1
MATCH2
TRACE
READ TRACE DATA (DBG READ DATA BUS)
CONTROL
SECURE
BREAKPOINT REQUESTS
COMPARATOR
MATCH CONTROL
TRIGGER
TAG &
MATCH
CONTROL
LOGIC
TAGS
TAGHITS
STATE
TO CPU
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6.2 External Signal Description
There are no external signals associated with this module.
6.3 Memory Map and Registers
6.3.1 Module Memory Map
A summary of the registers associated with the DBG sub-block is shown in Figure 6-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Address Name Bit 7 6 5 4 3 2 1 Bit 0
0x0020 DBGC1 RARM 00
BDM DBGBRK 0COMRV
W TRIG
0x0021 DBGSR R1TBF 0 0 0 0 SSF2 SSF1 SSF0
W
0x0022 DBGTCR R0TSOURCE 00 TRCMOD 0TALIGN
W
0x0023 DBGC2 R000000 ABCM
W
0x0024 DBGTBH R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
0x0025 DBGTBL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
0x0026 DBGCNT R1TBF 0 CNT
W
0x0027 DBGSCRX R0000
SC3 SC2 SC1 SC0
W
0x0027 DBGMFR R00000MC2MC1MC0
W
20x0028 DBGACTL RSZE SZ TAG BRK RW RWE NDB COMPE
W
30x0028 DBGBCTL RSZE SZ TAG BRK RW RWE 0COMPE
W
40x0028 DBGCCTL R0 0 TAG BRK RW RWE 0COMPE
W
0x0029 DBGXAH R000000
Bit 17 Bit 16
W
0x002A DBGXAM RBit 15 14 13 12 11 10 9 Bit 8
W
0x002B DBGXAL RBit 7 6 5 4 3 2 1 Bit 0
W
Figure 6-2. Quick Reference to DBG Registers
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6.3.2 Register Descriptions
This section consists of the DBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module
registers that can be written are ARM, TRIG, and COMRV[1:0]
6.3.2.1 Debug Control Register 1 (DBGC1)
Read: Anytime
Write: Bits 7, 1, 0 anytime
Bit 6 can be written anytime but always reads back as 0.
Bits 4:3 anytime DBG is not armed.
NOTE
When disarming the DBG by clearing ARM with software, the contents of
bits[4:3] are not affected by the write, since up until the write operation,
ARM = 1 preventing these bits from being written. These bits must be
cleared using a second write if required.
0x002C DBGADH RBit 15 14 13 12 11 10 9 Bit 8
W
0x002D DBGADL RBit 7 6 5 4 3 2 1 Bit 0
W
0x002E DBGADHM RBit 15 14 13 12 11 10 9 Bit 8
W
0x002F DBGADLM RBit 7 6 5 4 3 2 1 Bit 0
W
1This bit is visible at DBGCNT[7] and DBGSR[7]
2This represents the contents if the Comparator A control register is blended into this address.
3This represents the contents if the Comparator B control register is blended into this address
4This represents the contents if the Comparator C control register is blended into this address
Address: 0x0020
76543210
RARM 00
BDM DBGBRK 0COMRV
W TRIG
Reset 00000000
= Unimplemented or Reserved
Figure 6-3. Debug Control Register (DBGC1)
Address Name Bit 7 6 5 4 3 2 1 Bit 0
Figure 6-2. Quick Reference to DBG Registers
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6.3.2.2 Debug Status Register (DBGSR)
Table 6-3. DBGC1 Field Descriptions
Field Description
7
ARM
Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user
software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with
tracing not enabled. On setting this bit the state sequencer enters State1.
0 Debugger disarmed
1 Debugger armed
6
TRIG
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of state
sequencer status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK
and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If the
DBGTCR_TSOURCE bit is clear no tracing is carried out. If tracing has already commenced using BEGIN trigger
alignment, it continues until the end of the tracing session as defined by the TALIGN bit, thus TRIG has no affect.
In secure mode tracing is disabled and writing to this bit cannot initiate a tracing session.
The session is ended by setting TRIG and ARM simultaneously.
0 Do not trigger until the state sequencer enters the Final State.
1 Trigger immediately
4
BDM
Background Debug Mode Enable — This bit determines if a breakpoint causes the system to enter Background
Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the
ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
3
DBGBRK
S12SDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint
on reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion
of the tracing session. If tracing is not enabled, the breakpoint is generated immediately.
0 No Breakpoint generated
1 Breakpoint generated
1–0
COMRV
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See Table 6-4.
Table 6-4. COMRV Encoding
COMRV Visible Comparator Visible Register at 0x0027
00 Comparator A DBGSCR1
01 Comparator B DBGSCR2
10 Comparator C DBGSCR3
11 None DBGMFR
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Read: Anytime
Write: Never
Address: 0x0021
76543210
R TBF 0 0 0 0 SSF2 SSF1 SSF0
W
Reset
POR
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-4. Debug Status Register (DBGSR)
Table 6-5. DBGSR Field Descriptions
Field Description
7
TBF
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
Other system generated resets have no affect on this bit
This bit is also visible at DBGCNT[7]
2–0
SSF[2:0]
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal event, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 6-6.
Table 6-6. SSF[2:0] — State Sequence Flag Bit Encoding
SSF[2:0] Current State
000 State0 (disarmed)
001 State1
010 State2
011 State3
100 Final State
101,110,111 Reserved
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6.3.2.3 Debug Trace Control Register (DBGTCR)
Read: Anytime
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.
Address: 0x0022
76543210
R0 TSOURCE 00 TRCMOD 0TALIGN
W
Reset 00000000
Figure 6-5. Debug Trace Control Register (DBGTCR)
Table 6-7. DBGTCR Field Descriptions
Field Description
6
TSOURCE
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU
system is secured, this bit cannot be set and tracing is inhibited.
This bit must be set to read the trace buffer.
0 Debug session without tracing requested
1 Debug session with tracing requested
3–2
TRCMOD
Trace Mode Bits — See Section 6.4.5.2, “Trace Modes for detailed Trace Mode descriptions. In Normal Mode,
change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries
into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored.
In Compressed Pure PC mode the program counter value for each instruction executed is stored. See Table 6-8.
0
TALIGN
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0 Trigger at end of stored data
1 Trigger before storing data
Table 6-8. TRCMOD Trace Mode Bit Encoding
TRCMOD Description
00 Normal
01 Loop1
10 Detail
11 Compressed Pure PC
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6.3.2.4 Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
6.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)
Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set.
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer
contents.
Address: 0x0023
76543210
R000000 ABCM
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-6. Debug Control Register2 (DBGC2)
Table 6-9. DBGC2 Field Descriptions
Field Description
1–0
ABCM[1:0]
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in Table 6-10.
Table 6-10. ABCM Encoding
ABCM Description
00 Match0 mapped to comparator A match: Match1 mapped to comparator B match.
01 Match 0 mapped to comparator A/B inside range: Match1 disabled.
10 Match 0 mapped to comparator A/B outside range: Match1 disabled.
11 Reserved1
1Currently defaults to Comparator A, Comparator B disabled
Address: 0x0024, 0x0025
1514131211109876543210
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
PORXXXXXXXXXXXXXXXX
Other
Resets ————————————————
Figure 6-7. Debug Trace Buffer Register (DBGTB)
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Table 6-11. DBGTB Field Descriptions
Field Description
15–0
Bit[15:0]
Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 20-bit wide data lines of the
Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer
which points to the next address to be read. When the ARM bit is set the trace buffer is locked to prevent reading.
The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the
module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned
access of these registers return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. Similarly reads while the debugger is armed or with the TSOURCE bit clear, return 0 and do not affect
the trace buffer pointer. The POR state is undefined. Other resets do not affect the trace buffer contents.
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6.3.2.6 Debug Count Register (DBGCNT)
Read: Anytime
Write: Never
Address: 0x0026
76543210
R TBF 0 CNT
W
Reset
POR
—
0
—
0
—
0
—
0
—
0
—
0
—
0
—
0
= Unimplemented or Reserved
Figure 6-8. Debug Count Register (DBGCNT)
Table 6-12. DBGCNT Field Descriptions
Field Description
7
TBF
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
Other system generated resets have no affect on this bit
This bit is also visible at DBGSR[7]
5–0
CNT[5:0]
Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer.
Table 6-13 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in
end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT
register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset
occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer
entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace
buffer.
Table 6-13. CNT Decoding Table
TBF CNT[5:0] Description
0 000000 No data valid
0 000001
000010
000100
000110
..
111111
1 line valid
2 lines valid
4 lines valid
6 lines valid
..
63 lines valid
1 000000 64 lines valid; if using Begin trigger alignment,
ARM bit will be cleared and the tracing session ends.
1 000001
..
..
111110
64 lines valid,
oldest data has been overwritten by most recent data
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6.3.2.7 Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
Table 6-14. State Control Register Access Encoding
COMRV Visible State Control Register
00 DBGSCR1
01 DBGSCR2
10 DBGSCR3
11 DBGMFR
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6.3.2.7.1 Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 6-1 and described in 6.3.2.8.1. Comparators must be enabled by setting
the comparator enable bit in the associated DBGXCTL control register.
The priorities described in Table 6-36 dictate that in the case of simultaneous matches, a match leading to
final state has priority followed by the match on the lower channel number (0,1,2). Thus with
SC[3:0]=1101 a simultaneous match0/match1 transitions to final state.
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-9. Debug State Control Register 1 (DBGSCR1)
Table 6-15. DBGSCR1 Field Descriptions
Field Description
3–0
SC[3:0]
These bits select the targeted next state whilst in State1, based upon the match event.
Table 6-16. State1 Sequencer Next State Selection
SC[3:0] Description (Unspecified matches have no effect)
0000 Any match to Final State
0001 Match1 to State3
0010 Match2 to State2
0011 Match1 to State2
0100 Match0 to State2....... Match1 to State3
0101 Match1 to State3.........Match0 to Final State
0110 Match0 to State2....... Match2 to State3
0111 Either Match0 or Match1 to State2
1000 Reserved
1001 Match0 to State3
1010 Reserved
1011 Reserved
1100 Reserved
1101 Either Match0 or Match2 to Final State........Match1 to State2
1110 Reserved
1111 Reserved
S12S Debug Module (S12SDBGV2)
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212 Freescale Semiconductor
6.3.2.7.2 Debug State Control Register 2 (DBGSCR2)
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 6-1 and described in Section 6.3.2.8.1, “Debug Comparator Control
Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated
DBGXCTL control register.
The priorities described in Table 6-36 dictate that in the case of simultaneous matches, a match leading to
final state has priority followed by the match on the lower channel number (0,1,2)
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-10. Debug State Control Register 2 (DBGSCR2)
Table 6-17. DBGSCR2 Field Descriptions
Field Description
3–0
SC[3:0]
These bits select the targeted next state whilst in State2, based upon the match event.
Table 6-18. State2 —Sequencer Next State Selection
SC[3:0] Description (Unspecified matches have no effect)
0000 Match0 to State1....... Match2 to State3.
0001 Match1 to State3
0010 Match2 to State3
0011 Match1 to State3....... Match0 Final State
0100 Match1 to State1....... Match2 to State3.
0101 Match2 to Final State
0110 Match2 to State1..... Match0 to Final State
0111 Either Match0 or Match1 to Final State
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Either Match0 or Match1 to Final State........Match2 to State3
1101 Reserved
1110 Reserved
1111 Either Match0 or Match1 to Final State........Match2 to State1
S12S Debug Module (S12SDBGV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 213
6.3.2.7.3 Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 6-1 and described in Section 6.3.2.8.1, “Debug Comparator Control
Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated
DBGXCTL control register.
The priorities described in Table 6-36 dictate that in the case of simultaneous matches, a match leading to
final state has priority followed by the match on the lower channel number (0,1,2).
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-11. Debug State Control Register 3 (DBGSCR3)
Table 6-19. DBGSCR3 Field Descriptions
Field Description
3–0
SC[3:0]
These bits select the targeted next state whilst in State3, based upon the match event.
Table 6-20. State3 — Sequencer Next State Selection
SC[3:0] Description (Unspecified matches have no effect)
0000 Match0 to State1
0001 Match2 to State2........ Match1 to Final State
0010 Match0 to Final State....... Match1 to State1
0011 Match1 to Final State....... Match2 to State1
0100 Match1 to State2
0101 Match1 to Final State
0110 Match2 to State2........ Match0 to Final State
0111 Match0 to Final State
1000 Reserved
1001 Reserved
1010 Either Match1 or Match2 to State1....... Match0 to Final State
1011 Reserved
1100 Reserved
1101 Either Match1 or Match2 to Final State....... Match0 to State1
1110 Match0 to State2....... Match2 to Final State
1111 Reserved
S12S Debug Module (S12SDBGV2)
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214 Freescale Semiconductor
6.3.2.7.4 Debug Match Flag Register (DBGMFR)
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further comparator matches on the same channel in the same session have no affect on that flag.
6.3.2.8 Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module
register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data
bus compare registers, two data bus mask registers and a control register). Comparator B consists of four
register bytes (three address bus compare registers and a control register). Comparator C consists of four
register bytes (three address bus compare registers and a control register).
Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register.
Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be
written. The control register for comparator B differs from those of comparators A and C.
6.3.2.8.1 Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Address: 0x0027
76543210
R00000MC2MC1MC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-12. Debug Match Flag Register (DBGMFR)
Table 6-21. Comparator Register Layout
0x0028 CONTROL Read/Write Comparators A,B and C
0x0029 ADDRESS HIGH Read/Write Comparators A,B and C
0x002A ADDRESS MEDIUM Read/Write Comparators A,B and C
0x002B ADDRESS LOW Read/Write Comparators A,B and C
0x002C DATA HIGH COMPARATOR Read/Write Comparator A only
0x002D DATA LOW COMPARATOR Read/Write Comparator A only
0x002E DATA HIGH MASK Read/Write Comparator A only
0x002F DATA LOW MASK Read/Write Comparator A only
S12S Debug Module (S12SDBGV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 215
Read: DBGACTL if COMRV[1:0] = 00
DBGBCTL if COMRV[1:0] = 01
DBGCCTL if COMRV[1:0] = 10
Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed
DBGBCTL if COMRV[1:0] = 01 and DBG not armed
DBGCCTL if COMRV[1:0] = 10 and DBG not armed
Address: 0x0028
76543210
RSZE SZ TAG BRK RW RWE NDB COMPE
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-13. Debug Comparator Control Register DBGACTL (Comparator A)
Address: 0x0028
76543210
RSZE SZ TAG BRK RW RWE 0COMPE
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-14. Debug Comparator Control Register DBGBCTL (Comparator B)
Address: 0x0028
76543210
R0 0 TAG BRK RW RWE 0COMPE
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-15. Debug Comparator Control Register DBGCCTL (Comparator C)
Table 6-22. DBGXCTL Field Descriptions
Field Description
7
SZE
(Comparators
A and B)
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
6
SZ
(Comparators
A and B)
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
0 Word access size is compared
1 Byte access size is compared
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216 Freescale Semiconductor
Table 6-23 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the
corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution
stage of the instruction queue.
5
TAG
Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate
state sequencer transition or tag the opcode at the matched address. Tagged opcodes trigger only if they
reach the execution stage of the instruction queue.
0 Allow state sequencer transition immediately on match
1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition
4
BRK
Break— This bit controls whether a comparator match terminates a debug session immediately, independent
of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled
using the DBGC1 bit DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
tracing, if active, is terminated and the module disarmed.
3
RW
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same
register is set.
0 Write cycle is matched1Read cycle is matched
2
RWE
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator.This bit is ignored if the TAG bit in the same register is set
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
1
NDB
(Comparator A)
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same
register is set. This bit is only available for comparator A.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
0
COMPE
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
Table 6-23. Read or Write Comparison Logic Table
RWE Bit RW Bit RW Signal Comment
0 x 0 RW not used in comparison
0 x 1 RW not used in comparison
1 0 0 Write data bus
1 0 1 No match
1 1 0 No match
1 1 1 Read data bus
Table 6-22. DBGXCTL Field Descriptions (continued)
Field Description
S12S Debug Module (S12SDBGV2)
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Freescale Semiconductor 217
6.3.2.8.2 Debug Comparator Address High Register (DBGXAH)
The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window
from 0x0028 to 0x002F as shown in Section Table 6-24., “Comparator Address Register Visibility
Table 6-24. Comparator Address Register Visibility
Read: Anytime. See Table 6-24 for visible register encoding.
Write: If DBG not armed. See Table 6-24 for visible register encoding.
6.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM)
Read: Anytime. See Table 6-24 for visible register encoding.
Write: If DBG not armed. See Table 6-24 for visible register encoding.
Address: 0x0029
76543210
R000000
Bit 17 Bit 16
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-16. Debug Comparator Address High Register (DBGXAH)
COMRV Visible Comparator
00 DBGAAH, DBGAAM, DBGAAL
01 DBGBAH, DBGBAM, DBGBAL
10 DBGCAH, DBGCAM, DBGCAL
11 None
Table 6-25. DBGXAH Field Descriptions
Field Description
1–0
Bit[17:16]
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator compares the address bus bits [17:16] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Address: 0x002A
76543210
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 6-17. Debug Comparator Address Mid Register (DBGXAM)
S12S Debug Module (S12SDBGV2)
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218 Freescale Semiconductor
6.3.2.8.4 Debug Comparator Address Low Register (DBGXAL)
Read: Anytime. See Table 6-24 for visible register encoding.
Write: If DBG not armed. See Table 6-24 for visible register encoding.
6.3.2.8.5 Debug Comparator Data High Register (DBGADH)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
Table 6-26. DBGXAM Field Descriptions
Field Description
7–0
Bit[15:8]
Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the
selected comparator compares the address bus bits [15:8] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Address: 0x002B
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 6-18. Debug Comparator Address Low Register (DBGXAL)
Table 6-27. DBGXAL Field Descriptions
Field Description
7–0
Bits[7:0]
Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the
selected comparator compares the address bus bits [7:0] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Address: 0x002C
76543210
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 6-19. Debug Comparator Data High Register (DBGADH)
S12S Debug Module (S12SDBGV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 219
6.3.2.8.6 Debug Comparator Data Low Register (DBGADL)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
6.3.2.8.7 Debug Comparator Data High Mask Register (DBGADHM)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
Table 6-28. DBGADH Field Descriptions
Field Description
7–0
Bits[15:8]
Comparator Data High Compare Bits— The Comparator data high compare bits control whether the selected
comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
Address: 0x002D
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 6-20. Debug Comparator Data Low Register (DBGADL)
Table 6-29. DBGADL Field Descriptions
Field Description
7–0
Bits[7:0]
Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected
comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
Address: 0x002E
76543210
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 6-21. Debug Comparator Data High Mask Register (DBGADHM)
S12S Debug Module (S12SDBGV2)
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220 Freescale Semiconductor
6.3.2.8.8 Debug Comparator Data Low Mask Register (DBGADLM)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
6.4 Functional Description
This section provides a complete functional description of the DBG module. If the part is in secure mode,
the DBG module can generate breakpoints but tracing is not possible.
6.4.1 S12SDBG Operation
Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data
in the trace buffer and generation of breakpoints to the CPU. The DBG module is made up of four main
blocks, the comparators, control logic, the state sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor
address bus activity. Comparator A can also be configured to monitor databus activity and mask out
individual data bus bits during a compare. Comparators can be configured to use R/W and word/byte
access qualification in the comparison. A match with a comparator register value can initiate a state
sequencer transition to another state (see Figure 6-24). Either forced or tagged matches are possible. Using
Table 6-30. DBGADHM Field Descriptions
Field Description
7–0
Bits[15:8]
Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected
comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. Data bus
comparisons are only performed if the TAG bit in DBGACTL is clear
0 Do not compare corresponding data bit Any value of corresponding data bit allows match.
1 Compare corresponding data bit
Address: 0x002F
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 6-22. Debug Comparator Data Low Mask Register (DBGADLM)
Table 6-31. DBGADLM Field Descriptions
Field Description
7–0
Bits[7:0]
Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected
comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. Data bus
comparisons are only performed if the TAG bit in DBGACTL is clear
0 Do not compare corresponding data bit. Any value of corresponding data bit allows match
1 Compare corresponding data bit
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Freescale Semiconductor 221
a forced match, a state sequencer transition can occur immediately on a successful match of system busses
and comparator registers. Whilst tagging, at a comparator match, the instruction opcode is tagged and only
if the instruction reaches the execution stage of the instruction queue can a state sequencer transition occur.
In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated.
A state sequencer transition to final state (with associated breakpoint, if enabled) can be initiated by
writing to the TRIG bit in the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and must be read out using
standard 16-bit word reads.
Figure 6-23. DBG Overview
6.4.2 Comparator Modes
The DBG contains three comparators, A, B and C. Each comparator compares the system address bus with
the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares
the data buses to the data stored in DBGADH, DBGADL and allows masking of individual data bus bits.
All comparators are disabled in BDM and during BDM accesses.
The comparator match control logic (see Figure 6-23) configures comparators to monitor the buses for an
exact address or an address range, whereby either an access inside or outside the specified range generates
a match condition. The comparator configuration is controlled by the control register contents and the
range control by the DBGC2 contents.
A match can initiate a transition to another state sequencer state (see Section 6.4.4, “State Sequence
Control”). The comparator control register also allows the type of access to be included in the comparison
through the use of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write
comparison is enabled for the associated comparator and the RW bit selects either a read or write access
CPU BUS
TRACE BUFFER
BUS INTERFACE
TRANSITION
MATCH0
STATE
COMPARATOR B
COMPARATOR C
COMPARATOR A
STATE SEQUENCER
MATCH1
MATCH2
TRACE
READ TRACE DATA (DBG READ DATA BUS)
CONTROL
SECURE
BREAKPOINT REQUESTS
COMPARATOR
MATCH CONTROL
TRIGGER
TAG &
MATCH
CONTROL
LOGIC
TAGS
TAGHITS
STATE
TO CPU
S12S Debug Module (S12SDBGV2)
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222 Freescale Semiconductor
for a valid match. Similarly the SZE and SZ bits allow the size of access (word or byte) to be considered
in the compare. Only comparators A and B feature SZE and SZ.
The TAG bit in each comparator control register is used to determine the match condition. By setting TAG,
the comparator qualifies a match with the output of opcode tracking logic and a state sequencer transition
occurs when the tagged instruction reaches the CPU execution stage. Whilst tagging the RW, RWE, SZE,
and SZ bits and the comparator data registers are ignored; the comparator address register must be loaded
with the exact opcode address.
If the TAG bit is clear (forced type match) a comparator match is generated when the selected address
appears on the system address bus. If the selected address is an opcode address, the match is generated
when the opcode is fetched from the memory, which precedes the instruction execution by an indefinite
number of cycles due to instruction pipelining. For a comparator match of an opcode at an odd address
when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an
opcode at odd address (n), the comparator register must contain address (n–1).
Once a successful comparator match has occurred, the condition that caused the original match is not
verified again on subsequent matches. Thus if a particular data value is verified at a given address, this
address may not still contain that data value when a subsequent match occurs.
Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see
Section 6.3.2.4, “Debug Control Register2 (DBGC2)). Comparator channel priority rules are described in
the priority section (Section 6.4.3.4, “Channel Priorities).
6.4.2.1 Single Address Comparator Match
With range comparisons disabled, the match condition is an exact equivalence of address bus with the
value stored in the comparator address registers. Further qualification of the type of access (R/W,
word/byte) and databus contents is possible, depending on comparator channel.
6.4.2.1.1 Comparator C
Comparator C offers only address and direction (R/W) comparison. The exact address is compared, thus
with the comparator address register loaded with address (n) a word access of address (n–1) also accesses
(n) but does not cause a match.
Table 6-32. Comparator C Access Considerations
Condition For Valid Match Comp C Address RWE RW Examples
Read and write accesses of ADDR[n] ADDR[n]1
1A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
0 X LDAA ADDR[n]
STAA #$BYTE ADDR[n]
Write accesses of ADDR[n] ADDR[n] 1 0 STAA #$BYTE ADDR[n]
Read accesses of ADDR[n] ADDR[n] 1 1 LDAA #$BYTE ADDR[n]
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Freescale Semiconductor 223
6.4.2.1.2 Comparator B
Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is
set the access size (word or byte) is compared with the SZ bit value such that only the specified size of
access causes a match. Thus if configured for a byte access of a particular address, a word access covering
the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are
shown in Table 6-33.
Access direction can also be used to qualify a match for Comparator B in the same way as described for
Comparator C in Table 6-32.
6.4.2.1.3 Comparator A
Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison.
Table 6-34 lists access considerations with data bus comparison. On word accesses the data byte of the
lower address is mapped to DBGADH. Access direction can also be used to qualify a match for
Comparator A in the same way as described for Comparator C in Table 6-32.
Table 6-34. Comparator A Matches When Accessing ADDR[n]
Table 6-33. Comparator B Access Size Considerations
Condition For Valid Match Comp B Address RWE SZE SZ8 Examples
Word and byte accesses of ADDR[n] ADDR[n]1
1A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
0 0 X MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
Word accesses of ADDR[n] only ADDR[n] 0 1 0 MOVW #$WORD ADDR[n]
LDD ADDR[n]
Byte accesses of ADDR[n] only ADDR[n] 0 1 1 MOVB #$BYTE ADDR[n]
LDAB ADDR[n]
SZE SZ DBGADHM,
DBGADLM
Access
DH=DBGADH, DL=DBGADL Comment
0 X $0000 Byte
Word
No databus comparison
0 X $FF00 Byte, data(ADDR[n])=DH
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Match data( ADDR[n])
0 X $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match data( ADDR[n+1])
0 X $00FF Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL Possible unintended match
0 X $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data( ADDR[n], ADDR[n+1])
0 X $FFFF Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL Possible unintended match
1 0 $0000 Word No databus comparison
1 0 $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match only data at ADDR[n+1]
1 0 $FF00 Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Match only data at ADDR[n]
1 0 $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data at ADDR[n] & ADDR[n+1]
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224 Freescale Semiconductor
6.4.2.1.4 Comparator A Data Bus Comparison NDB Dependency
Comparator A features an NDB control bit, which allows data bus comparators to be configured to either
trigger on equivalence or trigger on difference. This allows monitoring of a difference in the contents of
an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by
clearing the corresponding mask bit (DBGADHM/DBGADLM) so that it is ignored in the comparison. A
match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register
bits are clear, then a match is based on the address bus only, the data bus is ignored.
When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any
data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored
and prevents a match because no difference can be detected. In this case address bus equivalence does not
cause a match.
6.4.2.2 Range Comparisons
Using the AB comparator pair for a range comparison, the data bus can also be used for qualification by
using the comparator A data registers. Furthermore the DBGACTL RW and RWE bits can be used to
qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are
ignored. The SZE and SZ control bits are ignored in range mode. The comparator A TAG bit is used to tag
range comparisons. The comparator B TAG bit is ignored in range modes. In order for a range comparison
using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both
must be cleared. The comparator A BRK bit is used to for the AB range, the comparator B BRK bit is
ignored in range mode.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
6.4.2.2.1 Inside Range (CompA_Addr ≤ address ≤ CompB_Addr)
In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons.
This configuration depends upon the control register (DBGC2). The match condition requires that a valid
1 1 $0000 Byte No databus comparison
1 1 $FF00 Byte, data(ADDR[n])=DH Match data at ADDR[n]
Table 6-35. NDB and MASK bit dependency
NDB DBGADHM[n] /
DBGADLM[n] Comment
0 0 Do not compare data bus bit.
0 1 Compare data bus bit. Match on equivalence.
1 0 Do not compare data bus bit.
1 1 Compare data bus bit. Match on difference.
SZE SZ DBGADHM,
DBGADLM
Access
DH=DBGADH, DL=DBGADL Comment
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match for both comparators happens on the same bus cycle. A match condition on only one comparator is
not valid. An aligned word access which straddles the range boundary is valid only if the aligned address
is inside the range.
6.4.2.2.2 Outside Range (address < CompA_Addr or address > CompB_Addr)
In the Outside Range comparator mode, comparator pair A and B can be configured for range comparisons.
A single match condition on either of the comparators is recognized as valid. An aligned word access
which straddles the range boundary is valid only if the aligned address is outside the range.
Outside range mode in combination with tagging can be used to detect if the opcode fetches are from an
unexpected range. In forced match mode the outside range match would typically be activated at any
interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $3FFFF or
lower range limit to $00000 respectively.
6.4.3 Match Modes (Forced or Tagged)
Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register
TAG bits select the match mode. The modes are described in the following sections.
6.4.3.1 Forced Match
When configured for forced matching, a comparator channel match can immediately initiate a transition
to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control
register for the current state determines the next state. Forced matches are typically generated 2-3 bus
cycles after the final matching address bus cycle, independent of comparator RWE/RW settings.
Furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an
opcode address typically precedes a tagged match at the same address.
6.4.3.2 Tagged Match
If a CPU taghit occurs a transition to another state sequencer state is initiated and the corresponding
DBGSR flags are set. For a comparator related taghit to occur, the DBG must first attach tags to
instructions as they are fetched from memory. When the tagged instruction reaches the execution stage of
the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition.
6.4.3.3 Immediate Trigger
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing
to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into
the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the
session and issues a forced breakpoint request to the CPU.
It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of
the current state of ARM.
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6.4.3.4 Channel Priorities
In case of simultaneous matches the priority is resolved according to Table 6-36. The lower priority is
suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher
priority. The priorities described in Table 6-36 dictate that in the case of simultaneous matches, the match
pointing to final state has highest priority followed by the lower channel number (0,1,2).
6.4.4 State Sequence Control
Figure 6-24. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then
state1 of the state sequencer is entered. Further transitions between the states are then controlled by the
state control registers and channel matches. From Final State the only permitted transition is back to the
disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the
SSF[2:0] flags in DBGSR accordingly to indicate the current state.
Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of
comparator matches.
Independent of the state sequencer, each comparator channel can be individually configured to generate an
immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers.
Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer
transition can be initiated by a match on other channels. If a debug session is ended by a match on a channel
the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing
Table 6-36. Channel Priorities
Priority Source Action
Highest TRIG Enter Final State
Channel pointing to Final State Transition to next state as defined by state control registers
Match0 (force or tag hit) Transition to next state as defined by state control registers
Match1 (force or tag hit) Transition to next state as defined by state control registers
Lowest Match2 (force or tag hit) Transition to next state as defined by state control registers
State1
Final State State3
ARM = 1
Session Complete
(Disarm)
State2
State 0
(Disarmed)
ARM = 0
ARM = 0
ARM = 0
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and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and
the debug module is disarmed.
6.4.4.1 Final State
On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control
as defined by the TALIGN bit (see Section 6.3.2.3, “Debug Trace Control Register (DBGTCR)”). If the
TSOURCE bit in DBGTCR is clear then the trace buffer is disabled and the transition to Final State can
only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is
enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If
tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor
breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug
module is disarmed.
6.4.5 Trace Buffer Operation
The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information
in the RAM array in a circular buffer format. The system accesses the RAM array through a register
window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 20-bit trace buffer
line is read, an internal pointer into the RAM increments so that the next read receives fresh information.
Data is stored in the format shown in Table 6-37 and Table 6-40. After each store the counter register
DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace
buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented.
6.4.5.1 Trace Trigger Alignment
Using the TALIGN bit (see Section 6.3.2.3, “Debug Trace Control Register (DBGTCR)) it is possible to
align the trigger with the end or the beginning of a tracing session.
If end alignment is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the
transition to Final State signals the end of the tracing session. Tracing with Begin-Trigger starts at the
opcode of the trigger. Using end alignment or when the tracing is initiated by writing to the TRIG bit whilst
configured for begin alignment, tracing starts in the second cycle after the DBGC1 write cycle.
6.4.5.1.1 Storing with Begin Trigger Alignment
Storing with begin alignment, data is not stored in the Trace Buffer until the Final State is entered. Once
the trigger condition is met the DBG module remains armed until 64 lines are stored in the Trace Buffer.
If the trigger is at the address of the change-of-flow instruction the change of flow associated with the
trigger is stored in the Trace Buffer. Using begin alignment together with tagging, if the tagged instruction
is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is
generated, thus the breakpoint does not occur at the tagged instruction boundary.
6.4.5.1.2 Storing with End Trigger Alignment
Storing with end alignment, data is stored in the Trace Buffer until the Final State is entered, at which point
the DBG module becomes disarmed and no more data is stored. If the trigger is at the address of a change
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of flow instruction, the trigger event is not stored in the Trace Buffer. If all trace buffer lines have been
used before a trigger event occurrs then the trace continues at the first line, overwriting the oldest entries.
6.4.5.2 Trace Modes
Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register.
Tracing is enabled using the TSOURCE bit in the DBGTCR register. The modes are described in the
following subsections.
6.4.5.2.1 Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses are stored.
COF addresses are defined as follows:
• Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
• Destination address of indexed JMP, JSR, and CALL instruction
• Destination address of RTI, RTS, and RTC instructions
• Vector address of interrupts, except for BDM vectors
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
Stored information includes the full 18-bit address bus and information bits, which contains a
source/destination bit to indicate whether the stored address was a source address or destination address.
NOTE
When a COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets executed after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
LDX #SUB_1
MARK1 JMP 0,X ; IRQ interrupt occurs during execution of this
MARK2 NOP ;
SUB_1 BRN * ; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
NOP ;
ADDR1 DBNE A,PART5 ; Source address TRACE BUFFER ENTRY 4
IRQ_ISR LDAB #$F0 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
STAB VAR_C1
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RTI ;
The execution flow taking into account the IRQ is as follows
LDX #SUB_1
MARK1 JMP 0,X ;
IRQ_ISR LDAB #$F0 ;
STAB VAR_C1
RTI ;
SUB_1 BRN *
NOP ;
ADDR1 DBNE A,PART5 ;
6.4.5.2.2 Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the
DBG module writes this value into a background register. This prevents consecutive duplicate address
entries in the Trace Buffer resulting from repeated branches.
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG
module is designed to help find.
6.4.5.2.3 Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This
mode is intended to supply additional information on indexed, indirect addressing modes where storing
only the destination address would not provide all information required for a user to determine where the
code is in error. This mode also features information bit storage to the trace buffer, for each address byte
storage. The information bits indicate the size of access (word or byte) and the type of access (read or
write).
When tracing in Detail Mode, all cycles are traced except those when the CPU is either in a free or opcode
fetch cycle.
6.4.5.2.4 Compressed Pure PC Mode
In Compressed Pure PC Mode, the PC addresses of all executed opcodes, including illegal opcodes are
stored. A compressed storage format is used to increase the effective depth of the trace buffer. This is
achieved by storing the lower order bits each time and using 2 information bits to indicate if a 64 byte
boundary has been crossed, in which case the full PC is stored.
Each Trace Buffer row consists of 2 information bits and 18 PC address bits
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NOTE:
When tracing is terminated using forced breakpoints, latency in breakpoint
generation means that opcodes following the opcode causing the breakpoint
can be stored to the trace buffer. The number of opcodes is dependent on
program flow. This can be avoided by using tagged breakpoints.
6.4.5.3 Trace Buffer Organization (Normal, Loop1, Detail modes)
ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix refers
to the tracing count. The information format for Loop1 and Normal modes is identical. In Detail mode, the
address and data for each entry are stored on consecutive lines, thus the maximum number of entries is 32.
In this case DBGCNT bits are incremented twice, once for the address line and once for the data line, on
each trace buffer entry. In Detail mode CINF comprises of R/W and size access information (CRW and
CSZ respectively).
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL)
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte1 and the byte at the higher address is stored to byte0.
6.4.5.3.1 Information Bit Organization
The format of the bits is dependent upon the active trace mode as described below.
Field2 Bits in Detail Mode
In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU.
Table 6-37. Trace Buffer Organization (Normal,Loop1,Detail modes)
Mode Entry
Number
4-bits 8-bits 8-bits
Field 2 Field 1 Field 0
Detail Mode
Entry 1 CINF1,ADRH1 ADRM1 ADRL1
0 DATAH1 DATAL1
Entry 2 CINF2,ADRH2 ADRM2 ADRL2
0 DATAH2 DATAL2
Normal/Loop1
Modes
Entry 1 PCH1 PCM1 PCL1
Entry 2 PCH2 PCM2 PCL2
Bit 3 Bit 2 Bit 1 Bit 0
CSZ CRW ADDR[17] ADDR[16]
Figure 6-25. Field2 Bits in Detail Mode
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Field2 Bits in Normal and Loop1 Modes
6.4.5.4 Trace Buffer Organization (Compressed Pure PC mode)
Table 6-40. Trace Buffer Organization Example (Compressed PurePC mode)
Table 6-38. Field Descriptions
Bit Description
3
CSZ
Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail Mode
0 Word Access
1 Byte Access
2
CRW
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access when tracing in Detail Mode.
0 Write Access
1 Read Access
1
ADDR[17]
Address Bus bit 17— Corresponds to system address bus bit 17.
0
ADDR[16]
Address Bus bit 16— Corresponds to system address bus bit 16.
Bit 3 Bit 2 Bit 1 Bit 0
CSD CVA PC17 PC16
Figure 6-26. Information Bits PCH
Table 6-39. PCH Field Descriptions
Bit Description
3
CSD
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored
address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.
0 Source Address
1 Destination Address
2
CVA
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector
address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set.
This bit has no meaning in Compressed Pure PC mode.
0 Non-Vector Destination Address
1 Vector Destination Address
1
PC17
Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17.
0
PC16
Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16.
Mode Line
Number
2-bits 6-bits 6-bits 6-bits
Field 3 Field 2 Field 1 Field 0
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NOTE
Configured for end aligned triggering in compressed PurePC mode, then
after rollover it is possible that the oldest base address is overwritten. In this
case all entries between the pointer and the next base address have lost their
base address following rollover. For example in Table 6-40 if one line of
rollover has occurred, Line 1, PC1, is overwritten with a new entry. Thus the
entries on Lines 2 and 3 have lost their base address. For reconstruction of
program flow the first base address following the pointer must be used, in
the example, Line 4. The pointer points to the oldest entry, Line 2.
Field3 Bits in Compressed Pure PC Modes
Each time that PC[17:6] differs from the previous base PC[17:6], then a new base address is stored. The
base address zero value is the lowest address in the 64 address range
The first line of the trace buffer always gets a base PC address, this applies also on rollover.
6.4.5.5 Reading Data from Trace Buffer
The data stored in the Trace Buffer can be read provided the DBG module is not armed, is configured for
tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer
is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word
write to DBGTB when the module is disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid lines can be determined. DBGCNT does not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no rollover has occurred, the pointer points to line0, otherwise
it points to the line with the oldest entry. In compressed Pure PC mode on rollover the line with the oldest
Compressed
Pure PC Mode
Line 1 00 PC1 (Initial 18-bit PC Base Address)
Line 2 11 PC4 PC3 PC2
Line 3 01 0 0 PC5
Line 4 00 PC6 (New 18-bit PC Base Address)
Line 5 10 0 PC8 PC7
Line 6 00 PC9 (New 18-bit PC Base Address)
Table 6-41. Compressed Pure PC Mode Field 3 Information Bit Encoding
INF1 INF0 TRACE BUFFER ROW CONTENT
0 0 Base PC address TB[17:0] contains a full PC[17:0] value
0 1 Trace Buffer[5:0] contain incremental PC relative to base address zero value
1 0 Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value
1 1 Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value
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data entry may also contain newer data entries in fields 0 and 1. Thus if rollover is indicated by the TBF
bit, the line status must be decoded using the INF bits in field3 of that line. If both INF bits are clear then
the line contains only entries from before the last rollover.
If INF0=1 then field 0 contains post rollover data but fields 1 and 2 contain pre rollover data.
If INF1=1 then fields 0 and 1 contain post rollover data but field 2 contains pre rollover data.
The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables
an interrupted trace buffer read sequence to be easily restarted from the oldest data entry.
The least significant word of line is read out first. This corresponds to the fields 1 and 0 of Table 6-37. The
next word read returns field 2 in the least significant bits [3:0] and “0” for bits [15:4].
Reading the Trace Buffer while the DBG module is armed returns invalid data and no shifting of the RAM
pointer occurs.
6.4.5.6 Trace Buffer Reset State
The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system
reset occur, the trace session information from immediately before the reset occurred can be read out and
the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current
trace buffer address is initialized by unlocking the trace buffer and points to the oldest valid data even if a
reset occurred during the tracing session. To read the trace buffer after a reset, TSOURCE must be set,
otherwise the trace buffer reads as all zeroes. Generally debugging occurrences of system resets is best
handled using end trigger alignment since the reset may occur before the trace trigger, which in the begin
trigger alignment case means no information would be stored in the trace buffer.
The Trace Buffer contents and DBGCNT bits are undefined following a POR.
NOTE
An external pin RESET that occurs simultaneous to a trace buffer entry can,
in very seldom cases, lead to either that entry being corrupted or the first
entry of the session being corrupted. In such cases the other contents of the
trace buffer still contain valid tracing information. The case occurs when the
reset assertion coincides with the trace buffer entry clock edge.
6.4.6 Tagging
A tag follows program information as it advances through the instruction queue. When a tagged instruction
reaches the head of the queue a tag hit occurs and can initiate a state sequencer transition.
Each comparator control register features a TAG bit, which controls whether the comparator match causes
a state sequencer transition immediately or tags the opcode at the matched address. If a comparator is
enabled for tagged comparisons, the address stored in the comparator match address registers must be an
opcode address.
Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the
transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started.
Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when
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the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is
generated immediately, before the tagged instruction is carried out.
R/W monitoring, access size (SZ) monitoring and data bus monitoring are not useful if tagging is selected,
since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on
the type of access. Thus these bits are ignored if tagging is selected.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
Tagging is disabled when the BDM becomes active.
6.4.7 Breakpoints
It is possible to generate breakpoints from channel transitions to final state or using software to write to
the TRIG bit in the DBGC1 register.
6.4.7.1 Breakpoints From Comparator Channels
Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for
tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the
instruction queue.
If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session
has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion
of the subsequent trace (see Table 6-42). If no tracing session is selected, breakpoints are requested
immediately.
If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing
trigger alignment.
6.4.7.2 Breakpoints Generated Via The TRIG Bit
If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the
TALIGN bit. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the
tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only
on completion of the subsequent trace (see Table 6-42). If no tracing session is selected, breakpoints are
Table 6-42. Breakpoint Setup For CPU Breakpoints
BRK TALIGN DBGBRK Breakpoint Alignment
0 0 0 Fill Trace Buffer until trigger then disarm (no breakpoints)
0 0 1 Fill Trace Buffer until trigger, then breakpoint request occurs
0 1 0 Start Trace Buffer at trigger (no breakpoints)
0 1 1 Start Trace Buffer at trigger
A breakpoint request occurs when Trace Buffer is full
1 x 1 Terminate tracing and generate breakpoint immediately on trigger
1 x 0 Terminate tracing immediately on trigger
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requested immediately. TRIG breakpoints are possible with a single write to DBGC1, setting ARM and
TRIG simultaneously.
6.4.7.3 Breakpoint Priorities
If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an
effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is
followed by a subsequent comparator channel match, it has no effect, since tracing has already started.
If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is
activated by the BGND and the breakpoint to SWI is suppressed.
6.4.7.3.1 DBG Breakpoint Priorities And BDM Interfacing
Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU
is executing out of BDM firmware, thus comparator matches and associated breakpoints are disabled. In
addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active,
the breakpoint gives priority to BDM requests over SWI requests if the breakpoint happens to coincide
with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed.
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via
a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes
the BDM firmware code, checks the ENABLE and returns if ENABLE is not set. If not serviced by the
monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow.
If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code
could coincide with a DBG breakpoint. The CPU ensures that BDM requests have a higher priority than
SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid a repeated
breakpoint at the same address.
Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows
the BGND instruction is the first instruction executed when normal program execution resumes.
Table 6-43. Breakpoint Mapping Summary
DBGBRK BDM Bit
(DBGC1[4])
BDM
Enabled
BDM
Active
Breakpoint
Mapping
0 X X X No Breakpoint
1 0 X 0 Breakpoint to SWI
X X 1 1 No Breakpoint
1 1 0 X Breakpoint to SWI
1 1 1 0 Breakpoint to BDM
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NOTE
When program control returns from a tagged breakpoint using an RTI or
BDM GO command without program counter modification it returns to the
instruction whose tag generated the breakpoint. To avoid a repeated
breakpoint at the same location reconfigure the DBG module in the SWI
routine, if configured for an SWI breakpoint, or over the BDM interface by
executing a TRACE command before the GO to increment the program flow
past the tagged instruction.
6.5 Application Information
6.5.1 State Machine scenarios
Defining the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2
respectively. SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only
in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR
register. Thus the existing encoding for SCRx[2:0] is not changed.
6.5.2 Scenario 1
A trigger is generated if a given sequence of 3 code events is executed.
Figure 6-27. Scenario 1
Scenario 1 is possible with S12SDBGV1 SCR encoding
6.5.3 Scenario 2
A trigger is generated if a given sequence of 2 code events is executed.
Figure 6-28. Scenario 2a
State1 Final State
State3
State2
SCR1=0011 SCR2=0010 SCR3=0111
M1 M2 M0
State1 Final State
State2
SCR1=0011 SCR2=0101
M1 M2
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A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.
Figure 6-29. Scenario 2b
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry
into a range (COMPA,COMPB configured for range mode)
Figure 6-30. Scenario 2c
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
6.5.4 Scenario 3
A trigger is generated immediately when one of up to 3 given events occurs
Figure 6-31. Scenario 3
Scenario 3 is possible with S12SDBGV1 SCR encoding
6.5.5 Scenario 4
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B
and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate
State1 Final State
State2
SCR1=0111 SCR2=0101
M01 M2
State1 Final State
State2
SCR1=0010 SCR2=0011
M2 M0
State1 Final State
SCR1=0000
M012
S12S Debug Module (S12SDBGV2)
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238 Freescale Semiconductor
event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A
cause a trigger. This is possible by using CompA and CompC to match on the same address as shown.
Figure 6-32. Scenario 4a
This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2
comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown.
Figure 6-33. Scenario 4b (with 2 comparators)
The advantage of using only 2 channels is that now range comparisons can be included (channel0)
This however violates the S12SDBGV1 specification, which states that a match leading to final state
always has priority in case of a simultaneous match, whilst priority is also given to the lowest channel
number. For S12SDBG the corresponding CPU priority decoder is removed to support this, such that on
simultaneous taghits, taghits pointing to final state have highest priority. If no taghit points to final state
then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG
would break on a simultaneous M0/M2.
State1
State 3 Final State
State2
M0
M0
M2
M1
M1
M1
SCR1=0100
SCR2=0011
SCR3=0001
State1
State 3 Final State
State2
M0
M01
M0
M2
M2
M2
SCR1=0110
SCR2=1100
SCR3=1110
M1 disabled in
range mode
S12S Debug Module (S12SDBGV2)
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Freescale Semiconductor 239
6.5.6 Scenario 5
Trigger if following event A, event C precedes event B. i.e. the expected execution flow is A->B->C.
Figure 6-34. Scenario 5
Scenario 5 is possible with the S12SDBGV1 SCR encoding
6.5.7 Scenario 6
Trigger if event A occurs twice in succession before any of 2 other events (BC) occurs. This scenario is
not possible using the S12SDBGV1 SCR encoding. S12SDBGV2 includes additions shown in red. The
change in SCR1 encoding also has the advantage that a State1->State3 transition using M0 is now possible.
This is advantageous because range and data bus comparisons use channel0 only.
Figure 6-35. Scenario 6
6.5.8 Scenario 7
Trigger when a series of 3 events is executed out of order. Specifying the event order as M1,M2,M0 to run
in loops (120120120). Any deviation from that order should trigger. This scenario is not possible using the
S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding
OR forks as shown in red this scenario is possible.
Figure 6-36. Scenario 7
State1 Final State
State2
SCR1=0011 SCR2=0110
M1 M0
M2
State1 Final State
State3
SCR1=1001 SCR3=1010
M0 M0
M12
State1 Final State
State3
State2
SCR1=1101 SCR2=1100 SCR3=1101
M1 M2 M12
M0
M02
M01
S12S Debug Module (S12SDBGV2)
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240 Freescale Semiconductor
On simultaneous matches the lowest channel number has priority so with this configuration the forking
from State1 has the peculiar effect that a simultaneous match0/match1 transitions to final state but a
simultaneous match2/match1transitions to state2.
6.5.9 Scenario 8
Trigger when a routine/event at M2 follows either M1 or M0.
Figure 6-37. Scenario 8a
Trigger when an event M2 is followed by either event M0 or event M1
Figure 6-38. Scenario 8b
Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding
6.5.10 Scenario 9
Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed
again. This cannot be realized with theS12SDBGV1 SCR encoding due to OR limitations. By changing
the SCR2 encoding as shown in red this scenario becomes possible.
Figure 6-39. Scenario 9
6.5.11 Scenario 10
Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1.
As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one
or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger
State1 Final State
State2
SCR1=0111 SCR2=0101
M01 M2
State1 Final State
State2
SCR1=0010 SCR2=0111
M2 M01
State1 Final State
State2
SCR1=0111 SCR2=1111
M01 M01
M2
S12S Debug Module (S12SDBGV2)
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Freescale Semiconductor 241
is generated. Configuring CompA and CompC the same, it is possible to generate a breakpoint on the third
consecutive occurrence of event M0 without a reset M1.
Figure 6-40. Scenario 10a
Figure 6-41. Scenario 10b
Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point
in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before
M1 then a trigger is generated.
State1 Final State
State3
State2
SCR1=0010 SCR2=0100 SCR3=0010
M2 M2 M0
M1
M1
State1 Final State
State3
State2
SCR1=0010 SCR2=0011 SCR3=0000
M2 M1
M0
M0
S12S Debug Module (S12SDBGV2)
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Freescale Semiconductor 243
Chapter 7
Interrupt Module (S12SINTV1)
7.1 Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to the CPU. The INT module supports:
• I bit and X bit maskable interrupt requests
• A non-maskable unimplemented op-code trap
• A non-maskable software interrupt (SWI) or background debug mode request
• Three system reset vector requests
• A spurious interrupt vector
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
7.1.1 Glossary
Table 7-2 contains terms and abbreviations used in the document.
7.1.2 Features
• Interrupt vector base register (IVBR)
• One spurious interrupt vector (at address vector base1 + 0x0080).
Version
Number
Revision
Date
Effective
Date Author Description of Changes
01.02 13 Sep
2007
updates for S12P family devices:
- re-added XIRQ and IRQ references since this functionality is used
on devices without D2D
- added low voltage reset as possible source to the pin reset vector
01.03 21 Nov
2007
added clarification of “Wake-up from STOP or WAIT by XIRQ with
X bit set” feature
01.04 20 May
2009
added footnote about availability of “Wake-up from STOP or WAIT
by XIRQ with X bit set” feature
Table 7-2. Terminology
Term Meaning
CCR Condition Code Register (in the CPU)
ISR Interrupt Service Routine
MCU Micro-Controller Unit
Interrupt Module (S12SINTV1)
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244 Freescale Semiconductor
• 2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2).
• I bit maskable interrupts can be nested.
• One X bit maskable interrupt vector request (at address vector base + 0x00F4).
• One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
• One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
• Three system reset vectors (at addresses 0xFFFA–0xFFFE).
• Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU
request
• Wakes up the system from stop or wait mode when an appropriate interrupt request occurs.
7.1.3 Modes of Operation
• Run mode
This is the basic mode of operation.
• Wait mode
In wait mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from wait mode if an interrupt occurs. Please refer to Section 7.5.3, “Wake Up
from Stop or Wait Mode” for details.
• Stop Mode
In stop mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from stop mode if an interrupt occurs. Please refer to Section 7.5.3, “Wake Up
from Stop or Wait Mode” for details.
• Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to Section 7.3.1.1, “Interrupt Vector Base Register (IVBR)” for details.
7.1.4 Block Diagram
Figure 7-1 shows a block diagram of the INT module.
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as upper byte) and 0x00 (used as lower byte).
Interrupt Module (S12SINTV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 245
Figure 7-1. INT Block Diagram
7.2 External Signal Description
The INT module has no external signals.
7.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the INT module.
7.3.1 Register Descriptions
This section describes in address order all the INT registers and their individual bits.
7.3.1.1 Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
Address: 0x0120
76543210
RIVB_ADDR[7:0]
W
Reset 11111111
Figure 7-2. Interrupt Vector Base Register (IVBR)
Wake Up
IVBR
Interrupt
Requests
Interrupt Requests CPU
Vector
Address
Peripheral
To CPU
Priority
Decoder
Non I bit Maskable Channels
I bit Maskable Channels
Interrupt Module (S12SINTV1)
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246 Freescale Semiconductor
7.4 Functional Description
The INT module processes all exception requests to be serviced by the CPU module. These exceptions
include interrupt vector requests and reset vector requests. Each of these exception types and their overall
priority level is discussed in the subsections below.
7.4.1 S12S Exception Requests
The CPU handles both reset requests and interrupt requests. A priority decoder is used to evaluate the
priority of pending interrupt requests.
7.4.2 Interrupt Prioritization
The INT module contains a priority decoder to determine the priority for all interrupt requests pending for
the CPU. If more than one interrupt request is pending, the interrupt request with the higher vector address
wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
1. The local interrupt enabled bit in the peripheral module must be set.
2. The I bit in the condition code register (CCR) of the CPU must be cleared.
3. There is no SWI, TRAP, or X bit maskable request pending.
NOTE
All non I bit maskable interrupt requests always have higher priority than
the I bit maskable interrupt requests. If the X bit in the CCR is cleared, it is
possible to interrupt an I bit maskable interrupt by an X bit maskable
interrupt. It is possible to nest non maskable interrupt requests, for example
by nesting SWI or TRAP calls.
Since an interrupt vector is only supplied at the time when the CPU requests it, it is possible that a higher
priority interrupt request could override the original interrupt request that caused the CPU to request the
vector. In this case, the CPU will receive the highest priority vector and the system will process this
interrupt request first, before the original interrupt request is processed.
Table 7-3. IVBR Field Descriptions
Field Description
7–0
IVB_ADDR[7:0]
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
reset these bits are set to 0xFF (that means vectors are located at 0xFF80–0xFFFE) to ensure compatibility
to HCS12.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
Note: If the BDM is active (that means the CPU is in the process of executing BDM firmware code), the
contents of IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”. This is done
to enable handling of all non-maskable interrupts in the BDM firmware.
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If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the CPU vector request), the vector address supplied
to the CPU will default to that of the spurious interrupt vector.
NOTE
Care must be taken to ensure that all interrupt requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0080)).
7.4.3 Reset Exception Requests
The INT module supports three system reset exception request types (please refer to the Clock and Reset
generator module for details):
1. Pin reset, power-on reset or illegal address reset, low voltage reset (if applicable)
2. Clock monitor reset request
3. COP watchdog reset request
7.4.4 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon
request by the CPU is shown in Table 7-4.
Table 7-4. Exception Vector Map and Priority
Vector Address1
116 bits vector address based
Source
0xFFFE Pin reset, power-on reset, illegal address reset, low voltage reset (if applicable)
0xFFFC Clock monitor reset
0xFFFA COP watchdog reset
(Vector base + 0x00F8) Unimplemented opcode trap
(Vector base + 0x00F6) Software interrupt instruction (SWI) or BDM vector request
(Vector base + 0x00F4) X bit maskable interrupt request (XIRQ or D2D error interrupt)2
2D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt
(Vector base + 0x00F2) IRQ or D2D interrupt request3
3D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt
(Vector base + 0x00F0–0x0082) Device specific I bit maskable interrupt sources (priority determined by the low byte of the
vector address, in descending order)
(Vector base + 0x0080) Spurious interrupt
Interrupt Module (S12SINTV1)
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248 Freescale Semiconductor
7.5 Initialization/Application Information
7.5.1 Initialization
After system reset, software should:
1. Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFF80–0xFFF9).
2. Enable I bit maskable interrupts by clearing the I bit in the CCR.
3. Enable the X bit maskable interrupt by clearing the X bit in the CCR.
7.5.2 Interrupt Nesting
The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the
CPU.
• I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, other I bit maskable interrupt requests can interrupt the
current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
1. Service interrupt, that is clear interrupt flags, copy data, etc.
2. Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt
requests)
3. Process data
4. Return from interrupt by executing the instruction RTI
7.5.3 Wake Up from Stop or Wait Mode
7.5.3.1 CPU Wake Up from Stop or Wait Mode
Every I bit maskable interrupt request is capable of waking the MCU from stop or wait mode. To determine
whether an I bit maskable interrupts is qualified to wake-up the CPU or not, the same conditions as in
normal run mode are applied during stop or wait mode:
• If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking-up the MCU.
Since there are no clocks running in stop mode, only interrupts which can be asserted asynchronously can
wake-up the MCU from stop mode.
The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the
X bit in CCR is set1.
1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is
shared with other peripheral modules on the device. Please refer to the Device section of the MCU reference manual for details.
Interrupt Module (S12SINTV1)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 249
If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in the CCR set, the
associated ISR is not called. The CPU then resumes program execution with the instruction following the
WAI or STOP instruction. This features works following the same rules like any interrupt request, that is
care must be taken that the X interrupt request used for wake-up remains active at least until the system
begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not
occur.
Interrupt Module (S12SINTV1)
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Chapter 8
Analog-to-Digital Converter (ADC12B6CV2)
Revision History
8.1 Introduction
The ADC12B6C is a 6-channel, , multiplexed input successive approximation analog-to-digital converter.
Refer to device electrical specifications for ATD accuracy.
8.1.1 Features
• 8-, 10-bit resolution.
• Automatic return to low power after conversion sequence
• Automatic compare with interrupt for higher than or less/equal than programmable value
Version
Number
Revision
Date
Effective
Date Author Description of Changes
V02.00 17 June 2009 17 June 2009 Initial version copied from 8 channel version
V02.01 09 Feb 2010 09 Feb 2010
Updated Table 8-15 Analog Input Channel Select Coding -
description of internal channels.
Updated register ATDDR (left/right justified result) description
in section 8.3.2.12.1/8-270 and 8.3.2.12.2/8-271 and added
Table 8-21 to improve feature description.
Fixed typo in Table 8-9 - conversion result for 3mV and 10bit
resolution
V02.03 26 Feb 2010 26 Feb 2010 Corrected Table 8-15 Analog Input Channel Select Coding -
description of internal channels.
V02.04 26 Mar 2010 26 Mar 2010 Corrected typo: Reset value of ATDDIEN register
V02.05 14 Apr 2010 14 Apr 2010 Corrected typos to be in-line with SoC level pin naming
conventions for VDDA, VSSA, VRL and VRH.
V02.06 25 Aug 2010 25 Aug 2010 Removed feature of conversion during STOP and general
wording clean up done in Section 8.4, “Functional Description
V02.07 09 Sep 2010 09 Sep 2010 Update of internal only information.
V02.08 11 Feb 2011 11 Feb 2011 Connectivity Information regarding internal channel_6 added
to Table 8-15.
Analog-to-Digital Converter (ADC12B6CV2)
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252 Freescale Semiconductor
• Programmable sample time.
• Left/right justified result data.
• External trigger control.
• Sequence complete interrupt.
• Analog input multiplexer for 6 analog input channels.
• Special conversions for VRH, VRL, (VRL+VRH)/2 and ADC temperature sensor.
• 1-to-6 conversion sequence lengths.
• Continuous conversion mode.
• Multiple channel scans.
• Configurable external trigger functionality on any AD channel or any of four additional trigger
inputs. The four additional trigger inputs can be chip external or internal. Refer to device
specification for availability and connectivity.
• Configurable location for channel wrap around (when converting multiple channels in a sequence).
Analog-to-Digital Converter (ADC12B6CV2)
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8.1.2 Modes of Operation
8.1.2.1 Conversion Modes
There is software programmable selection between performing single or continuous conversion on a
single channel or multiple channels.
8.1.2.2 MCU Operating Modes
• Stop Mode
Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted
restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion
sequence with write to ATDCTL5. So after exiting from stop mode with a previously aborted
sequence all flags are cleared etc.
•Wait Mode
ADC12B6C behaves same in Run and Wait Mode. For reduced power consumption continuous
conversions should be aborted before entering Wait mode.
•Freeze Mode
In Freeze Mode the ADC12B6C will either continue or finish or stop converting according to the
FRZ1 and FRZ0 bits. This is useful for debugging and emulation.
Analog-to-Digital Converter (ADC12B6CV2)
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254 Freescale Semiconductor
8.1.3 Block Diagram
Figure 8-1. ADC12B6C Block Diagram
VSSA
AN4
ATD_12B8C
Analog
MUX
Mode and
Successive
Approximation
Register (SAR)
Results
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
and DAC
Sample & Hold
VDDA
VRL
VRH
Sequence Complete
+
-
Comparator
Clock
Prescaler
Bus Clock
ATD Clock
AN3
AN2
AN1
AN5
ETRIG0
(See device specifi-
cation for availability
ETRIG1
ETRIG2
ETRIG3
and connectivity)
Timing Control
ATDDIENATDCTL1
Trigger
Mux Interrupt
Compare Interrupt
AN0
Analog-to-Digital Converter (ADC12B6CV2)
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8.2 Signal Description
This section lists all inputs to the ADC12B6C block.
8.2.1 Detailed Signal Descriptions
8.2.1.1 ANx (x = 5, 4, 3, 2, 1, 0)
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
8.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connectivity of these inputs!
8.2.1.3 VRH, VRL
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
8.2.1.4 VDDA, VSSA
These pins are the power supplies for the analog circuitry of the ADC12B6C block.
8.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC12B6C.
8.3.1 Module Memory Map
Figure 8-2 gives an overview on all ADC12B6C registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address Name Bit 7 6 5 4 3 2 1 Bit 0
0x0000 ATDCTL0 RReserved 000
WRAP3 WRAP2 WRAP1 WRAP0
W
0x0001 ATDCTL1 RETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
W
0x0002 ATDCTL2 R0 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE
W
= Unimplemented or Reserved
Figure 8-2. ADC12B6C Register Summary (Sheet 1 of 2)
Analog-to-Digital Converter (ADC12B6CV2)
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256 Freescale Semiconductor
0x0003 ATDCTL3 RDJM S8C S4C S2C S1C FIFO FRZ1 FRZ0
W
0x0004 ATDCTL4 RSMP2 SMP1 SMP0 PRS[4:0]
W
0x0005 ATDCTL5 R0 SC SCAN MULT CD CC CB CA
W
0x0006 ATDSTAT0 RSCF 0ETORF FIFOR CC3 CC2 CC1 CC0
W
0x0007 Unimple-
mented
R0 000 0 0 0 0
W
0x0008 ATDCMPEH R0 000 0 0 0 0
W
0x0009 ATDCMPEL R0 0 CMPE[5:0]
W
0x000A ATDSTAT2H R0 000 0 0 0 0
W
0x000B ATDSTAT2L R 0 0 CCF[5:0]
W
0x000C ATDDIENH R1 111 1 1 1 1
W
0x000D ATDDIENL R1 1 IEN[5:0]
W
0x000E ATDCMPHTH R0 000 0 0 0 0
W
0x000F ATDCMPHTL 00 0 CMPHT[5:0]
0x0010 ATDDR0 RSee Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0012 ATDDR1 RSee Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0014 ATDDR2 RSee Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0016 ATDDR3 RSee Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0018 ATDDR4 RSee Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x001A ATDDR5 RSee Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x001C-
0x002F
Unimple-
mented
R0 000 0 0 0 0
W
Address Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 8-2. ADC12B6C Register Summary (Sheet 2 of 2)
Analog-to-Digital Converter (ADC12B6CV2)
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8.3.2 Register Descriptions
This section describes in address order all the ADC12B6C registers and their individual bits.
8.3.2.1 ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Module Base + 0x0000
76543210
RReserved 000
WRAP3 WRAP2 WRAP1 WRAP0
W
Reset 00001111
= Unimplemented or Reserved
Figure 8-3. ATD Control Register 0 (ATDCTL0)
Table 8-1. ATDCTL0 Field Descriptions
Field Description
3-0
WRAP[3-0]
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in Table 8-2.
Table 8-2. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
0 0 0 0 Reserved1
0001 AN1
0010 AN2
0011 AN3
0100 AN4
0101 AN5
0110 AN5
0111 AN5
1000 AN5
1001 AN5
1010 AN5
1011 AN5
1100 AN5
1101 AN5
1110 AN5
1111 AN5
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
258 Freescale Semiconductor
8.3.2.2 ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
1If only AN0 should be converted use MULT=0.
Module Base + 0x0001
76543210
R
ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
W
Reset 00101111
Figure 8-4. ATD Control Register 1 (ATDCTL1)
Table 8-3. ATDCTL1 Field Descriptions
Field Description
7
ETRIGSEL
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0
inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in Table 8-5.
6–5
SRES[1:0]
A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 8-4 for coding.
4
SMP_DIS
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
3–0
ETRIGCH[3:0]
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
as source for the external trigger. The coding is summarized in Table 8-5.
Table 8-4. A/D Resolution Coding
SRES1 SRES0 A/D Resolution
0 0 8-bit data
0 1 10-bit data
10
1 1 Reserved
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 259
8.3.2.3 ATD Control Register 2 (ATDCTL2)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Table 8-5. External Trigger Channel Select Coding
ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is
0 0 0 0 0 AN0
0 0 0 0 1 AN1
0 0 0 1 0 AN2
0 0 0 1 1 AN3
0 0 1 0 0 AN4
0 0 1 0 1 AN5
0 0 1 1 0 AN5
0 0 1 1 1 AN5
0 1 0 0 0 AN5
0 1 0 0 1 AN5
0 1 0 1 0 AN5
0 1 0 1 1 AN5
0 1 1 0 0 AN5
0 1 1 0 1 AN5
0 1 1 1 0 AN5
0 1 1 1 1 AN5
1 0 0 0 0 ETRIG01
1Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
1 0 0 0 1 ETRIG11
1 0 0 1 0 ETRIG21
1 0 0 1 1 ETRIG31
1 0 1 X X Reserved
1 1 X X X Reserved
Module Base + 0x0002
76543210
R0
AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-5. ATD Control Register 2 (ATDCTL2)
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
260 Freescale Semiconductor
Table 8-6. ATDCTL2 Field Descriptions
Field Description
6
AFFC
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
5
Reserved
Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior.
4
ETRIGLE
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 8-7 for details.
3
ETRIGP
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 8-7 for details.
2
ETRIGE
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in Table 8-5. If the external trigger source is one of the AD channels, the digital
input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with
external events.
0 Disable external trigger
1 Enable external trigger
1
ASCIE
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
0
ACMPIE
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n(CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare
Interrupt will be requested whenever any of the respective CCF flags is set.
Table 8-7. External Trigger Configurations
ETRIGLE ETRIGP External Trigger Sensitivity
0 0 Falling edge
0 1 Rising edge
1 0 Low level
1 1 High level
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 261
8.3.2.4 ATD Control Register 3 (ATDCTL3)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x0003
76543210
R
DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0
W
Reset 00100000
= Unimplemented or Reserved
Figure 8-6. ATD Control Register 3 (ATDCTL3)
Table 8-8. ATDCTL3 Field Descriptions
Field Description
7
DJM
Result Register Data Justification — Result data format is always unsigned. This bit controls justification of
conversion data in the result registers.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Table 8-9 gives example ATD results for an input signal range between 0 and 5.12 Volts.
6–3
S8C, S4C,
S2C, S1C
Conversion Sequence Length — These bits control the number of conversions per sequence. Table 8-10
shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity
to HC12 family.
2
FIFO
Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result
registers based on the conversion sequence; the result of the first conversion appears in the first result register
(ATDDR0), the second result in the second result register (ATDDR1), and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
conversion sequence, the result register counter will wrap around when it reaches the end of the result register
file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register
file, the current conversion result will be placed.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the first
result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register
(ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion
(ETRIG=1).
Which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode
may be useful in a particular application to track valid data.
If this bit is one, automatic compare of result registers is always disabled, that is ADC12B6C will behave as if
ACMPIE and all CPME[n] were zero.
0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 Conversion results are placed in consecutive result registers (wrap around at end).
1–0
FRZ[1:0]
Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
to a breakpoint as shown in Table 8-11. Leakage onto the storage node and comparator reference capacitors
may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
262 Freescale Semiconductor
Table 8-9. Examples of ideal decimal ATD Results
Input Signal
VRL = 0 Volts
VRH = 5.12 Volts
8-Bit
Codes
(resolution=20mV)
10-Bit
Codes
(resolution=5mV)
5.120 Volts
...
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.003
0.002
0.000
255
...
1
1
1
1
1
1
1
0
0
0
0
0
0
1023
...
4
4
4
3
3
2
2
2
1
1
1
0
0
Table 8-10. Conversion Sequence Length Coding
S8C S4C S2C S1C Number of Conversions
per Sequence
0000 6
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 6
1000 6
1001 6
1010 6
1011 6
1100 6
1101 6
1110 6
1111 6
Table 8-11. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1 FRZ0 Behavior in Freeze Mode
0 0 Continue conversion
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 263
8.3.2.5 ATD Control Register 4 (ATDCTL4)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
0 1 Reserved
1 0 Finish current conversion, then freeze
1 1 Freeze Immediately
Module Base + 0x0004
76543210
R
SMP2 SMP1 SMP0 PRS[4:0]
W
Reset 00000101
Figure 8-7. ATD Control Register 4 (ATDCTL4)
Table 8-12. ATDCTL4 Field Descriptions
Field Description
7–5
SMP[2:0]
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
Table 8-13 lists the available sample time lengths.
4–0
PRS[4:0]
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
Refer to Device Specification for allowed frequency range of fATDCLK.
Table 8-13. Sample Time Select
SMP2 SMP1 SMP0
Sample Time
in Number of
ATD Clock Cycles
000 4
001 6
010 8
011 10
100 12
101 16
110 20
111 24
Table 8-11. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1 FRZ0 Behavior in Freeze Mode
fATDCLK
fBUS
2PRS1+()×
-------------------------------------=
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
264 Freescale Semiconductor
8.3.2.6 ATD Control Register 5 (ATDCTL5)
Writes to this register will abort current conversion sequence and start a new conversion sequence. If the
external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting
of a conversion sequence which will then occur on each trigger event. Start of conversion means the
beginning of the sampling phase.
Read: Anytime
Write: Anytime
Module Base + 0x0005
76543210
R0
SC SCAN MULT CD CC CB CA
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-8. ATD Control Register 5 (ATDCTL5)
Table 8-14. ATDCTL5 Field Descriptions
Field Description
6
SC
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CD,
CC, CB and CA of ATDCTL5. Table 8-15 lists the coding.
0 Special channel conversions disabled
1 Special channel conversions enabled
5
SCAN
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once. If external trigger function is enabled (ETRIGE=1) setting this bit has no effect, thus
the external trigger always starts a single conversion sequence.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
4
MULT
Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified
analog input channel for an entire conversion sequence. The analog channel is selected by channel selection
code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples
across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C,
S1C). The first analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits);
subsequent channels sampled in the sequence are determined by incrementing the channel selection code or
wrapping around to AN0 (channel 0).
0 Sample only one channel
1 Sample across several channels
3–0
CD, CC,
CB, CA
Analog Input Channel Select Code — These bits select the analog input channel(s). Table 8-15 lists the coding
used to select the various analog input channels.
In the case of single channel conversions (MULT=0), this selection code specifies the channel to be examined.
In the case of multiple channel conversions (MULT=1), this selection code specifies the first channel to be
examined in the conversion sequence. Subsequent channels are determined by incrementing the channel
selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel
Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by
WRAP3-0 the first wrap around will be AN5 to AN0.
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 265
Table 8-15. Analog Input Channel Select Coding
SC CD CC CB CA Analog Input
Channel
00000 AN0
0001 AN1
0010 AN2
0011 AN3
0100 AN4
0101 AN5
0110 AN5
0111 AN5
1000 AN5
1001 AN5
1010 AN5
1011 AN5
1100 AN5
1101 AN5
1110 AN5
1111 AN5
1 0 0 0 0 Internal_6,
Temperature sense of ADC
hardmacro
0 0 0 1 Internal_7
0 0 1 0 Internal_0
0 0 1 1 Internal_1
0100 VRH
0101 VRL
0 1 1 0 (VRH+VRL) / 2
0 1 1 1 Reserved
1 0 0 0 Internal_2
1 0 0 1 Internal_3
1 0 1 0 Internal_4
1 0 1 1 Internal_5
1 X X X Reserved
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
266 Freescale Semiconductor
8.3.2.7 ATD Status Register 0 (ATDSTAT0)
This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and
the conversion counter.
Read: Anytime
Write: Anytime (No effect on (CC3, CC2, CC1, CC0))
Module Base + 0x0006
76543210
R
SCF
0
ETORF FIFOR
CC3 CC2 CC1 CC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-9. ATD Status Register 0 (ATDSTAT0)
Table 8-16. ATDSTAT0 Field Descriptions
Field Description
7
SCF
Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN=1), the flag is set after each one is completed. This flag is cleared
when one of the following occurs:
A) Write “1” to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and a result register is read
0 Conversion sequence not completed
1 Conversion sequence has completed
5
ETORF
External Trigger Overrun Flag — While in edge sensitive mode (ETRIGLE=0), if additional active edges are
detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
following occurs:
A) Write “1” to ETORF
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No External trigger overrun error has occurred
1 External trigger overrun error has occurred
4
FIFOR
Result Register Overrun Flag — This bit indicates that a result register has been written to before its associated
conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because
the flag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been overwritten before it has been read
(i.e. the old data has been lost). This flag is cleared when one of the following occurs:
A) Write “1” to FIFOR
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No overrun has occurred
1 Overrun condition exists (result register has been written while associated CCFx flag was still set)
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 267
8.3.2.8 ATD Compare Enable Register (ATDCMPE)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
3–0
CC[3:0]
Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1,
CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO
mode (FIFO=0) the conversion counter is initialized to zero at the beginning and end of the conversion sequence.
If in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counter wraps around when its
maximum value is reached.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.
Module Base + 0x0008
1514131211109876543210
R 0 0 0 0 0 00000 CMPE[5:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-10. ATD Compare Enable Register (ATDCMPE)
Table 8-17. ATDCMPE Field Descriptions
Field Description
5–0
CMPE[5:0]
Compare Enable for Conversion Number n(n= 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number, NOT
channel number!) — These bits enable automatic compare of conversion results individually for conversions of
a sequence. The sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT register.
For each conversion number with CMPE[n]=1 do the following:
1) Write compare value to ATDDRnresult register
2) Write compare operator with CMPHT[n] in ATDCPMHT register
CCF[n] in ATDSTAT2 register will flag individual success of any comparison.
0 No automatic compare
1 Automatic compare of results for conversion n of a sequence is enabled.
Table 8-16. ATDSTAT0 Field Descriptions (continued)
Field Description
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
268 Freescale Semiconductor
8.3.2.9 ATD Status Register 2 (ATDSTAT2)
This read-only register contains the Conversion Complete Flags CCF[5:0].
Read: Anytime
Write: Anytime, no effect
Module Base + 0x000A
1514131211109876543210
R 0 0 0 0 0 0 0 0 0 0 CCF[5:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-11. ATD Status Register 2 (ATDSTAT2)
Table 8-18. ATDSTAT2 Field Descriptions
Field Description
5–0
CCF[5:0]
Conversion Complete Flag n (n= 5, 4, 3, 2, 1, 0) (n conversion number, NOT channel number!)— A
conversion complete flag is set at the end of each conversion in a sequence. The flags are associated with the
conversion position in a sequence (and also the result register number). Therefore in non-fifo mode, CCF[4] is
set when the fifth conversion in a sequence is complete and the result is available in result register ATDDR4;
CCF[5] is set when the sixth conversion in a sequence is complete and the result is available in ATDDR5, and
so forth.
If automatic compare of conversion results is enabled (CMPE[n]=1 in ATDCMPE), the conversion complete flag
is only set if comparison with ATDDRnis true. If ACMPIE=1 a compare interrupt will be requested. In this case,
as the ATDDRnresult register is used to hold the compare value, the result will not be stored there at the end of
the conversion but is lost.
A flag CCF[n] is cleared when one of the following occurs:
A) Write to ATDCTL5 (a new conversion sequence is started)
B) If AFFC=0, write “1” to CCF[n]
C) If AFFC=1 and CMPE[n]=0, read of result register ATDDRn
D) If AFFC=1 and CMPE[n]=1, write to result register ATDDRn
In case of a concurrent set and clear on CCF[n]: The clearing by method A) will overwrite the set. The clearing
by methods B) or C) or D) will be overwritten by the set.
0 Conversion number n not completed or successfully compared
1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn.
If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare
operator CMPGT[n] is true. (No result available in ATDDRn)
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 269
8.3.2.10 ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
8.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x000C
1514131211109876543210
R 1 1 1 1 1 11111 IEN[5:0]
W
Reset 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-12. ATD Input Enable Register (ATDDIEN)
Table 8-19. ATDDIEN Field Descriptions
Field Description
5–0
IEN[5:0]
ATD Digital Input Enable on channel x(x=5,4,3,2,1,0)— This bit controls the digital input buffer from the
analog input pin (ANx) to the digital data register.
0 Disable digital input buffer to ANx pin
1 Enable digital input buffer on ANx pin.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
Module Base + 0x000E
1514131211109876543210
R 0 0 0 0 0 00000 CMPHT[5:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-13. ATD Compare Higher Than Register (ATDCMPHT)
Table 8-20. ATDCMPHT Field Descriptions
Field Description
5–0
CMPHT[5:0]
Compare Operation Higher Than Enable for conversion number n (n= 5, 4, 3, 2, 1, 0) of a Sequence (n
conversion number, NOT channel number!) — This bit selects the operator for comparison of conversion
results.
0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2
1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
270 Freescale Semiconductor
8.3.2.12 ATD Conversion Result Registers (ATDDRn)
The A/D conversion results are stored in 6 result registers. Results are always in unsigned data
representation. Left and right justification is selected using the DJM control bit in ATDCTL3.
If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must
be written with the compare values in left or right justified format depending on the actual value of the
DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be
stored there at the end of the conversion but is lost.
Attention, n is the conversion number, NOT the channel number!
Read: Anytime
Write: Anytime
NOTE
For conversions not using automatic compare, results are stored in the result
registers after each conversion. In this case avoid writing to ATDDRn except
for initial values, because an A/D result might be overwritten.
8.3.2.12.1 Left Justified Result Data (DJM=0)
Table 8-21 shows how depending on the A/D resolution the conversion result is transferred to the ATD
result registers for left justified data. Compare is always done using all 12 bits of both the conversion result
and the compare value in ATDDRn.
Table 8-21. Conversion result mapping to ATDDRn
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5
1514131211109876543210
RResult-Bit[11:0] 0000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-14. Left justified ATD conversion result register (ATDDRn)
A/D
resolution DJM conversion result mapping to ATDDRn
8-bit data 0 Result-Bit[11:4] = conversion result,
Result-Bit[3:0]=0000
10-bit data 0 Result-Bit[11:2] = conversion result,
Result-Bit[1:0]=00
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 271
8.3.2.12.2 Right Justified Result Data (DJM=1)
Table 8-22 shows how depending on the A/D resolution the conversion result is transferred to the ATD
result registers for right justified data. Compare is always done using all 12 bits of both the conversion
result and the compare value in ATDDRn.
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5
1514131211109876543210
R 0 000 Result-Bit[11:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-15. Right justified ATD conversion result register (ATDDRn)
Table 8-22. Conversion result mapping to ATDDRn
A/D
resolution DJM conversion result mapping to ATDDRn
8-bit data 1 Result-Bit[7:0] = result,
Result-Bit[11:8]=0000
10-bit data 1 Result-Bit[9:0] = result,
Result-Bit[11:10]=00
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
272 Freescale Semiconductor
8.4 Functional Description
The ADC12B6C consists of an analog sub-block and a digital sub-block.
8.4.1 Analog Sub-Block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.
8.4.1.1 Sample and Hold Machine
The Sample and Hold Machine controls the storage and charge of the sample capacitor to the voltage level
of the analog signal at the selected ADC input channel.
During the sample process the analog input connects directly to the storage node.
The input analog signals are unipolar and must be within the potential range of VSSA to VDDA.
During the hold process the analog input is disconnected from the storage node.
8.4.1.2 Analog Input Multiplexer
The analog input multiplexer connects one of the 6 external analog input channels to the sample and hold
machine.
8.4.1.3 Analog-to-Digital (A/D) Machine
The A/D Machine performs analog to digital conversions. The resolution is program selectable to be either
8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the
sampled and stored analog voltage with a series of binary coded discrete voltages. By following a binary
search algorithm, the A/D machine identifies the discrete voltage that is nearest to the sampled and stored
voltage.
When not converting the A/D machine is automatically powered down.
Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result
in a non-railed digital output code.
8.4.2 Digital Sub-Block
This subsection describes some of the digital features in more detail. See Section 8.3.2, “Register
Descriptions” for all details.
8.4.2.1 External Trigger Input
The external trigger feature allows the user to synchronize ATD conversions to an external event rather
than relying only on software to trigger the ATD module when a conversions is about to take place. The
external trigger signal (out of reset ATD channel 5, configurable in ATDCTL1) is programmable to be edge
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 273
or level sensitive with polarity control. Table 8-23 gives a brief description of the different combinations
of control bits and their effect on the external trigger function.
In either level or edge sensitive mode, the first conversion begins when the trigger is received.
Once ETRIGE is enabled a conversion must be triggered externally after writing to ATDCTL5 register.
During a conversion in edge sensitive mode, if additional trigger events are detected the overrun error flag
ETORF is set.
If level sensitive mode is active and the external trigger de-asserts and later asserts again during a
conversion sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger is left
active in level sensitive mode when a sequence is about to be complete, another sequence will be triggered
immediately.
8.4.2.2 General-Purpose Digital Port Operation
Each ATD input pin can be switched between analog or digital input functionality. An analog multiplexer
makes each ATD input pin selected as analog input available to the A/D converter.
The pad of the ATD input pin is always connected to the analog input channel of the analog mulitplexer.
Each pad input signal is buffered to the digital port register.
This buffer can be turned on or off with the ATDDIEN register for each ATD input pin.
This is important so that the buffer does not draw excess current when an ATD input pin is selected as
analog input to the ADC12B6C.
Table 8-23. External Trigger Control Bits
ETRIGLE ETRIGP ETRIGE SCAN Description
X X 0 0 Ignores external trigger. Performs one
conversion sequence and stops.
X X 0 1 Ignores external trigger. Performs
continuous conversion sequences.
0 0 1 X Trigger falling edge sensitive. Performs
one conversion sequence per trigger.
0 1 1 X Trigger rising edge sensitive. Performs one
conversion sequence per trigger.
1 0 1 X Trigger low level sensitive. Performs
continuous conversions while trigger level
is active.
1 1 1 X Trigger high level sensitive. Performs
continuous conversions while trigger level
is active.
Analog-to-Digital Converter (ADC12B6CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
274 Freescale Semiconductor
8.5 Resets
At reset the ADC12B6C is in a power down state. The reset state of each individual bit is listed within the
Register Description section (see Section 8.3.2, “Register Descriptions”) which details the registers and
their bit-field.
8.6 Interrupts
The interrupts requested by the ADC12B6C are listed in Table 8-24. Refer to MCU specification for
related vector address and priority.
See Section 8.3.2, “Register Descriptions” for further details.
Table 8-24. ATD Interrupt Vectors
Interrupt Source CCR
Mask Local Enable
Sequence Complete Interrupt I bit ASCIE in ATDCTL2
Compare Interrupt I bit ACMPIE in ATDCTL2
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 275
Chapter 9
Pulse-Width Modulator (S12PWM8B8CV2)
9.1 Introduction
The Version 2 of S12 PWM module is a channel scalable and optimized implementation of S12
PWM8B8C Version 1. The channel is scalable in pairs from PWM0 to PWM7 and the available channel
number is 2, 4, 6 and 8. The shutdown feature has been removed and the flexibility to select one of four
clock sources per channel has improved. If the corresponding channels exist and shutdown feature is not
used, the Version 2 is fully software compatible to Version 1.
9.1.1 Features
The scalable PWM block includes these distinctive features:
• Up to eight independent PWM channels, scalable in pairs (PWM0 to PWM7)
• Available channel number could be 2, 4, 6, 8 (refer to device specification for exact number)
• Programmable period and duty cycle for each channel
• Dedicated counter for each PWM channel
• Programmable PWM enable/disable for each channel
• Software selection of PWM duty pulse polarity for each channel
• Period and duty cycle are double buffered. Change takes effect when the end of the effective period
is reached (PWM counter reaches zero) or when the channel is disabled.
• Programmable center or left aligned outputs on individual channels
• Up to eight 8-bit channel or four 16-bit channel PWM resolution
• Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
• Programmable clock select logic
9.1.2 Modes of Operation
There is a software programmable option for low power consumption in wait mode that disables the input
clock to the prescaler.
In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is
useful for emulation.
Wait: The prescaler keeps on running, unless PSWAI in PWMCTL is set to 1.
Freeze: The prescaler keeps on running, unless PFRZ in PWMCTL is set to 1.
Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
276 Freescale Semiconductor
9.1.3 Block Diagram
Figure 9-1 shows the block diagram for the 8-bit up to 8-channel scalable PWM block.
Figure 9-1. Scalable PWM Block Diagram
9.2 External Signal Description
The scalable PWM module has a selected number of external pins. Refer to device specification for exact
number.
9.2.1 PWM7 - PWM0 — PWM Channel 7 - 0
Those pins serve as waveform output of PWM channel 7 - 0.
Period and Duty Counter
Channel 6
Clock Select PWM Clock
Period and Duty Counter
Channel 5
Period and Duty Counter
Channel 4
Period and Duty Counter
Channel 3
Period and Duty Counter
Channel 2
Period and Duty Counter
Channel 1
Alignment
Polarity
Control
PWM8B8C
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
Enable
PWM Channels
Period and Duty Counter
Channel 7
Period and Duty Counter
Channel 0
PWM0
PWM7
Bus Clock
Maximum possible channels, scalable in pairs from PWM0 to PWM7.
Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 277
9.3 Memory Map and Register Definition
9.3.1 Module Memory Map
This section describes the content of the registers in the scalable PWM module. The base address of the
scalable PWM module is determined at the MCU level when the MCU is defined. The register decode map
is fixed and begins at the first address of the module address offset. The figure below shows the registers
associated with the scalable PWM and their relative offset from the base address. The register detail
description follows the order they appear in the register map.
Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented
functions are indicated by shading the bit.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
9.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the scalable PWM module.
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
0x0000
PWME1RPWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
W
0x0001
PWMPOL1RPPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
W
0x0002
PWMCLK1RPCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
W
0x0003
PWMPRCLK
R0 PCKB2 PCKB1 PCKB0 0PCKA2 PCKA1 PCKA0
W
0x0004
PWMCAE1RCAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
W
0x0005
PWMCTL1RCON67 CON45 CON23 CON01 PSWAI PFRZ 00
W
0x0006
PWMCLKAB
1
R
PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0
W
= Unimplemented or Reserved
Figure 9-2. The scalable PWM Register Summary (Sheet 1 of 4)
Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
278 Freescale Semiconductor
0x0007
RESERVED
R00 0 00000
W
0x0008
PWMSCLA
RBit 7 6 5 4 3 2 1 Bit 0
W
0x0009
PWMSCLB
RBit 7 6 5 4 3 2 1 Bit 0
W
0x000A
RESERVED
R00 0 00000
W
0x000B
RESERVED
R00 0 00000
W
0x000C
PWMCNT02R Bit 7 6 5 4 3 2 1 Bit 0
W00 0 00000
0x000D
PWMCNT12R Bit 7 6 5 4 3 2 1 Bit 0
W00 0 00000
0x000E
PWMCNT22R Bit 7 6 5 4 3 2 1 Bit 0
W00 0 00000
0x000F
PWMCNT32R Bit 7 6 5 4 3 2 1 Bit 0
W00 0 00000
0x0010
PWMCNT42R Bit 7 6 5 4 3 2 1 Bit 0
W00 0 00000
0x0011
PWMCNT52R Bit 7 6 5 4 3 2 1 Bit 0
W00 0 00000
0x0012
PWMCNT62R Bit 7 6 5 4 3 2 1 Bit 0
W00 0 00000
0x0013
PWMCNT72R Bit 7 6 5 4 3 2 1 Bit 0
W00 0 00000
0x0014
PWMPER02RBit 7 6 5 4 3 2 1 Bit 0
W
0x0015
PWMPER12RBit 7 6 5 4 3 2 1 Bit 0
W
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 9-2. The scalable PWM Register Summary (Sheet 2 of 4)
Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 279
0x0016
PWMPER22RBit 7 6 5 4 3 2 1 Bit 0
W
0x0017
PWMPER32RBit 7 6 5 4 3 2 1 Bit 0
W
0x0018
PWMPER42RBit 7 6 5 4 3 2 1 Bit 0
W
0x0019
PWMPER52RBit 7 6 5 4 3 2 1 Bit 0
W
0x001A
PWMPER62RBit 7 6 5 4 3 2 1 Bit 0
W
0x001B
PWMPER72RBit 7 6 5 4 3 2 1 Bit 0
W
0x001C
PWMDTY02RBit 7 6 5 4 3 2 1 Bit 0
W
0x001D
PWMDTY12RBit 7 6 5 4 3 2 1 Bit 0
W
0x001E
PWMDTY22RBit 7 6 5 4 3 2 1 Bit 0
W
0x001F
PWMDTY32RBit 7 6 5 4 3 2 1 Bit 0
W
0x0010
PWMDTY42RBit 7 6 5 4 3 2 1 Bit 0
W
0x0021
PWMDTY52RBit 7 6 5 4 3 2 1 Bit 0
W
0x0022
PWMDTY62RBit 7 6 5 4 3 2 1 Bit 0
W
0x0023
PWMDTY72RBit 7 6 5 4 3 2 1 Bit 0
W
0x0024
RESERVED
R00 0 00000
W
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 9-2. The scalable PWM Register Summary (Sheet 3 of 4)
Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
280 Freescale Semiconductor
9.3.2.1 PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
NOTE
The first PWM cycle after enabling the channel can be irregular.
An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their
corresponding PWM output lines are disabled.
While in run mode, if all existing PWM channels are disabled (PWMEx–0 = 0), the prescaler counter shuts
off for power savings.
Read: Anytime
Write: Anytime
0x0025
RESERVED
R00 0 00000
W
0x0026
RESERVED
R00 0 00000
W
0x0027
RESERVED
R00 0 00000
W
1The related bit is available only if corresponding channel exists.
2The register is available only if corresponding channel exists.
Module Base + 0x0000
76543210
RPWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
W
Reset 00000000
Figure 9-3. PWM Enable Register (PWME)
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 9-2. The scalable PWM Register Summary (Sheet 4 of 4)
Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 281
9.3.2.2 PWM Polarity Register (PWMPOL)
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the
PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle
and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts
low and then goes high when the duty count is reached.
Table 9-2. PWME Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field Description
7
PWME7
Pulse Width Channel 7 Enable
0 Pulse width channel 7 is disabled.
1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when
its clock source begins its next cycle.
6
PWME6
Pulse Width Channel 6 Enable
0 Pulse width channel 6 is disabled.
1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit 6 when
its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled.
5
PWME5
Pulse Width Channel 5 Enable
0 Pulse width channel 5 is disabled.
1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when
its clock source begins its next cycle.
4
PWME4
Pulse Width Channel 4 Enable
0 Pulse width channel 4 is disabled.
1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when
its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output line 4 is disabled.
3
PWME3
Pulse Width Channel 3 Enable
0 Pulse width channel 3 is disabled.
1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when
its clock source begins its next cycle.
2
PWME2
Pulse Width Channel 2 Enable
0 Pulse width channel 2 is disabled.
1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when
its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output line 2 is disabled.
1
PWME1
Pulse Width Channel 1 Enable
0 Pulse width channel 1 is disabled.
1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when
its clock source begins its next cycle.
0
PWME0
Pulse Width Channel 0 Enable
0 Pulse width channel 0 is disabled.
1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when
its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line 0 is disabled.
Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
282 Freescale Semiconductor
Read: Anytime
Write: Anytime
NOTE
PPOLx register bits can be written anytime. If the polarity is changed while
a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition
9.3.2.3 PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of four clocks to use as the clock source for that channel as described
below.
Read: Anytime
Write: Anytime
NOTE
Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
Module Base + 0x0001
76543210
RPPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
W
Reset 00000000
Figure 9-4. PWM Polarity Register (PWMPOL)
Table 9-3. PWMPOL Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field Description
7–0
PPOL[7:0]
Pulse Width Channel 7–0 Polarity Bits
0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is
reached.
1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is
reached.
Module Base + 0x0002
76543210
RPCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
W
Reset 00000000
Figure 9-5. PWM Clock Select Register (PWMCLK)
Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VR Family Reference Manual, Rev. 2.8
Freescale Semiconductor 283
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK and PCLKABx bits
in PWMCLKAB (see Section 9.3.2.7, “PWM Clock A/B Select Register (PWMCLKAB)). For Channel
0, 1, 4, 5, the selection is shown in Table 9-5; For Channel 2, 3, 6, 7, the selection is shown in Table 9-6.
Table 9-5. PWM Channel 0, 1, 4, 5 Clock Source Selection
Table 9-6. PWM Channel 2, 3, 6, 7 Clock Source Selection
9.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
Read: Anytime
Write: Anytime
NOTE
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
Table 9-4. PWMCLK Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field Description
7-0
PCLK[7:0]
Pulse Width Channel 7-0 Clock Select
0 Clock A or B is the clock source for PWM channel 7-0, as shown in Table 9-5 and Table 9-6.
1 Clock SA or SB is the clock source for PWM channel 7-0, as shown in Table 9-5 and Table 9-6.
PCLKAB[0,1,4,5] PCLK[0,1,4,5] Clock Source Selection
0 0 Clock A
0 1 Clock SA
1 0 Clock B
1 1 Clock SB
PCLKAB[2,3,6,7] PCLK[2,3,6,7] Clock Source Selection
0 0 Clock B
0 1 Clock SB
1 0 Clock A
1 1 Clock SA
Module Base + 0x0003
76543210
R0 PCKB2 PCKB1 PCKB0 0PCKA2 PCKA1 PCKA0
W
Reset 00000000
= Unimplemented or Reserved
Figure 9-6. PWM Prescale Clock Select Register (PWMPRCLK)
