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FEATURES DESCRIPTION
APPLICATIONS
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER
•Spread-Spectrum Clock Compatible
The CDCVF857 is a high-performance, low-skew,low-jitter, zero-delay buffer that distributes a•Operating Frequency: 60 MHz to 220 MHz
differential clock input pair (CLK, CLK) to 10•Low Jitter (Cycle-Cycle): ±35 ps
differential pairs of clock outputs (Y[0:9], Y[0:9]) and•Low Static Phase Offset: ±50 ps
one differential pair of feedback clock outputs•Low Jitter (Period): ±30 ps (FBOUT, FBOUT). The clock outputs are controlledby the clock inputs (CLK, CLK), the feedback clocks•1-to-10 Differential Clock Distribution (SSTL2)
(FBIN, FBIN), and the analog power input (AVDD).•Best in Class for V
OX
= V
DD
/2 ±0.1 V
When PWRDWN is high, the outputs switch in phase•Operates From Dual 2.6-V or 2.5-V Supplies
and frequency with CLK. When PWRDWN is low, alloutputs are disabled to a high-impedance state•Available in a 40-Pin MLF Package, 48-Pin
(3-state) and the PLL is shut down (low-powerTSSOP Package, 56-Ball MicroStar Junior™
mode). The device also enters this low-power modeBGA Package
when the input frequency falls below a suggested•Consumes < 100- µA Quiescent Current
detection frequency that is below 20 MHz (typical 10MHz). An input frequency detection circuit detects•External Feedback Pins (FBIN, FBIN) Are Used
the low frequency condition and, after applying ato Synchronize the Outputs to the Input
>20-MHz input signal, this detection circuit turns theClocks
PLL on and enables the outputs.•Meets/Exceeds JEDEC Standard (JESD82-1)
When AV
DD
is strapped low, the PLL is turned offFor DDRI-200/266/333 Specification
and bypassed for test purposes. The CDCVF857 is•Meets/Exceeds Proposed DDRI-400
also able to track spread spectrum clocking forSpecification (JESD82-1A)
reduced EMI.•Enters Low-Power Mode When No CLK Input
Because the CDCVF857 is based on PLL circuitry, itSignal Is Applied or PWRDWN Is Low
requires a stabilization time to achieve phase-lock ofthe PLL. This stabilization time is required followingpower up. The CDCVF857 is characterized for both•DDR Memory Modules (DDR400/333/266/200)
commercial and industrial temperature ranges.•Zero-Delay Fan-Out Buffer
A
A
AVAILABLE OPTIONS
T
A
TSSOP (DGG) 40-Pin MLF 56-Ball BGA
(1)
–40 °C to 85 °C CDCVF857DGG CDCVF857RTB CDCVF857GQL–40 °C to 85 °C CDCVF857RHA CDCVF857ZQL
(1) Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum T
A
allowed is 70 °C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.MicroStar Junior is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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FUNCTION TABLE
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
11 12 13 14 15 16 17 18 19 20
37 36 35 34 3338 32 31
40 39
GND
GND
Y3
Y2
Y3
Y2
VDDQ
VDDQ
Y4
CLK
Y9
CLK
Y4
VDDQ
Y9
AVDD
VDDQ
AGND
Y8
GND
Y8
Y7
Y1
Y7
Y1
VDDQ
VDDQ
PWRDWN
Y0
FBIN
Y0
FBIN
Y5
VDDQ
Y5
VDDQ
VDDQ
FBOUT
Y6
FBOUT
Y6
P0053-01
RHA/RTBPACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DGGPACKAGE
(TOP VIEW)
GND
Y0
Y0
VDDQ
Y1
Y1
GND
GND
Y2
Y2
VDDQ
VDDQ
CLK
CLK
VDDQ
AVDD
AGND
GND
Y3
Y3
VDDQ
Y4
Y4
GND
GND
Y5
Y5
VDDQ
Y6
Y6
GND
GND
Y7
Y7
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
VDDQ
Y9
Y9
GND
P0052-01
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
(Select Functions)INPUTS OUTPUTS PLL
AVDD PWRDWN CLK CLK Y[0:9] Y[0:9] FBOUT FBOUTGND H L H L H L H Bypassed/offGND H H L H L H L Bypassed/offX L L H Z Z Z Z OffX L H L Z Z Z Z Off2.5 V (nom) H L H L H L H On2.5 V (nom) H H L H L H L On2.5 V (nom) X <20 MHz <20 MHz Z Z Z Z Off
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65
A
B
C
D
E
F
3
21
G
H
4
Y2
CLK
NC
NC
NC
NC
NB
NB NB
NC NC
NC
Y1
J
K
NC
GND
VDDQ
VDDQ
AGND
Y3
Y3
GND
AVDD
CLK
VDDQ
Y2
GND
Y1
Y6
Y6
GND
GND
Y7
Y7
PWRDWN
VDDQ
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
Y0
Y0
VDDQ
GND
VDDQ
GND
Y5
Y5
MicroStarJunior BGA (GQL/ZQL)PACKAGE
(TOP VIEW)
™
NB=NoBall
NC=NoConnection
Y4
Y9
Y4
Y9
GND
GND
VDDQ
VDDQ
P0054-01
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
MicroStar Junior™
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30
Y8
29
40
Y7
39
43
Y6
44
47
Y5
46
23
Y4
22
19
Y3
20
9
Y2
10
6
Y1
5
Y0
3
2
26
Y9
27
33
FBOUT
32
16
37
13
36
14
35
PLL
PWRDWN
AVDD
CLK
CLK
FBIN
FBIN
FBOUT
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
PowerDown
and
TestLogic
B0196-01
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
FUNCTIONAL BLOCK DIAGRAM
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ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME DGG RHA/RTB GQL/ZQL
AGND 17 9 H1 – Ground for 2.5-V analog supplyAV
DD
16 8 G2 – 2.5-V analog supplyCLK, CLK 13, 14 5, 6 F1, F2 I Differential clock inputFBIN, FBIN 35, 36 25, 26 F5, F6 I Feedback differential clock inputFBOUT,
32, 33 21, 22 H6, G5 O Feedback differential clock outputFBOUT
1, 7, 8, 18, 24, 25, A3, A4, C1, C2, C5,GND 1, 10 – Ground31, 41, 42, 48 C6, H2, H5, K3, K4PWRDWN 37 27 E6 I Output enable for Y and Y4, 11, 12, 15, 21, 28, 4, 7, 13, 18, 23, 24, B3, B4, E1, E2, E5,V
DDQ
– 2.5-V supply34, 38, 45 28, 33, 38 G1, G6, J3, J4Y0, Y0 3, 2 37, 36 A1, A2 OY1, Y1 5, 6 39, 40 B2, B1 OY2, Y2 10, 9 3, 2 D1, D2 OY3, Y3 20, 19 12,11 J2, J1 OY4, Y4 22, 23 14, 15 K1, K2 O
Buffered output copies of input clock, CLK, CLKY5, Y5 46, 47 34, 35 A6, A5 OY6, Y6 44, 43 32, 31 B5, B6 OY7, Y7 39, 40 29, 30 D6, D5 OY8, Y8 29, 30 19, 20 J5, J6 OY9, Y9 27, 26 17, 16 K6, K5 O
over operating free-air temperature range (unless otherwise noted)
(1)
V
DDQ
, AV
DD
Supply voltage range 0.5 V to 3.6 VV
I
Input voltage range
(2) (3)
–0.5 V to V
DDQ
+ 0.5 VV
O
Output voltage range
(2) (3)
–0.5 V to V
DDQ
+ 0.5 VI
IK
Input clamp current V
I
< 0 or V
I
> V
DDQ
±50 mAI
OK
Output clamp current V
O
< 0 or V
O
> V
DDQ
±50 mAI
O
Continuous output current V
O
= 0 to V
DDQ
±50 mAI
DDC
Continuous current to GND or V
DDQ
±100 mAT
stg
Storage temperature range –65 °C to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.(3) This value is limited to 3.6 V maximum.
R
θJA
for TSSOP (DGG) Package
(1)
R
θJA
for MLF (RHA/RTB) Package R
θJA
for BGA (GQL/ZQL) Package
(2)
Airflow Low K High K Airflow With 4 Thermal Vias Airflow High K
0 ft/min 89.1 °C/W 70 °C/W 0 ft/min 44.7 °C/W 0 ft/min 132.2 °C/W150 ft/min 78.5 °C/W 65.3 °C/W 150 ft/min 150 ft/min 126.4 °C/W
(1) The package thermal impedance is calculated in accordance with JESD 51.(2) Connecting the NC-balls (C3, C4, D3, D4, G3, G4, H3, H4) to a ground plane improves the θ
JA
to 114.8 °C/W (0 airflow).
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
MIN NOM MAX UNIT
V
DDQ
PC1600 – PC3200 2.3 2.7Supply voltage VAVDD V
DDQ
– 0.12 2.7CLK, CLK, FBIN, FBIN V
DDQ
/2 – 0.18V
IL
Low-level input voltage VPWRDWN –0.3 0.7CLK, CLK, FBIN, FBIN VDDQ/2 + 0.18V
IH
High-level input voltage VPWRDWN 1.7 V
DDQ
+ 0.3DC input signal voltage
(1)
–0.3 V
DDQ
+ 0.3 VDC CLK, FBIN 0.36 V
DDQ
+ 0.6V
ID
Differential input signal voltage
(2)
VAC CLK, FBIN 0.7 V
DDQ
+ 0.6V
IX
Input differential pair cross voltage
(3) (4)
V
DDQ
/2 – 0.2 V
DDQ
/2 + 0.2 VI
OH
High-level output current –12 mAI
OL
Low-level output current 12 mASR Input slew rate 1 4 V/nsT
A
Operating free-air temperature –40 85 °C
(1) The unused inputs must be held high or low to prevent them from floating.(2) The dc input signal voltage specifies the allowable dc execution of the differential input.(3) The differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true inputlevel and VCP is the complementary input level.(4) The differential cross-point voltage tracks variations of V
CC
and is the voltage at which the differential signals must cross.
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
Input voltage, all inputs V
DDQ
= 2.3 V, I
I
= –18 mA –1.2 VV
DDQ
= min to max, I
OH
= –1 mA V
DDQ
– 0.1V
OH
High-level output voltage VV
DDQ
= 2.3 V, I
OH
= –12 mA 1.7V
DDQ
= min to max, I
OL
= 1 mA 0.1V
OL
Low-level output voltage VV
DDQ
= 2.3 V, I
OL
= 12 mA 0.6V
OD
Output voltage swing
(2)
1.1 V
DDQ
– 0.4 VDifferential outputs are terminated withOutput differential
120 Ω, C
L
= 14 pF (see Figure 3 )V
OX
V
DDQ
/2 – 0.1 V
DDQ
/2 V
DDQ
/2 + 0.1 Vcross-voltage
(3)
I
I
Input current V
DDQ
= 2.7 V, V
I
= 0 V to 2.7 V ±10 µAHigh-impedance-state outputI
OZ
V
DDQ
= 2.7 V, V
O
= V
DDQ
or GND ±10 µAcurrent
Power-down current on V
DDQ
CLK and CLK = 0 MHz; PWRDWN =I
DDPD
20 100 µA+ AV
DD
Low; Σof I
DD
and AI
DD
f
O
= 170 MHz 6 8AI
DD
Supply current on AV
DD
mAf
O
= 200 MHz 8 10C
I
Input capacitance V
DDQ
= 2.5 V, V
I
= V
DDQ
or GND 2 2.5 3.5 pFf
O
= 170 MHz 120 140Without load
f
O
= 200 MHz 125 150Differential outputs f
O
= 170 MHz 220 270terminated with 120 Ω, C
LI
DD
Dynamic current on V
DDQ
mAf
O
= 200 MHz 230 280= 0 pFDifferential outputs f
O
= 170 MHz 280 330terminated with 120 Ω, C
L
f
O
= 200 MHz 300 350= 14 pF
(1) All typical values are at nominal V
DDQ
.(2) The differential output signal voltage specifies the differential voltage |VTR – VCP|, where VTR is the true output level and VCP is thecomplementary output level.(3) The differential cross-point voltage tracks variations of V
DDQ
and is the voltage at which the differential signals must cross.
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TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Part-to-part input∆C V
DDQ
= 2.5 V, V
I
= V
DDQ
or GND 1 pFcapacitance variationInput capacitance differenceC
I( ∆)
between CLK and CLK, V
DDQ
= 2.5 V, V
I
= V
DDQ
or GND 0.25 pFFBIN, and FBIN
over recommended ranges of supply voltage and operating free-air temperature
PARAMETER MIN MAX UNIT
Operating clock frequency 60 220f
CLK
MHzApplication clock frequency 90 220Input clock duty cycle 40% 60%Stabilization time (PLL mode)
(1)
10 µsStabilization time (bypass mode)
(2)
30 ns
(1) The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to beobtained, a fixed-frequency, fixed-phase reference signal must be present at CLK and V
DD
must be applied. Until phase lock is obtained,the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. Thisparameter does not apply for input modulation under SSC application.(2) A recovery time is required when the device goes from power-down mode into bypass mode (AV
DD
at GND).
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
(1)
Low-to-high level propagation delay time Test mode/CLK to any output 3.5 nst
PHL
(1)
High-to-low level propagation delay time Test mode/CLK to any output 3.5 ns100 MHz (PC1600) –65 65t
jit(per)
(2)
Jitter (period), see Figure 7 ps133/167/200 MHz (PC2100/2700/3200) –30 30100 MHz (PC1600) –50 50t
jit(cc)
(2)
Jitter (cycle-to-cycle), see Figure 4 ps133/167/200 MHz (PC2100/2700/3200) –35 35100 MHz (PC1600) –100 100t
jit(hper)
(2)
Half-period jitter, see Figure 8 ps133/167/200 MHz (PC2100/2700/3200) –75 75t
slr(o)
Output clock slew rate, see Figure 9 Load: 120 Ω, 14 pF 1 2 V/nst
(φ)
Static phase offset, see Figure 5 100/133/167/200 MHz –50 50 pst
sk(o)
Output skew, see Figure 6 Load: 120 Ω, 14 pF; 100/133/167/200 MHz 40 ps
(1) Refers to the transition of the noninverting output.(2) This parameter is assured by design but cannot be 100% production tested.
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PARAMETER MEASUREMENT INFORMATION
GND
VDD
R=60 W
VYx
R=60 WV /2
DD
VYx
CDCVF857
S0229-01
Scope
C=14pF
Z=60 W
Z=60 WZ=50 W
Z=50 W
R=50 W
R=50 W
V(TT)
V(TT)
C=14pF
–VDD/2
–VDD/2
V =GND
(TT)
–VDD/2
VDD/2
R=10 W
R=10 W
CDCVF857
S0230-01
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
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Probe
C=14pF
Z=60 W
Z=60 W
R=1MW
R=1MW
V(TT)
V(TT)
C=14pF
GND
GND
C=1pF
C=1pF
V =GND
(TT)
GND
VDD
R=120 W
CDCVF857
S0231-01
(N>1000Samples)
FBIN
t( )nft( )n+1f
CLK
FBIN
CLK
t( )nf
t( )f=
n=N
1
N
S
T0175-01
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Output Load Test Circuit for Crossing Point
Figure 4. Cycle-to-Cycle Jitter
Figure 5. Phase Offset
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Yx,FBOUT
tsk(o)
Yx
YxFBOUT,
Yx
T0176-01
Yx,FBOUT
Yx,FBOUT
YxFBOUT,
YxFBOUT,
T0177-01
tc(n)
f0= AverageInputFrequencyMeasuredatCLK/CLK
f0
1
tjit(per) =tc(n) –f0
1
Yx,FBOUT
YxFBOUT,
T0178-01
f0= AverageInputFrequencyMeasuredatCLK/CLK
n= AnyHalfCycle
f0
1
t(hper_n) t(hper_n+1)
tjit(hper) =t(hper_n) –2 f´0
1
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Output Skew
Figure 7. Period Jitter
Figure 8. Half-Period Jitter
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ClockInputs
andOutputs
80%
20%
80%
20%
trtf
V ,V
OH IH
V ,V
OL IL
tslr(I/O) =tr
V – V
80% 20% tslf(I/O) =tf
V – V
80% 20%
T0179-01
VDDQ
AVDD
AGND
GND
Card
Via
Card
Via
4.7 F
1206
m0.1 F
0603
m2200pF
0603
(1)
PLL
S0232-01
Bead
0603
(2)
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Input and Output Slew Rates
(1) Place the 2200-pF capacitor close to the PLL.(2) Recommended bead: Fair-Rite P/N 2506036017Y0 or equilvalent (0.8 Ωdc maximum, 600 Ωat 100 MHz).NOTE: Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connecttrace to one GND via (farthest from the PLL).
Figure 10. Recommended AV
DD
Filtering
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CDCVF857DGG ACTIVE TSSOP DGG 48 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CDCVF857DGGG4 ACTIVE TSSOP DGG 48 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CDCVF857DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CDCVF857DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CDCVF857GQLR ACTIVE BGA
MICROSTAR
JUNIOR
GQL 56 1000 TBD SNPB Level-2A-220C-4 WKS
CDCVF857RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CDCVF857RHARG4 ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CDCVF857RHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CDCVF857RHATG4 ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CDCVF857RTBR OBSOLETE VQFN RTB 40 TBD Call TI Call TI
CDCVF857RTBT OBSOLETE VQFN RTB 40 TBD Call TI Call TI
CDCVF857ZQLR ACTIVE BGA
MICROSTAR
JUNIOR
ZQL 56 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Jul-2012
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CDCVF857DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
CDCVF857GQLR BGA MI
CROSTA
R JUNI
OR
GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1
CDCVF857RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
CDCVF857RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
CDCVF857ZQLR BGA MI
CROSTA
R JUNI
OR
ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCVF857DGGR TSSOP DGG 48 2000 367.0 367.0 45.0
CDCVF857GQLR BGA MICROSTAR
JUNIOR GQL 56 1000 333.2 345.9 28.6
CDCVF857RHAR VQFN RHA 40 2500 367.0 367.0 38.0
CDCVF857RHAT VQFN RHA 40 250 210.0 185.0 35.0
CDCVF857ZQLR BGA MICROSTAR
JUNIOR ZQL 56 1000 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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