2
ICS951901
0670B—07/15/04
General Description
Pin Configuration
The ICS951901 is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary
clock signals for such a system.
The ICS951901 belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing
output functions, changing output frequency, configuring
output strength, configuring output to output skew, changing
spread spectrum amount, changing group divider ratio and
dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system becomes
unstable from over clocking.
Power Gr oups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
EDOM 12niP 72niP82niP03niP13niP
011MARDS01MARDS9MARDS8MARDS
1#POTS_UPC#POTS_ICP#POTS_MARDS#DP
MODE Pin Power Management Control Input
PIN NUMBER PIN NAME TYPE DESCRIPTI O N
1, 7, 15, 22, 25,
35, 43 VDD PWR 3.3V Power supply for SD RA M output buffers , PCI output buf fers,
reference out put buffer s and 48MHz out put
AG PSEL IN AG P frequency s elect pin.
REF 0 O UT 14. 318 MHz reference c lock .
F S 3 I N Frequency s elec t pin.
REF 1 O UT 14. 318 MHz reference c lock .
4, 14, 18, 19, 29,
32, 39, 44 G ND PW R G r ound pin f or 3V out puts.
5 X1 I N Cr ys t al input,nom inally 14. 318M Hz .
6 X2 O UT Cry s t al out put, nominally 14. 318M Hz .
F S 1 I N Frequency s elec t pin.
PCICLK_F O UT PCI clock output, not affec ted by PCI _S T OP#
F S 2 I N Frequency s elec t pin.
PCICLK0 O UT PCI clock output.
13, 12, 11, 10 PCICLK (4: 1) O UT PCI clock outputs .
17, 16, AGP (1:0) O UT AGP out put s def ined as 2X P CI . T hese m ay not be stopped.
F S 0 I N Frequency s elec t pin.
48MHz O UT 48MHz output c loc k
MODE IN P in 27, 28, 30, & 31 func tion select pin
0=Des k top 1=Mobile mode
24_48MHz O UT Clock output for super I/ O /USB default is 24MHz
23 SDATA I/O Data pin for I2C c irc uit r y 5V tolerant
24 SCLK IN Clock pin of I 2C circ uit r y 5V toler ant
CPU_STOP# IN S tops all PCI CLK s bes ides the PCI CLK_F clock s at logic 0 level,
when input is low and MO DE pin is in Mobile mode
SD RAM11 OUT SD RAM clock output
PCI_STOP# IN Stops all CPUCLKs cloc k s at logic 0 level, when input is low and
MODE pin is in Mobile mode
SD RAM10 OUT SD RAM clock output
SDRA M9 OUT SDRA M c loc k output
SDRAM_STOP# IN S tops all SDRAM cloc k s at logic 0 level, w hen input is low and
MODE pin is in Mobile mode
PD# IN
int o a low power state. The int er nal cloc k s ar e disabled and t he
VCO and t he c r ys tal are st opped. The latenc y of the power down will
SDRA M8 OUT SDRA M c loc k output
26 33, 34, 36,
37, 38, 40, 41,
42
SDRA M ( 12,
7:0) OUT SDRA M clock outputs
45, 46, 47 CPUCLK (2:0) O UT CP U cloc k out puts.
48 VDDL PWR Power pin for t he CPUCLK s . 2.5V
31
20
2
8
9
21
3
30
27
28