General Description
The MAX5938 is a hot-swap controller for -10V to -80V
rails. The MAX5938 allows circuit line cards to be safely
hot-plugged into a live backplane without causing a
glitch on the power supply. It integrates an adjustable
circuit-breaker function requiring no RSENSE.
The MAX5938 provides a controlled turn-on for circuit
cards, which limits inrush current and prevents both
glitches on the power-supply rail and damage to board
connectors and components. Before startup, the
MAX5938 performs a Load Probe™ test to detect the
presence of a short-circuit condition. If a short-circuit
condition does not exist, the device limits the inrush cur-
rent drawn by the load by gradually turning on the exter-
nal MOSFET. Once the external MOSFET is fully
enhanced, the MAX5938 provides overcurrent and short-
circuit protection by monitoring the voltage drop across
the RDS(ON) of the external power MOSFET. The
MAX5938 integrates a 400mA fast GATE pulldown to
guarantee that the external MOSFET is rapidly turned off
in the event of an overcurrent or short-circuit condition.
The MAX5938 also protects the system against input
voltage (VIN) steps. During an input voltage step, the
device limits the current drawn by the load to a safe level
without shutting down the load. The device also includes
ON/OFF control, selectable PGOOD output polarity,
undervoltage (UV) and overvoltage (OV) protection.
The device offers latched (MAX5938L) or autoretry
(MAX5938A) fault management. Both the MAX5938A
and MAX5938L are available in a 16-pin QSOP package
and are specified for the extended (-40°C to +85°C)
temperature range.
Applications
Servers
Telecom Line Cards
Network Switches
Solid-State Circuit Breakers
Network Routers
Features
♦-10V to -80V Operation
♦No External RSENSE Required
♦Drives Large Power MOSFETS
♦Eliminates Inrush Current Spikes During Hot Plug
into Powered Backplane
♦Eliminates Inrush Current Spikes and Dropping of
Load During Large VIN Steps
♦Adjustable Circuit-Breaker Threshold with
Temperature Compensation
♦Circuit-Breaker Fault with Transient Rejection
♦Shorted Load Detection (Load Probe) Before
Power MOSFET Turn-On
♦Programmable Load-Voltage Slew Rate Controls
Inrush Current
♦±2.4% Accuracy, Programmable Turn-On/Off
Voltage (UVLO)
♦Overvoltage Fault Protection with Transient
Rejection
♦Autoretry and Latched Fault Management
Available
♦Low Quiescent Current (1mA)
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
________________________________________________________________ Maxim Integrated Products 1
19-3320; Rev 1; 1/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX5938AEEE
-40°C to +85°C 16 QSOP
MAX5938LEEE -40°C to +85°C 16 QSOP
Typical Operating Circuit appears at end of data sheet.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GND PGOOD
N.C.
VOUT
N.C.
CB_ADJ
GATE
N.C.
LP
TOP VIEW
MAX5938
QSOP
N.C.
OFF
STEP_MON
ON
OV
POL_SEL
VEE
Pin Configuration
Load Probe is a trademark of Maxim Integrated Products, Inc.
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VEE, VOUT, PGOOD, LP,
STEP_MON to GND............................................+0.3V to -85V
PGOOD to VOUT.....................................................-0.3V to +85V
VOUT, LP, STEP_MON to VEE .................................-0.3V to +85V
GATE to VEE ...........................................................-0.3V to +20V
ON, OFF, OV, POL_SEL, CB_ADJ to VEE ................-0.3V to +6V
Input Current
LP (internally duty-cycle limited)..........................................1A
PGOOD (continuous) ......................................................80mA
GATE (during 15V clamp, continuous) ...........................30mA
GATE (during 2V clamp, continuous) .............................50mA
GATE (during gate pulldown, continuous)......................50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
ELECTRICAL CHARACTERISTICS
(VEE = -10V to -80V, VIN = (GND - VEE), VSTEP_MON =V
EE, RLP = 200Ω, VON = VOFF = 2V, VOV = VCB_ADJ = VEE, POL_SEL open, TA
= -40°C to +85°C, unless otherwise noted. Typical values are at VEE = -48V, TA= +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Operating Voltage Range VEE Referenced to GND -80 -10 V
Operating Supply Current ICC
0.95
1.4 mA
ON/OFF, OV
ON Reference Threshold Rising
VON_REF
,
R
VON increasing
1.219 1.25 1.281
V
ON Reference Threshold Falling
VON_REF
,
F
VON decreasing
1.069 1.125 1.181
V
ON Glitch Rejection (Note 3) tREJ VON decreasing
0.80
1.5
2.25
ms
OFF Reference Threshold
VOFF_REF 1.219 1.25 1.281
V
ON/OFF/OV Input Bias Current IBIAS -25
+25
nA
OV Reference Threshold, Rising
VOV_REF
,
R
VOV increasing
1.219 1.25 1.281
V
OV Reference Threshold, Falling
VOV_REF
,
F
VOV decreasing
1.069 1.125 1.181
V
OV Transient Rejection tOVREJ OV increasing
0.80
1.5
2.25
ms
Power-Up Delay (Note 4) tONDLY 80
220 380
ms
VOUT to VEE Leakage Current VOFF = VEE = -80V, VOUT = GND,
PGOOD open
0.01
1µA
LP to VEE Leakage Current VOFF = VEE = -80V, LP = GND
0.01
1µA
POL_SEL to VEE Input Current POL_SEL = VEE -50 -34 -20 µA
GATE DRIVE
VIN = 10V 6.5 6.8 7.2
External Gate-Drive Voltage VGS VGATE - VEE 14V < VIN < 80V 8.1 10
12.8
V
ICLAMP = 9mA
13.5
16
MOSFET fully
enhanced ICLAMP = 20mA 17
19.5
ICLAMP = 1mA 2.1
2.55
GATE to VEE Clamp Voltage
Power-off,
VEE = GND ICLAMP = 10mA 2.5
2.93
V
Open-Loop Gate Charge Current
IG,ON VGATE = VEE, VOUT = GND -66 -52 -35 µA
VIN > 10V 9.0
14.1
GATE Pulldown Switch
On-Resistance RG,OFF VGATE - VEE =
500mV VIN > 14V 7.5
12.5
mA
Output-Voltage Slew Rate SR l dVOUT/dt l, CSLEW = 0 2.4 9.0
14.8
V/ms
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -10V to -80V, VIN = (GND - VEE), VSTEP_MON =V
EE, RLP = 200Ω, VON = VOFF = 2V, VOV = VCB_ADJ = VEE, POL_SEL open, TA
= -40°C to +85°C, unless otherwise noted. Typical values are at VEE = -48V, TA= +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
UNITS
CIRCUIT BREAKER AND SHORT CIRCUIT
TA = +85°C 55 72 89
TA = +25°C 39 50 61
CB_ADJ Bias Current
ICB_ADJ
CB_ADJ = VEE
TA = -40°C 33
µA
TA = +85°C 59 72 85
TA = +25°C 41 50 59
CB_ADJ = VEE
TA = -40°C 33
TA = +85°C 123
144 165
TA = +25°C 85
100 115
TA = -10°C 66 82 98
Circuit-Breaker Threshold VCB
RCB_ADJ = 2kΩ
TA = -40°C 66
mV
ICB_ADJ Temperature Coefficient -40°C < TA < +85°C
6000
ppm/°C
Circuit-Breaker Glitch Rejection
tCB_DLY
1.0 1.2 1.6 ms
TA = +85°C 112
144 176
TA = +25°C 75
100 125
TA = -10°C 50 82
114
CB_ADJ = VEE
TA = -40°C 66
TA = +85°C 224
288 352
TA = +25°C 159
200 241
TA = -10°C 108
164 220
Short-Circuit Threshold (Note 5) VSC
RCB_ADJ = 2kΩ
TA = -40°C
132
mV
Short-Circuit Response Time 150mV overdrive, CLOAD = 0,
to GATE below 1V
330 500
ns
INPUT-VOLTAGE STEP PROTECTION
Input-Voltage-Step Detection
Threshold
STEPTH 1.219 1.25 1.281
V
Input-Voltage-Step Threshold
Offset Current
ISTEP_OS -10.8
-10
-9.2
µA
LOAD-PROBE CIRCUIT
Load-Probe Switch On-Resistance
VLP - VEE = 1V 7.5 11 Ω
Load-Probe Timeout tLP 80
220 380
ms
Load-Probe Retry Time tLP_OFF 16 x
tLP s
Shorted Load Detection Voltage
Threshold VTH_LP Referenced to GND
-220 -200 -180
mV
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
4_______________________________________________________________________________________
Note 1: All currents into pins are positive and all currents out of pins are negative. All voltages referenced to VEE, unless otherwise
specified.
Note 2: All limits are 100% tested at +25°C and +85°C. Limits at -40°C and -10°C are guaranteed by characterization.
Note 3: VON drops below the VON_REF,F threshold are ignored during this time.
Note 4: Delay time from a valid on condition until the load-probe test begins.
Note 5: The short-circuit threshold is VSC = 2 x VCB.
Note 6: The time when PGOOD condition is met until PGOOD signal is asserted.
Typical Operating Characteristics
(VEE = -48V, GND = 0V, VIN = GND - VEE, POL_SEL = floating, all voltages are referenced to VEE, unless otherwise noted. TA= +25°C,
unless otherwise noted.)
SUPPLY CURRENT
vs. INPUT VOLTAGE
MAZ5938 toc01
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
706040 503020
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
10 80
SUPPLY CURRENT
vs. TEMPERATURE
MAX5938 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
0.2
0.4
0.6
0.8
1.0
1.2
0
-40 85
VIN = 72V
VIN = 48V
VIN = 12V
GATE-DRIVE VOLTAGE
vs. INPUT VOLTAGE
MAX5938 toc03
INPUT VOLTAGE (V)
GATE DRIVER VOLTAGE (V)
706040 503020
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
6.0
10 80
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -10V to -80V, VIN = (GND - VEE), VSTEP_MON =V
EE, RLP = 200Ω, VON = VOFF = 2V, VOV = VCB_ADJ = VEE, POL_SEL open, TA
= -40°C to +85°C, unless otherwise noted. Typical values are at VEE = -48V, TA= +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
UNITS
LOGIC AND FAULT MANAGEMENT
Autoretry Delay tRETRY 16 x
tLP s
|VOUT - VEE| falling 0.74
x VCB
PGOOD Assertion Threshold
Hysteresis 0.26
x VCB
mV
PGOOD Assertion Delay Time
(Note 6) tPGOOD
0.70 1.26 1.85
ms
PGOOD Low Voltage VOL ISINK = 1mA, referenced to VOUT,
VOUT < (GND - 5V )
0.05
0.4 V
PGOOD Open-Drain Leakage ILVEE = -80V, PGOOD = GND
0.01
1µA
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
_______________________________________________________________________________________ 5
VOUT SLEW RATE
vs. TEMPERATURE
MAX5938 toc10
TEMPERATURE (°C)
SLEW RATE (V/ms)
603510-15
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
5.0
-40 85
CGATE = 0, CLOAD = 100µF
VIN = 48V
VIN = 72V
VIN = 12V
GATE PULLDOWN CURRENT
vs. GATE VOLTAGE
MAX5938 toc04
VGATE (V)
GATE PULLDOWN CURRENT (mA)
986 72 3 4 51
50
100
150
200
250
300
350
400
450
500
0
010
RETRY TIME
vs. TEMPERATURE
MAX5938 toc05
TEMPERATURE (°C)
RETRY TIME (s)
603510-15
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
3.0
-40 85
CGATE = 0, CLOAD = 100µF
STARTUP WAVEFORM
MAX5938 toc06
40ms/div
VIN
50V/div
VGATE
10V/div
VOUT
50V/div
IIN
2A/div
VPGOOD
50V/div
RLOAD = 48Ω
CLOAD = 100µF
CIRCUIT-BREAKER EVENT
MAX5938 toc07
1ms/div
IRFR1310
RCB_ADJ = 2kΩ
POL_SEL = OPEN
VGATE
10V/div
VOUT
50V/div
IIN
2A/div
VPGOOD
50V/div
VIN = 48V
SHORT-CIRCUIT EVENT
MAX5938 toc08
400ns/div
IRFR1310
RCB_ADJ = 2kΩ
RLOAD = 48Ω
POL_SEL = OPEN
VGATE
10V/div
VOUT
50V/div
IIN
10A/div
VPGOOD
50V/div
VIN = 48V
NORMALIZED CIRCUIT-BREAKER
THRESHOLD vs. TEMPERATURE
MAX5938 toc09
TEMPERATURE (°C)
NORMALIZED CIRCUIT-BREAKER THRESHOLD (%)
603510-15
0.6
0.8
1.0
1.2
1.4
1.6
0.4
-40 85
Typical Operating Characteristics (continued)
(VEE = -48V, GND = 0V, VIN = GND - VEE, POL_SEL = floating, all voltages are referenced to VEE, unless otherwise noted. TA= +25°C,
unless otherwise noted.)
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
6_______________________________________________________________________________________
INPUT VOLTAGE STEP TO
FAULT MANAGEMENT
MAX5938 toc12
4ms/div
IRFR1310
RCB_ADJ = 2kΩ
RLOAD = 20Ω
VIN
50V/div
VGATE
10V/div
VOUT
100V/div
IIN
2A/div
VPGOOD
100V/div
CIRCUIT-BREAKER
THRESHOLD
OVERVOLTAGE TRANSIENT (NO FAULT)
MAX5938 toc13
4ms/div
VGND
50V/div
VGATE
10V/div
VOUT
50V/div
VPGOOD
50V/div
OVERVOLTAGE TRANSIENT TO
FAULT MANAGEMENT
MAX5938 toc14
2ms/div
VIN
50V/div
VGATE
10V/div
VOUT
50V/div
VPGOOD
50V/div
tOVREJ
GATE TO VEE CLAMP VOLTAGE AT
POWER-OFF vs. GATE SINK CURRENT
MAX5938 toc15
ISINK (mA)
GATE-CLAMPING VOLTAGE (V)
18161412108642
0.5
1.0
1.5
2.0
2.5
3.0
0
020
VEE = GND = 0V
GATE TO VEE CLAMP VOLTAGE MOSFET
FULLY ENHANCED vs. GATE SINK CURRENT
MAX5938 toc16
ISINK (mA)
GATE-CLAMPING VOLTAGE (V)
181612 144 6 8 102
9
10
11
12
13
14
15
16
17
18
8
020
VEE = -48V, VON = VOFF = 2V
INPUT VOLTAGE STEP EVENT (NO FAULT)
MAX5938 toc11
4ms/div
IRFR1310
RCB_ADJ = 2kΩ
RLOAD = 80Ω
VIN
50V/div
VGATE
10V/div
VOUT
50V/div
IIN
1A/div
VPGOOD
50V/div
ALL VOLTAGES REFERENCED TO VEE
Typical Operating Characteristics (continued)
(VEE = -48V, GND = 0V, VIN = GND - VEE, POL_SEL = floating, all voltages are referenced to VEE, unless otherwise noted. TA= +25°C,
unless otherwise noted.)
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
_______________________________________________________________________________________ 7
Detailed Description
The MAX5938 hot-swap controller incorporates over-
current and overvoltage fault management and is
intended for negative-supply-rail applications. The
MAX5938 eliminates the need for an external RSENSE
and includes VIN input step protection and load probe,
which prevents powering up into a shorted load. It is
intended for negative 48V telecom power systems
where low cost, flexibility, multifault management, and
compact size are required. The MAX5938 is ideal for
the widest range of systems from those requiring low
current with small MOSFETs to high-current systems
requiring large power MOSFETs and low on-resistance.
The MAX5938 controls an external n-channel power
MOSFET placed in the negative supply path of an
external load. When no power is applied, the GATE out-
put of the MAX5938 clamps the VGS of the MOSFET to 2V
keeping the MOSFET turned off (Figure 2). When power
is applied to the MAX5938, the 2V clamp at the GATE
output is replaced by a strong pulldown device, which
pulls GATE to VEE and the VGS of the MOSFET to 0.
As shown in Figure 2, this transition enables the
MAX5938 to keep the power MOSFET continually off
during the board insertion phase when the circuit board
first makes contact with the backplane. Without this
clamp, the GATE output of a powered-down controller
would be floating and the MOSFET reverse transfer
PIN
NAME FUNCTION
1GND Ground. The high supply connection for a negative rail hot-swap controller.
2, 10,
13, 15
N.C. No Connection. Not internally connected. Leave open.
3OFF Off Control Input. Referenced to VEE. Drive OFF and ON above 1.25V (typ) to turn on the MAX5938. When the
ON input low requirements are met and OFF falls below 1.25V (typ), the MAX5938 turns off.
4ON
On Control Input. Referenced to VEE. Drive ON and OFF above the 1.25V rising thresholds to turn on the
MAX5938. When the voltage at OFF falls below its 1.25V (typ) threshold and the voltage at ON falls below
1.125V for longer than the ON 1.5ms glitch rejection period, the MAX5938 turns off.
5OV
Overvoltage Control Input. Referenced to VEE. When the voltage at OV rises above the 1.25V rising threshold,
GATE pulls to VEE until OV falls below the 1.125V falling threshold. If the overvoltage condition remains longer
than 1.5ms, fault management initiates and PGOOD deasserts (see the Detailed Description).
6
STEP_MON
Input Voltage Step Monitor. Connect a resistor between STEP_MON and VEE to set the step sensitivity.
Connect a capacitor from GND to STEP_MON to adjust the step response relative to a negative step at VEE to
eliminate false circuit-breaker and short-circuit faults. Connect to VEE to disable the step immunity function.
See the Selecting Resistor and Capacitor Values for Step Monitor section in the Applications Information.
7
POL_SEL
PGOOD Output Polarity Select. Leave POL_SEL open for an active-low PGOOD assertion. Connect POL_SEL
to VEE for an active-high open-drain PGOOD assertion.
8V
EE Negative Input Voltage
9LP
Load-Probe Detect. Connect a resistor from LP to VOUT to set the load-probe test current. Limit load-probe
test current to 1A. Connect to VEE to disable load-probe function.
11 GATE Gate-Drive Output. Connect to the gate of the external n-channel MOSFET.
12
CB_ADJ
Circuit-Breaker Adjust. Connect a resistor from CB_ADJ to VEE to adjust the circuit-breaker threshold. Short
CB_ADJ to VEE for the default circuit-breaker 50mV (typ) threshold. Leave CB_ADJ open to disable circuit-
breaker and short-circuit fault detection.
14 VOUT Output Voltage Sense. VOUT is the negative rail of the load. Connect to the drain of the external n-channel
MOSFET.
16
PGOOD
Power-Good Open-Drain Output. Referenced to VOUT. PGOOD asserts high (POL_SEL = VEE) or low
(POL_SEL open) when VOUT is within limits and there is no fault condition. PGOOD is deasserted when
ON and OFF are cycled low.
Pin Description
capacitance (gate-to-drain) would pull up and turn on
the MOSFET gate when the MOSFET drain is rapidly
pulled up by the VIN step during backplane contact.
The MAX5938 GATE clamp can overcome the gate-to-
drain capacitance of large power MOSFETs with added
slew-rate control (CSLEW) capacitors while eliminating
the need for additional gate-to-source capacitance.
The MAX5938 keeps the MOSFET off indefinitely if the
supply voltage is below the user-set ON and OFF
thresholds, if the supply voltage is above the user-set
overvoltage (OV) threshold, or if a short circuit (user-
defined) is detected in the load connected to the drain
of the power MOSFET.
The MAX5938 conducts a load-probe test after contact
transients from the hot plug-in have settled. This follows
the MAX5938 power-up (when the ON, OFF, and OV
conditions have been met for 220ms (tLP)) and prior to
the turn-on of the power MOSFET. This test pulls a user-
programmable current through the load (1A, max) for up
to 220ms (tLP) and tests for a voltage of 200mV across
the load at VOUT (Figure 3). This current is set by an
external resistor, RLP (Figure 17) between VOUT and LP.
When the voltage across the load exceeds 200mV, the
test is truncated and the GATE turn-on sequence is start-
ed. If at the end of the 200ms (tLP) test period the volt-
age across the load has not reached 200mV, the load is
assumed to be shorted and the current to the load from
Figure 1. Functional Diagram
10V REG
AND
5V REG
PGOOD
POLARITY
LOGIC
ON, OFF,
AND OV
LOGIC CONTROL
BANDGAP
REF
VBG
10µA
FAULT
DETECTION
SEQUENCER
CONTROLLER
TIMER
GATE
CONTROL
LOAD-PROBE
TEST
VSC, VCB, AND
75% OF VCB
COMPARATORS
STEP
50µA TEMP
COMPENSATED
CURRENT SOURCE
VBG (1.25V)
+5V
+10V
52µA
2V AND
15V
CLAMP
PGOOD
LOGIC
MAX5938
PGOOD
VOUT
GATE
LP
RLOAD CLOAD
ON
GND
STEP_MON
VEE
GND
VEE
RINT
2kΩCB_ADJ
PG
OV
PG
OFF
OV
POL_SEL
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
8_______________________________________________________________________________________
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
_______________________________________________________________________________________ 9
Figure 3. Load-Probe Test During Initial Power-Up
40ms/div
CLOAD = 100µF
RLP = 75kΩVEE
20V/div
VOUT
200mV/div
VLP
20V/div
GND
GND
GND
Figure 2. GATE Voltage Clamp During Power-Up
VIN
20V/div
VGATE
1V/div
4ms/div
CIN = 100µF
LP is shut off. The MAX5938A times out for 16 x tLP then
retry the load-probe test. The MAX5938L latches the fault
condition indefinitely until ON and OFF are cycled low for
1.5ms or the power is recycled. See the Applications
Information for recommendations on selecting RLP to set
the load-probe current level.
Upon successful completion of the load-probe test, the
MAX5938 enters the power-up GATE cycle and begins
ramping the GATE voltage with a 52µA current source.
This current source is restricted if VOUT begins to ramp
down faster than the default 9V/ms slew rate. The VOUT
slew rate can be reduced to below 9V/ms by adding
CSLEW from GATE to VOUT. Charging up GATE
enhances the power MOSFET in a controlled manner
and ramping VOUT at a user-settable rate controls the
inrush current from the backplane. The MAX5938 con-
tinues to charge up the GATE until one of two events
occurs: a normal power-up GATE cycle is completed or
a power-up-to-fault-management fault is detected (see
the GATE Cycles section in Appendix A). In a normal
power-up GATE cycle, the voltage at VOUT (referenced
to VEE) ramps to below 74% of the programmed circuit-
breaker threshold voltage, VCB. At this time, the remain-
ing GATE voltage is rapidly pulled up to full
enhancement. PGOOD is asserted 1.26ms after GATE
is fully enhanced (see Figure 4). If the voltage at VOUT
remains above 74% of the programmed VCB (when
GATE reaches 90% of full enhancement), then a power-
up-to-fault-management fault has occurred). GATE is
rapidly pulled to VEE, turning off the power MOSFET
and disconnecting the load. PGOOD remains deassert-
ed and the MAX5938 enters the fault management
mode (Figure 5).
When the power MOSFET is fully enhanced, the
MAX5938 monitors the drain voltage (VOUT) for circuit-
breaker and short-circuit faults. The MAX5938 makes
use of the power MOSFET’s RDS(ON) as the current-
sense resistance to detect excessive current through
Figure 4. MAX5938 Normal Startup (POL_SEL = Floating)
VIN
50V/div
VPGOOD
50V/div
40ms/div
VGATE
10V/div
VOUT
50V/div
IIN
2A/div
Figure 5. MAX5938 Startup into Fault Condition (POL_SEL =
Floating)
VIN
50V/div
VPGOOD
50V/div
40ms/div
VGATE
10V/div
VOUT
50V/div
IIN
2A/div
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
10 ______________________________________________________________________________________
the load. The short-circuit threshold voltage, VSC, is
twice VCB (VSC = 2 x VCB) and is set by adjusting the
resistance between CB_ADJ and VEE. There is an inter-
nal 2kΩprecision-trimmed resistor and an internal 50µA
current source at CB_ADJ, which results in the mini-
mum or default VSC of 100mV when CB_ADJ is con-
nected to VEE. The current source is temperature
compensated (increasing with temperature) to track the
normalized temperature coefficient of RDS(ON) for typical
power MOSFETs.
When the load current is increased during full enhance-
ment, this causes VOUT to exceed VCB but remains less
than VSC, and starts the 1.2ms circuit-breaker glitch
rejection timer. At the end of the glitch rejection period,
if VOUT still exceeds VCB, the GATE is immediately
pulled to VEE (330ns), PGOOD is deasserted, and the
part enters fault management. Alternatively, during full
enhancement when VOUT exceeds VSC, there is no
glitch rejection timer. GATE is immediately pulled to
VEE, PGOOD is deasserted, and the part enters fault
management.
The VIN step immunity provides a means for transitioning
through a large step increase in VIN with minimal back-
plane inrush current and without shutting down the load.
Without VIN step immunity (when the power MOSFET is
fully enhanced), a step increase in VIN will result in a
high inrush current and a large step in VOUT, which can
trip the circuit breaker.
With VIN step immunity, the STEP_MON input detects
the step before a short circuit is detected at VOUT and
alters the MAX5938 response to VOUT exceeding
VSC due to the step. The 1.25V voltage threshold at
STEP_MON and a 10µA current source at STEP_MON
allow the user to set the sensitivity of the step detection
with an external resistor to VEE. A capacitor is placed
between GND and the STEP_MON input, which in con-
junction with the resistor, sets the STEP_MON time
constant.
When a step is detected by the STEP_MON input rising
above its threshold (STEPTH), the overcurrent fault
management is blocked and remains blocked as long
as STEPTH is exceeded. When STEPTH is exceeded,
the MAX5938 takes no action until VOUT rises above
VSC or above VCB for the 1.2ms circuit-breaker glitch
rejection period. When either of these conditions
occurs, a step GATE cycle begins and the GATE is
immediately brought to VEE, which turns off the power
MOSFET to minimize the resulting inrush current surge
from the backplane. PGOOD remains asserted. GATE
is held at VEE for 350µs, and after about 1ms, begins to
ramp up, enhancing the power MOSFET in a controlled
manner as in the power-up GATE cycle. This provides a
controlled inrush current to charge the load capaci-
tance to the new supply voltage (see the GATE Cycles
section in Appendix A).
As in the case of the power-up GATE cycle, if VOUT
drops to less than 74% of the programmed VCB, inde-
pendent of the state of STEP_MON, the GATE voltage is
rapidly pulled to full enhancement. PGOOD remains
asserted throughout the step (Figure 6). Otherwise, if the
STEP_MON input has decayed below its threshold but
VOUT remains above 74% of the programmed VCB
(when GATE reaches 90% of full enhancement), a step-
to-fault-management fault has occurred. GATE is rapidly
pulled to VEE, turning off the power MOSFET and dis-
connecting the load; PGOOD is deasserted and the
MAX5938 enters the fault management mode (Figure 7).
Figure 6. MAX5938 Response to a Step Input with No Fault
(VOUT < 0.75VCB)
VIN
5V/div
VPGOOD
20V/div
2ms/div
VGATE
10V/div
VOUT
20V/div
IIN
1A/div
CLOAD = 100µF
RLOAD = 100Ω
40V
Figure 7. MAX5938 Response to a Step Input Ending in a Fault
(VOUT > 0.75VCB)
VIN
20V/div
VPGOOD
50V/div
4ms/div
VGATE
10V/div
VOUT
50V/div
IIN
5A/div
40V
20V
CLOAD = 100µF
RLOAD = 20Ω
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
______________________________________________________________________________________ 11
Fault Management
Fault management can be triggered by the following
conditions:
•V
OUT exceeds 74% of VCB during GATE ramp at
90% of full enhancement,
•V
OUT exceeds the VCB for longer than 1.2ms during
full enhancement,
•V
OUT exceeds the VSC during full enhancement,
•Load-probe test fails,
•V
IN exceeds the programmed overvoltage (OV) limit
for more than 1.5ms.
Once in the fault management mode, GATE will always be
pulled to VEE, which turns off the external MOSFET and
always deasserts PGOOD. If CB_ADJ is left open, short-
circuit and circuit-breaker faults are ignored. The
MAX5938A version has automatic retry following a fault
while the MAX5938L remains latched in the fault condition.
Autoretry Fault Management (MAX5938A)
If the MAX5938A entered fault management due to an
OV fault, it will start the autoretry timer when the OV
fault is removed. For circuit-breaker and short-circuit
faults, the autoretry timer starts immediately. The timer
times out in 3.5s (typ) after which the sequencer initi-
ates a load-probe test and if successful, initiates a nor-
mal power-up GATE cycle.
Latched Fault Management (MAX5938L)
When the MAX5938L enters fault management it
remains in this condition indefinitely until the power is
recycled or until OFF is brought below 1.25V (no time
dependence) and ON is brought below 1.125V for
1.5ms (typ). In addition, if the MAX5938L enters fault
management due to an overvoltage fault, the overvolt-
age fault must be removed. When the last of these con-
ditions has been met, the sequencer initiates a load-
probe test and if successful, a normal power-up GATE
cycle begins. A manual reset circuit as in Figure 2 can
be used to clear the latch.
Circuit-Breaker Threshold
The MAX5938 has a minimum circuit-breaker threshold
voltage of 50mV when CB_ADJ is connected to VEE. The
VCB is half VSC and can be increased by placing a resis-
tor between CB_ADJ and VEE according to the following:
VCB(mV) = 1/2x VSC (mV) = 1/2x ICB_ADJ(µA)
x [RINT(kΩ) + RCB_ADJ(kΩ)]
where ICB_ADJ = 50µA (typ at +25°C), RINT is an internal
precision, ±0.5%, 2kΩresistor at CB_ADJ and RCB_ADJ
is the external resistor between CB_ADJ and VEE. The
current source ICB_ADJ is temperature-compensated
(increasing with temperature) to track the normalized
temperature coefficient of typical power MOSFETs.
The proper circuit-breaker threshold for an application
depends on the RDS(ON) of the external power MOSFET
and the maximum current the load is expected to draw.
To avoid false fault indication and dropping of the load,
the designer must take into account the load response to
voltage ripples and noise from the backplane power sup-
ply as well as switching currents in the downstream DC-
DC converter that is loading the circuit. While the
circuit-breaker threshold has glitch rejection that ignores
ripples and noise lasting less than 1.2ms, the short-cir-
cuit detection is designed to respond very quickly (less
than 330ns) to a short circuit. For this reason, set VSC
and VCB with an adequate margin to cover all possible
ripples, noise, and system current transients (see the
Setting the Circuit-Breaker and Short-Circuit Thresholds
section in the Applications Information).
Figure 8. Resetting the MAX5938L after a Fault Condition
Using a Push-Button Switch
MAX5938
GND
OFF
ON
VIN = (GND - VEE)
R4
R3
R2
R1
OV
VEE
Disabling Circuit-Breaker and
Short-Circuit Functions
In the MAX5938, the circuit-breaker and short-circuit
functions can be disabled, if desired, although this is
not recommended. (See Warning note in the PGOOD
Open-Drain Output section). This can be accomplished
by leaving CB_ADJ open. In this case, PGOOD asserts
1.26ms after GATE has ramped to 90% of full enhance-
ment, after which VOUT is ignored, resulting in the cir-
cuit-breaker and short-circuit faults being ignored.
PGOOD Open-Drain Output
The power-good output, PGOOD, is open drain and is
referenced to VOUT. It asserts and latches if VOUT
ramps below 74% of VCB, and with the built-in delay,
this occurs 1.26ms after the external MOSFET becomes
fully enhanced. PGOOD deasserts any time the part
enters fault management. PGOOD has a delayed
response to ON and OFF. The GATE will go to VEE
when OFF is brought below 1.25V (no time depen-
dence) while ON is brought below 1.125V for 1.5ms.
This turns off the power MOSFET and allows VOUT to
rise depending on the RC time constant of the load.
PGOOD, in this situation, deasserts when VOUT rises
above VCB for more than 1.4ms or above VSC,
whichever occurs first (see Figure 9b).
Since PGOOD is open drain, it requires an external
pullup resistor to GND. Due to this external pullup,
PGOOD does not follow positive VIN steps as well as if
it were driven by an active pullup. As a result, when
PGOOD is asserted high, an apparent negative glitch
appears at PGOOD during a positive VIN step. This
negative glitch is a result of the RC time constant of the
external resistor and the PGOOD pin capacitance lag-
ging the VIN step. It is not due to switching of the inter-
nal logic. To minimize this negative transient, it may be
necessary to increase the pullup current and/or to add
a small amount of capacitance from PGOOD to GND to
compensate for the pin capacitance.
The PGOOD output logic polarity is selected using
POL_SEL input. For an active-high output, connect
POL_SEL to VEE. Leave POL_SEL open for an active-
low output.
WARNING: When disabling the circuit-breaker and
short-circuit functions (CB_ADJ open), PGOOD asserts
1.26ms after the power MOSFET is fully enhanced inde-
pendent of VOUT. Once the MOSFET is fully enhanced
and ON and OFF are pulled below their respective
thresholds, the GATE will be pulled to VEE to turn off the
power MOSFET and disconnect the load. When the cir-
cuit-breaker and short-circuit functions are disabled
and ON and OFF are cycled low, PGOOD is deassert-
ed. In summary, when CB_ADJ is open (once the MOS-
FET is fully enhanced), the MAX5938 ignores VOUT and
deasserts PGOOD only for an overvoltage fault, when
ON and OFF are cycled low or when the power to the
MAX5938 is fully recycled.
Figure 9. ON and OFF Timing Diagram
(a)
ON
ILP
220ms LOAD-PROBE
DETECTION TEST
BEGINS
VON_REF,R
OFF
VOFF_REF
1.3ms
VON_REF,F
ON
VOFF_REF
OFF
GATE
VOUT
PGOOD
(b)
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
12 ______________________________________________________________________________________
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
______________________________________________________________________________________ 13
Figure 10. Overvoltage Gate Cycle Without a Fault (tOV < 1.3ms)
VIN
10V/div
VPGOOD
10V/div
1ms/div
VGATE
10V/div
VOUT
10V/div
48V
Figure 11. Overvoltage Fault (tOV > 1.3ms)
VIN
5V/div
VPGOOD
50V/div
2ms/div
VGATE
10V/div
VOUT
50V/div
48V
tOVREJ
Undervoltage Lockout (OFF and ON) and
OV Functions
OV, ON, and OFF provide an accurate means to set the
overvoltage, turn-on, and turn-off voltage levels. All three
are high-impedance inputs and by use of a 4-element
resistor-divider from GND to VEE, the user can set an
upper VEE threshold for triggering an overvoltage fault, a
middle threshold for turning the part on, and a lower
threshold for turning the part off.
The input voltage threshold at OFF is 1.25V. ON has
hysteresis with a rising threshold of 1.25V and a falling
threshold of 1.125V. The logic of the inputs is such that
both OFF and ON must be above their thresholds to
latch the part on. Both OFF and ON must be below their
respective thresholds to latch the part off, otherwise the
part stays in its current state. There is glitch rejection on
the ON input going low, which additionally requires that
ON remain below its falling threshold for 1.5ms to turn
off the part. A startup delay of 220ms allows contacts
and voltages to settle prior to initiating the startup
sequence. This startup delay is from a valid ON condi-
tion until the start of the load-probe test.
The OV input has hysteresis with a rising threshold of
1.25V and a falling threshold of 1.125V. The OV input
also has a rising fault transient delay of 1.5ms. When
OV rises above its threshold, an OV GATE cycle is
immediately initiated (see the GATE Cycles section in
Appendix A). The GATE output is brought to VEE with
about 300ns of propagation delay. If the OV input drops
below its falling threshold before the fault transient
delay of about 1.5ms, the device will not enter fault
management mode and the GATE output will ramp up
to fully enhance the external MOSFET (Figure 10).
Otherwise, an OV fault occurs (Figure 11). See the
Setting ON, OFF, and OV Voltage Levels section in the
Applications Information.
Output Voltage (VOUT)
Slew-Rate Control
The VOUT slew rate controls the inrush current required
to charge the load capacitor. The MAX5938 has a
default internal slew rate set for 9V/ms. The internal cir-
cuit establishing this slew rate accommodates up to
about 1000pF of reverse transfer capacitance (Miller
Capacitance) in the external power MOSFET without
effecting the default slew rate. Using the default slew
rate, the inrush current required to charge the load
capacitance is given by:
IINRUSH (mA) = CLOAD (µF) x SR (V/ms)
where SR = 9V/ms (default, typ).
The slew rate can be reduced by adding an external
slew-rate control capacitor (CSLEW) from VOUT (the
drain of the power MOSFET) to the GATE output of the
MAX5938 (Figure 19). Values of CSLEW < 4700pF have
little effect on the slew rate because of the default slew-
rate control circuit. For CSLEW > 4700pF, the combina-
tion of CSLEW and reverse transfer capacitance of the
external power MOSFET dominate the slew rate. When
CSLEW > 4700pF, SR and CSLEW are inversely related
as follows (Figure 18):
SR (V/ms) = 23 / CSLEW (nF)
If the reverse transfer capacitance of the external
power MOSFET is large compared to the externally
added CSLEW, then it should be added to CSLEW in the
equation above.
See the Adjusting the VOUT Slew Rate section in the
Applications Information and Figure 18, which graphi-
cally displays the relation between CSLEW and slew
rate. This section discusses specific recommendations
for compensating power MOSFET parasitics that may
lead to oscillation when an external CSLEW is added.
Applications Information
Setting ON, OFF, and OV Voltage Levels
The trip levels for ON, OFF, and OV can readily be set
with a 4-element resistor-divider. Total resistance is a
trade off of quiescent current, threshold tolerance due
to pin input bias current (25nA), and the ability to follow
very fast supply transients. Both ON and OV have hys-
teresis on the reference threshold voltage: the rising
reference threshold is 1.25V and the falling threshold is
1.125V. The reference threshold voltage for OFF is
1.25V. In determining a set of resistors, use VREF =
1.25V for ON, OFF, and OV and an RTOT = 100kΩin
this example. See Figure 12 for nomenclature. For this
example, use VOV = 80V, VON = 42V, and VOFF = 38V
as the desired voltage trip levels.
1) R4= RTOT x VREF / VOV
2) R3= RTOT x VREF / VON - R4
3) R2= RTOT x VREF / VOFF - R3- R4
4) R1= RTOT - R2- R3- R4
The exact result to three decimal places is R1 =
96.711kΩ, R2 = 313Ω, R3 = 1.414kΩ, and R4 =
1.563kΩ. When converted to the nearest 1% standard
resistor, the values become R1 = 97.6kΩ, R2 = 316Ω,
R3 = 1.40kΩ, and R4 = 1.58kΩ.
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
14 ______________________________________________________________________________________
Figure 12. Programming the MAX5938’s ON, OFF, and OV
Thresholds
MAX5938
GND
OFF
ON
VIN = (GND - VEE)
R4
R3
R2
R1
OV
VEE
Figure 13. MAX5938 Circuit-Breaker Threshold Adjustment
MAX5938
CLOAD LOAD
SC TRIP
RON
VOUT
ILOAD
CB TRIP
tCB_DLY
RINT
2kΩ
±0.5%
RCB_ADJ
R
R
VSC
VEE
GND
50µA
CB_ADJ
ICB_ADJ
Determine the trip voltages these values will actually
yield for rising and falling voltages. Rising voltages use
the VREF = 1.25V reference threshold, while falling volt-
ages use VLO = 1.125V reference threshold.
1) RTOT = R1+ R2+ R3+ R4
2) VOV,RISING = VREF x RTOT / R4
3) VOV,FALLING = VLO x RTOT / R4
4) VON,RISING = VREF x RTOT / (R3+ R4)
5) VON,FALLING = VLO x RTOT / (R3+ R4)
6) VOFF = VREF x RTOT / (R2+ R3+ R4)
The resulting voltage levels are VOV,RISING = 79.82V
±2.5%, VOV,FALLING = 71.84V ±5%, VON,RISING =
42.32V ±2.5%, VON,FALLING = 38.09V ±5%, and VOFF
= 38.26V ±2.5%. The voltage tolerance does not
account for the tolerance of the resistors.
Setting the Circuit-Breaker and
Short-Circuit Thresholds
The MAX5938 can operate with a wide range of power
MOSFETs to meet the requirements of almost any appli-
cation. MOSFETs mentioned here are done to demon-
strate certain capabilities and features of the MAX5938.
They should not be construed as a recommendation or a
limitation of the interoperability of the MAX5938.
In the implementation of the circuit-breaker and short-
circuit functions, the MAX5938 eliminates the need for
an external current-sense resistor at the source of the
power MOSFET. As in any other hot-swap controller,
the proper circuit-breaker threshold for an application
must take into account the DC level of VOUT, while at
the same time accommodating the AC response of
VOUT to the modulation of VIN. The AC response from
VIN to VOUT is dependent on the parasitics of the load,
especially the load capacitor, in conjunction with the
RDS(ON) of the power MOSFET. It behaves as a highly
dampened second-order system. As such, this system
functions as a bandpass filter from VIN to VOUT. The
response of VOUT to load-switching currents and volt-
age ripple and noise from the backplane power supply
must be taken into account. Adequate margin must be
provided between VCB, VSC, and the DC level of VOUT,
which depends on the RDS(ON) of the power MOSFET
(with VGS at 10V) and the maximum current the load is
expected to draw. While the circuit-breaker threshold
has glitch rejection for VOUT excursions lasting less
than 1.4ms, the short-circuit detection is designed to
respond very quickly (less than 330ns) to a short cir-
cuit. In the application, select a value for RCB_ADJ
resulting in a VCB that exceeds the product of RDS(ON)
and the maximum load current plus one half the peak-
to-peak AC response of VOUT to load-switching cur-
rents and the noise and ripple at VIN:
RDS(ON) (Ω) x ILOAD,MAX(mA) + 1/2x VOUTAC
< VCB(mV)
where
VCB(mV) = 1/2x ICB_ADJ(µA) x [RINT(kΩ)
+ RCB_ADJ(kΩ)]
RDS(ON) in a power MOSFET has a positive tempera-
ture coefficient and the MAX5938, when placed adja-
cent to the power MOSFET, tracks and compensates
for this temperature coefficient. In the MAX5938, VCB is
half of VSC, which is set by placing an external resis-
tance between CB_ADJ and VEE. The minimum
(default) short-circuit threshold voltage, VSC, is set by
an internal 2kΩprecision-trimmed (±0.5%) resistor pro-
viding a minimum series resistance and a temperature-
compensated 50µA (+25°C) current source. When
CB_ADJ is connected to VEE this gives a 50mV circuit-
breaker threshold. When an external resistor, RCB_ADJ,
is placed between CB_ADJ and VEE, the new circuit-
breaker threshold becomes:
VCB (mV) = 1/2x VSC (mV) = 1/2x ICB_ADJ (µA)
x (2kΩ+ RCB_ADJ)
and at +25°C, it becomes:
VCB (mV) = 1/2VSC (mV) = 1/2x 50µA
x (2kΩ+ RCB_ADJ)
The short-circuit and circuit-breaker voltages are sensed
at VOUT, which is the drain of the power MOSFET. The
RDS(ON) of the MOSFET is the current-sense resistance
and so the total current through the load and load
capacitance is the drain current of the power MOSFET.
Accordingly, the voltage at VOUT as a function of
MOSFET drain current is:
VOUT = ID,MOSFET x RDS(ON)
The temperature compensation of the MAX5938 is
designed to track the RDS(ON) of the typical power
MOSFET. Figure 14 shows the typical normalized temp-
co of the circuit-breaker threshold along with the nor-
malized tempco of RDS(ON) for several typical power
MOSFETS. When determining the circuit-breaker
threshold in an application go to the power MOSFET
manufacturer’s data sheet and locate the maximum
RDS(ON) at +25°C with a VGS of 10V. Next, find the fig-
ure presenting the tempco of normalized RDS(ON) or
on-resistance vs. temperature. Since this curve is in
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
______________________________________________________________________________________ 15
normalized units, typically with a value of 1 at +25°C, it
is possible to multiply the curve by the drain voltage at
+25°C and convert the curve to drain voltage. Now
compare this curve to that of the MAX5938 normalized
tempco of the circuit-breaker threshold to make a
determination of the tracking error in mV between the
power MOSFET [ID,MOSFET x RDS(ON)] and the
MAX5938 [ICB_ADJ (µA) x (2kΩ+ RCB_ADJ)] over the
operating temperature range of the application.
If the tempco of the power MOSFET is greater than the
MAX5938’s, then additional margin in setting the circuit-
breaker and short-circuit voltages will be required at
higher temperatures as compared to +25°C (Figure 15).
When dissipation in the power MOSFET is expected to
lead to local temperature elevation relative to ambient
conditions, it becomes imperative that the MAX5938 be
located as close as possible to the power MOSFET. The
marginal effect of temperature differences on circuit-
breaker and short-circuit voltages can be estimated
from a comparative plot such as Figure 14.
Selecting a Resistor and Capacitor
for Step Monitor
When a positive VIN step or ramp occurs, the VIN
increase results in a voltage rise at both STEP_MON
and VOUT relative to VEE. When the voltage at
STEP_MON is above STEPTH,the MAX5938 blocks
short-circuit and circuit-breaker faults. During this
STEP_MON high condition, if VOUT rises above VSC, the
MAX5938 will immediately and very rapidly pull GATE to
VEE. This turns off the power MOSFET to avoid inrush
current spiking. GATE is held low for 350µs. About 1ms
after the start of GATE pulldown, the MAX5938 begins to
ramp GATE up to turn on the MOSFET in a controlled
manner that results in ramping VOUT down to the new
supply level (see the GATE Cycles section in Appendix
A). This occurs with the least possible disturbance to
VOUT, although during the brief period that the MOSFET
is off, the voltage across the load droops slightly
depending on the load current and load storage capaci-
tance. PGOOD remains asserted throughout the VIN
step event.
The objective in selecting the resistor and capacitor for
the step monitor function is to ensure that the VIN steps
of all anticipated slopes and magnitudes will be proper-
ly detected and blocked, which otherwise would result
in a circuit-breaker or short-circuit fault. The following is
a brief analysis for finding the resistor and capacitor.
For a more complete analysis, see Appendix B.
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
16 ______________________________________________________________________________________
Figure 14. MAX5938 Normalized Circuit Breaker
NORMALIZED MOSFET ON-RESISTANCE
vs. TEMPERATURE
TEMPERATURE (°C)
NORMALIZED MOSFET ON-RESISTANCE
603510-15
0.6
0.8
1.0
1.2
1.4
1.6
0.4
-40 85
IRF1310NS
NORMALIZED RON
IRFR3910
NORMALIZED RON
MAX5938
NORMALIZED VCB
Figure 15. Circuit-Breaker Voltage Margin For High and Low Tempco Power MOSFETS
CIRCUIT-BREAKER
TRIP REGION
CIRCUIT-BREAKER
TRIP REGION
TA = +25°CTA = +25°C
ID x RDS(ON)
∆VCB,MIN
∆VCB,MIN
ID x RDS(ON)
RDS(ON) HIGH TEMPCO RDS(ON) LOW TEMPCO
VOLTAGE
TEMPERATURETEMPERATURE
VOLTAGE
1/2 x ICB_ADJ x RCB_ADJ 1/2 x ICB_ADJ x RCB_ADJ
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
______________________________________________________________________________________ 17
FAULT
MGT
CYCLE
GATE
LOW
tCB_DLY
ESL
ESR
C
LOADCLOAD
CSTEP_MON
RSTEP_MON
VSTEP_MON
RDS,ON
GATEVEE VOUT
VIN STEP
STEP_MON
ISTEP
ISTEP_OS
GND
STEPTH
STEP_DET
VSC
VCB CB TRIP
MAX5938
SC TRIP
NOTE: VSC, VCB, VSTEPTH, VSTEP_MON, AND VOUT ARE REFERENCED TO VEE.
Figure 16 is a functional diagram exhibiting the elements
of the MAX5938 involved in the step immunity function.
This functional diagram shows the parallel relationship
between VOUT and VSTEP-MON. Each has an I*R compo-
nent establishing the DC level prior to a step. While it is
referred to as a VIN step, it is the dynamic response to a
finite voltage ramp that is of interest.
Given a positive VIN ramp with a ramp rate of dV/dt, the
approximate response of VOUT to VIN is:
VOUT(t) = (dV/dt) x τCx (1-e(-t / τL,eqv) ) + RDS(ON)
ILOAD
where τC= CLOAD x RDS(ON) and τL,eqv is the equiva-
lent time constant of the load that must be found empir-
ically (see Appendix B).
Similarly, the response of STEP_MON to a VIN ramp is:
VSTEP_MON(t) = (dV/dt) x τSTEP x (1-e(-t / τSTEP) ) + 10µA
x RSTEP
where τSTEP = RSTEP_MON x CSTEP_MON.
For proper step detection, VSTEP_MON must exceed
STEPTH prior to VOUT reaching VSC or within 1.4ms of
VOUT reaching VCB (over all VIN ramp rates anticipated in
the application). VSTEP_MON must be set below STEPTH
with an adequate margin, ∆VSTEP_MON, to accommodate
the tolerance of both ISTEP_OS (±8%) and RSTEP_MON.
RSTEP_MON is typically set to 100kΩ, which gives a
∆VSTEP_MON for a worst-case high of 0.36V.
The margin of VOUT, with respect to VSC and VCB, was
set when RCB_ADJ was selected as described in the
Setting the Circuit-Breaker and Short-Circuit Thresholds
section. This margin may be lower at one of the temper-
ature extremes and if so, that value should be used in
the following discussion. These margins will be called
∆VCB and ∆VSC and they represent the minimum VOUT
excursion required to trip the respective fault.
To set τSTEP to block all VCB and VSC faults for any
ramp rate, find the ratio of ∆VSTEP_MON to ∆VCB and
choose τSTEP so:
τSTEP = 1.2 x τCx ∆VSTEP_MON / ∆VCB
And since RSTEP_MON = 100kΩ. This results in
CSTEP_MON = τSTEP / 100kΩ.
After the first-pass component selection, if sufficient
timing margin exists (see Appendix B), it is possible but
not necessary to lower RSTEP_MON below 100kΩto
reduce the sensitivity of STEP_MON to VIN noise.
Figure 16. MAX5938 Step Immunity Functional Diagram
Appendix B gives a more complete analysis and dis-
cussion of the step monitor function. It provides meth-
ods for the characterization of the load response to a
VIN ramp and graphical verification of the step monitor
timing margins for a set of design parameters.
Selecting the PGOOD Pullup Resistor
Due to the open-drain driver, PGOOD requires an exter-
nal pullup resistor to GND. This resistor should be
selected to minimize the current load while PGOOD is
low. The PGOOD output specification for VOL is 0.4V at
1mA. As described in the Detailed Description, the
external pullup interferes with the ability of PGOOD to
follow positive VIN steps as well as if it were driven by an
active pullup. When PGOOD is asserted high, an appar-
ent negative glitch appears at PGOOD during a positive
VIN step. To minimize this negative transient it may be
necessary to increase the pullup current and/or to add a
small amount of capacitance from PGOOD to GND to
compensate for the pin capacitance.
Setting the Test Current Level for
Load-Probe Test
The load-probe test is a current test of the load that
avoids turning on the power MOSFET. The MAX5938
has an internal switch (Q1 in Figure 17) that pulls cur-
rent through the load and through an external current-
limiting resistor, RLP. During the test, this switch is
pulsed on for up to 220ms (typ). Current is pulled
through the load, which should charge up the load
capacitance unless there is a short. If the voltage
across the load exceeds 200mV, the test is truncated
and normal power-up is allowed to proceed. If the volt-
age across the load does not reach 200mV in the
220ms period that the current is on, the load is
assumed to be shorted and the current to the load from
LP is shut off. The MAX5938A will timeout for 16 x tLP
then retry the load-probe test. The MAX5938L will latch
the fault condition indefinitely until ON and OFF are
cycled low for 1.5ms or the power is recycled.
In the application, the current-limiting resistor should be
selected to minimize the current pulled through the
load while guaranteeing that it will charge the maximum
expected load capacitance to 220mV in 90ms. These
parameters are the maximum load-probe test voltage
and the minimum load-probe current pulse period,
respectively. The maximum current possible is 1A,
which is adequate to test a load capacitance as large
as 190,000µF over the typical telecom operating
voltage range.
ITEST (A) = CLOAD,MAX (F) x 220mV / 90ms
TIMING
LOGIC
MAX5938
CLOAD LOAD
LOAD
OK
VIN
VEE
Q1
RON
GATE VOUT
RLP
ITEST
ILOAD
200mV
GND
LP
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
18 ______________________________________________________________________________________
Figure 17. Load Probe Functional Diagram
Since the minimum intended VIN for the application will
result in the lowest ITEST during the load-probe test, this
VIN,MIN should be used to set the RLP. This voltage will
likely be near VON,FALLING or VOFF for the application.
RTEST(Ω) = VIN,MIN / ITEST = VIN,MIN x 90ms /
(CLOAD(MAX) x 220mV)
Example: VIN operating range = 36V to 72V, CLOAD =
10,000µF. First, find the RLP that will guarantee a suc-
cessful test of the load.
RLP = 36V x 90ms / (10,000µF x 220mV) = 1.472Ω⇒
1.47kΩ±1%
Next, evaluate the RLP at the maximum operating volt-
age to verify that it will not exceed the 1A current limit
for the load-probe test.
ITEST,MAX = VIN,MAX / RLP = 72V / 1.47kΩ= 49.0mA
If the CLOAD(MAX) is increased to 190,000µF, the test
current will approach the limit. In this case, RLP will be
a much lower value and must include the internal
switch resistance. To find the external series resistor
value that will guarantee a successful test at the lowest
supply voltage, the maximum value for the load-probe
switch on-resistance of 11Ωshould be used:
RLP,TOT = 36V x 90ms / (190,000µF x 220mV) =
90Ω= 11Ω+ RLP
RLP = 77.51Ω- 11Ω= 66.51Ω⇒66.5Ω±1%
Again RLP must be evaluated at the maximum operat-
ing voltage to verify that it will not exceed the 1A cur-
rent limit for the load-probe test. In this case, the
minimum value for the load-probe switch on-resistance
of 6Ωshould be used:
ITEST,MAX = VIN,MAX / RLP,TOT = 72V / (66.5Ω+ 6Ω) =
993mA
Adjusting the VOUT Slew Rate
The default slew rate is set internally for 9V/ms. The slew
rate can be reduced by placing an external capacitor
from the drain of the power MOSFET to the GATE output
of the MAX5938. Figure 18 shows a graph of Slew Rate
vs. CSLEW. This graph shows that for CSLEW < 4700pF
there is very little effect to the addition of external slew-
rate control capacitance. This is intended so the GATE
output can drive large MOSFETs with significant gate
capacitance and still achieve the default slew rate. To
select a slew-rate control capacitor, go into the graph
with the desired slew rate and find the value of the Miller
Capacitance. When CSLEW > 4700pF, SR and CSLEW
are inversely related. Given the desired slew rate, the
required CSLEW is found as follows:
CSLEW(nF) = 23 / SR (V/ms)
From the data sheet of the power MOSFET find the
reverse transfer capacitance (gate-to-drain capacitance)
above 10V. If the reverse transfer capacitance of the
external power MOSFET is 5% or more of CSLEW, then it
should be subtracted from CSLEW in the equation above.
Figure 19 gives an example of the external circuit for con-
trolling slew rate. Depending on the parasitics associated
with the selected power MOSFET, the addition of CSLEW
may lead to oscillation while the MOSFET and GATE con-
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
______________________________________________________________________________________ 19
Figure 18. MAX5938 Slew Rate vs. CSLEW
SLEW RATE vs. CSLEW
CSLEW (nF)
SLEW RATE (V/ms)
100101
0.1
1
10
0.01
0.1 1000
Figure 19. Adjusting the MAX5938 Slew Rate
MAX5938
VOUT
CLOAD LOAD
GATEVEE
GND
CSLEW
RGATE
-48V
GND
trol are in the linear range. If this is an issue, an external
resistor, RGATE, in series with gate of the MOSFET is rec-
ommended to prevent possible oscillation. It should be as
small as possible, e.g., 5Ωto 10Ω, to avoid impacting the
MOSFET turn-off performance of the MAX5938.
Layout Guidelines
To benefit from the temperature compensation designed
into the MAX5938, the part should be placed as close as
possible to the power MOSFET that it is controlling. The
VEE pin of the MAX5938 should be placed close to the
source pin of the power MOSFET and they should share
a wide trace. A common top layer plane would service
both the thermal and electrical requirements. The load-
probe current must be taken into account. If this current
is high, the layout traces and current-limiting resistor
must be sized appropriately. Stray inductance must be
minimized in the traces of the overall layout of the hot-
swap controller, the power MOSFET and the load capac-
itor. Starting from the board contacts, all high-current
traces should be short, wide, and direct. The potentially
high pulse current pins of the MAX5938 are GATE (when
pulling GATE low), load probe, and VEE. Because of the
nature of the hot-swap requirement no decoupling
capacitor is recommended for the MAX5938. Because
there is no decoupling capacitor, stray inductance may
result in excessive ringing at the GND pin during power-
up or during very rapid VIN steps. This should be exam-
ined in every application design since ringing at the
GND pin may exceed the absolute maximum supply rat-
ing for the part.
Input Transient Protection
During hot plug-in/unplug and fast VIN steps, stray
inductance in the power path may cause voltage ring-
ing above the normal input DC value, which may
exceed the absolute maximum supply rating. An input
transient such as that caused by lightning can also put
a severe transient peak voltage on the input rail. The
following techniques are recommended to reduce the
effect of transients:
1) Minimize stray inductance in the power path using
wide traces and minimize loop area including the
power traces and the return ground path.
2) Add a high-frequency (ceramic) bypass capacitor
on the backplane as close as possible to the plug-
in connector (Figure 20).
3) Add a 1kΩresistor in series with the MAX5938’s
GND pin and a 0.1µF capacitor from GND to VEE to
limit transient current going into this pin.
Appendix A
GATE Cycles
The power-up GATE cycle, step GATE cycle, and the OV
GATE cycle are quite similar but have distinct differ-
ences. Understanding these differences may clarify
application issues.
GATE Cycle During Power-Up
The power-up GATE cycle occurs during the initial
power-up of the MAX5938 and the associated power
MOSFET and load. The power-up GATE cycle can
result in full enhancement or in a fault (all voltages are
relative to VEE).
Power-Up-to-Full-Enhancement Fault:
1) At the beginning of the power-up sequence to the
start of the power-up GATE cycle, the GATE is held
at VEE. Following a successful completion of the
load-probe test, GATE is held at VEE for an additional
350µs and then is allowed to float for 650µs. At this
point, the GATE begins to ramp with 52µA charging
the gate of the power MOSFET. [GATE turn-on]
2) When GATE reaches the gate threshold voltage of
the power MOSFET, VOUT begins to ramp down
toward VEE. [VOUT ramp]
3) When VOUT ramps below 74% VCB, the GATE is
rapidly pulled to full enhancement and the power-
up GATE cycle is complete. 1.26ms after GATE is
pulled to full enhancement, PGOOD asserts. [Full
enhancement]
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
20 ______________________________________________________________________________________
Figure 20. Protecting the MAX5938 Input from High-Voltage
Transients
0.1µF
0.1µF
1µF
1kΩ
100kΩ
VEE
PGOOD
GND
BACKPLANE
48V
PLUG-IN CARD
OFF
ON
OV
STEP_MON
Power-Up-to-Fault-Management Fault:
1) Same as step 1 above. [GATE turn-on]
2) Same as step 2 above. [VOUT ramp]
3) GATE ramps to 90% of full enhancement while
VOUT remains above 74% VCB, at which point the
GATE is rapidly pulled to VEE and fault manage-
ment is initiated. [Fault management]
GATE Cycle During VIN Step
A step GATE cycle occurs only after a successful
power-up GATE cycle to full enhancement occurs and
as a result of a positive VIN step (all voltages are
relative to VEE).
Step-to-Full-Enhancement Fault:
1) A VIN step occurs resulting in STEP_MON rising
above STEPTH before VOUT rises above VSC. [Step
detection]
2) After a step is detected, VOUT rises above VSC in
response to the step. When VOUT rises above VSC,
GATE is immediately pulled to VEE, rapidly turning
off the power MOSFET. GATE is held at VEE for
350µs to damp any ringing. Once GATE is pulled to
VEE, the gate cycle has begun and STEP_MON can
safely drop below STEPTH and successfully com-
plete a step GATE cycle to full enhancement without
initiating fault management. [GATE pulldown]
3) Following the 350µs of GATE pulldown, GATE is
allowed to float for 650µs. At this point, the GATE
begins to ramp with 52µA charging the gate of the
power MOSFET. [GATE turn-on]
4) When GATE reaches the gate threshold voltage of
the power MOSFET, VOUT begins to ramp down
toward the new lower VEE. In the interval where
GATE is below the MOSFET threshold, the MOSFET
is off and VOUT will droop depending on the RC
time constant of the load. [VOUT ramp]
5) When VOUT ramps below 74% VCB, the GATE pulls
rapidly to full enhancement and the step GATE
cycle is complete. If STEP_MON remains above
STEPTH when GATE has ramped to 90% of full
enhancement and VOUT remains above 74% of VCB,
GATE remains at 90% and is not pulled to full
enhancement. In this condition, if VOUT drops below
74% of VCB before STEP_MON drops below
STEPTH, GATE is rapidly pulled to full enhancement
and the step GATE cycle is complete. PGOOD
remains asserted throughout the step GATE cycle.
[Full enhancement]
Step-to-Fault-Management Fault:
1) Same as step 1 above. [Step detection]
2) Same as step 2 above. [GATE pulldown]
3) Same as step 3 above. [GATE turn-on]
4) Same as step 4 above. [VOUT ramp]
5) If STEP_MON is below STEPTH when GATE ramps
to 90% of full enhancement and VOUT remains
above 74% VCB, GATE is rapidly pulled to VEE.
Fault management is initiated and PGOOD is de-
asserted. If STEP_MON is above STEPTH when
GATE ramps to 90% of full enhancement and VOUT
remains above 74% of VCB, GATE remains at 90%.
It is not pulled to full enhancement nor is it pulled to
VEE. In this condition, if VOUT drops below 74% of
VCB before STEP_MON drops below STEPTH,
GATE is rapidly pulled to full enhancement and a
fault is avoided. Conversely, if STEP_MON drops
below STEPTH first, the GATE is rapidly pulled to
VEE, fault management is initiated, and PGOOD is
deasserted. [Fault management]
It should be emphasized that while STEP_MON remains
above STEPTH the current fault management is
blocked. During this time it is possible for there to be
multiple events involving VOUT rising above VSC then
falling below 74% VCB. In each of these events, when
VOUT rises above VSC, a full GATE cycle is initiated
where GATE is first pulled low then allowed to ramp up.
Then finally, when VOUT conditions are met, it will be
fully enhanced.
GATE Cycle During Momentary Overvoltage
An OV GATE cycle occurs only after a successful
power-up GATE cycle to full enhancement and as a
result of a momentary excursion of OV above the OV
threshold voltage. An OV GATE cycle does not result in
an OV fault unless OV remains above the threshold for
more than 1.5ms (all voltages are relative to VEE).
OV GATE Cycle to Full enhancement:
1) When OV rises above the OV threshold voltage,
GATE is immediately pulled to VEE, rapidly turning
off the power MOSFET. GATE is held at VEE indefi-
nitely while OV is above the OV threshold voltage. It
is held for an additional 350µs to damp any ringing.
[GATE pulldown]
2) Following the GATE pulldown, GATE is allowed to
float for 650µs. At this point, the GATE begins to
ramp with 52µA charging the gate of the power
MOSFET. [GATE turn-on]
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
______________________________________________________________________________________ 21
3) When GATE reaches the gate threshold voltage of
the power MOSFET, VOUT begins to ramp back
down toward VEE. In the interval where GATE is
below the MOSFET threshold, the MOSFET is off
and VOUT will droop depending on the RC time con-
stant of the load. [VOUT ramp]
4) When VOUT ramps below 74% VCB, the GATE is
rapidly pulled to full enhancement and the OV GATE
cycle is complete. [Full enhancement]
OV GATE Cycle to Fault management:
1) Same as step 1 above. [GATE pulldown]
2) Same as step 2 above. [GATE turn-on]
3) Same as step 3 above. [VOUT ramp]
4) If GATE ramps to 90% of full enhancement and
VOUT remains above 74% VCB, GATE is rapidly
pulled to VEE, fault management is initiated, and
PGOOD is deasserted. [Fault management]
GATE Output
GATE is a complex output structure and its condition at
any moment is dependent on various timing
sequences in response to multiple inputs. A diode to
VEE prevents negative excursions. For positive excur-
sions, the states are:
1) Power-off with 2V clamp.
2) 8Ωpulldown to VEE.
a. Continuous during startup delay and during
fault conditions.
b. Pulsed following detected step or OV
condition.
3) Floating with 16V clamp [prior to GATE ramp].
4) 52µA current source with 16V clamp [GATE ramp].
5) Pullup to internal 10V supply with 16V clamp [full
enhancement].
Appendix B
Step Monitor Component
Selection Analysis
As mentioned previously in the Setting the Circuit-
Breaker and Short-Circuit Thresholds section, the AC
response from VIN to VOUT is dependent on the para-
sitics of the load. This is especially true for the load
capacitor in conjunction with the power MOSFET’s
RDS(ON). The load capacitor (with parasitic ESR and
LSR) and the power MOSFET’s RDS(ON) can be mod-
eled as a heavily damped second-order system. As
such, this system functions as a bandpass filter from
VIN to VOUT limiting the ability of VOUT to follow the VIN
ramp. STEP_MON lags the VIN ramp with a first-order
RC response, while VOUT lags with an overdamped
second-order response.
Given a positive VIN ramp with a ramp rate of dV/dt, the
approximate response of VOUT to VIN is:
VOUT(t) = (dV/dt) x τCx (1-e(-t / τL,eqv) )
+ RDS(ON) x ILOAD (Equation 1)
where τC= CLOAD x RDS(ON).
Equation 1 is a simplification for the overdampened
second-order response of the load to a ramp input, τC
= CLOAD x RDS(ON) and corresponds to the ability of
the load capacitor to transfer dV/dt current to the fully
enhanced power MOSFET’s RDS(ON). The equivalent
time constant of the load (τL,eqv) accounts for the para-
sitic series inductance and resistance of the capacitor
and board interconnect. To characterize the load
dynamic response to VIN ramps, determine τL,eqv
empirically with a few tests.
Similarly, the response of STEP_MON to a VIN ramp is:
VSTEP_MON(t) = (dV/dt) x τSTEP x (1-e(-t / τSTEP) )
+ 10µA x RSTEP_MON (Equation 2)
where τSTEP = RSTEP_MON x CSTEP_MON.
For proper step detection, VSTEP_MON must exceed
STEPTH prior to VOUT reaching VSC or within 1.4ms of
VOUT reaching VCB (or overall VIN ramp rates anticipat-
ed in the application). It is impossible to give a fixed set
of design guidelines that rigidly apply over the wide
array of applications using the MAX5938. There are,
however, limiting conditions and recommendations that
should be observed.
One limiting condition that must be observed is to
ensure that the STEP_MON time constant, τSTEP, is not
so low that at the lowest ramp rate, the anticipated
STEPTH cannot be obtained. The product (dV/dt) x
τSTEP = τSTEP_MON,MAX, is the maximum differential
voltage at STEP_MON if the VIN ramp were to continue
indefinitely. A related condition is setting the
STEP_MON voltage below STEPTH with adequate mar-
gin, ∆VSTEP_MON, to accommodate the tolerance of
both ISTEP_OS (±8%) and RSTEP_MON. In determining
τSTEP_MON, use the 9.2µA limit to ensure sufficient mar-
gin with worst-case ISTEP_OS.
The margin of VOUT (with respect to VSC and VCB) is
set when RCB_ADJ is selected as described in the
Setting the Circuit-Breaker and Short-Circuit Thresholds
section. This margin may be lower at one of the temper-
ature extremes and if so, that value should be used in
the following discussion. These margins will be called
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
22 ______________________________________________________________________________________
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
______________________________________________________________________________________ 23
∆VCB and ∆VSC and they represent the minimum VOUT
excursion required to trip the respective fault.
RSTEP_MON will typically be set to 100kΩ±1%. This
gives a ∆VSTEP_MON of 0.25V, a worst-case low of
0.13V, and a worst-case high of 0.37V. In finding τSTEP
in the equation below, use ∆VSTEP_MON = 0.37V to
ensure sufficient margin with worst-case ISTEP_OS.
To set τSTEP to block all VCB and VSC faults for any
ramp rate, find the ratio of ∆VSTEP_MON to ∆VCB and
choose τSTEP so:
τSTEP = 1.2 x τCx ∆VSTEP_MON / ∆VCB
and since RSTEP_MON = 100kΩ:
CSTEP_MON = τSTEP / RSTEP_MON = τSTEP / 100kΩ
After the first-pass component selection, if sufficient
timing margin exists, it is possible (but not necessary)
to lower RSTEP below 100kΩto reduce the sensitivity of
STEP_MON to VIN noise.
Verification of the Step
Monitor Timing
It is prudent to verify conclusively that all circuit-breaker
and short-circuit faults will be blocked for all ramp
rates. To do this, some form of graphical analysis is
recommended but first, find the value of τL,eqv of the
load by a series of ramp tests as indicated earlier.
These tests include evaluating the load with a series of
VIN ramps of increasing ramp rates and monitoring the
rate of rise of VOUT during the ramp. Each VIN ramp
should have a constant slope. The VOUT response data
must be taken only during the positive ramp. Data
taken after VIN has leveled off at the new higher value
must not be used.
Figure 21 shows the load in parallel with the load
capacitor, CLOAD, and the parallel connection in series
with the power MOSFET, which is fully enhanced with
VGS = 10V. The objective is to determine τL,eqv from
the VOUT response.
Figure 22 shows the general response of VOUT to a VIN
ramp over time t. Equation 1 gives the response of VOUT
to a ramp of dV/dt. The product (dV/dt) x τC=
∆VOUT(max) or the maximum VOUT voltage differential if
the VIN ramp were to continue indefinitely. The parame-
ter of interest is ∆VOUT due to the ramp dV/dt, thus it is
necessary to subtract the DC shift in VOUT due to the
load resistance. For some loads, which are relatively
independent of supply voltage, this may be insignificant.
VOUT(t) = VOUT(t) – RDS(ON) x ILOAD
where ILOAD is a function of the VOUT level that should
be determined separately with DC tests.
Figure 21. VIN Ramp Test Of Load
LEQU
REQV
CLOAD
LOAD
LOAD CAPACITOR
WITH PARASITICS
VIN RAMP
VIN = GND = VEE
10V
RDS,ON
VIN
Figure 22. General Response of VOUT to a VIN Ramp
dv
dt τC
dv
dt
VIN
VOUT.F
VOUTi
VIN RAMP
0
t1 t2 t3 t4
Figure 23. VOUT Response to VIN Ramp of 300V/ms
VOUT RESPONSE TO VIN RAMP OF 300V/ms
TIME (µs)
∆VOLTAGES (V)
764 52 31
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0
08
A
B
dVIN
dt
tCB tSC EF
C
D
A = VIN (GND - VEE)
B = ∆VSTEP_MON
C = ∆VOUT
D = ∆VSTEP,TH
E = ∆VCB
F = ∆VSC
tSTEP
MAX5938
At any time (t) the ∆VOUT fraction of ∆VOUT(max) is:
∆VOUT(t) / [(dV/dt) x τC] = (1-e(-t / τL,eqv))
If VOUT(t) is measured at time t, then the equivalent
time constant of the load is found from:
τL,eqv = -t / ln(1 – ∆VOUT / [(dV/dt) x τC])
As mentioned earlier, several measurements of ∆VOUT
at times t1, t2, t3, and t4 should be made during the
ramp. Each of these may result in slightly different val-
ues of τL,eqv and all values should then be averaged.
In making the measurements, the VIN ramp duration
should be such that ∆VOUT reaches 2 or 3 times the
selected ∆VSC. The ramp tests should include three
ramp rates: ∆VSC / τC, 2 x ∆VSC / τC, and 4 x ∆VSC / τC.
The values of τL,eqv may vary over the range of slew
rates due to measurement error, nonlinear dynamics in
the load, and due to the fact that Equation 1 is a simpli-
fication from a higher order dynamic system. The
resulting range of τL,eqv values should be used to vali-
date the performance of the final design.
Having τC, τL,eqv, RSTEP, and CSTEP in a graphical
analysis using Equation 1 and Equation 2 can verify the
step monitor function by displaying the relative timing
of tCB, tSTEP, and tSC, which are the times when VCB,
VSTEP_MON,and VSC voltage thresholds are exceeded.
A simple Excel spreadsheet for this purpose can be
supplied by Maxim upon request. Figures 23, 24, and
25 graphically verify a particular solution over 3
decades of VIN ramp rates. In addition, Figure 25 veri-
fies that this solution will block all circuit-breaker and
short-circuit faults for even the lowest VIN ramp that will
cause VOUT to exceed VCB.
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
24 ______________________________________________________________________________________
Figure 24. VOUT Response to VIN Ramp of 30V/ms
VOUT RESPONSE TO VIN RAMP OF 30V/ms
TIME (µs)
∆VOLTAGES (V)
A
B
tCB E
F
C
D
A = VIN (GND - VEE)
B = ∆VSTEP_MON
C = ∆VOUT
D = ∆VSTEP,TH
E = ∆VCB
F = ∆VSC
3632282420161284
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
040
tSC
tSTEP
Figure 25. VOUT Response to VIN Ramp of 3V/ms
VOUT RESPONSE TO VIN RAMP OF 3V/ms
TIME (µs)
∆VOLTAGES (V)
A = VIN (GND - VEE)
B = ∆VSTEP_MON
C = ∆VOUT
D = ∆VSTEP,TH
E = ∆VCB
F = ∆VSC
400300100 200
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
0500
A
B
D
E
F
C
tSTEP
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
______________________________________________________________________________________ 25
Timing Table
NAME
SYMBOL
TYPICAL
TIME (s)
Power-Up Delay tONDLY 220m
Load-Probe Test Timeout tLP 220m
Load-Probe Retry Time tLP_OFF 3.5
PGOOD Assertion
Delay Time tPGOOD 1.26m
Autoretry Delay tRETRY 3.5
Circuit-Breaker Glitch Rejection tCB_DLY 1.4m
ON Glitch Rejection tREJ 1.5m
OV Transient Rejection tOVREJ 1.5m
GATE Pulldown Pulse Following
a VIN Step —350µ
GATE Low after a VIN Step,
Prior to Ramp —1m
*OPTIONAL COMPONENT.
**OPTIONAL COMPONENT REPLACED BY SHORT.
MAX5938
PGOOD
VOUT
OFF
CLOAD
DC-DC
CONVERTER
V+
ON
V-
BACKPLANE
GND
-48V
**
*
GATE
VEE
STEP_MON
LP
GND
POL_SEL
ON
OV
CB_ADJ
(VIN = GND - VEE)
VIN
Typical Operating Circuit
Chip Information
TRANSISTOR COUNT: 2320
PROCESS: BiCMOS
MAX5938
-48V Hot-Swap Controller with VIN Step Immunity,
No RSENSE, and Overvoltage Protection
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
E
1
1
21-0055
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH