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for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
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8-Bit Serial Input DMOS Power Driver
A6595
Date of status change: May 3, 2010
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Discontinued Product
Description
The A6595 combines an 8-bit CMOS shift register and
accompanying data latches, control circuitry, and DMOS
power driver outputs. Power driver applications include
relays, solenoids, and other medium-current or high-voltage
peripheral power loads.
The serial-data input, CMOS shift register and latches allow
direct interfacing with microprocessor-based systems. Serial-
data input rates are over 5 MHz. Use with TTL may require
appropriate pull-up resistors to ensure an input logic high.
A CMOS serial-data output enables cascade connections in
applications requiring additional drive lines.
The A6595 DMOS open-drain outputs are capable of sinking
up to 750 mA. All of the output drivers are disabled (the
DMOS sink drivers turned off) by the OUTPUT ENABLE
input high.
The A6595 is furnished in a 20-pin dual in-line plastic package
that is lead (Pb) free, with 100% matte tin leadframe plating.
Copper leadframe base material, reduced supply current
requirements, and low on-state resistance allow the device
to sink 150 mA from all outputs continuously, to ambient
temperatures to 125°C.
26185.120a
Features and Benefits
▪ 50 V minimum output clamp voltage
▪ 250 mA output current (all outputs simultaneously)
▪ 1.3 Ω typical rDS(on)
▪ Low power consumption
▪ Replacements for TPIC6595N and TPIC6595DW
8-Bit Serial Input DMOS Power Driver
Package: 20-pin DIP (suffix A)
Pin-out Diagram
Not to scale
A6595
LOGIC
GROUND
1
2
3
8
9
13
14
15
16
17
19
4
5
6
7
12
18
20
SERIAL
DATA OUT
SERIAL
DATA IN
LOGIC
SUPPLY VDD
STROBE
POWER
GROUND
CLOCKCLK
ST
OUT
7
OUT
6
OUT
5
OUT
0
OUT
1
OUT
2
OUT
3
OUT
4
10 11
POWER
GROUND
POWER
GROUND
OUTPUT
ENABLE OE
REGISTER
CLEAR
POWER
GROUND
LATCHES
REGISTER
REGISTER
LATCHES
CLR
8-Bit Serial Input DMOS Power Driver
A6595
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Units
Logic Supply Voltage VDD 7.0 V
Input Voltage Range VI–0.3 to 7.0 V
Output Voltage VO50 V
Output Drain Current
IOContinuous, each output, all outputs on 250 mA
IOM
Pulsed tw ≤100 μs, duty cycle ≤ 2%; each out-
put, all outputs on 750 mA
Pulsed tw ≤100 μs, duty cycle ≤ 2%; 2.0 A
Single-Pulse Avalanche Energy EAS 75 mJ
Operating Ambient Temperature TARange K –40 to 125 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
*These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static
electrical charges.
Selection Guide
Part Number Packing
A6595KA-T 18 pieces per tube
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 32 ºC/W
*Additional thermal information available on the Allegro website.
50 75 100 125 150
4.0
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE
o
C)
3.5
3.0
2.5
2.0
1.0
1.5
25
8-Bit Serial Input DMOS Power Driver
A6595
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
POWER
GROUND
Dwg. FP-013-5
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
D-TYPE LATCHES
VDD LOGIC
SUPPLY
REGISTER
CLEAR
(ACTIVE LOW)
OUT 0OUT N
LOGIC
GROUND
POWER
GROUND
Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
Functional Block Diagram
2
G3C2
SRG8
C1
R
1D
2
4
5
6
7
14
15
16
17
18
9
12
8
3
13
Device Logic Diagram
8-Bit Serial Input DMOS Power Driver
A6595
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TRUTH TABLE
stnetnoC tuptuOstnetnoC hctaLlaireSstnetnoC retsigeR tfihS tuptuOataDkcolCataD
Input Input I0I1I2... I6I7Output Strobe I0I1I2... I6I7Enable I0I1I2…I
6I7
HHR
0R1…R
5R6R6
LLR
0R1…R
5R6R6
XR
0R1R2…R
6R7R7
XXX … XX X — R
0R1R2…R
6R7
P0P1P2…P
6P7P7P0P1P2…P
6P7LP
0P1P2…P
6P7
XXX … XX H HHH … HH
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous Stat e
SERIAL DATA OUT
LOGIC INPUTS
Dw g. EP-063-2
VDD
OU T
DMOS POWER DRIVER OUTPUT
IN
Dwg. EP-010-15
VDD
Dwg. EP-063-3
OU T
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤0.15VDD
8-Bit Serial Input DMOS Power Driver
A6595
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Limits
stinU.xaM.pyT.niMsnoitidnoC tseTlobmyScitsiretcarahC
Output Breakdown V(BR)DSX IOV——05Am 1 =
Voltage
Off-State Output IDSX VO0.150.0—V 04 = μA
Current VO = 40 V, TA = 125°C — 0.15 5.0 μA
Static Drain-Source rDS(on) IO = 250 mA, VDD = 4.5 V — 1.3 2.0 Ω
On-State Resistance IO = 250 mA, VDD = 4.5 V, TA = 125°C— 2.0 3.2 Ω
IO = 500 mA, VDD = 4.5 V (see note) — 1.3 2.0 Ω
Nominal Output ION VDS(on) = 0.5 V, TA = 85°C—250—mA
Current
Logic Input Current IIH VI = VDD 0.1——V 5.5 = μA
IIL VI = 0, VDD 0.1-——V 5.5 = μA
Logic Input Hysteresis VI(hys) —1.3— V
SERIAL-DATA VOH IOH = -20 μA, VDD = 4.5 V 4.4 4.49 — V
Output Voltage IOH = -4 mA, VDD = 4.5 V 4.1 4.3 — V
VOL IOL = 20 μA, VDD = 4.5 V — 0.002 0.1 V
IOL = 4 mA, VDD = 4.5 V — 0.2 0.4 V
Prop. Delay Time tPLH IO = 250 mA, CL = 30 pF — 650 — ns
tPHL IO = 250 mA, CL = 30 pF — 150 — ns
Output Rise Time trIO = 250 mA, CL = 30 pF — 7500 — ns
Output Fall Time tfIO = 250 mA, CL = 30 pF — 425 — ns
Supply Current IDD(OFF) 00151—wol stupni llA μA
IDD(ON) VDD = 5.5 V, Outputs on — 150 300 μA
IDD(fclk) fclk = 5 MHz, CL = 30 pF, Outputs off — 0.6 5.0 mA
Typical Data is at V DD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤100 μs, duty cycle ≤2%.
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤100 μs, duty cycle ≤2%.
8-Bit Serial Input DMOS Power Driver
A6595
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 10 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 10 ns
C. Clock Pulse Width, tw(CLK) ............................................. 20 ns
D. Time Between Clock Activation
and Strobe, tsu(ST) ....................................................... 50 ns
E. Strobe Pulse Width, tw(ST) ............................................... 50 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 μs
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Serial data present at the input is transferred to the shift reg-
ister on the rising edge of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With the
OUTPUT ENABLE input low, the outputs are controlled by the
state of their respective latches.
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
OU T
N
Dwg. WP-029-2
50%
SERIAL
DATA OU
T
DATA
DATA
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
OUTPUT
ENABLE
OU T
N
Dwg. WP-030-2
DATA
10%
50%
PHL
t
PLH
t
HIGH = ALL OUTPUTS DISABLED
90%
f
t
r
t
8-Bit Serial Input DMOS Power Driver
A6595
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TEST CIRCUITS
Single-Pulse Avalanche Energy Test Circuit and
Waveforms
EAS = IAS x V(BR)DSX x tAV/2
Dwg. EP-066-1
OU T
INPUT
I
O
V
O
t
av
I
AS
= 1.0 A
V
(BR)DSX
V
O(ON)
0.11Ω
100 mH
+15 V
DUT
8-Bit Serial Input DMOS Power Driver
A6595
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TERMINAL DESCRIPTIONS
Terminal No. Terminal Name Function
1 POWER GROUND Reference terminal for output voltage measurements (OUT0-3).
2 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V).
3 SERIAL DATA IN Serial-data input to the shift-register.
4-7 OUT0-3 Current-sinking, open-drain DMOS output terminals.
8 CLEAR When (active) low, the registers are cleared (set low).
9 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output driv-
ers are turned OFF (blanked).
10 POWER GROUND Reference terminal for output voltage measurements (OUT0-3).
11 POWER GROUND Reference terminal for output voltage measurements (OUT0-7).
12 STROBE Data strobe input terminal; shift register data is latched on rising edge.
13 CLOCK Clock input terminal for data shift on rising edge.
14-17 OUT4-7 Current-sinking, open-drain DMOS output terminals.
18 SERIAL DATA OUT CMOS serial-data output to the following shift register.
19 LOGIC GROUND Reference terminal for input voltage measurements.
20 POWER GROUND Reference terminal for output voltage measurements (OUT4-7).
NOTE — Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
8-Bit Serial Input DMOS Power Driver
A6595
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
C
SEATING
PLANE
5.33 MAX
0.46 ±0.12
6.35 +0.76
–0.25
26.16 +0.76
–1.27
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
7.62
2.54
0.38 +0.10
–0.05
21
20
A
Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
Package A, 20-Pin DIP
Copyright ©2000-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
