SN54GTL16622, SN74GTL16622
18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS
SCES049C – AUGUST 1995 – REVISED OCT OBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Translate Between GTL/GTL+ Signal Levels
and LVTTL
D
Members of the Texas Instruments
Widebus
Family
D
Support GTL/GTL+ Signal Operation on
B Port
D
D-Type Flip-Flops With Qualified Storage
Enable
D
Bus-Hold Data Inputs Eliminate the Need
for External Pullup or Pulldown Resistors
on A Port
D
Flow-Through Architecture Facilitates
Printed-Circuit-Board Layout
D
Package Options Include Plastic
Thin-Shrink Small-Outline (DGG) and
Ceramic Quad Flat (HV) Packages
SN74GTL16622 . . . DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OEAB
1A1
GND
1A2
1A3
GND
VCC
1A4
GND
1A5
1A6
GND
1A7
1A8
GND
1A9
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
VCC
GND
2A7
2A8
GND
2A9
OEBA
CLKAB
1CEAB
1CEBA
1B1
GND
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
GND
1B9
2B1
GND
2B2
2B3
GND
2B4
2B5
2B6
VREF
2B7
2B8
GND
2B9
2CEBA
2CEAB
CLKBA
SN54GTL16622 . . . HV PACKAGE
(TOP VIEW)
1B4
1B5
1B6
GND
1B7
1B8
GND
1B9
NC
2B1
GND
1A4
GND
1A3
1A2
GND
NC
GND
1B2
2B2
2B3
GND
2B4
2B5
2B6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9876543216867666564636261
GND
1A5
1A6
GND
1A7
1A8
GND
1A9
NC
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
GND
2A7
2A8
GND
2A9
CLKBA
2B9
GND
2B8
2B7
VCC
VREF
VCC
OEAB
CLKAB
1CEAB
1CEBA
1A1
1B1
1B3
VCC
2A6
NC
NC – No internal connection
OEBA
2CEAB
2CEBA
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
SN54GTL16622, SN74GTL16622
18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS
SCES049C – AUGUST 1995 – REVISED OCT OBER 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
These 18-bit registered bus transceivers contain two sets of D-type flip-flops for temporary storage of data
flowing in either direction.
The B port operates at GTL (VTT = 1.2 V and VREF = 0.8 V) and GTL+ (VTT = 1.5 V and VREF = 1 V) levels, while
the A port and control inputs are compatible with LVTTL logic levels.
Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA)
inputs. The clock-enable (CEAB and CEBA) inputs are designed to control each 9-bit transceiver independently,
which makes the device more versatile.
For A-to-B data flow, the devices operate on the low-to-high transition of CLKAB if CEAB is low. When OEAB
is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for
B to A is similar to that for A to B, but uses OEBA, CLKBA, and CEBA.
Active bus-hold circuitry is provided to hold unused or floating TTL inputs at a valid logic state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54GTL16622 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74GTL16622 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE†
INPUTS OUTPUT
MODE
CEAB OEAB CLKAB A B
MODE
X H X X Z
H L X X B0‡
Latched storage of A data
XL H or L X B0‡
Latched
storage
of
A
data
L L ↑L L
Clocked storage of A data
L L ↑H H
Clocked
storage
of
A
data
†A-to-B data flow is shown: B-to-A data flow is similar but uses OEBA, CLKBA, and
CEBA.
‡Output level before the indicated steady-state input conditions are established
SN54GTL16622, SN74GTL16622
18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS
SCES049C – AUGUST 1995 – REVISED OCT OBER 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
CE
CE
1D
CLK
1D
CLK
1B1
OEAB
1CEAB
CLKAB
CLKBA
1CEBA
OEBA
1A1
1
63
64
33
62
32
261
To Eight Other Channels
CE
CE
1D
CLK
1D
CLK
2B1
2CEAB
2CEBA
2A1
34
35
17 48
To Eight Other Channels
Pin numbers shown are for the DGG package.
SN54GTL16622, SN74GTL16622
18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS
SCES049C – AUGUST 1995 – REVISED OCT OBER 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): A port/B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO
(see Note 1): A port/B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DGG package 1.3 W. . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 1000 mils.
For more information, refer to the
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS T echnology Data
Book
.
recommended operating conditions (see Note 3)
SN54GTL16622 SN74GTL16622
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 3.15 3.3 3.45 3.15 3.3 3.45 V
VTT
Termination GTL 1.14 1.2 1.26 1.14 1.2 1.26
V
V
TT voltage GTL+ 1.35 1.5 1.65 1.35 1.5 1.65
V
VREF
Supply GTL 0.74 0.8 0.87 0.74 0.8 0.87
V
V
REF
y
voltage GTL+ 0.87 1 1.1 0.87 1 1.1
V
VI
In
p
ut voltage
B port 0 VTT 0 VTT
V
V
I
Inp
u
t
v
oltage
Except B port 0 VCC 0 VCC
V
VIH
High-level B port VREF+50 mV VREF+50 mV
V
V
IH
g
input voltage Except B port 2 2
V
VIL
Low-level B port VREF–50 mV VREF–50 mV
V
V
IL input voltage Except B port 0.8 0.8
V
IIK Input clamp current –18 –18 mA
IOH High-level
output current A port –24 –24 mA
IOL
Low-level output A port 24 24
mA
I
OL current B port 50 50
mA
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused control inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54GTL16622, SN74GTL16622
18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS
SCES049C – AUGUST 1995 – REVISED OCT OBER 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VREF = 1 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54GTL16622 SN74GTL16622
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 3.15 V, II = –18 mA –1.2 –1.2 V
VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC–0.2 VCC–0.2
VOH A port
VCC = 3 15 V
IOH = –12 mA 2.4 2.4 V
V
CC =
3
.
15
V
IOH = –24 mA 2 2
VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2 0.2
A port
VCC = 3 15 V
IOL = 12 mA 0.4 0.4
V
CC =
3
.
15
V
IOL = 24 mA 0.5 0.5
VOL VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2 0.2 V
B
p
ort
IOL = 10 mA 0.2 0.2
B
port
VCC = 3.15 V IOL = 40 mA 0.4 0.4
IOL = 50 mA 0.55 0.55
I
I
Control
inputs VCC = 3.45 V, VI = VCC or GND ±5±5
µ
A
I
B port VCC = 3.45 V, VI = VTT or GND ±5±5
µ
Ioff A port VCC = 0, VI or VO = 0 to 3.45 V 100 100 µA
VCC = 3 15 V
VI = 0.8 V 75 75
II(hold) A port
V
CC =
3
.
15
V
VI = 2 V –75 –75 µA
()
VCC = 3.45 V‡, VI = 0.8 V to 2 V ±500 ±500
IOZH B port VCC = 3.45 V, VO = 1.5 V 10 10 µA
IOZ§A port VCC = 3.45 V, VO = VCC or GND ±10 ±10 µA
ICC A or B port VCC = 3.45 V, IO = 0, VI = VCC or GND 60 60 mA
∆ICC¶A port or
control
inputs
VCC = 3.45 V,
A port or control inputs at VCC or GND,
One input at VCC – 0.6 V 500 500 µA
CiControl
inputs VI = 3.15 V or 0 3 3 pF
Ci
A port VO = 3.15 V or 0 10 10 p
F
C
io B port Per IEEE 1194.1 8.5 8.5
pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡This is the bus-hold maximum dynamic current required to switch the input from one state to another.
§For I/O ports, the parameter IOZ includes the input leakage current.
¶This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54GTL16622, SN74GTL16622
18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS
SCES049C – AUGUST 1995 – REVISED OCT OBER 1996
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature for GTL (unless otherwise noted)†
SN54GTL16622 SN74GTL16622
UNIT
MIN MAX MIN MAX
UNIT
fclock Clock frequency 0 200 0 200 MHz
twPulse duration, CLK high or low 2.5 2.5 ns
t
Setu
p
time
Data before CLK↑3.1 3
ns
t
su
Set
u
p
time
CE before CLK↑2.8 2.7
ns
th
Hold time
Data after CLK↑0.7 0.6
ns
t
h
Hold
time
CE after CLK↑0.4 0.3
ns
†These parameters are warranted but not production tested.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature for GTL (see Figure 1)†
PARAMETER
FROM TO SN54GTL16622 SN74GTL16622
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN TYP‡MAX MIN TYP‡MAX
UNIT
fmax 200 200 MHz
tPLH
CLKAB
B
2.7 6.5 2.8 4.3 6.1
ns
tPHL
CLKAB
B
1.9 6.2 2 3.6 5.5
ns
tPLH
OEAB
B
2.5 6.4 2.6 4.2 6
ns
tPHL
OEAB
B
1.6 5.8 1.7 3.1 5.1
ns
Slew rate Both transitions 0.5 0.5 V/ns
trT ransition time, B outputs (0.6 V to 1 V) 0.5 2.6 0.6 1.2 2.5 ns
tfT ransition time, B outputs (1 V to 0.6 V) 0.3 2.3 0.4 0.8 2 ns
tPLH
CLKBA
A
2.1 5.6 2.2 3.7 5.3
ns
tPHL
CLKBA
A
2.2 5.6 2.3 3.8 5.2
ns
ten
OEBA
A
1.7 5.4 1.8 3.3 5
ns
tdis
OEBA
A
2.2 6.2 2.4 4.1 5.7
ns
†These parameters are warranted but not production tested.
‡All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54GTL16622, SN74GTL16622
18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS
SCES049C – AUGUST 1995 – REVISED OCT OBER 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature for GTL+ (unless otherwise noted)
SN54GTL16622 SN74GTL16622
UNIT
MIN MAX MIN MAX
UNIT
fclock Clock frequency 0 200 0 200 MHz
twPulse duration, CLK high or low 2.5 2.5 ns
t
Setu
p
time
Data before CLK↑2.8 2.5
ns
t
su
Set
u
p
time
CE before CLK↑2.7 2.6
ns
th
Hold time
Data after CLK↑0.6 0.5
ns
t
h
Hold
time
CE after CLK↑0.2 0.1
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature for GTL+ (see Figure 1)
PARAMETER
FROM TO SN54GTL16622 SN74GTL16622
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN TYP†MAX MIN TYP†MAX
UNIT
fmax 200 200 MHz
tPLH
CLKAB
B
2.8 6.6 2.9 4.2 6.1
ns
tPHL
CLKAB
B
2 6.6 2.1 3.7 5.7
ns
tPLH
OEAB
B
2.6 6.4 2.7 4.1 5.9
ns
tPHL
OEAB
B
1.7 6.1 1.8 3.3 5.3
ns
Slew rate Both transitions 0.5 0.5 V/ns
trT ransition time, B outputs (0.6 V to 1.3 V) 0.9 3.1 1 1.6 3 ns
tfT ransition time, B outputs (1.3 V to 0.6 V) 0.6 4.3 0.7 1.4 3.3 ns
tPLH
CLKBA
A
2.1 5.6 2.2 3.7 5.3
ns
tPHL
CLKBA
A
2.2 5.6 2.3 3.8 5.2
ns
ten
OEBA
A
1.6 5.4 1.7 3.2 5
ns
tdis
OEBA
A
2.2 6.2 2.4 4.1 5.7
ns
†All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54GTL16622, SN74GTL16622
18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS
SCES049C – AUGUST 1995 – REVISED OCT OBER 1996
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1
6 V
Open
GND
500 Ω
500 Ω TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
tPLH tPHL
Output
Control
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 3 V
0 V
VREF VREF
VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈ 0 V
1.5 V 3 V
0 V
1.5 V 1.5 V 0 V
3 V
0 V
1.5 V 1.5 V
tw
Input
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLKAB to B port)
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
Timing
Input
Data input
A port
Output
Input
VTT
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
25 Ω
LOAD CIRCUIT FOR B OUTPUTS
tPLH tPHL
0 V
1.5 V 1.5 V VOH
VOL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLKBA to A port)
Output
3 V
1.5 V
1.5 V
VREF VREF 0 V
VTT
Data input
B port
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74GTL16622DGGR OBSOLETE TSSOP DGG 64 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 17-May-2005
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’ s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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