Switch-mode Schottky Power Rectifier Surface Mount Power Package MBRD5H100, NBRD5H100 This series of Power Rectifiers employs the Schottky Barrier principle in a large metal-to-silicon power diode. State-of-the-art geometry features epitaxial construction with oxide passivation and metal overlay contact. Ideally suited for use in low voltage, high frequency switching power supplies, free wheeling diodes, and polarity protection diodes. Features * * * * * * * www.onsemi.com SCHOTTKY BARRIER RECTIFIER 5 AMPERES, 100 VOLTS Guardring for Stress Protection Low Forward Voltage 175C Operating Junction Temperature Epoxy Meets UL 94 V-0 @ 0.125 in Short Heat Sink Tab Manufactured - Not Sheared! NBRD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable These Devices are Pb-Free and are RoHS Compliant* DPAK CASE 369C 1 4 3 (Pin 1: No Connect) Mechanical Characteristics: * Case: Epoxy, Molded, Epoxy Meets UL 94 V-0 * Weight: 0.4 grams (approximately) * Finish: All External Surfaces Corrosion Resistant and Terminal MARKING DIAGRAM Leads are Readily Solderable AYWW B 5100G * Lead and Mounting Surface Temperature for Soldering Purposes: * * 260C Max. for 10 Seconds Device Meets MSL1 Requirements ESD Ratings: Machine Model = C (> 400 V) Human Body Model = 3B (> 8000 V) A Y WW B5100 G = Assembly Location = Year = Work Week = Device Code = Pb-Free Package ORDERING INFORMATION Package Shipping MBRD5H100T4G DPAK (Pb-Free) 2,500 / Tape & Reel NBRD5H100T4G DPAK (Pb-Free) 2,500 / Tape & Reel NBRD5H100T4G-VF01 DPAK (Pb-Free) 2,500 / Tape & Reel Device *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2016 August, 2020 - Rev. 9 1 For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MBRD5H100/D MBRD5H100, NBRD5H100 MAXIMUM RATINGS Symbol Value Unit Peak Repetitive Reverse Voltage Working Peak Reverse Voltage DC Blocking Voltage Rating VRRM VRWM VR 100 V Average Rectified Forward Current TC = 171C IF(AV) Peak Repetitive Forward Current (Square Wave, Duty = 0.5) TC = 171C IFRM Nonrepetitive Peak Surge Current (Surge applied at rated load conditions halfwave, single phase, 60 Hz) IFSM Operating Junction and Storage Temperature Range (Note 1) TJ, Tstg 5 10 105 -65 to +175 A A A C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The heat generated must be less than the thermal conductivity from Junction-to-Ambient: dPD/dTJ < 1/RqJA. THERMAL CHARACTERISTICS Characteristic Thermal Resistance Junction-to-Case (Note 2) Junction-to-Ambient (Note 2) Symbol Value RqJC RqJA 1.6 95.8 Symbol Value Unit C/W 2. When mounted using minimum recommended pad size on FR-4 board. ELECTRICAL CHARACTERISTICS Characteristic Maximum Instantaneous Forward Voltage (Note 3) (IF = 5 A, TJ = 25C) (IF = 5 A, TJ = 125C) VF Maximum Instantaneous Reverse Current (Note 3) (Rated dc Voltage, TJ = 125C) (Rated dc Voltage, TJ = 25C) IR 0.71 0.60 4.5 3.5 Unit V mA mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width = 300 ms, Duty Cycle 2.0% www.onsemi.com 2 MBRD5H100, NBRD5H100 100 100 10 1 150C 25C 125C 0.1 0.1 0.2 10 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 10 1 150C 25C 125C 0.1 0.1 0.2 0.4 0.6 0.7 0.8 0.9 1.0 Figure 1. Typical Forward Voltage Figure 2. Maximum Forward Voltage 1.1 1.2 100 1 125C 0.01 0.001 25C 0.0001 10 150C 1 125C 0.1 0.01 25C 0.001 0.00001 0.0001 0 10 20 30 40 50 60 70 80 90 0 100 10 20 VR, REVERSE VOLTAGE (V) 30 40 50 60 70 80 90 100 VR, REVERSE VOLTAGE (V) Figure 3. Typical Reverse Current Figure 4. Maximum Reverse Current 10 I F(AV) , AVERAGE FORWARD CURRENT (A) 1200 TJ = 25C f = 1 MHz 1000 C, CAPACITANCE (pF) 0.5 VF, INSTANTANEOUS FORWARD VOLTAGE (V) 150C 0.1 0.3 VF, INSTANTANEOUS FORWARD VOLTAGE (V) Ir, REVERSE CURRENT (mA) Ir, REVERSE CURRENT (mA) IF, INSTANTANEOUS FORWARD CURRENT (A) IF, INSTANTANEOUS FORWARD CURRENT (A) TYPICAL CHARACTERISTICS 800 600 400 200 0 0 20 40 60 80 100 9 8 RqJC = 1.6 C/W dc 7 6 Square 5 4 3 2 1 0 145 150 155 160 165 170 TC, CASE TEMPERATURE (C) VR, REVERSE VOLTAGE (V) Figure 5. Typical Capacitance Figure 6. Current Derating, Case www.onsemi.com 3 175 180 MBRD5H100, NBRD5H100 5 P F(AV) , AVERAGE POWER DISSIPATION (W) I F(AV) , AVERAGE FORWARD CURRENT (A) TYPICAL CHARACTERISTICS RqJA = 95.8 C/W 4 dc 3 Square Wave 2 1 0 0 100 R(t) (C/W) 10 1.0 20 40 60 80 100 120 140 160 22 20 18 Square Wave 16 14 12 dc 10 8 6 4 2 0 180 0 5 10 15 TA, AMBIENT TEMPERATURE (C) IF(AV), AVERAGE FORWARD CURRENT (A) Figure 7. Current Derating, Ambient Figure 8. Forward Power Dissipation 20 50% (DUTY CYCLE) 20% 10% 5.0% 2.0% 1.0% 0.1 0.01 SINGLE PULSE 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 PULSE TIME (s) Figure 9. Thermal Response, Junction-to-Case www.onsemi.com 4 10 100 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E C A b3 B c2 4 L3 Z D 1 2 H DETAIL A 3 L4 NOTE 7 c SIDE VIEW b2 e b 0.005 (0.13) TOP VIEW BOTTOM VIEW C M Z H L2 GAUGE PLANE C L SEATING PLANE BOTTOM VIEW A1 L1 DETAIL A Z ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 --- 0.040 0.155 --- MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 --- 1.01 3.93 --- GENERIC MARKING DIAGRAM* STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. 2.58 0.102 1.60 0.063 IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. 6.17 0.243 SCALE 3:1 AYWW XXX XXXXXG XXXXXX A L Y WW G 3.00 0.118 5.80 0.228 XXXXXXG ALYWW mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: STATUS: NEW STANDARD: 98AON10527D ON SEMICONDUCTOR STANDARD REF TO JEDEC TO-252 http://onsemi.com DPAK SINGLE GAUGE SURFACE 1 MOUNT (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 - Rev. 0 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON10527D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001 A ADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008 B ADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009 C ADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009 D RELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A. CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010 E ADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAMBALIZA. 06 FEB 2014 F ADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K. MUSTAFA. 21 JUL 2015 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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