FM25V20-G - CYPRESS SEMICONDUCTOR

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THIS SPEC IS OBSOLETE

Spec No

001

84500

Spec Title

FM25V20, 2

MBIT (256 K X 8) SERIAL (SPI) F

RAM

Sunset Owner

Girija Chougala

(

GVCH

)

Replaced by

NONE

FM25V20

2-Mbit (256 K × 8) Serial (SPI) F-RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-84500 Rev. *G Revised June 2, 2015

2-Mbit (256 K × 8) Serial (SPI) F-RAM

Features

■2-Mbit ferroelectric random access memory (F-RAM) logically

organized as 256 K × 8

❐High-endurance 100 trillion (1014) read/writes

❐151-year data retention (See the Data Retention and Endur-

ance table)

❐NoDelay™ writes

❐Advanced high-reliability ferroelectric process

■Very fast serial peripheral interface (SPI)

❐Up to 40-MHz frequency

❐Direct hardware replacement for serial flash and EEPROM

❐Supports SPI mode 0 (0, 0) and mode 3 (1, 1)

■Sophistica te d w r ite protecti on s c he me

❐Hardware protection using the Write Protect (WP) pin

❐Software protection using Write Disable instruction

❐Software block protection for 1/4, 1/2, or entire array

■Device ID

❐Manufacturer ID and Product ID

■Low power consumption

❐300 A active current at 1 MHz

❐100 A (typ) standby current

❐3 A sleep mode current

■Low-voltage operation: VDD = 2.0 V to 3.6 V

■Industrial temperature –40 C to +85 C

■Packages

❐8-pin small outline integrated circuit (SOIC) package

❐8-pin thin dual flat no leads (TDFN) package

■Restriction of hazardous substances (RoHS) compliant

Functional Overview

The FM25V20 is a 2-Mbit nonvolatile memory employing an

advanced ferroelectric process. A ferroelectric random access

memory or F-RAM is nonvolatile and performs reads and writes

similar to a RAM. It provides reliable data retention for 151 years

while eliminating the complexities, overhead, and system-level

reliability problems caused by seri al flash, EEPROM, and othe r

nonvolatile memories.

Unlike serial flash and EEPROM, the FM25V20 performs write

operations at bus speed. No write delays are incurred. Data is

written to the memory array immediately after each byte is

successfully transferred to the device. The next bus cycle can

commence without the need for data polling. In addition, the

product offers substantial write endura nce compared with other

nonvolatile memories. The FM25V20 is capable of supporting

1014 read/write cycles, or 100 million times more write cycles

than EEPROM.

These capabilities make the FM25V20 ideal for nonvolatile

memory applications, requiring frequent or rapid writes.

Examples range from data collection, where the number of write

cycles may be critical, to demanding industrial controls where the

long write time of serial flash or EEPROM can cause data loss.

The FM25V20 provides substantial benefits to users of serial

EEPROM or flash as a hardware drop-in replacement. The

FM25V20 uses the high-speed SPI bus, which enhances the

high-speed write capability of F-RAM technology. The device

incorporates a read-only Device ID that allows the host to

determine the manufacturer, product density, and product

revision. The device specifications are guaranteed over an

industrial temperature range of –40 C to +85 C.

For a complete list of related documentation, click here.

Logic Block Diagram

Instruction Decoder

Clock Generator

Control Logic

Write Protect

Instruction Register

Address Register

Counter

256 K x 8

F-RAM Array

Data I/ O Register

Nonvolatile Status

HOLD

SCK

SOSI

FM25V20

Document Number: 001-84500 Rev. *G Page 2 of 24

Contents

Pinouts ..............................................................................3

Pin Definitions ..................................................................3

Overview ............................................................................4

Memory Architecture ................... ... ................. .................4

Serial Peripheral Interface – SPI Bus ........................ ... ...4

SPI Overview ............................. ............................... ...4

SPI Modes .................................... ................. ..............5

Power Up to First Access ............................................6

Command Structure ....................................................6

WREN - Set Write Enable Latch .................................6

WRDI - Reset Write Enable Latch ...............................6

Status Register and Write Protection ............................. 7

RDSR - Read Status Register .....................................8

WRSR - Write Status Register ....................................8

Memory Operation ............... .............................................8

Write Operation ................. .............................. ............8

Read Operation ...........................................................9

Fast Read Operation .................... ... ................ ............9

HOLD Pin Operation .................................................10

Sleep Mode ...............................................................11

Device ID ...................................................................11

Endurance .................................................................12

Maximum Ratings ...........................................................13

Operating Range .............................................................13

DC Electrical Characteristics ............ ... ................. ... .. ...13

Data Retention and Endurance .....................................14

Capacitance ....................................................................14

Thermal Resistance ........................................................14

AC Test Conditions ........ ................. ...............................14

AC Switching Characteristi cs ... ................. .. .................15

Power Cycle Timing .......................................................17

Ordering Information ......................................................18

Ordering Code Definitions .........................................18

Package Diagrams ..........................................................19

Acronyms ........................................................................21

Document Conventions ........................ ................. ........21

Units of Measure ............. ... ... ................. ................ ...21

Document History Page .............................. ................ ...22

Sales, Solutions, and Legal Information ......................24

Worldwide Sales and Design Support .......................24

Products ....................................................................24

PSoC® Solutions ......................................................24

Cypress Developer Community ...................... ... ........24

Technical Support .....................................................24

FM25V20

Document Number: 001-84500 Rev. *G Page 3 of 24

Pinouts Figure 1. 8-pin SOIC pinout

Figure 2. 8-pin TDF N pinout

HOLD

SCK

4 5

CS 8

VDD

Top View

not to scale

VDD

SCK

HOLD

PAD

EXPOSED

Top View

not to scale

Pin Definitions

Pin Name I/O Type Description

CS Input Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power

standby mode, ignores other i nputs, and the outpu t is tristated. When LOW, the device intern ally

activates the SCK signal. A falling edge on CS must occur before every opcode.

SCK Input Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising

edge and outputs occur on the falling edge. Because the device is synchronous, the clock

frequency may be any value between 0 and 40 MHz and may be interrupted at any time.

SI[1] Input Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of

SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD

specifications.

SO[1] Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all

other times including when HOLD is LOW. Data transitions are driven on the falling edge of the

serial clock.

WP Input Write Protect. This Active LOW pin prevents write opera tion to the Status Regi ster when WPEN

is set to ‘1’. This is critical because other write protection features are controlled through the St atus

Protection” on page 7. This pin must be tied to VDD if not used.

HOLD Input HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for

another task. When HOLD is LOW, the curren t operation is suspended. The device ignores any

transition on SCK or CS. All transitions on HOLD must occur while SCK is LOW . This pin must be

tied to VDD if not used.

VSS Power supply Ground for the device. Must be connected to the ground of the system.

VDD Power supply Power supply inputs to the device.

EXPOSED PAD No connect The EXPOSED PAD on the bottom of 8-pin TDFN package is not connected to the die. The

EXPOSED PAD should be left floating.

Note

1. SI may be connected to SO for a single pin data interface.

FM25V20

Document Number: 001-84500 Rev. *G Page 4 of 24

Overview

The FM25V20 is a serial F-RAM memory. The memory array is

logically organized as 262,144 × 8 bits and is accessed using an

industry-standard serial peripheral interface (SPI) bus. The

functional operation of the F-RAM is similar to serial flash and

serial EEPROMs. The major difference between the FM25V20

and a serial flash or EEPROM with the same pinout is the

F-RAM's superior write performance, high endurance, and low

power consumption.

Memory Architecture

When accessing the FM25V20, the user addresses 256K

locations of eight data bits each. These eight data bits are shifted

in or out serially. The addresses are accessed using the SPI

protocol, which includes a chip select (to permit multiple devices

on the bus), an opcode, and a three- byte address. The upp er 6

bits of the address range are 'don't care' values. The complete

address of 18 bits specifies each byte address uniquely.

Most functions of the FM25V20 are either controlled by the SPI

interface or handled by on-board circuitry. The access time for

the memory operation is essentially zero, beyond the time

needed for the serial protocol. That is, the memory is read or

written at the speed of the SPI bus. Unlike a serial flash or

EEPROM, it is not necessary to poll the device for a ready

condition beca us e wr it es oc cur at b us sp eed . B y the time a n ew

bus transaction can be shifted into the device , a write operation

is complete. This is explained in more detail in the interface

section.

Serial Peripheral Interface – SPI Bus

The FM25V20 is a SPI slave device and operates at spe eds up

to 40 MHz. This high-speed serial bus provides

high-performance serial communication to a SPI master. Many

common microcontrollers have hardware SPI ports allowing a

direct interface. It is quite simple to emulate the port using

ordinary port pins for microcontrollers that do not. The FM25V20

operates in SPI Mode 0 and 3.

SPI Overview

The SPI is a four-pin interface with Chip Select (CS), Serial Input

(SI), Serial Output (SO), and Serial Clock (SCK) pins.

The SPI is a synchronous serial interface, which uses clock and

data pins for memory access and su pports multiple devices on

the data bus. A device on the SPI bus is activated using the CS

pin.

The relationship between chip select, clock, and data is dictated

by the SPI mode. This device supports SPI modes 0 and 3. In

both of these modes, data is clocked into the F-RAM on the rising

edge of SCK starting from the first rising edge after CS goes

active.

The SPI protocol is controlled by opcodes. These opcodes

specify the commands from the bus master to the slave devi ce.

After CS is activated, the first byte transferred from the bus

master is the opcode. Following the opcode, any addresses and

data are then transferred. The CS must go inactive after an

operation is complete and befo re a new opcod e can be issue d.

The commonly used terms in the SPI protocol are as follows:

SPI Master

The SPI master device controls the operations on a SPI bus. An

SPI bus may have only one master with one or more slave

devices. All the slaves share the same SPI bus lines and the

master may select any of the slave devices using the CS pin. All

of the operations must be initiated by the master activating a

slave device by pulling the CS pin of the slave LOW . The master

also generates the SCK and all the data transmission on SI and

SO lines are synchronized with this clock.

SPI Slave

The SPI slave device is activated by the master through the Chip

Select line. A slave device gets the SCK as an input from the SPI

master and all the communication is synchronized with this

clock. An SPI slave never initiates a communication on the SPI

bus and acts only on the instruction from the master.

The FM25V20 operates as an SPI slave and may share the SPI

bus with other SPI slave devices.

Chip Select (CS)

To select any slave device, the master needs to pull down the

corresponding CS pi n. Any instruction can be i ssued to a slave

device only while the CS pin is LOW. When the device is not

selected, data through the SI pin is ignored and the serial output

pin (SO) remains in a high-impedan ce state.

Note A new instruction must begin with the falling edge of CS.

Therefore, only one opcode can be issued fo r each active Chip

Select cycle.

Serial Clock (SCK)

The Serial Clock is generated by the SPI master and the

communication is synchronized with this clock after CS goes

LOW.

The FM25V20 enables SPI modes 0 and 3 for data

communication. In both of these modes, the inputs are latched

by the slave device on the rising edge of SCK and ou tputs are

issued on the falling edge. Therefore, the first rising edge of SCK

signifies the arrival of the first bit (MSB) of a SPI instruction on

the SI pin. Further, all data inputs and outputs are synchronized

with SCK.

Data Transmission (SI/SO)

The SPI data bus consists of two lines, SI and SO, for serial dat a

communication. SI is also referred to as Master Out Slave In

(MOSI) and SO is referred to as Master In Slave Out (MISO). The

master issues instructions to the slave through the SI pin, while

the slave responds through the SO pin. Multiple slave devices

may share the SI and SO line s as de scri b ed ea rl i er.

The FM25V20 has two separate pins for SI and SO, which can

be connected with the master as shown in Figure 3.

FM25V20

Document Number: 001-84500 Rev. *G Page 5 of 24

For a microcontroller that has no dedicated SPI bus, a

general-purpose port may be used. To reduce hardware

resources on the controller , it is possible to connect the two data

pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.

Figure 4 shows such a configuration, which uses only three pins.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data tran s missi on .

The 2-Mbit serial F-RAM requires a 3-byte address for any read

or write operation. Because the address is only 1 8 bits, the first

six bits, which are fed in are ignored by the device. Although

these six bits are ‘don’t care’, Cypress recommends that these

bits be set to 0s to enable seamless transition to higher memory

densities.

Serial Opcode

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

FM25V20 uses the standard opcodes for memory accesses.

Invalid Opcode

If an invalid opcode i s received, the opcode is ignored and the

device ignores any additio nal serial data on the SI pin until the

next falling edge of CS, and the SO pin remains tristated.

Status Register

FM25V20 has an 8-bit Status Register. The bits in the Status

described in Table 3 on page 7.

SPI Modes

FM25V20 may be driven by a microcontroller with its SPI

peripheral running in either of the following two modes:

■SPI Mode 0 (CPOL = 0, CPHA = 0)

■SPI Mode 3 (CPOL = 1, CPHA = 1)

For both these modes, the i nput data is latched in on the rising

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

Figure 3. System Configuration with SPI Port

CS1

CS2

HOLD1

HOLD2

FM25V20 FM25V20

WP1

WP2

SCK SI SO SCK SI SO

CS HOLD WP CS HOLD WP

SCK

MOSI

MISO

SPI

Microcontroller

Figure 4. System Configuration without SPI Port

FM25V20

Microcontroller

SCK SI SO

CS HOLD WP

P1.2

P1.1

P1.0

FM25V20

Document Number: 001-84500 Rev. *G Page 6 of 24

The two SPI modes are shown in Figure 5 on page 6 and Figure

6 on page 6. The status of the clock when the bus master is not

transferring data is:

■SCK remains at 0 for Mode 0

■SCK remains at 1 for Mode 3

The device detects the SPI mode from the status of the SCK pin

when the device is selected by bringi ng the CS pin LOW. If the

SCK pin is LOW when the device is selected, SPI Mode 0 is

assumed and if the SCK pin is HIGH, it works in SPI Mode 3.

Power Up to First Access

The FM25V20 is not accessible for a tPU time after power-up.

Users must comply with the timing parameter, tPU, which is the

minimum time from VDD (min) to the first CS LOW.

Command Structure

There are nine commands, called opco des, that can be issued

by the bus master to the FM25V20. They are listed in Table 1.

These opcodes control the functions performed by the memory.

WREN - Set Write Enable Latch

The FM25V20 will power up with writes disabled. The WREN

command must be issued before any write operation. Sending

the WREN opcode allows the user to issue subsequent opcodes

for write operations. These include writing the Status Register

(WRSR) and writing the memory (WRITE).

Sending the WREN opcode causes the internal Write Enable

Latch to be set. A flag bit in the Status Register, called WEL,

indicates the state of the latch. WEL = ’1’ indicates that writes are

permitted. Attempting to write the WEL bit in the Status Re gister

has no effect on the state of this bit – only the WREN opcode can

set this bit. The WEL bit will be automatically cleared on the rising

edge of CS following a W RDI, a WRSR, or a WRIT E opera tion.

This preve nt s f ur ther wr it es to the Status Register or the F-RAM

array without another WREN command. Figure 7 illustrates the

WREN command bus configuration.

WRDI - Reset Write Enable Latch

The WRDI command disables all write activity by clearing the

Write Enable Latch. The user can verify that writes are disabled

by reading the WEL bit in the Status Register and verifying th at

WEL is equal to ‘0’. Figure 8 illustrates the WRDI command bus

configuration.

Figure 5. SPI Mode 0

Figure 6. SPI Mode 3

Table 1. Opcode Commands

Name Description Opcode

WREN Set write enable latch 0000 0110b

WRDI Reset write enable latch 0000 0100b

RDSR Read Status Register 0000 0101b

WRSR Write Status Register 0000 0001b

READ Read memory data 0000 0011b

FSTRD Fast read memory data 0000 1011b

WRITE Write memory data 0000 0010b

SLEEP Enter sleep mode 1011 1001b

RDID Read device ID 1001 1111b

LSB

MSB

76543210

SCK

012 3 4 567

SCK

SI 76543210

LSB

MSB

012 3 4 567

Figure 7. WREN Bus Configuration

Figure 8. WRDI Bus Configuration

0 0 0 0 0 1 1 0

SCK

HI-Z

0 1 2 3 4 5 6 7

0 0 0

SCK

HI-Z

0 1 2 3 4 5 6 7

001

FM25V20

Document Number: 001-84500 Rev. *G Page 7 of 24

Status Register and Write Protection

The write protection features of the FM25V20 are multi-tiered

and are enabled through the status register. The S t atus Register

is organized as follows. (The default value shipped from the

factory for bit 0, WEL, BP0, BP1, bits 4–5, WPEN i s ‘0’, a nd for

bit 6 is ‘1’.)

Bits 0 and 4-5 are fixed at ‘0’ and bit 6 is fixed at ‘1’; none of these

bits can be modified. Note that bit 0 ("Ready or Write in progress”

bit in serial flash and EEPROM) is unnecessary, as the F-RAM

writes in real-time and is never busy, so it reads out as a ‘0’. An

exception to this is when the device is waking up from sleep

mode, which is descri bed in Sleep Mode on page 11. The BP1

and BP0 control the software write-protection features and are

nonvolatile bits. The WEL flag indicates the state of the Write

Enable Latch. Attempting to directly write the WEL bit in the

S tatus Register has no effect on it s state. This bit is internally set

and cleared via the WREN and WRDI commands, respectively.

BP1 and BP0 are memory block write protection bits. They

specify portions of memory that are write-protected as shown in

Table 4.

The BP1 and BP0 bits and the Write Enable L atch are the onl y

mechanisms that protect the memory from writes. The remaining

write protection features protect inadvertent changes to the block

protect bits.

The write protect enable bit (WPEN) in the Status Register

controls the effect of the hardware write protect (WP) pin. When

the WPEN bit is set to '0', the status of the WP pin is ignored.

When the WPEN bit is set to '1', a LOW on the WP pin inhibits a

write to the Status Register. Thus the Status Register is

write-protected only when WPEN = '1' and WP = '0'.

Table 5 summarizes the write protection conditions.

Tab le 2. Status Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN (0) X (1) X (0) X (0) BP1 (0) BP0 (0) WEL (0) X (0)

Table 3. Status Register Bit Definition

Bit Definition Description

Bit 0 Don’t care This bit is non-writable and always returns ‘0’ upon read.

Bit 1 (WEL) Write Enable WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up.

WEL = '1' --> Write enabled

WEL = '0' --> Write disabled

Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details, see Table 4 on page 7.

Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details, see Table 4 on page 7.

Bit 4-5 Don’t care These bits are non-writable and always return ‘0’ upon read.

Bit 6 Don’t care This bit is non-writable and always returns ‘1’ upon read.

Bit 7 (WPEN) Write Protect Enable bit Used to enable the function of Write Protect Pin (WP). For details, see Table 5 on page 7.

Table 4. Block Memory Write Protection

BP1 BP0 Protected Addres s Ran ge

0 0 None

0 1 30000h to 3FFFFh (upper 1/4)

1 0 20000h to 3FFFFh (upper 1/2)

1 1 00000h to 3FFFFh (all)

Table 5. Write Protection

WEL WPEN WP Protected

Blocks Unprotected

Blocks Status

0 X X Protected Protected Protected

1 0 X Protected Unprotected Unprotected

1 1 0 Protected Unprotected Protected

1 1 1 Protected Unprotected Unprotected

FM25V20

Document Number: 001-84500 Rev. *G Page 8 of 24

RDSR - Read Status Register

The RDSR command allows the bus master to verify the

contents of the Status Register. Reading the status register

provides information about the current state of the

write-protection features. Following the RDSR opcode, the

FM25V20 will return one byte with the contents of the Status

WRSR - Write Status Register

The WRSR command allows the SPI bus master to write into the

Status Register and change the write protect configuration by

setting the WPEN, BP0 and BP1 bits as required. Before issuing

a WRSR command, the WP pin must be HIGH or inactive. Note

that on the FM25V20, WP only prevents writing to the Status

command, the user must send a WREN command to enable

writes. Executing a WRSR command is a write operation and

therefore, clears the Write Enable Latch.

Memory Operation

The SPI interface, which is capable of a high clock frequency,

highlights the fast write capability of the F-RAM technology.

Unlike serial flash and EEPROMs, the FM25V20 can perform

sequential writes at b us speed. No page register is needed and

any number of sequential writes may be performed.

Write Operation

All writes to the memory begin with a WREN opcode with CS

being asserted and deasserted. The next opcode is WRITE. The

WRITE opcode is followed by a three-byte address containing

the 18-bit address (A17-A0) of the first data byte to be written into

the memory. The upper six bits of the three-byte address are

ignored. Subsequent bytes are data bytes, which are written

sequentially. Addresses are incremented internally as long as

the bus master continues to issue clocks and keeps CS LOW. If

the last address of 3FFFFh is reached, the counter will roll over

to 00000h. Data is written MSB first. The rising edge of CS

terminates a write operation. A write operation is shown in

Figure 11.

Note When a burst write reaches a protected block address, the

automatic address increment stops and all the subsequent data

bytes received fo r write will be ignored by the device.

EEPROMs use page buffers to increase their write throughput.

This compensates for the technology's inherently slow write

operations. F-RAM memories do not have page buffers because

each byte is written to the F-RAM array immediately after it is

clocked in (after the eighth clock). This allows any number of

bytes to be written without page buffer delays.

Note If the power is lost in the middle of the write operation, only

the last completed byte will be written.

Figure 9. RDSR Bus Configuration

Figure 10. WRSR Bus Configuration (WREN not shown)

SCK

01234567

000001 0 0

HI-Z

012345 67

LSB

D0D1D2D3D4D5D6

MSB

Opcode

Data

SCK

01 23 4567

00000001

MSB LSB

D2D3D7

HI-Z

012345 67

Opcode Data

FM25V20

Document Number: 001-84500 Rev. *G Page 9 of 24

Read Operation

After the falling edge of CS, the bus master can issue a READ

opcode. Followi ng the READ command is a three-byte address

containing the 18-bit address (A17-A0) of the first byte of the

read operation. The upper six bits of the address are ignored.

After the opcode and address are issued, the device drives out

the read data on the next eight clocks. The SI input is ignored

during read data bytes. Subsequent bytes are data bytes, which

are read out sequentia lly. Addresses are incremented in ternall y

as long as the bus master continues to issue clocks and CS is

LOW. If the last add ress of 3FFFFh is reached, the cou nter will

roll over to 00000h. Data is read MSB first. The rising edge of CS

terminates a read operation and tristates the SO pin. A read

operation is shown in Figure 12.

Fast Read Operation

The FM25V20 supports a FAST READ opcode (0Bh) that is

provided for code compatibility with serial flash devices. The

FAST READ opcode is followed by a three-byte address

containing the 18-bit address (A17-A0) of the first byte of the

read operation and then a dummy byte. The dummy byte inserts

a read latency of 8-clock cycle. The fast read operation is

otherwise the same as an ordinary read operation excep t that it

requires an additional dummy byte. After receiving opcode,

address, and a dummy byte, the FM25V20 starts driving its SO

line with data bytes, with MSB first, and continues transmitting

as long as the device is selected and the clock is available. In

case of bulk read, the internal address counter is incremented

automatically, and after the last address 3FFFFh is reached, the

counter rolls over to 00000h. When the device is driving data on

its SO line, any transition on its SI line is ignored. The rising edge

of CS terminates a fast read operation and tristates the SO pin.

A Fast Read operation is shown in Figure 13.

Figure 11. Memory Write (WREN not shown) Operation

Figure 12. Memory Read Operation

SCK

01234 5 6 70 7654321 2021222301234567

MSB LSB

Data

D0D1D2D3D4D5D6D7

Opcode

0000001

X X X X X A17

A16 A3 A1A2 A0

18-bit Address

MSB LSB

HI-Z

SCK

01 23456 70 7654321 20212223012345 6 7

MSB LSB

Data

Opcode

0000001

X X X X X A17

A16 A3 A1A2 A0

18-bit Address

MSB LSB

D0D1D2D3D4D5D6D7

HI-Z

FM25V20

Document Number: 001-84500 Rev. *G Page 10 of 24

HOLD Pin Operation

The HOLD pin can be used to interrupt a serial operation without

aborting it. If the bus master pulls the HOLD pin LOW whi le SCK

is LOW, the current operation will pause. Taking the HOLD pin

HIGH while SCK is LOW will resume an operation. The

transitions of HOLD must occur while SCK is LOW , but the SCK

and CS pin can toggle duri ng a hold state.

Figure 13. Fast Read Operation

SCK

012345670 7654321 202122232425262728 293031

Data

Opcode

0000101 XXX X A171X

A16 A3 A1A2 A0

18-bit Address

MSB LSB

D0D1D2D3D4D5D6D7

012345 67

XXXXXXXX

Dummy Byte

HI-Z

Figure 14. HOLD Operation[2]

SCK

HOLD

SI VALID IN VALID IN

Note

2. Figure shows HOLD operation for input mode and output mode.

FM25V20

Document Number: 001-84500 Rev. *G Page 11 of 24

Sleep Mode

A low-power sleep mode is implemented on the FM25V20

device. The device will enter the low-power state when the

SLEEP opcode B9h is clocked in and a rising edge of CS is

applied. When in sleep mode, the SCK and SI pins are ignored

and SO will be HI-Z, but the device continues to monitor the CS

pin. On the next falling edge of CS, the device will return to

normal operation within tREC time. The SO pin remains in a HI-Z

state during the wakeup period. The device does not necessarily

respond to an opcode within the wakeup period. To start the

wakeup procedure, the controller may send a “dummy” read, for

example, and wait the remaining tREC time.

Device ID

The FM25V20 device can be interrogated for its manufacturer,

product identification, and die revision. The RDID opcode 9Fh

allows the user to read the manufacturer ID and product ID, both

of which are read-only bytes. The JEDEC-assigned

manufacturer ID places the Cypress (Ramtron) identifier in bank

7; therefore, there are six bytes of the continuation code 7Fh

followed by the singl e byte C2h. The re are tw o byte s of product

ID, which includes a family code, a density code, a sub code, and

the product revi si o n co de .

Figure 15. Sleep Mode Operation

SCK

HI-Z

Enters Sleep Mode

VALID IN

tSU

tREC Recovers from Sleep Mode

1011 1 00 1

1 2 3 4 5 6 7

Table 6. Device ID

Device ID

(9 bytes)

Device ID Description

71–16

(56 bits) 15–13

(3 bits) 12–8

(5 bits) 7–6

(2 bits) 5–3

(3 bits) 2–0

(3 bits)

Manufacturer ID Product ID

Family Density Sub Rev Rsvd

7F7F7F7F7F7FC22500h 0111111101111111011111110111

1111011111110111111111000010 001 00101 00 000 000

Figure 16. Read Device ID

SCK

Opcode

01 2 3 456 70 7654321 444546 5556575859606162636465666768697071

10011111

LSBMSB

HI-Z

47 48 49 50 51 52 53 54

9-Byte Device ID

D7 D6 D5 D4 D3 D2 D1 D0 D3 D1 D7D2 D0 D5 D3 D1D4 D2 D7 D5 D3D6 D4D6 D0 D1 D7 D5D0 D6 D3 D1D2 D0D2 D4

FM25V20

Document Number: 001-84500 Rev. *G Page 12 of 24

Endurance

The FM25V20 devices are capable of being accessed at least

1014 times, reads or writes. An F-RAM memory operates with a

read and restore mechan ism. Therefor e, an endurance cycl e is

applied on a row basis for each access (read or write) to the

memory array. The F-RAM architecture is b ased on an array of

rows and columns of 32K rows of 64-bits each. The entire row is

internally accessed once, whether a single byte or all eight bytes

are read or written. Each byte in the row is counted only once in

an endurance calculation. Table 7 shows endurance calculations

for a 64-byte repeating loop, which includes an opcode, a starting

address, and a sequential 64-byte data stream. This causes

each byte to experience one enduran ce cycl e through th e loop.

F-RAM read and write endurance is virtually unlimited even at a

40-MHz clock rate.

Tab le 7. Time to Reach Endurance Limit for Repeating

64-byte Loop

SCK Freq

(MHz) Endurance

Cycles/sec Endurance

Cycles/year Years to Reach

Limit

40 73,520 2.32 × 1012 43.1

10 18,380 5.79 × 1011 172.7

5 9,190 2.90 × 1011 345.4

FM25V20

Document Number: 001-84500 Rev. *G Page 13 of 24

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Storage temperature ................................ –55 C to +125 C

Maximum junction temperature ................................... 95 C

Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V

Input voltage ...........–1.0 V to +4.5 V and VIN < VDD + 1.0 V

DC voltage applied to outputs

in High-Z state ....................................–0.5 V to VDD + 0.5 V

Transient voltage (< 20 ns) on

any pin to ground potential .................–2.0 V to VDD + 2.0 V

Package power dissipation

capability (TA = 25 °C) ................ ................. ................1.0 W

Surface mount lead soldering

temperature (3 seconds) ......................................... +260 C

DC output current (1 output at a time, 1s duration) ....15 mA

Electrostatic Discharge Vo ltage

Human Body Model (JEDEC Std JESD22-A114-B) .............. 4 kV

Charged Device Model (JEDEC Std JESD22-C101-A) ..... 1.25 kV

Machine Model (JEDEC Std JESD22-A115-A)......................250 V

Latch-up current ....................................................> 140 mA

Operating Range

Range Ambient Temperature (TA) VDD

Industrial –40 C to +85 C 2.0 V to 3.6 V

DC Electrical Characteristics

Over the Operating Range

Parameter Description Test Condition s Min Typ[3] Max Unit

VDD Power supply 2.0 3.3 3.6 V

IDD VDD supply current SCK toggling

between

VDD – 0.2 V and VSS,

other inputs

VSS or VDD – 0.2 V.

SO = Open

fSCK = 1 MHz; – 0.13 0.30 mA

fSCK = 40 MHz; – 1.4 3 mA

ISB VDD standby current CS = VDD. All other input s VSS or VDD. – 100 250 A

IZZ Sleep mode current CS = VDD.

All other inputs VSS or

VDD.

TA = 25 C–35A

TA = 85 C––8A

ILI Input leakage current VSS < VIN < VDD ––±1A

ILO Output leakage current VSS < VOUT < VDD ––±1A

VIH Input HIGH vol tage 0.7 × VDD –V

DD + 0.3 V

VIL Input LOW voltage – 0.3 – 0.3 × VDD V

VOH1 Output HIGH voltage IOH = –1 mA, VDD = 2.7 V. 2.4 – – V

VOH2 Output HIGH voltage IOH = –100 AV

DD – 0.2 – – V

VOL1 Output LOW voltage IOL = 2 mA, VDD = 2.7 V – – 0.4 V

VOL2 Output LOW voltage IOL = 150 A––0.2V

Note

3. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.

FM25V20

Document Number: 001-84500 Rev. *G Page 14 of 24

AC Test Conditions

Input pulse levels .................................10% and 90% of VDD

Input rise and fall times ................................................... 3 ns

Input and output timing reference levels ................0.5 × VDD

Output load capacitance ..............................................30 pF

Data Retention and Endurance

Parameter Description Test condition Min Max Unit

TDR Dat a re tention TA = 85 C10–Years

TA = 75 C38–

TA = 65 C 151 –

NVCEndurance Over operating temperature 1014 – Cycles

Capacitance

Parameter [4] Description Test Conditions Max Unit

COOutput pin capacitance (SO) TA = 25 C, f = 1 MHz, VDD = VDD(typ) 8 pF

CIInput pin capacitance 6pF

Thermal Resist ance

Parameter Description Test Conditions 8-pin SOIC 8-pin TDFN Unit

JA Thermal resistance

(junction to ambient) Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA / JESD51.

114 17 C/W

JC Thermal resistance

(junction to case) 40 11 C/W

Note

4. This parameter is characterized and not 100% tested.

FM25V20

Document Number: 001-84500 Rev. *G Page 15 of 24

AC Switching Characteristics

Over the Operating Range

Parameters [5]

Description VDD = 2. 0 V to 2.7 V VDD = 2.7 V to 3.6 V Unit

Cypress

Parameter Alt.

Parameter Min Max Min Max

fSCK –SCK clock frequency 025 040 MHz

tCH –Clock HIGH time 18 –11 –ns

tCL –Clock LOW time 18 –11 –ns

tCSU tCSS Chip select setup 12 –10 –ns

tCSH tCSH Chip select hold 12 –10 –ns

tOD[6, 7] tHZCS Output disable time –20 –12 ns

tODV tCO Output data valid time –16 – 9 ns

tOH –Output hold time 0 – 0 – ns

tD–Deselect time 60 –40 –ns

tR[8, 9] –Data in rise time –50 –50 ns

tF[8, 9] –Data in fall time –50 –50 ns

tSU tSD Data setup time 8 – 5 – ns

tHtHD Data hold time 8 – 5 – ns

tHS tSH HOLD setup time 12 –10 –ns

tHH tHH HOLD hold time 12 –10 –ns

tHZ[6, 7] tHHZ HOLD LOW to HI-Z –25 –20 ns

tLZ[7] tHLZ HOLD HIGH to data active –25 –20 ns

Notes

5. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of

the specified IOL/IOH and 30 pF load capacitance shown in AC Test Conditions on page 14.

6. tOD and tHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state

7. This parameter is characterized and not 100% test ed.

8. Rise and fall times measured between 10% and 90% of waveform.

9. These parameters are guaranteed by design and are not tested.

FM25V20

Document Number: 001-84500 Rev. *G Page 16 of 24

Figure 17. Synchronous Data Timing (Mode 0)

Figure 18. HOLD Timing

HI-Z

VALID IN

HI-Z

SCK

tCL

tCH

tCSU

tSU tH

tODV tOH

tCSH

tOD

VALID IN VALID IN

SCK

HOLD

tHS

tHZ tLZ

tHH

tHS

tHH

tSU

VALID IN VALID IN

FM25V20

Document Number: 001-84500 Rev. *G Page 17 of 24

Power Cycle Timing

Over the Operating Range

Parameter Description Min Max Unit

tPU Power-up VDD(min) to first access (CS LOW) 1 – ms

tPD Last access (CS HIGH) to power-down (VDD(min)) 0 – µs

tVR [10] VDD power-up ramp rate 50 –µs/V

tVF [10] VDD power-down ramp rate 100 –µs/V

tREC [11] Recovery time from sleep mode –450 µs

Figure 19. Power Cycle Timing

tPU

tVR tVF

VDD

VDD(min)

tPD

VDD(min)

Notes

10.Slope measured at any point on the VDD waveform.

11. Gua r a nteed by design. Refe r to Figure 15 for sleep mode recovery timing.

FM25V20

Document Number: 001-84500 Rev. *G Page 18 of 24

Ordering Code Definitions

Ordering Information

Ordering Code Package

Diagram Package Type Operating

Range

FM25V20-G 001-85261 8-pin SOIC Industrial

FM25V20-GTR 001-85261 8-pin SOIC

FM25V20-DG 001-85579 8-pin TDFN

FM25V20-DGTR 001-85579 8-pin TDFN

All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.

Option:

blank = Standard; TR = Tape and Reel

Package Type:

G = 8-pin SOIC; DG = 8-pin TDFN

Density: 20 = 2-Mbit

Voltage: V = 2.0 V to 3.6 V

SPI F-RAM

Cypress

25FM V 20 - G TR

FM25V20

Document Number: 001-84500 Rev. *G Page 19 of 24

Package Diagrams Figure 20. 8-pi n SOIC (208 Mils) Package Outline, 00 1-85261

001-85261 **

FM25V20

Document Number: 001-84500 Rev. *G Page 20 of 24

Figure 21. 8-pin DFN (5 mm × 6 mm × 0.75 mm) Package Outline, 001-85579

Package Diagrams (continued)

001-85579 *A

FM25V20

Document Number: 001-84500 Rev. *G Page 21 of 24

Acronyms Document Conventions

Units of Measure

Acronym Description

CPHA Clock Phase

CPOL Clock Polarity

EEPROM Electrically Erasable Programmable Read-Only

Memory

EIA Electronic Industries Alliance

F-RAM Ferroelectric Random Access Memory

I/O Input/Output

JEDEC Joint Electron Devi ces Engineering Council

JESD JEDEC Standards

LSB Least Significant Bit

MSB Most Significant Bit

RoHS Restriction of Hazardous Substances

SPI Serial Peripheral Interface

SOIC Small Outline Integrated Circuit

TDFN Thin Dual Flat No-lead

Symbol Unit of Measure

°C degree Celsius

Hz hertz

kHz kilohertz

kkilohm

Mbit megabit

MHz megahertz

Amicroampere

Fmicrofarad

smicrosecond

mA milliampere

ms millisecond

ns nanosecond

ohm

%percent

pF picofarad

Vvolt

Wwatt

FM25V20

Document Number: 001-84500 Rev. *G Page 22 of 24

Document History Page

Document Title: FM25V20, 2-Mbit (256 K × 8) Serial (SPI) F-RAM

Document Number: 001-84500

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

** 3869802 GVCH 01/15/13 New spec.

*A 3938799 GVCH 05/08/13 Removed PDIP package.

*B 4123023 GVCH 09/20/2013 Converted source from word file to frame maker file.

Updated AC Switching Characteristics:

Changed minimum value of tCH parameter from 20 ns to 18 ns for “VDD = 2.0 V

to 2.7 V”.

Changed minimum value of tCL p arameter from 20 ns to 18 ns for “VDD = 2.0 V

to 2.7 V”.

Changed maximum value of tODV parameter from 18 ns to 16 ns for

“VDD = 2.0 V to 2.7 V”.

*C 4136685 GVCH 10/01/2013 Updated Pin Definitions:

Updated description of WP and HOLD pins (Added additional information “This

pin must be tied to VDD if not used”.

Updated description of VDD and VSS pins for clarity.

Updated Memory Operation:

Updated Sleep Mode:

Updated Figure 15 (Adde d tREC timing).

Updated Power Cycle Timing:

Changed description o f tVR parameter from “VDD rise time” to “VDD power-up

slew rate”.

Changed description of tVF parameter from “VDD fall time” to “VDD power-down

slew rate”.

FM25V20

Document Number: 001-84500 Rev. *G Page 23 of 24

*D 4223057 GVCH 01/23/2014 Changed status from Preliminary to Final.

Updated Figure 2

Updated Device ID:

Updated Table 6:

Changed Device ID (9 bytes) from 7F7F7F7F7F7FC20025h to

7F7F7F7F7F7FC22500h.

Updated DC El ectrical Characteristics:

Updated Test Conditions of ILI parameter (Removed VSS < VOUT < VDD).

Updated Test Conditions of ILO parameter (Removed VSS < VIN < VDD).

Updated Data Retention and Endura nce :

Changed minimum value of TDR parameter from 37 years to 38 years at Test

Condition “75 C”.

Changed minimum value of TDR parameter from 145 years to 151 years at Test

Condition “85 C”.

Updated Power Cycle Timing:

Changed description of tVR parameter from “VDD power-up slew rate” to “VDD

power-up ramp rate”.

Changed description of tVF parameter from “VDD power-down slew rate” to

“VDD power-down ramp rate”.

Updated Package Diagrams:

Updated Figure 21.

Completing Sunset Review.

*E 4462384 GVCH 07/31/2014 Updated Package Diagrams:

spec 001-85579 – Changed revision fro m ** to *A.

*F 4563141 GVCH 11/06/2014 Added related documentation hyperlink in page 1.

*G 4784456 GVCH 06/02/2015 Obsolete document.

Document History Page (continued)

Document Title: FM25V20, 2-Mbit (256 K × 8) Serial (SPI) F-RAM

Document Number: 001-84500

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

Document Number: 001-84500 Rev. *G Revised June 2, 2015 Page 24 of 24

All products and company names mentioned in this document may be the trademarks of their respective holders.

FM25V20

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre s s pro d ucts ar e not war ran t ed no r int end ed to be used fo r

medical, life supp or t, l if e savin g, cr it ical control or safety ap pl i cat ions, unless pursuan t to a n exp re ss wr itten agreement with Cypress. Furthermore, Cyp ress doe s not author i ze its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (United States and fore ign),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjuncti on with a Cypress

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except as specified above is prohibited wi thout

the express written perm ission of Cypres s.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABI LITY AND FITNESS FOR A PA RTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials de scribed herei n. Cypress d oes not

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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