3.0 V to 5.5 V, 12 kV IEC ESD Protected, 500 kbps/50 Mbps RS-485 Transceivers ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E FUNCTIONAL BLOCK DIAGRAMS TIA/EIA RS-485 compliant over full supply range 3.0 V to 5.5 V operating voltage range on VCC 1.62 V to 5.5 V VIO logic supply option available ESD protection on the bus pins IEC 61000-4-2 12 kV contact discharge IEC 61000-4-2 12 kV air discharge HBM: 30 kV Full hot swap support (glitch free power-up/power-down) High speed 50 Mbps data rate (ADM3065E/ADM3066E/ ADM3067E/ADM3068E) Low speed 500 kbps data rate for long cables (ADM3061E/ ADM3062E/ADM3063E) Full receiver short-circuit, open circuit, and bus idle fail-safe Extended temperature range up to 125C PROFIBUS compliant at VCC 4.5 V Half duplex and full duplex models available Allows connection of up to 128 transceivers onto the bus Space-saving package options 10-lead, 3 mm x 3 mm LFCSP 8-lead and 10-lead, 3 mm x 3 mm MSOP 8-lead and 14-lead, narrow body SOIC VCC R RO RE A B DE D DI ADM3061E/ADM3065E GND Figure 1. ADM3061E/ADM3065E Functional Block Diagram VCC A R RO B RE DE DI Z D Y ADM3063E/ADM3067E GND APPLICATIONS 14666-001 FEATURES 14666-103 Data Sheet Figure 2. ADM3063E/ADM3067E Functional Block Diagram Industrial fieldbuses Process control Building automation PROFIBUS networks Motor control servo drives and encoders VCC VIO R RO RE A LEVEL TRANSLATOR B DE D DI 14666-002 ADM3062E/ADM3066E GND Figure 3. ADM3062E/ADM3066E Functional Block Diagram VCC VIO R RO A B RE LEVEL TRANSLATOR DE Y D Z ADM3068E GND 14666-104 DI Figure 4. ADM3068E Functional Block Diagram Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 IEC ESD Protected RS-485 ....................................................... 21 Applications ....................................................................................... 1 High Driver Differential Output Voltage ................................ 21 Functional Block Diagrams ............................................................. 1 IEC 61000-4-2 ESD Protection ................................................ 21 Revision History ............................................................................... 2 Truth Tables................................................................................. 22 General Description ......................................................................... 4 Receiver Fail-Safe ....................................................................... 22 Specifications..................................................................................... 5 Hot Swap Capability................................................................... 22 Timing Specifications .................................................................. 7 128 Transceivers on the Bus ...................................................... 22 Absolute Maximum Ratings.......................................................... 11 Driver Output Protection .......................................................... 22 Thermal Resistance .................................................................... 11 Applications Information .............................................................. 23 ESD Caution ................................................................................ 11 Isolated High Speed RS-485 Node ........................................... 24 Pin Configurations and Function Descriptions ......................... 12 Outline Dimensions ....................................................................... 25 Typical Performance Characteristics ........................................... 16 Ordering Guide .......................................................................... 27 Test Circuits ..................................................................................... 20 Theory of Operation ...................................................................... 21 REVISION HISTORY 6/2019--Rev. E to Rev. F Added ADM3068E ............................................................. Universal Added Figure 2; Renumbered Sequentially .................................. 1 Changes to Features Section and Figure 4..................................... 1 Changes to Table 1 Title ................................................................... 4 Changes to Table 2 ............................................................................ 5 Changes to ADM3061E/ADM3062E/ADM3063E Section and Table 3 ................................................................................................ 7 Changes to ADM3065E/ADM3066E/ADM3067E/ADM3068E Section and Table 4 ........................................................................... 8 Changes to Figure 5 and Figure 7 ................................................... 9 Changes to Figure 8 ........................................................................ 10 Added Endnote 1 to Digital Input and Output Voltage (DE, RE, DI, and RO) Parameter, Table 5 .................................................... 11 Changes to Digital Input and Output Voltage (DE, RE, DI, and RO) Parameter, Table 5 .................................................................. 11 Changes to Table 8 .......................................................................... 13 Added Figure 14 and Table 10; Renumbered Sequentially ....... 15 Changes to Figure 19 Caption....................................................... 16 Changes to Figure 43 and Figure 44 ............................................. 20 Changes to Isolated High Speed RS-485 Node Section ............. 24 Changes to Ordering Guide .......................................................... 27 4/2019--Rev. D to Rev. E Added ADM3063E ............................................................. Universal Change to Features Section ............................................................. 1 Changes to Figure 3 .......................................................................... 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 5 Added Endnote 1, Table 2; Renumbered Sequentially ................ 5 Change to Table 7 ........................................................................... 11 Changes to Table 8 .......................................................................... 12 Changes to Figure 12 and Table 9 ................................................. 13 Changes to Figure 14, Figure 15, Figure 16, and Figure 18 Captions ........................................................................................... 14 Changes to Figure 19, Figure 20, Figure 23, and Figure 24 Captions ........................................................................................... 15 Change to Figure 25 Caption ........................................................ 14 Changes to Figure 39...................................................................... 18 Changes to IEC ESD Protected RS-485 Section ......................... 19 Changes to Truth Tables Section, Table 11, Table 12, and Receiver Fail-Safe Section ............................................................. 20 Added Table 10; Renumbered Sequentially ................................ 20 Changes to Isolated High Speed RS-485 Node Section and Figure 47 .......................................................................................... 22 Changes to Ordering Guide ................................................................... 25 3/2019--Rev. C to Rev. D Added ADM3067E and 14-Lead SOIC_N, R-14 ........... Universal Changes to Feature Section ...................................................................... 1 Added Figure 3; Renumbered Sequentially .......................................... 1 Moved Table 1 to ........................................................................................ 4 Changes to Table 2 ..................................................................................... 5 Changes to ADM3065E/ADM3066E/ADM3067E Section .............. 7 Change to Pin 3, Description Column, Table 7 ................................. 11 Changes to Figure 10, Figure 11, and Table 8 ..................................... 12 Added Figure 12 and Table 9; Renumbered Sequentially ................ 13 Changes to Figure 14 ............................................................................... 14 Moved Test Circuits to ............................................................................ 18 Changes to Table 10 and Table 11 ......................................................... 20 Updated Outline Dimensions................................................................ 26 Changes to Ordering Guide ................................................................... 27 1/2018--Rev. B to Rev. C Added ADM3062E ............................................................. Universal Changes to Figure 2 and Table 1 ............................................................. 1 Rev. F | Page 2 of 28 Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Changes to ADM3061E/ADM3062E Timing Specifications Section and Figure 3 ...................................................................................6 Changes to Figure 5 and Figure 6..............................................................7 Changes to Figure 9 and Figure 10 ........................................................ 11 Changes to Figure 16 and Figure 17 ...................................................... 12 Changes to Figure 44 ................................................................................. 21 Changes to Figure 45 ................................................................................. 22 Changes to Ordering Guide .................................................................... 25 Changed High Speed IEC ESD Protected RS-485 Section to IEC ESD Protected RS-485 Section ................................................................17 Changes to IEC ESD Protected RS-485 Section .................................17 Added Endnote 4, Table 9.........................................................................18 Changes to Table 10 ...................................................................................18 Changes to Figure 44 .................................................................................21 Changes to Figure 45 .................................................................................22 Changes to Ordering Guide ........................................................... 25 12/2017--Rev. A to Rev. B Added ADM3061E............................................................. Universal Changes to Product Title, Features Section, Figure 1, and Table 1 ...1 Changes to General Description Section ....................................... 3 Changes to Table 2 ............................................................................ 4 Added ADM3061E Timing Specification Section and Table 3; Renumbered Sequentially ................................................................ 6 Moved Figure 3 .................................................................................. 6 Moved Figure 4, Figure 5, and Figure 6.......................................... 7 Changes to ADM3065E/ADM3066E Timing Specification Section Title ....................................................................................... 8 Added 10-Lead MSOP Parameter and 10-Lead LFCSP Parameter, Table 5.................................................................................................. 9 Changes to Operating Temperature Range Parameter, Table 5 and Table 6 ......................................................................................... 9 Changes to Figure 7, Figure 8, and Table 7 .....................................10 Changes to Table 8 ..........................................................................11 Changes to Figure 11 ......................................................................12 Added Figure 23; Renumbered Sequentially ...............................13 Added Figure 24, Figure 25, Figure 26, Figure 27, and Figure 28 .. 14 5/2017--Rev. 0 to Rev. A Added ADM3066E............................................................. Universal Changes to Features Section, Figure 1, and Table 1...................... 1 Added Figure 2; Renumbered Sequentially ................................... 1 Moved General Description Section .............................................. 3 Changes to General Description Section ....................................... 3 Changes to Specifications Section and Table 2 ............................. 4 Changes to Timing Specifications Section and Figure 3 ............. 5 Changes to Figure 4, Figure 5, and Figure 6 .................................. 6 Added VIO to GND Parameter, Table 4 .......................................... 7 Changes to Thermal Resistance Section and Table 5 ................... 7 Added Figure 8 .................................................................................. 8 Changes to Table 6 ............................................................................ 8 Added Figure 9 and Figure 10 ......................................................... 9 Added Table 7; Renumbered Sequentially ..................................... 9 Changes to Figure 14, Figure 16, and Figure 17 .......................... 10 Changes to Table 8 and Table 9 ..................................................... 15 Added Figure 42 and Figure 43 ..................................................... 20 Changes to Ordering Guide ........................................................... 21 3/2017--Revision 0: Initial Version Rev. F | Page 3 of 28 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E GENERAL DESCRIPTION The ADM3061E/ADM3062E/ADM3063E/ADM3065E/ ADM3066E/ADM3067E/ADM3068E are 3.0 V to 5.5 V, IEC electrostatic discharge (ESD) protected RS-485 transceivers, allowing the devices to withstand 12 kV contact discharges on the transceiver bus pins without latch-up or damage. The ADM3062E/ADM3066E/ADM3068E feature a VIO logic supply pin that allow a flexible digital interface capable of operating as low as 1.62 V. The ADM3065E/ADM3066E/ADM3067E/ADM3068E are suitable for high speed, 50 Mbps, bidirectional data communication on multipoint bus transmission lines. The ADM3061E/ ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ ADM3068E feature a 1/4 unit load input impedance that allows up to 128 transceivers on a bus. The ADM3061E/ADM3062E/ ADM3063E models offer all of the same features as the ADM3065E/ADM3066E/ADM3067E/ADM3068E models at a low 500 kbps data rate that is suitable for operation over long cable runs. The ADM3061E/ADM3062E/ADM3065E/ADM3066E are halfduplex RS-485 transceivers, fully compliant to the PROFIBUS(R) standard with increased 2.1 V bus differential voltage at VCC 4.5 V. The ADM3063E/ADM3067E/ADM3068E are full duplex RS-485 transceiver options. Data Sheet The RS-485 transceivers are available in a number of spacesaving packages, such as the 10-lead, 3 mm x 3 mm lead frame chip-scale package (LFCSP), the 8-lead or 10-lead, 3 mm x 3 mm mini small outline package (MSOP), and the 8-lead or 14-lead, narrow body standard small outline packages (SOIC_N). Models with operating temperature ranges of -40C to +125C and -40C to +85C are available. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. If a significant temperature increase is detected in the internal driver circuitry during fault conditions, this feature forces the driver output into a high impedance state. The ADM3061E/ADM3062E/ADM3063E/ADM3065E/ ADM3066E/ADM3067E/ADM3068E guarantee a logic high receiver output when the receiver inputs are shorted, open, or connected to a terminated transmission line with all drivers disabled. Table 1 presents an overview of the ADM3061E/ADM3062E/ ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E data rate capability across temperature, power supply, and package options. Refer to the Ordering Guide for model numbering. Table 1. Summary of the ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Operating Conditions--Data Rate Capability Across Temperature, Power Supply, and Package Maximum Data Rate1 50 Mbps 50 Mbps 50 Mbps 500 kbps 1 Maximum VCC (V) 5.5 5.5 3.6 5.5 Maximum Temperature -40C to +125C -40C to +105C -40C to +125C -40C to +125C Package Description 10-lead LFCSP 8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, and 14-lead SOIC_N 8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, and 14-lead SOIC_N 8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, 10-lead LFCSP, and 14-lead SOIC_N The ADM3065E/ADM3066E/ADM3067E/ADM3068E data input (DI) is transmitting 50 Mbps (or 500 kbps for the ADM3061E/ADM3062E/ADM3063E) clock data, and the ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E driver enable (DE) is enabled for 50% of the DI transmit time Rev. F | Page 4 of 28 Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E SPECIFICATIONS VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3066E/ADM3068E), TA = TMIN (-40C) to TMAX (+125C), unless otherwise noted. All typical specifications are at TA = 25C, VIO = VCC = 3.3 V, unless otherwise noted. Table 2. Parameter POWER SUPPLY No Load Supply Current Symbol Min Typ Max Unit Test Conditions/Comments ICC 7.5 7.5 4.5 172 mA mA mA mA DE = VIO 1, RE = 0 V DE = VIO, RE = VIO DE = 0 V, RE = 0 V Load resistance (RL) = 54 , DE = VIO, RE = 0 V (VCC 4.5 V) ADM3065E/ADM3066E/ADM3067E/ ADM3068E Supply Current, Data Rate = 50 Mbps ICC 3.5 3.5 3 107 ADM3061E/ADM3062E/ADM3063E Supply Current, Data Rate = 500 kbps ICC 67 100 75 165 mA mA RL = 54 , DE = VIO, RE = 0 V (VCC = 3.0 V) RL = 54 , DE = VIO, RE = 0 V (VCC 4.5 V) Supply Current in Shutdown Mode VIO Shutdown Current 2 ISHDN IIOSHDN 56 210 1 74 450 50 mA A A RL = 54 , DE = VIO, RE = 0 V (VCC = 3.0 V) DE = 0 V, RE = VIO DE = 0 V, RE = VIO DRIVER Differential Outputs Output Voltage, Loaded Change in Differential Input Voltage for Complementary Output States Common-Mode Output Voltage Change in Common Mode Voltage for Complementary Output States Output Short-Circuit Current ADM3063E/ADM3067E Output Leakage (Y, Z) |VOD2| |VOD2| |VOD2| |VOD2| |VOD3| 2.0 1.5 2.1 2.1 1.5 2.5 2.1 3.5 3 2.1 VCC VCC VCC VCC VCC V V V V V |VOD3| |VOD| 2.1 3 VCC 0.2 V V VCC 3.0 V, RL = 50 , see Figure 38 VCC 3.0 V, RL = 27 (RS-485), see Figure 38 VCC 4.5 V, RL = 50 , see Figure 38 VCC 4.5 V, RL = 27 (RS-485), see Figure 38 VCC 3.0 V, -7 V common-mode voltage (VCM) +12 V, see Figure 39 VCC 4.5 V, -7 V VCM +12 V, see Figure 39 RL = 27 or 50 , see Figure 38 1.6 3.0 0.2 V V RL = 27 or 50 , see Figure 38 RL = 27 or 50 , see Figure 38 +250 +100 mA A -7 V < output voltage (VOUT) < +12 V DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, input voltage (VIN) = 12 V DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = -7 V VOC |VOC| IOS IO -250 -100 Logic Inputs (DE, RE, DI) Input Voltage Low High Input Current VIL VIH II 0.67 x VIO -2 A 0.33 x VIO V V +2 A Rev. F | Page 5 of 28 DE, RE, DI, 1.62 V VIO 5.5 V DE, RE, DI, 1.62 V VIO 5.5 V DE, RE, DI, 1.62 V VIO 5.5 V, 0 V VIN VIO ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Parameter RECEIVER Differential Inputs Differential Input Threshold Voltage Input Voltage Hysteresis Input Current (A, B) Line Input Resistance Logic Outputs Output Voltage Low High Short-Circuit Current Three-State Output Leakage 1 2 3 Symbol Min Typ VTH VHYS II -125 -30 30 0.1 0.25 -0.1 96 RIN -200 -0.20 48 VOL VOH IOZR Max Data Sheet Unit Test Conditions/Comments mV mV mA mA k -7 V < VCM < +12 V -7 V < VCM < +12 V DE = 0 V, VCC = powered/unpowered, VIN = 12 V DE = 0 V, VCC = powered/unpowered, VIN = -7 V -7 V VCM +12 V 0.4 V 0.4 0.2 V V V V V mA A VIO = 3.6 V, output current (IOUT) = 2 mA, VID 3 -0.2 V VIO = 2.7 V, IOUT = 1 mA, VID -0.2 V2 VIO = 1.95 V, IOUT = +500 A, VID -0.2 V2 VIO = 3.0 V, IOUT = -2 mA, VID -0.03 V VIO = 2.3 V, IOUT = -1 mA, VID -0.03 V2 VIO = 1.65 V, IOUT = -500 A, VID -0.03 V2 VOUT = GND or VIO RO pin = 0 V or VIO 2.4 2.0 VIO - 0.2 85 2 VIO = VCC for ADM3061E/ADM3063E/ADM3065E/ADM3067E. ADM3062E/ADM3066E/ADM3068E only. VID is the receiver input differential voltage. Rev. F | Page 6 of 28 Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E TIMING SPECIFICATIONS ADM3061E/ADM3062E/ADM3063E VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E), TA = TMIN (-40C) to TMAX (+125C), unless otherwise noted. All typical specifications are at TA = 25C, VIO = VCC = 3.3 V, unless otherwise noted. Table 3. Parameter DRIVER Maximum Data Rate 1 Propagation Delay Typ Max Unit tDPLH, tDPHL 220 800 kbps ns Skew tDSKEW 5 100 ns Rise/Fall Times tDR, tDF 300 800 ns 100 100 350 600 550 550 1000 1000 2000 2000 2000 2000 ns ns ns ns ns ns tRPLH, tRPHL 200 kbps ns Skew/Pulse Width Distortion tRSKEW 50 ns Enable to Output High tRZH 10 50 ns Enable to Output Low tRZL 10 50 ns Disable Time from Low tRLZ 10 50 ns Disable Time from High tRHZ 10 50 ns Enable from Shutdown to High tRZH(SHDN) 3 2000 ns Enable from Shutdown to Low tRZL(SHDN)3 2000 ns Enable to Output High Enable to Output Low Disable Time from Low Disable Time from High Enable Time from Shutdown to High Enable Time from Shutdown to Low RECEIVER Maximum Data Rate Propagation Delay TIME TO SHUTDOWN Symbol Min 500 120 tDZH tDZL tDLZ tDHZ tDZH(SHDN) 2 tDZL(SHDN)2 500 tSHDN 4 40 Test Conditions/Comments RLDIFF capacitor = 54 , CL1 capacitor = CL2 capacitor = 100 pF, see Figure 5 and Figure 40 RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 5 and Figure 40 RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 5 and Figure 40 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 CL = 15 pF, |VID| 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42 CL = 15 pF, |VID| 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42 RL = 1 k, CL = 15 pF, |VID| 1.5 V, DE high, see Figure 8 and Figure 44 RL = 1 k, CL = 15 pF, |VID| 1.5 V, DE high, see Figure 8 and Figure 44 RL = 1 k, CL = 15 pF, |VID| 1.5 V, see Figure 8 and Figure 44 RL = 1 k, CL = 15 pF, |VID| 1.5 V, see Figure 8 and Figure 44 RL = 1 k, CL = 15 pF, |VID| 1.5 V, see Figure 8 and Figure 43 RL = 1 k, CL = 15 pF, |VID| 1.5 V, see Figure 8 and Figure 43 ns Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:0.5:1. tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. RE = VCC for this condition. 3 tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when RE changes from VCC to 0 V. DE = 0 V for this condition. 4 Minimum time required to put the device into shutdown: DE and RE must be disabled for more than 40 ns for the device to go into shutdown. 1 2 Rev. F | Page 7 of 28 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet ADM3065E/ADM3066E/ADM3067E/ADM3068E VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3066E/ADM3068E), TA = TMIN (-40C) to TMAX (+125C), unless otherwise noted. All typical specifications are at TA = 25C, VIO = VCC = 3.3 V, unless otherwise noted. Table 4. Parameter DRIVER Maximum Data Rate 1 Propagation Delay Typ Max Unit tDPLH, tDPHL 9 15 Mbps ns Skew tDSKEW 1 2 ns Rise/Fall Times tDR, tDF 4 6.7 ns tDZH tDZL tDLZ tDHZ tDZH(SHDN) 2 tDZL(SHDN)2 10 10 10 10 550 550 30 30 30 30 2000 2000 ns ns ns ns ns ns tRPLH, tRPHL 20 35 Mbps ns Skew/Pulse Width Distortion tRSKEW 1 3 ns Enable to Output High tRZH 10 35 ns Enable to Output Low tRZL 10 35 ns Disable Time from Low tRLZ 10 35 ns Disable Time from High tRHZ 10 35 ns Enable from Shutdown to High tRZH(SHDN) 3 450 2000 ns Enable from Shutdown to Low tRZL(SHDN)3 450 2000 ns Enable to Output High Enable to Output Low Disable Time from Low Disable Time from High Enable Time from Shutdown to High Enable Time from Shutdown to Low RECEIVER Maximum Data Rate Propagation Delay TIME TO SHUTDOWN Symbol Min 50 50 tSHDN 4 40 Test Conditions/Comments RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 5 and Figure 40 RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 5 and Figure 40 RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 5 and Figure 40 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 RL = 110 , CL = 50 pF, see Figure 6 and Figure 41 CL = 15 pF, |VID| 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42 CL = 15 pF, |VID| 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42 RL = 1 k, CL = 15 pF, |VID| 1.5 V, DE high, see Figure 8 and Figure 44 RL = 1 k, CL = 15 pF, |VID| 1.5 V, DE high, see Figure 8 and Figure 44 RL = 1 k, CL = 15 pF, |VID| 1.5 V, see Figure 8 and Figure 44 RL = 1 k, CL = 15 pF, |VID| 1.5 V, see Figure 8 and Figure 44 RL = 1 k, CL = 15 pF, |VID| 1.5 V, see Figure 8 and Figure 43 RL = 1 k, CL = 15 pF, |VID| 1.5 V, see Figure 8 and Figure 43 ns Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:1:1. tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. RE = VCC for this condition. 3 tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when RE changes from VCC to 0 V. DE = 0 V for this condition. 4 Minimum time required to put the device into shutdown: DE and RE must be disabled for more than 40 ns for the device to go into shutdown. 1 2 Rev. F | Page 8 of 28 Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Timing Diagrams VCC 1/2VCC 1/2VCC tSKEW = tDPLH - tDPHL tDPLH tDPHL 0V B, Z VOD 1/2VOD Y, A +VOD 90% POINT -VOD 90% POINT VOD = V(A) - V(B) VOD 10% POINT 10% POINT tDF tDR 14666-003 NOTES 1. VOD IS THE DIFFERENCE BETWEEN A AND B, WITH +VOD BEING THE MAXIMUM POINT OF VOD, AND -VOD BEING THE MINIMUM POINT OF VOD. 2. VCC = VIO FOR ADM3062E/ADM3066E/ADM3068E. Figure 5. Driver Propagation Delay Rise and Fall Timing Diagram VIO DE 1/2VIO 1/2VIO 0V tDZL tDLZ VCC 1/2 (VCC + VOL) A OR B tDZH VOL + 0.5V VOL tDHZ VOH - 0.5V A OR B 1/2VOH VOH 14666-004 0V NOTES 1. VIO = VCC FOR ADM3061E/ADM3063E/ADM3065E/ADM3067E 2. A = Y, B = Z FOR ADM3063E/ADM3067E/ADM3068E Figure 6. Driver Enable and Disable Timing Diagram A-B 0V 0V tRPLH tRPHL VOH 1/2VCC 1/2VCC tRSKEW = |tRPLH - tRPHL | NOTES 1. VCC = VIO FOR ADM3062E/ADM3066E/ADM3068E. Figure 7. Receiver Propagation Delay Timing Diagram Rev. F | Page 9 of 28 VOL 14666-005 RO ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E VCC RE 1/2VCC 1/2VCC 0V tRZL tRLZ VCC 1/2VCC RO OUTPUT LOW tRZH RO VOL + 0.5V tRHZ OUTPUT HIGH 1/2VCC VOL VOH VOH - 0.5V NOTES 1. VCC = VIO FOR ADM3062E/ADM3066E/ADM3068E. Figure 8. Receiver Enable and Disable Timing Diagram Rev. F | Page 10 of 28 14666-006 0V Data Sheet Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter VCC to GND VIO to GND Digital Input and Output Voltage (DE, RE, DI, and RO) Driver Output and Receiver Input Voltage Operating Temperature Ranges Storage Temperature Range Continuous Total Power Dissipation 8-Lead SOIC_N 8-Lead MSOP 10-Lead MSOP 10-Lead LFCSP 14-Lead SOIC_N Maximum Junction Temperature (TJ) Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) ESD on the Bus Pins (A, B, Y, Z) IEC 61000-4-2 Contact Discharge IEC 61000-4-2 Air Discharge 10 Positive and 10 Negative Discharges Three Positive or Three Negative Discharges ESD Human Body Model (HBM) On the Bus Pins (A, B, Y, Z) All Other Pins 1 Rating 6V -0.3 V to +6 V -0.3 V to VIO1 + 0.3 V -9 V to +14 V -40C to +85C -40C to +125C -65C to +150C 0.225 W 0.151 W 0.151 W 0.450 W 0.239 W 150C Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Table 6. Thermal Resistance Package Type R-8 RM-8 RM-10 R-14 CP-10-9 1 JC1 58.63 49.61 49.61 42.90 33.22 Unit C/W C/W C/W C/W C/W Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with no bias. See JEDEC JESD-51. ESD CAUTION 300C 215C 220C JA1 110.88 165.69 165.69 104.5 55.65 12 kV 12 kV 15 kV 30 kV 8 kV VIO = VCC on the ADM3061E/ADM3063E/ADM3065E/ADM3067E. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. F | Page 11 of 28 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet RE 2 DE 3 DI 4 ADM3061E/ ADM3065E TOP VIEW (Not to Scale) 8 VCC RO 1 7 B RE 2 6 A DE 3 5 GND 14666-007 RO 1 DI 4 ADM3061E/ ADM3065E TOP VIEW (Not to Scale) 8 VCC 7 B 6 A 5 GND 14666-008 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 10. ADM3061E/ADM3065E 8-Lead MSOP Pin Configuration Figure 9. ADM3061E/ADM3065E 8-Lead Narrow Body SOIC_N Pin Configuration Table 7. ADM3061E/ADM3065E Pin Function Descriptions Pin No. 1 Mnemonic RO 2 RE 3 DE 4 5 6 DI GND A 7 B 8 VCC Description Receiver Output Data. This output is high when (A - B) -30 mV and low when (A - B) -200 mV. This output is tristated when the receiver is disabled; that is, when RE is driven high. Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high disables the receiver. Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver output into a high impedance state. Transmit Data Input. Data to be transmitted by the driver is applied to this input. Ground. Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is put into a high impedance state to avoid overloading the bus. Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put into a high impedance state to avoid overloading the bus. 3.0 V to 5.5 V Power Supply. Adding a 0.1 F decoupling capacitor between the VCC pin and the GND pin is recommended. Rev. F | Page 12 of 28 VIO 1 RO 2 10 VCC DE 3 ADM3062E/ ADM3066E RE 4 TOP VIEW (Not to Scale) DI 5 9 B VIO 1 10 VCC RO 2 ADM3062E/ ADM3066E 9 B 8 A TOP VIEW (Not to Scale) 7 NIC 6 GND DE 3 8 A RE 4 7 NIC DI 5 6 GND NOTES 1. NIC = NO INTERNAL CONNECTION. THIS PIN IS NOT INTERNALLY CONNECTED. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. 1. NIC = NO INTERNAL CONNECTION. THIS PIN IS NOT INTERNALLY CONNECTED. 14666-010 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E 14666-009 Data Sheet Figure 12. ADM3062E/ADM3066E 10-Lead MSOP Pin Configuration Figure 11. ADM3062E/ADM3066E 10-Lead LFCSP Pin Configuration Table 8. ADM3066E/ADM3062E Pin Function Descriptions Pin No. 1 Mnemonic VIO 2 RO 3 DE 4 RE 5 6 7 8 DI GND NIC A 9 B 10 VCC EPAD Description 1.62 V to 5.5 V Logic Supply. Adding a 0.1 F decoupling capacitor between the VIO pin and the GND pin is recommended. Receiver Output Data. This output is high when (A - B) -30 mV and is low when (A - B) -200 mV. This output is tristated when the receiver is disabled; that is, when RE is driven high. Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver output into a high impedance state. Receiver Enable Input. This is an active low input. Driving this input low enables the receiver, and driving it high disables the receiver. Transmit Data Input. Data to be transmitted by the driver is applied to this input. Ground. No Internal Connection. This pin is not internally connected. Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is put into a high impedance state to avoid overloading the bus. Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put into a high impedance state to avoid overloading the bus. 3.0 V to 5.5 V Power Supply. Adding a 0.1 F decoupling capacitor between the VCC pin and the GND pin is recommended. Exposed Pad. The exposed pad must be connected to ground. Rev. F | Page 13 of 28 NIC 1 14 VCC RO 2 13 VCC 12 A RE 3 DE 4 ADM3063E/ ADM3067E DI 5 TOP VIEW (Not to Scale) 11 B 10 Z GND 6 9 Y GND 7 8 NIC NIC = NO INTERNAL CONNECTION. THIS PIN IS NOT INTERNALLY CONNECTED. Data Sheet 14666-111 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Figure 13. ADM3063E/ADM3067E 14-Lead SOIC Pin Configuration Table 9. ADM3063E/ADM3067E Pin Function Descriptions Pin No. 1, 8 2 Mnemonic NIC RO 3 RE 4 DE 5 6, 7 9 DI GND Y 10 Z 11 12 13, 14 B A VCC Description No Internal Connection. This pin is not internally connected. Receiver Output Data. This output is high when (A - B) -30 mV and is low when (A - B) -200 mV. This output is tristated when the receiver is disabled; that is, when RE is driven high. Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high disables the receiver. Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver output into a high impedance state. Transmit Data Input. Data to be transmitted by the driver is applied to this input. Ground. Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high impedance state to avoid overloading the bus. Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high impedance state to avoid overloading the bus. Inverting Receiver Input. Noninverting Receiver Input. 3.0 V to 5.5 V Power Supply. Adding a 0.1 F decoupling capacitor between the VCC pin and the GND pin is recommended. Rev. F | Page 14 of 28 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E VIO 1 14 VCC RO 2 13 NIC DE 3 RE 4 DI 5 10 Z GND 6 9 Y NIC 7 8 GND ADM3068E TOP VIEW (Not to Scale) 12 A 11 B NIC = NO INTERNAL CONNECTION. THIS PIN IS NOT INTERNALLY CONNECTED. 14666-114 Data Sheet Figure 14. ADM3068E 14-Lead SOIC Pin Configuration Table 10. ADM3068E Pin Function Descriptions Pin No. 1 Mnemonic VIO 2 RO 3 DE 4 RE 5 6, 8 7, 13 9 DI GND NIC Y 10 Z 11 12 14 B A VCC Description 1.62 V to 5.5 V Logic Supply. Adding a 0.1 F decoupling capacitor between the VIO pin and the GND pin is recommended. Receiver Output Data. This output is high when (A - B) -30 mV and is low when (A - B) -200 mV. This output is tristated when the receiver is disabled; that is, when RE is driven high. Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver output into a high impedance state. Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high disables the receiver. Transmit Data Input. Data to be transmitted by the driver is applied to this input. Ground. No Internal Connection. This pin is not internally connected. Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high impedance state to avoid overloading the bus. Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high impedance state to avoid overloading the bus. Inverting Receiver Input. Noninverting Receiver Input. 3.0 V to 5.5 V Power Supply. Adding a 0.1 F decoupling capacitor between the VCC pin and the GND pin is recommended. Rev. F | Page 15 of 28 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.12 350 0.10 VCC = 5.5V VCC = 4.5V VCC = 3.3V 300 SUPPLY CURRENT (ICC) (A) SHUTDOWN CURRENT (I SHDN ) (A) 400 250 200 150 100 VCC = 5.5V 0.08 VCC = 5.0V 0.06 VCC = 3.3V 0.04 0.02 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 0 14666-018 125 0 0.07 RL = 54 25 30 35 40 45 50 0.06 RL = 120 0.07 SUPPLY CURRENT (ICC) (A) 0.05 NO LOAD 0.04 0.03 0.02 0.06 0.05 VCC = 5.5V 0.04 VCC = 5.0V 0.03 0.02 VCC = 3.3V 0.01 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 0 14666-019 -25 125 0 5 10 15 20 25 30 35 40 45 50 DATA RATE (Mbps) 14666-022 SUPPLY CURRENT (ICC) (A) 20 0.08 0.01 Figure 19. Supply Current (ICC) vs. Data Rate with No Load Resistance, 50 Mbps Models Figure 16. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps, 50 Mbps Models, VCC = 3.3 V 0.12 0.10 VCC VCC VCC VCC RL = 54 0.10 SUPPLY CURRENT (ICC) (A) 0.08 SUPPLY CURRENT (ICC) (A) 15 DATA RATE (Mbps) 0.08 RL = 120 0.06 NO LOAD 0.04 0.02 = 3.3V, NO LOAD = 3.3V, 54 LOAD = 5V, NO LOAD = 5V, 54 LOAD 0.08 0.06 0.04 0.02 -35 -15 5 25 45 65 TEMPERATURE (C) 85 105 0 14666-020 0 -55 10 Figure 18. Supply Current (ICC) vs. Data Rate with 54 Load Resistance, 50 Mbps Models Figure 15. Shutdown Current (ISHDN) vs. Temperature 0 -40 5 125 Figure 17. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps, 50 Mbps Models, VCC = 5.0 V 0 50 100 150 200 250 300 DATA RATE (kbps) 350 400 450 500 14666-123 0 -40 14666-021 50 Figure 20. Supply Current (ICC) vs. Data Rate with 54 Load Resistance and No Load Resistance, 500 kbps Models Rev. F | Page 16 of 28 Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E 60 SUPPLY CURRENT (ICC) (mA) 50 VID 1 40 30 20 ROUT 10 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) CH1 1.0V B W CH2 1.0V B W A CH1 0V 14666-127 0 -55 14666-124 2 Figure 24. Receiver Propagation Delay (Oscilloscope Plot), Data Rate = 500 kbps, VID 1.5 V Figure 21. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps, 500 kbps Models, VCC = 3.0 V 140 DI 1 100 A 80 B 60 2 40 M1 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) 14666-125 0 -60 CH1 3.0V CH3 2.0V 240 220 200 180 160 140 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) Figure 23. Driver Differential Propagation Delay vs. Temperature, 500 kbps Models DRIVER DIFFERENTIAL PROPAGATION DELAY (ns) 260 14666-126 DRIVER DIFFERENTIAL PROPAGATION DELAY (ns) 280 tDPLH AT 5.5V tDPHL AT 5.5V tDPLH AT 3.0V tDPHL AT 3.0V W W CH2 2.0V M1 2.5V B A CH1 W 1.98V Figure 25. Driver Propagation Delay (Oscilloscope Plot), Data Rate = 500 kbps, 500 kbps Models Figure 22. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps, 500 kbps Models, VCC = 5.5 V 300 B B 14666-128 V OD 20 12 11 10 9 8 7 tDPHL , VCC = 3.0V tDPLH , VCC = 3.0V tDPHL , VCC = 5.5V tDPLH , VCC = 5.5V 6 5 4 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 14666-023 SUPPLY CURRENT (ICC) (mA) 120 Figure 26. Driver Differential Propagation Delay vs. Temperature, 50 Mbps Models Rev. F | Page 17 of 28 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet 0.04 DI DRIVER OUTPUT CURRENT (A) 1 VOD 0 -0.02 -0.04 -0.06 50 BW: 1.5G 50 BW: 1.5G 20ns/DIV 5.0GS/s 200ps/pt A C1 -0.10 -7 14666-024 C1 1.0V/DIV C2 2.0V/DIV 1.34V -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 DRIVER OUTPUT HIGH VOLTAGE (V) Figure 27. Driver Propagation Delay (Oscilloscope Plot), Data Rate = 50 Mbps, 50 Mbps models Figure 30. Driver Output Current vs. Driver Output High Voltage 0.10 0.04 VIO = VCC = 3.3 V 0.09 DRIVER OUTPUT CURRENT (A) 0.02 0 -0.02 -0.04 -0.06 VCC = 5.5V VCC = 4.5V VCC = 3.0V -0.08 -0.10 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0 14666-025 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V) Figure 28. Driver Output Current vs. Driver Differential Output Voltage 0 2 4 6 8 10 12 DRIVER OUTPUT LOW VOLTAGE (V) Figure 31. Driver Output Current vs. Driver Output Low Voltage 3.2 3.0 VID VCC = 4.5V 2.8 1 2.6 2.4 2.2 RO VCC = 3.0V 2.0 1.8 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 14666-026 1.4 -40 Figure 29. Driver Differential Output Voltage vs. Temperature C1 1.0V/DIV C2 1.0V/DIV 50 BW: 1.5G 50 BW: 1.5G 20ns/DIV 5.0GS/s 200ps/pt A C1 0.0V 14666-029 2 1.6 Figure 32. Receiver Propagation Delay at 50 Mbps, |VID| 1.5 V Rev. F | Page 18 of 28 14666-028 0.01 -0.12 DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V) 14666-027 -0.08 2 DRIVER OUTPUT CURRENT (A) VIO = VCC = 3.3 V 0.02 Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E 6.0 tRPLH 22 20 18 16 -40 -25 -10 5 35 50 20 65 TEMPERATURE (C) 80 95 110 125 5.6 5.4 5.2 5.0 -40 Figure 33. Receiver Propagation Delay vs. Temperature, 50 Mbps -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 14666-033 tRPHL 24 5.8 125 14666-034 RECEIVER OUTPUT HIGH VOLTAGE (V) 26 14666-030 RECEIVER PROPAGATION DELAY (ns) 28 Figure 36. Receiver Output High Voltage vs. Temperature 0.035 0.25 RECEIVER OUTPUT LOW VOLTAGE (V) RECEIVER OUTPUT CURRENT (A) VCC = 3.3V 0.030 0.025 0.020 0.015 0.010 0.005 0 0.5 1.0 1.5 2.0 2.5 3.0 RECEIVER OUTPUT LOW VOLTAGE (V) 14666-031 0 3.5 Figure 34. Receiver Output Current vs. Receiver Output Low Voltage (VCC = 3.3 V) VCC = 3.3V -0.010 -0.015 -0.020 -0.025 -0.030 -0.035 -0.040 1.0 1.5 2.0 2.5 3.0 RECEIVER OUTPUT HIGH VOLTAGE (V) 14666-032 RECEIVER OUTPUT CURRENT (A) -0.005 0.5 0.15 0.10 0.05 0 -40 -25 -10 5 35 50 65 20 TEMPERATURE (C) 80 95 110 Figure 37. Receiver Output Low Voltage vs. Temperature 0 0 0.20 3.5 Figure 35. Receiver Output Current vs. Receiver Output High Voltage (VCC = 3.3 V) Rev. F | Page 19 of 28 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet TEST CIRCUITS A RL INPUT GENERATOR VOC VOUT RE CL B 14666-015 RL VIN 14666-011 VOD2 DI RE = 0V Figure 38. Driver Voltage Measurements Figure 42. Receiver Propagation Delay/Skew 375 +1.5V VCC S1 VCM 60 RL -1.5V RE 14666-012 VOD3 DI 375 S2 VOUT CL 14666-016 RE IN NOTES 1. VCC = VIO FOR ADM3062E/ADM3066E/ADM3068E. Figure 39. Driver Voltage Measurements over Common-Mode Range Figure 43. Receiver Enable/Disable from Shutdown 14666-013 RLDIFF CL2 DI S1 D VCC Figure 40. Driver Propagation Delay A S2 VCC RL VOUT CL RL 0V OR VIO S2 S1 DE DE R B RE RE IN CL NOTES 1. VCC = VIO FOR ADM3062E/ADM3066E/ADM3068E. 14666-014 DE IN NOTES 1. VIO = VCC FOR ADM3061E/ADM3063E/ADM3065E/ADM3067E. Figure 44. Receiver Enable/Disable Figure 41. Driver Enable/Disable Rev. F | Page 20 of 28 14666-017 DI VCC VCC CL1 Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E THEORY OF OPERATION IEC ESD PROTECTED RS-485 IPEAK The ADM3065E/ADM3066E/ADM3067E/ADM3068E are 3.0 V to 5.5 V, 50 Mbps RS-485 transceivers with IEC 61000-4-2 Level 4 ESD protection on the bus pins. The ADM3061E/ADM3062E/ ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E can withstand up to 12 kV contact discharge on transceiver bus pins (A, B, Y, and Z) without latch-up or damage. The ADM3061E/ADM3062E/ADM3063E has the same robust IEC 61000-4-2 ESD protection as the ADM3065E/ADM3066E/ ADM3067E/ADM3068E models and operate at a lower, 500 kbps data rate. 30A 90% I30ns 16A 8A I60ns 30ns HIGH DRIVER DIFFERENTIAL OUTPUT VOLTAGE IEC 61000-4-2 ESD PROTECTION ESD is the sudden transfer of electrostatic charge between bodies at different potentials caused either by near contact or induced by an electric field. It has the characteristics of high current in a short time period. The primary purpose of the IEC 61000-4-2 test is to determine the immunity of systems to external ESD events outside the system during operation. IEC 61000-4-2 describes testing using two coupling methods: contact discharge and air discharge. Contact discharge implies a direct contact between the discharge gun and the equipment under test (EUT). During air discharge testing, the charged electrode of the discharge gun is moved toward the EUT until a discharge occurs as an arc across the air gap. The discharge gun does not make direct contact with the EUT. A number of factors affect the results and repeatability of the air discharge test, including humidity, temperature, barometric pressure, distance, and rate of approach to the EUT. This method is a more accurate representation of an actual ESD event but is not as repeatable. Therefore, contact discharge is the preferred test method. During testing, the data port is subjected to at least 10 positive and 10 negative single discharges. Selection of the test voltage is dependent on the system end environment. Figure 45 shows the 8 kV contact discharge current waveform as described in the IEC 61000-4-2 specification. Some of the key waveform parameters are rise times of less than 1 ns and pulse widths of approximately 60 ns. TIME tR = 0.7ns TO 1ns Figure 45. IEC 61000-4-2 ESD Waveform (8 kV) Figure 46 shows the 8 kV contact discharge current waveform from the IEC 61000-4-2 standard compared to the HBM ESD 8 kV waveform. Figure 46 shows that the two standards specify a different waveform shape and peak current. The peak current associated with an IEC 61000-4-2 8 kV pulse is 30 A, whereas the corresponding peak current for HBM ESD is more than five times less, at 5.33 A. The other difference is the rise time of the initial voltage spike, with the IEC 61000-4-2 ESD waveform having a much faster rise time of 1 ns, compared to the 10 ns associated with the HBM ESD waveform. The amount of power associated with an IEC ESD waveform is much greater than that of an HBM ESD waveform. The HBM ESD standard requires the EUT to be subjected to three positive and three negative discharges, whereas the IEC ESD standard requires 10 positive and 10 negative discharge tests. The ADM3061E/ADM3062E/ADM3063E/ADM3065E/ ADM3066E/ADM3067E/ADM3068E with IEC 61000-4-2 ESD ratings is better suited for operation in harsh environments compared to other RS-485 transceivers that state varying levels of HBM ESD protection. IPEAK 30A 90% IEC 61000-4-2 ESD 8kV I30ns 16A I60ns 8A 5.33A HBM ESD 8kV 10% 10ns 30ns 60ns TIME tR = 0.7ns TO 1ns Figure 46. IEC 61000-4-2 ESD Waveform 8 kV Compared to HBM ESD Waveform 8 kV Rev. F | Page 21 of 28 14666-036 The ADM3061E/ADM3062E/ADM3063E/ADM3065E/ ADM3066E/ADM3067E/ADM3068E have characteristics that are optimized for use in PROFIBUS applications. When powered at VCC 4.5 V, the ADM3061E/ADM3062E/ADM3063E/ ADM3065E/ADM3066E/ADM3067E/ADM3068E driver output differential voltage meets or exceeds the PROFIBUS requirements of 2.1 V with a 54 load. 60ns 14666-035 10% ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E TRUTH TABLES Table 12 and Table 13 use the abbreviations shown in Table 11. Table 11. Truth Table Abbreviations Letter H I L X Z Description High level Indeterminate Low level Any state High impedance (off ) On On On Off On Off 1 On On On On Off Off RE X X X X X X Inputs DE DI H H L X X X H L X X X X A/Y Outputs B/Z H L Z I Z Z L H Z I Z Z For the ADM3061E, ADM3063E, ADM3065E, and ADM3067E, the VIO pin is not applicable. Table 13. Receiving Truth Table Supply Status VIO1 VCC On On On On On On On On On On Off Off On On Off Off On Off 1 Inputs A-B >-0.03 V <-0.2 V -0.2 V A - B -0.03 V Inputs open/shorted X X X X X If the (A - B) input is less than or equal to -200 mV, RO is logic low. In the case of a shorted, open circuit or terminated bus with all transmitters disabled, the receiver differential input voltage is pulled to 0 V, resulting in a logic high with a 30 mV minimum noise margin. HOT SWAP CAPABILITY Table 12. Transmitting Truth Table Supply Status VIO1 VCC Data Sheet RE L L L DE Outputs RO X X X H L I L H L H L X X X X X X X H Z I Z I I When a circuit board is inserted into a powered (or hot) backplane, differential disturbances to the data bus can lead to data errors. During this period, processor logic output drivers are high impedance and are unable to drive the DE and RE inputs of the RS-485 transceivers to a defined logic level. Leakage currents up to 10 A from the high impedance state of the processor logic drivers can cause standard complementary metal-oxide semiconductor (CMOS) enable inputs of a transceiver to drift to an incorrect logic level. Additionally, parasitic circuit board capacitance can cause coupling of VCC or GND to the enable inputs. Without the hot swap capability, these factors can improperly enable the driver or receiver of the transceiver. When VCC or VIO rises, an internal pull-down circuit holds DE low and RE high. After the initial power-up sequence, the pull-down circuit becomes transparent, resetting the hot swap tolerable input. 128 TRANSCEIVERS ON THE BUS The standard RS-485 receiver input impedance is 12 k (one unit load), and the standard driver can drive up to 32 unit loads. The ADM3061E/ADM3062E/ADM3063E/ADM3065E/ ADM3066E/ADM3067E/ADM3068E transceivers have a one fourth unit load receiver input impedance (48 k), allowing up to 128 transceivers to be connected in parallel on one communication line. Any combination of these devices and other RS-485 transceivers with a total of 32 unit loads or fewer can be connected to the line. DRIVER OUTPUT PROTECTION For the ADM3061E, ADM3063E, ADM3065E, and ADM3067E, the VIO pin is not applicable. RECEIVER FAIL-SAFE The ADM3061E/ADM3062E/ADM3063E/ADM3065E/ ADM3066E/ADM3067E/ADM3068E guarantee a logic high receiver output when the receiver inputs are shorted, open, or connected to a terminated transmission line with all drivers disabled. This receiver output is achieved by setting the receiver input threshold between -30 mV and -200 mV. If the differential receiver input voltage (A - B) is greater than or equal to -30 mV, the RO pin is logic high. The ADM3061E/ADM3062E/ADM3063E/ADM3065E/ ADM3066E/ADM3067E/ADM3068E feature two methods to prevent excessive output current and power dissipation caused by faults or by bus contention. Current-limit protection on the output stage provides immediate protection against short circuits over the whole common-mode voltage range. In addition, a thermal shutdown circuit forces the driver outputs into a high impedance state if the die temperature rises excessively. This circuitry is designed to disable the driver outputs when a die temperature of 150C is reached. As the device cools, the drivers are reenabled at a temperature of 140C. Rev. F | Page 22 of 28 Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E APPLICATIONS INFORMATION To minimize reflections, terminate the line at both ends with a termination resistor (the value of the termination resistor must be equal to the characteristic impedance of the cable used) and keep stub lengths off the main line as short as possible. The ADM3061E/ADM3065E transceiver is designed for bidirectional data communications on multipoint bus transmission lines. Figure 47 shows a typical network applications circuit. VCC VCC ADM3061E/ ADM3065E ADM3061E/ ADM3065E R R RO A RE RO A RT RE RT DE DE B D DI GND GND VCC VCC ADM3061E/ ADM3065E ADM3061E/ ADM3065E R RO R RO A RE DE DI D A RE DE B D B D DI GND GND NOTES 1. THE MAXIMUM NUMBER OF NODES IS 128. 2. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED. Figure 47. ADM3061E/ADM3065E Typical Half-Duplex RS-485 Communications Network Rev. F | Page 23 of 28 14666-037 DI B ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E ISOLATED HIGH SPEED RS-485 NODE switching elements to transfer power through the transformers. Take care during PCB layout to meet emissions standards. See the AN-0971 Application Note for PCB layout recommendations. Galvanic isolation, with reinforced insulation and 5 kV rms transient withstand voltage, can be added to the ADM3065E using Analog Devices, Inc., iCoupler(R) and isoPower(R) technology. The ADuM6401 provides the required quad channels of 5 kV rms signal isolation, operating at rates up to 25 Mbps, together with an integrated dc-to-dc converter. The ADuM6401 combines with the ADM3065E (shown in Figure 48) with the VISO pin configured for 3.3 V by connecting the VSEL pin to GNDISO and a 5 V supply connected to VDD1. Operation at 3.3 V ensures the ADM3065E remains within the load capability of ADuM6401 even at 25 Mbps. Galvanic isolation of the ADM3065E at the full data rate, up to 50 Mbps, can be implemented using the ADuM241D quadchannel digital isolator and the ADuM6028 isolated dc-to-dc converter, as shown in Figure 49. The ADuM6028 is an 8-pin device that contains a 300 mW dc-to-dc converter optimized to meet emissions standards on a 2-layer PCB using two ferrite beads. The ADuM241D operates at a data rate up to 150 Mbps, and offers the precise timing required to fully support the ADM3065E at 50 Mbps. The dc-to-dc converter in the ADuM6401 isoPower device provides regulated, isolated power to the ADM3065E (and the ADuM241D). These isoPower devices use high frequency VCC 5V 1 GND1 16 2 15 VIA 3 14 VIB 4 VIC 5 0.1F 12 VOD 6 VDDL GND1 11 7 10 8 9 VISO 0.1F ADM3065E GNDISO VOA RO FERRITE BEAD R RE A VOB VOC DE B VID DI VSEL D GNDISO GND Figure 48. Signal and Power Isolated 25 Mbps RS-485 Solution (Simplified Diagram--All Connections Not Shown) ADuM6028 PDIS 1 GND1 +5V VDDP 0.1F 8 7 2 3 GND1 PCS OSC RECT REG 6 5 4 VSEL GNDISO FERRITE BEAD VISO GNDISO 10F 10nF FERRITE BEAD +5V VDD1 0.1F ADuM241D GND1 VDD2 VCC 0.1F GND2 RO VIA ENCODE DECODE VIB ENCODE DECODE VOB RE DECODE VOC DE VIC VOD DISABLE 1, VE1 GND1 ENCODE DECODE ENCODE R VOA A B VID D DISABLE 2, VE2 GND2 DI ADM3065E GND Figure 49. Signal and Power Isolated 50 Mbps RS-485 Solution (Simplified Diagram--All Connections Not Shown) Rev. F | Page 24 of 28 14666-039 5V 13 4-CHANNEL iCOUPLER CORE ADuM6401 10nF 14666-038 V DD1 0.1F Data Sheet Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 5 1 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 50. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 3.20 3.00 2.80 8 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15 MAX 1.10 MAX 0.40 0.25 6 0 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 51. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. F | Page 25 of 28 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15 MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6 0 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 52. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters DETAIL A (JEDEC 95) 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIE W TOP VIEW PKG-004362 0.80 0.75 0.70 SEATING PLANE SIDE VIEW 0.30 0.25 0.20 0.05 MAX 0.02 NOM COPLANARITY 0.08 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF Figure 53. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters Rev. F | Page 26 of 28 0.20 MIN 02-07-2017-C PIN 1 INDEX AREA Data Sheet Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E 8.75 (0.3445) 8.55 (0.3366) 8 14 1 7 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 060606-A 4.00 (0.1575) 3.80 (0.1496) Figure 54. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 ADM3061EARZ ADM3061EARZ-R7 ADM3061EBRZ ADM3061EBRZ-R7 ADM3061EARMZ ADM3061EARMZ-R7 ADM3061EBRMZ ADM3061EBRMZ-R7 ADM3062EACPZ ADM3062EACPZ-R7 ADM3062EBCPZ ADM3062EBCPZ-R7 ADM3062EARMZ ADM3062EARMZ-R7 ADM3062EBRMZ ADM3062EBRMZ-R7 ADM3063EARZ ADM3063EARZ-R7 ADM3063EBRZ ADM3063EBRZ-R7 ADM3065EARZ ADM3065EARZ-R7 ADM3065EBRZ ADM3065EBRZ-R7 ADM3065EARMZ ADM3065EARMZ-R7 ADM3065EBRMZ ADM3065EBRMZ-R7 Temperature Range -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 10-Lead Lead Frame Chip Scale Package [LFCSP] 10-Lead Lead Frame Chip Scale Package [LFCSP] 10-Lead Lead Frame Chip Scale Package [LFCSP] 10-Lead Lead Frame Chip Scale Package [LFCSP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] Rev. F | Page 27 of 28 Package Option R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 CP-10-9 CP-10-9 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 R-14 R-14 R-14 R-14 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 Marking Code MBY MBY MC0 MC0 MCC MCC MCD MCD MC7 MC7 MC8 MC8 MC1 MC1 MC2 MC2 ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Model1 ADM3066EACPZ ADM3066EACPZ-R7 ADM3066EBCPZ ADM3066EBCPZ-R7 ADM3066EARMZ ADM3066EARMZ-R7 ADM3066EBRMZ ADM3066EBRMZ-R7 ADM3067EARZ ADM3067EARZ-R7 ADM3067EBRZ ADM3067EBRZ-R7 ADM3068EARZ ADM3068EARZ-R7 ADM3068EBRZ ADM3068EBRZ-R7 EVAL-ADM3061EEBZ EVAL-ADM3061EEB1Z EVAL-ADM3062EEBZ EVAL-ADM3062EEB1Z EVAL-ADM3063EEBZ EVAL-ADM3065EEBZ EVAL-ADM3065EEB1Z EVAL-ADM3066EEBZ EVAL-ADM3066EEB1Z EVAL-ADM3067EEBZ EVAL-ADM3068EEBZ 1 Temperature Range -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C Package Description 10-Lead Lead Frame Chip Scale Package [LFCSP] 10-Lead Lead Frame Chip Scale Package [LFCSP] 10-Lead Lead Frame Chip Scale Package [LFCSP] 10-Lead Lead Frame Chip Scale Package [LFCSP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 8-Lead SOIC_N Evaluation Board 8-Lead MSOP Evaluation Board 10-Lead MSOP Evaluation Board 10-Lead LFCSP Evaluation Board 14-Lead SOIC_N Evaluation Board 8-Lead SOIC_N Evaluation Board 8-Lead MSOP Evaluation Board 10-Lead MSOP Evaluation Board 10-Lead LFCSP Evaluation Board 14-Lead SOIC_N Evaluation Board 14-Lead SOIC_N Evaluation Board Z = RoHS Compliant Part. (c)2017-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14666-0-6/19(F) Rev. F | Page 28 of 28 Package Option CP-10-9 CP-10-9 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 Data Sheet Marking Code MC9 MC9 MCA MCA MC4 MC4 MC5 MC5