MT18HTS25672R>> - Micron - Datasheet.Directory

DDR2 SDRAM SORDIMM

MT18HTS25672RHZ – 2GB

Features

• 200-pin, small-outline registered dual in-line mem-

ory module (SORDIMM)

• Fast data transfer rates: PC2-4200, PC2-5300, or

PC2-6400

• 2GB (256 Meg x 72)

• Supports ECC error detection and correction

• VDD = 1.8V

• VDDSPD = 3.0–3.6V

• JEDEC-standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

• 4n-bit prefetch architecture

• Multiple internal device banks for concurrent opera-

tion

• Programmable CAS latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths (BL): 4 or 8

• Adjustable data-output drive strength

• 64ms, 8192-cycle refresh

• On-die termination (ODT)

• Serial presence detect (SPD) with EEPROM

• Phase-lock loop (PLL) to reduce system clock line

• Gold edge contacts

•Dual rank, using 2Gb TwinDie™ devices

• Halogen-free

• Combination Temp Sensor/EEPROM

Figure 1: 200-Pin SORDIMM (R/C B)

Module height: 30mm (1.181 in)

Options Marking

• Operating temperature

– Commercial (0°C ≤ TA ≤ +70°C) None

– Industrial (–40°C ≤ TA ≤ +85°C)1I

• Package

– 200-pin DIMM (Halogen-free) Z

• Frequency/CL2

– 2.5 @ CL = 5 (DDR2-800) -80E

– 2.5 @ CL = 6 (DDR2-800) -800

– 3.0ns @ CL = 5 (DDR2-667) -667

Notes: 1. Contact Micron for industrial temperature

module offerings.

2. CL = CAS (READ) latency; registered mode

will add one clock cycle to CL.

Table 1: Key Timing Parameters

Speed

Grade

Industry

Nomenclature

Data Rate (MT/s) tRCD

(ns)

tRP

(ns)

tRC

(ns)CL = 6 CL = 5 CL = 4 CL = 3

-80E PC2-6400 800 800 533 400 12.5 12.5 55

-800 PC2-6400 800 667 533 400 15 15 55

-667 PC2-5300 – 667 553 400 15 15 55

-53E PC2-4200 – – 553 400 15 15 55

-40E PC2-3200 – – 400 400 15 15 55

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Features

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 1GB

Refresh count 8K

Row address 16K A[13:0]

Device bank address 8 BA[2:0]

Device configuration 2Gb TwinDie (256 Meg x 8)

Column address 1K A[9:0]

Module rank address 2 S#[1:0]

Table 3: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT47H256M8,1 2Gb DDR2 TwinDie SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT18HTS25672RH(I)Z-80E__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5

MT18HTS25672RH(I)Z-800__ 2GB 256Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6

MT18HTS25672RH(I)Z-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Notes: 1. The data sheet for the base device can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MT18HTS25672RHZ-80EM1.

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Features

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.

Pin Assignments

Table 4: Pin Assignments

200-Pin SORDIMM Front 200-Pin SORDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 VREF 51 DQ18 101 VDD 151 VSS 2 VSS 52 VSS 102 A6 152 VSS

3 DQ0 53 DQ19 103 A5 153 DQS5# 4 DQ4 54 DQ28 104 A4 154 DM5

5 VSS 55 VSS 105 A3 155 DQS5 6 DQ5 56 DQ29 106 VDD 156 VSS

7 DQ1 57 DQ24 107 A2 157 VSS 8 VSS 58 VSS 108 A1 158 DQ46

9 DQS0# 59 DQ25 109 VDD 159 DQ42 10 DM0 60 DM3 110 A0 160 DQ47

11 DQS0 61 VSS 111 A10 161 DQ43 12 VSS 62 VSS 112 BA1 162 VSS

13 VSS 63 DQS3# 113 BA0 163 VSS 14 DQ6 64 DQ30 114 VDD 164 DQ52

15 DQ2 65 DQS3 115 RAS# 165 DQ48 16 DQ7 66 DQ31 116 WE# 166 DQ53

17 DQ3 67 VSS 117 VDD 167 DQ49 18 VSS 68 VSS 118 S0# 168 VSS

19 VSS 69 DQ26 119 CAS# 169 VSS 20 DQ12 70 CB4 120 ODT0 170 DM6

21 DQ8 71 DQ27 121 S1# 171 DQS6# 22 DQ13 72 CB5 122 A13 172 VSS

23 DQ9 73 VSS 123 VDD 173 DQS6 24 VSS 74 VSS 124 VDD 174 DQ54

25 VSS 75 CB0 125 ODT1 175 VSS 26 DM1 76 DM8 126 CK0 176 DQ55

27 DQS1# 77 CB1 127 NC 177 DQ50 28 VSS 78 VSS 128 CK0# 178 VSS

29 DQS1 79 VSS 129 DQ32 179 DQ51 30 DQ14 80 CB6 130 VSS 180 DQ60

31 VSS 81 DQS8# 131 VSS 181 VSS 32 DQ15 82 CB7 132 DQ36 182 DQ61

33 DQ10 83 DQS8 133 DQ33 183 DQ56 34 VSS 84 VSS 134 DQ37 184 VSS

35 DQ11 85 VSS 135 DQS4# 185 DQ57 36 DQ20 86 CB2 136 VSS 186 DM7

37 VSS 87 CKE0 137 DQS4 187 VSS 38 DQ21 88 CB3 138 DM4 188 DQ62

39 DQ16 89 CKE1 139 VSS 189 DQS7# 40 VSS 90 VSS 140 VSS 190 VSS

41 DQ17 91 EVENT# 141 DQ34 191 DQS7 42 RESET# 92 BA2 142 DQ38 192 DQ63

43 VSS 93 VDD 143 DQ35 193 DQ58 44 DM2 94 NC 144 DQ39 194 SDA

45 DQS2# 95 A12 145 VSS 195 VSS 46 VSS 96 A11 146 VSS 196 SCL

47 DQS2 97 A9 147 DQ40 197 DQ59 48 DQ22 98 VDD 148 DQ44 198 SA1

49 VSS 99 A7 149 DQ41 199 VDDSPD 50 DQ23 100 A8 150 DQ45 200 SA0

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Pin Assignments

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR2

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 5: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command. See the Pin Assignments Table for density-specific

addressing information.

BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA define which mode register (MR0, MR1,

MR2, and MR3) is loaded during the LOAD MODE command.

CKx,

CK#x

Input Clock: Differential clock inputs. All control, command, and address input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-

try and clocks on the DDR2 SDRAM.

DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH, along with that input data, during a write ac-

cess. Although DM pins are input-only, DM loading is designed to match that of the

DQ and DQS pins.

ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-

nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,

ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input

will be ignored if disabled via the LOAD MODE command.

Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This

signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.

S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command

decoder.

SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C

bus.

SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the

SPD EEPROM on the I2C bus.

CBx I/O Check bits. Used for system error detection and correction.

DQx I/O Data input/output: Bidirectional data bus.

DQSx,

DQS#x

I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-

troller. Output with read data; input with write data for source synchronous opera-

tion. DQS# is only used when differential data strobe mode is enabled via the LOAD

MODE command.

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Pin Descriptions

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 5: Pin Descriptions (Continued)

Symbol Type Description

SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on

the I2C bus.

RDQSx,

RDQS#x

Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD

MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS

is output with read data only and is ignored during write data. When RDQS is disa-

bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled

and differential data strobe mode is enabled.

Err_Out# Output

(open drain)

Parity error output: Parity error found on the command and address bus.

VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-

ule VDD.

VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V.

VREF Supply Reference voltage: VDD/2.

VSS Supply Ground.

NC – No connect: These pins are not connected on the module.

NF – No function: These pins are connected within the module, but provide no functional-

ity.

NU – Not used: These pins are not used in specific module configurations/operations.

RFU – Reserved for future use.

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Pin Descriptions

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.

Functional Block Diagram

Figure 2: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1b

DM CS# DQS DQS#

U1t

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

U5b

U5t

DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U12b

DM CS# DQS DQS#

U12t

DM CS# DQS DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U2b

DM CS# DQS DQS#

U2t

DM CS# DQS DQS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U11b

DM CS# DQS DQS#

U11t

DM CS# DQS DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U9b

U9t

DM CS# DQS DQS# DM CS# DQS DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

U6b

U6t

DM CS# DQS DQS# DM CS# DQS DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U8b

U8t

DM CS# DQS DQS# DM CS# DQS DQS#

DQS0#

DQS0

DM0

RS0#

RS1#

DQS1#

DQS1

DM1

DQS2#

DQS2

DM2

DQS3#

DQS3

DM3

DQS4#

DQS4

DM4

DQS7#

DQS7

DM7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

U10b

DM CS# DQS DQS#

U10t

DM CS# DQS DQS#

DQS8#

DQS8

DM8

Rank0 = U1b, U2b, U5b, U6b, U8b–U12b

Rank1 = U1t, U2t, U5t, U6t, U8t–U12t

S0#

S1#

BA[2:0]

A[13:0]

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

RESET#

RS0#: Rank0

RS1#: Rank1

RBA[2:0]: DDR2 SDRAM

RA[13:0]: DDR2 SDRAM

RRAS#: DDR2 SDRAM

RCAS#: DDR2 SDRAM

RWE#: DDR2 SDRAM

RCKE0: Rank0

RCKE1: Rank1

RODT0: Rank0

RODT1: Rank1

Temperature

sensor/

SPD EEPROM

A1 A2

SA0 SA1

SDA

SCL

EVT

EVENT# VSS

PLL

CK0

CK0#

DDR2 SDRAM 2X

RESET#

VREF

VSS

DDR2 SDRAM

VDD

VDDSPD Temperature sensor/

SPD EEPROM

DDR2 SDRAM

DQS5#

DQS5

DM5

DQS6#

DQS6

DM6

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Functional Block Diagram

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.

General Description

DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-

ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM

modules use DDR architecture to achieve high-speed operation. DDR2 architecture is

essentially a 4n-prefetch architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM

module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the

internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data

transfers at the I/O pins.

DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK

and CK# to capture commands, addresses, and control signals. Differential clocks and

data strobes ensure exceptional noise immunity for these signals and provide precise

crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is

transmitted externally, along with data, for use in data capture at the receiver. DQS is a

strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-

troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned

with data for WRITEs.

DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-

mands (address and control signals) are registered at every positive edge of CK. Input

data is registered on both edges of DQS, and output data is referenced to both edges of

DQS, as well as to both edges of CK.

Serial Presence-Detect EEPROM Operation

DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-

ule type and various SDRAM organizations and timing parameters. The remaining 128

bytes of storage are available for use by the customer. System READ/WRITE operations

between the master (system logic) and the slave EEPROM device occur via a standard

I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect

(WP) is connected to VSS, permanently disabling hardware write protection.

DDR2 SDRAM modules operate in registered mode, where the command/address input

signals are latched in the registers on the rising clock edge and sent to the DDR2

SDRAM devices on the following rising clock edge (data access is delayed by one clock

cycle). A phase-lock loop (PLL) on the module receives and redrives the differential

clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize

system and clock loading. PLL clock timing is defined by JEDEC specifications and en-

sured by use of the JEDEC clock reference board. Registered mode will add one clock

cycle to CL.

Temperature Sensor

An on-board temperature sensor provides the ability to monitor the module tempera-

ture along with monitoring alarms. Programmable registers can be used to specify tem-

perature events and critical boundaries. An EVENT# pin is used to signal when different

conditions occur based on how the registers are defined.

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

General Description

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.

Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in the device data sheet are not implied. Exposure to abso-

lute maximum rating conditions for extended periods may adversely affect reliability.

Table 6: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –0.5 2.3 V

VIN, VOUT Voltage on any pin relative to VSS –0.5 2.3 V

IIInput leakage current; Any input 0V ≤ VIN ≤

VDD; VREF input 0V ≤ VIN ≤ 0.95V; (All other

pins not under test = 0V)

Address inputs, RAS#, CAS#,

WE#, S#, CKE, ODT, BA

–5 5 µA

CK0, CK0# –250 250

DM –10 10

IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ;

DQ and ODT are disabled

DQ, DQS, DQS# –10 10 µA

IVREF VREF leakage current; VREF = valid VREF level –36 36 µA

TAModule ambient operating temperature Commercial 0 70 °C

Industrial –40 85 °C

TC1DDR2 SDRAM component operating tem-

perature2

Commercial 0 85 °C

Industrial –40 95 °C

Notes: 1. The refresh rate is required to double when TC exceeds 85°C.

2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-

able on Micron’s Web site.

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Electrical Specifications

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.

DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR2 component data sheets.

Component specifications are available on Micron's Web site. Module speed grades cor-

relate with component speed grades.

Table 7: Module and Component Speed Grades

DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade Component Speed Grade

-1GA -187E

-80E -25E

-800 -25

-667 -3

-53E -37E

-40E -5E

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level. Mi-

cron encourages designers to simulate the signal characteristics of the system's memo-

ry bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

DRAM Operating Conditions

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.

IDD Specifications

Table 8: DDR2 IDD Specifications and Conditions – 2GB (Die Revision H)

Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie(256 Meg x

8) component data sheet

Parameter

Combined

Symbol -80E -667 Units

Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC

(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

ICDD0 648 603 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL

= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =

tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data pattern is same as IDD4W

ICDD1 738 693 mA

Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is

LOW; Other control and address bus inputs are stable; Data bus inputs are float-

ing

ICDD2P 126 126 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-

puts are floating

ICDD2Q 279 279 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH,

S# is HIGH; Other control and address bus inputs are switching; Data bus inputs

are switching

ICDD2N 315 279 mA

Active power-down current: All device banks open; tCK = tCK

(IDD); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

Fast PDN

exit

MR[12] = 0

ICDD3P 243 198 mA

Slow PDN

exit

MR[12] = 1

153 153

Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS

MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are switch-

ing

ICDD3N 360 333 mA

Operating burst write current: All device banks open; Continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =

tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data bus inputs are switching

ICDD4W 1188 1098 mA

Operating burst read current: All device banks open; Continuous burst read,

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),

tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

ICDD4R 1143 1053 mA

Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) in-

terval; CKE is HIGH, S# is HIGH between valid commands; Other control and ad-

dress bus inputs are switching; Data bus inputs are switching

ICDD5 1368 1323 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address

bus inputs are floating; Data bus inputs are floating

ICDD6 126 126 mA

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

IDD Specifications

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 8: DDR2 IDD Specifications and Conditions – 2GB (Die Revision H) (Continued)

Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie(256 Meg x

8) component data sheet

Parameter

Combined

Symbol -80E -667 Units

Operating bank interleave read current: All device banks interleaving

reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK

(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is

HIGH between valid commands; Address bus inputs are stable during deselects;

Data bus inputs are switching

ICDD7 1953 1728 mA

Table 9: DDR2 IDD Specifications and Conditions – 2GB (Die Revision M)

Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie(256 Meg x

8) component data sheet

Parameter

Combined

Symbol -80E -667 Units

Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC

(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

ICDD0 720 675 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL

= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =

tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data pattern is same as IDD4W

ICDD1 810 764 mA

Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is

LOW; Other control and address bus inputs are stable; Data bus inputs are float-

ing

ICDD2P 180 180 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-

puts are floating

ICDD2Q 306 306 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH,

S# is HIGH; Other control and address bus inputs are switching; Data bus inputs

are switching

ICDD2N 387 351 mA

Active power-down current: All device banks open; tCK = tCK

(IDD); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

Fast PDN

exit

MR[12] = 0

ICDD3P 360 342 mA

Slow PDN

exit

MR[12] = 1

270 270

Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS

MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are switch-

ing

ICDD3N 432 405 mA

Operating burst write current: All device banks open; Continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =

tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data bus inputs are switching

ICDD4W 1260 1170 mA

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

IDD Specifications

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 9: DDR2 IDD Specifications and Conditions – 2GB (Die Revision M) (Continued)

Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie(256 Meg x

8) component data sheet

Parameter

Combined

Symbol -80E -667 Units

Operating burst read current: All device banks open; Continuous burst read,

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),

tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

ICDD4R 1215 1125 mA

Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) in-

terval; CKE is HIGH, S# is HIGH between valid commands; Other control and ad-

dress bus inputs are switching; Data bus inputs are switching

ICDD5 1530 1485 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address

bus inputs are floating; Data bus inputs are floating

ICDD6 126 126 mA

Operating bank interleave read current: All device banks interleaving

reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK

(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is

HIGH between valid commands; Address bus inputs are stable during deselects;

Data bus inputs are switching

ICDD7 2025 1800 mA

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

IDD Specifications

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 10: Register Specifications

SSTU32872 devices or equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level

input voltage

VIH(DC) Control, command,

address

SSTL_18 VREF(DC) + 125 VDDQ + 250 mV

DC low-level

input voltage

VIL(DC) Control, command,

address

SSTL_18 0 VREF(DC) - 125 mV

AC high-level

input voltage

VIH(AC) Control, command,

address

SSTL_18 VREF(DC) + 250 VDD mV

AC low-level

input voltage

VIL(AC) Control, command,

address

SSTL_18 0 VREF(DC) - 250 mV

Output high

voltage

VOH Parity output SSTL_18 1.2 – V

Output low voltage VOL Parity output SSTL_18 – 0.5 V

Input current IIAll pins VI = VDDQ or VSSQ –5 5 µA

Static standby IDD All pins RESET# = VSSQ (IO = 0) – 200 µA

Static operating IDD All pins RESET# = VSSQ; VI =

VIH(AC) or VIL(DC) IO = 0

– 80 mA

Dynamic operating

(clock tree)

IDDD N/A RESET# = VDD;

VI = VIH(AC) or VIL(AC),

IO = 0; CK and CK#

switching 50% duty cy-

cle

– Varies by

manufacturer

µA

Dynamic operating

(per each input)

IDDD N/A RESET# = VDD;

VI = VIH(AC) or VIL(AC),

IO = 0; CK and CK#

switching 50% duty cy-

cle; One data input

switching at tCK/2, 50%

duty cycle

– Varies by

manufacturer

µA

Input capacitance

(per device, per pin)

CIAll inputs except

RESET#

VI = VREF ±250mV;

VDDQ = 1.8V

2.5 3.5 pF

Input capacitance

(per device, per pin)

CIRESET# VI = VDDQ or VSSQ – Varies by

manufacturer

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 11: PLL Specifications

CUA845 device or JEDEC82-21 equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level

input voltage

VIH OE, OS, CK, CK# LVCMOS 0.65 × VDD – V

DC low-level

input voltage

VIL OE, OS, CK, CK# LVCMOS – 0.35 × VDD V

Input voltage (limits) VIN –0.3 VDD + 0.3 V

Input differential-pair

cross voltage

VIX Differential input (VDD/2) - 0.15 (VDD/2) + 0.15 V

Input differential volt-

age

VID(DC) Differential input 0.3 VDD + 0.4 V

Input differential volt-

age

VID(AC) Differential input 600 VDD + 0.4 V

Input current IIOE, OS, FBIN,

FBIN#

VI = VDD or VSS –10 10 µA

CK, CK# VI = VDD or VSS –250 250 µA

Output disabled cur-

rent

IODL OE = L, VODL = 100mV 100 – µA

Static supply current IDDLD CL = 0pf – 500 µA

Dynamic supply IDD N/A CK and CK# = 410 MHz,

all outputs open (not

connected to PCB)

– 300 mA

Input capacitance CIN Each input VI = VDD or VSS 2 3 pF

Table 12: PLL Clock Driver Timing Requirements and Switching Characteristics

Parameter Symbol Min Max Units

Stabilization time tL – 6.0 μs

Input clock slew rate slr(i) 1.0 4.0 V/ns

SSC modulation frequency – 30 33.0 kHz

SSC clock input frequency deviation – 0.0 –0.5 %

PLL loop bandwidth (–3dB from unity gain) – 2.0 – MHz

Note: 1. PLL timing and switching specifications are critical for proper operation of the DDR2

DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information

is available in JEDEC Standard JESD82.

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Temperature Sensor with Serial Presence-Detect EEPROM

The temperature sensor continuously monitors the module’s temperature and can be

read back at any time over the I2C bus shared with the SPD EEPROM.

Serial Presence-Detect

For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.

Table 13: Temperature Sensor with SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 3.0 3.6 V

Supply current: VDD = 3.3V IDD – 2.0 mA

Input high voltage: Logic 1; SCL, SDA VIH 1.45 VDDSPD + 1 V

Input low voltage: Logic 0; SCL, SDA VIL – 0.55 V

Output low voltage: IOUT = 2.1mA VOL – 0.4 V

Input current IIN –5.0 5.0 µA

Temperature sensing range – –40 125 °C

Temperature sensor accuracy (class B) – –1.0 1.0 °C

Table 14: Temperature Sensor and SPD EEPROM Serial Interface Timing

Parameter/Condition Symbol Min Max Units

Time bus must be free before a new transition can

start

tBUF 4.7 – µs

SDA fall time tF 20 300 ns

SDA rise time tR – 1000 ns

Data hold time tHD:DAT 200 900 ns

Start condition hold time tH:STA 4.0 – µs

Clock HIGH period tHIGH 4.0 50 µs

Clock LOW period tLOW 4.7 – µs

SCL clock frequency tSCL 10 100 kHz

Data setup time tSU:DAT 250 – ns

Start condition setup time tSU:STA 4.7 – µs

Stop condition setup time tSU:STO 4.0 – µs

EVENT# Pin

The temperature sensor also adds the EVENT# pin (open drain). Not used by the SPD

EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be

set up in the sensor’s configuration register.

EVENT# has three defined modes of operation: interrupt mode, compare mode, and

critical temperature mode. Event thresholds are programmed in the 0x01 register using

a hysteresis. The alarm window provides a comparison window, with upper and lower

limits set in the alarm upper boundary register and the alarm lower boundary register,

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.

respectively. When the alarm window is enabled, EVENT# will trigger whenever the

temperature is outside the MIN or MAX values set by the user.

The interrupt mode enables software to reset EVENT# after a critical temperature

threshold has been detected. Threshold points are set in the configuration register by

the user. This mode triggers the critical temperature limit and both the MIN and MAX of

the temperature window.

The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by

the user and only returns to the logic HIGH state when the temperature falls below the

programmed thresholds.

Critical temperature mode triggers EVENT# only when the temperature has exceeded

the programmed critical trip point. When the critical trip point has been reached, the

temperature sensor goes into comparator mode, and the critical EVENT# cannot be

cleared through software.

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Module Dimensions

Figure 3: 200-Pin DDR2 SORDIMM

3.8 (0.15)

MAX

Pin 1

67.75 (2.667)

67.45 (2.656)

20.0 (0.787)

TYP

1.8 (0.071)

(2X)

0.6 (0.024)

TYP

0.45 (0.018)

TYP

2.0 (0.079) R

(2X)

Pin 199

Pin 200 Pin 2

Front view

2.0 (0.079)

TYP

6.0 (0.236)

TYP

2.504 (63.6)

TYP

3.5 (0.138) TYP

30.15 (1.187)

29.85 (1.175)

Back view

1.1 (0.043)

0.9 (0.035)

47.4 (1.87)

TYP 11.4 (0.45)

TYP

4.2 (0.165)

TYP

0.5 (0.0197) R

16.25 (0.64)

TYP

1.0 (0.039)

TYP

10.0 (0.394)

TYP

1.0 (0.039) R

(2X)

U1 U2

U4 U5 U6

U7 U9 U10 U11 U12

45° 4X

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for ad-

ditional design dimensions.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Module Dimensions

PDF: 09005aef83f287c1

hts18c256x72rhz.pdf - Rev. B 4/14 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.