ISL76683AROZ-T7 - Intersil - Datasheet.Directory

Light-to-Digital Output Sensor with Gain Selection,

Interrupt Function and I2C Interface

ISL76683

The ISL76683 is an integrated light sensor with an internal

integrating ADC intended for automotive applications. The ADC

provides 16-bit resolution and is capable of rejecting 50Hz and

60Hz flicker caused by artificial light sources. The I2C interface

provides four user programmable lux sensitivity ranges for

optimized counts/lux in a variety of lighting conditions. In

addition, the I2C interface provides multi-function control of the

sensor and remote monitoring capabilities.

In normal operation, power consumption is less than 300µA.

Furthermore, a software power-down mode controlled via the I2C

interface reduces power consumption to less than 1µA.

The ISL76683 supports twin (upper & lower) user programmed

thresholds and provides a hardware interrupt that remains

asserted low until the host clears it via the I2C control interface.

Designed to operate on supplies from 2.5V to 3.3V, the ISL76683 is

qualified to AECQ100 and specified for operation over the -40°C to

+105°C (grade 2) ambient temperature range. To achieve this, the

ISL76683 is packaged in a special extended temperature clear

package.

Features

• Range select via I2C

- Range 1 = 0 lux to 1000 lux

- Range 2 = 0 lux to 4000 lux

- Range 3 = 0 lux to 16,000 lux

- Range 4 = 0 lux to 64,000 lux

• Human Eye Response (540nm Peak Sensitivity)

• Temperature Compensated

• 16-bit Resolution

• Adjustable Sensitivity: up to 65 Counts per Lux

• User-programmable Upper and Lower Threshold Interrupt

• Simple Output Code, Directly Proportional to Lux

•IR + UV Rejection

• 50Hz/60Hz Rejection

• 2.5V to 3.3V Supply

•6 Ld ODFN (2.1mmx2mm)

• Pb-free (RoHS compliant)

Applications

• Automotive Ambient Light Sensing

• Backlight Control

• Lighting Controls

VDD

REXT GND

SDA

SCL

COMMAND

INTEGRATING

ADC DATA

I2C

PHOTODIODE 1

PHOTODIODE 2

MUX

3 2

FOSC

IREF

COUNTER

216

MODE

GAIN/RANGE

EXT

SHDN

INT TIME

4INT

INTERRUPT

ISL76683

TIMING

INT

FIGURE 1. BLOCK DIAGRAM

September 5, 2012

FN7697.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL76683

2FN7697.3

September 5, 2012

Pin Configuration

ISL76683

(6 LD ODFN)

TOP VIEW

THERMAL

PAD

VDD

GND

REXT

SDA

SCL

INT

Pin Descriptions

PIN NUMBER PIN NAME DESCRIPTION

1 VDD Positive supply; connect this pin to a regulated 2.5V to 3.3V supply

2 GND Ground pin. The thermal pad is connected to the GND pin

3 REXT External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100kΩ resistor

4INT

Interrupt pin; LO for interrupt/alarming. The INT pin is an open drain.

5SCLI

2C serial clock The I2C bus lines can be pulled above VDD, 5.5V max.

6SDAI

2C serial data

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

TEMP RANGE

(°C)

PACKAGE

(Pb-free) PKG. DWG. #

ISL76683AROZ-T7 -40 to +105 6 Ld ODFN L6.2x2.1

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4

termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified

at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL76683. For more information on MSL please see techbrief TB477.

ISL76683

3FN7697.3

September 5, 2012

Absolute Maximum Ratings (TA = +25°C) Thermal Information

VDD, Supply Voltage between VDD and GND. . . . . . . . . . . . . . . . . . . . . .3.6V

I2C Bus Pin Voltage (SCL, SDA). . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 5.5V

I2C Bus Pin Current (SCL, SDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA

INT, REXT Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to VDD

ESD Rating

Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV

Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . 200V

Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 1kV

Latch Up (Tested per JESD78B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

6 Ld ODFN Package (Notes 4, 5) . . . . . . . . 88 7.94

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+105°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θJA is measured with in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

5. For θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications VDD = 3V, TA = +25°C, REXT = 100kΩ 1% tolerance, unless otherwise specified, Internal Timing Mode

Operation (see “Principles of Operation” on page 6).

PARAMETER DESCRIPTION CONDITION

MIN

(Note 6) TYP

MAX

(Note 6) UNIT

VDD Power Supply Range 2.25 3.3 V

IDD Supply Current 0.29 0.33 mA

IDD1 Supply Current Disabled Software disabled, -40°C to +85°C 0.1 1 µA

Software disabled, -40°C to +105°C, VDD = 3.3V 0.1 8 µA

fOSC1 Internal Oscillator Frequency Gain/Range = 1 or 2 290 327 360 kHz

fOSC2 Internal Oscillator Frequency Gain/Range = 3 or 4 580 655 720 kHz

FI2CI

2C Clock Rate 1 400 kHz

DATA0 Diode1 Dark ADC Code E = 0 lux, Mode1, Gain/Range = 1 5 Counts

DATA1 Full Scale ADC Code 65535 Counts

DATA2 Diode1 ADC Code Gain/Range = 1

Accuracy

Mode1 E = 300 lux, fluorescent light,

Gain/Range = 1

(Note 7)

15760 20200 24440 Counts

DATA3 Diode2 ADC Code Gain/Range = 1

Accuracy

Mode2 2020 Counts

DATA4 Diode1 ADC Code Gain/Range = 2

Accuracy

Mode1 E = 300 lux, fluorescent light,

Gain/Range = 2

(Note 7)

5050 Counts

DATA5 Diode2 ADC Code Gain/Range = 2

Accuracy

Mode2 505 Counts

DATA6 Diode1 ADC Code Gain/Range = 3

Accuracy

Mode1 E = 300 lux, fluorescent light,

Gain/Range = 3

(Note 7)

1262 Counts

DATA5 Diode2 ADC Code Gain/Range = 3

Accuracy

Mode2 126 Counts

DATA6 Diode1 ADC Code Gain/Range = 4

Accuracy

Mode1 E = 300 lux, fluorescent light,

Gain/Range = 4

(Note 7)

316 Counts

DATA6 Diode2 ADC Code Gain/Range = 4

Accuracy

Mode2 32 Counts

VREF Voltage of REXT Pin -40°C to +85°C 0.485 0.51 0.535 V

-40°C to +105°C 0.545 V

VTL SCL and SDA Threshold LO (Note 8) 1.05 V

VTH SCL and SDA Threshold HI (Note 8) 1.95 V

ISL76683

4FN7697.3

September 5, 2012

ISDA SDA Current Sinking Capability 3 5 mA

IINT INT Current Sinking Capability 3 5 mA

NOTES:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

7. Fluorescent light is substituted by a white LED during production.

8. The voltage threshold levels of the SDA and SCL pins are VDD dependent: VTL = 0.35*VDD. VTH = 0.65*VDD.

Typical Performance Curves (REXT = 100kΩ)

FIGURE 2. SPECTRAL RESPONSE FIGURE 3. RADIATION PATTERN

FIGURE 4. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 5. OUTPUT CODE FOR 0 LUX vs SUPPLY VOLTAGE

Electrical Specifications VDD = 3V, TA = +25°C, REXT = 100kΩ 1% tolerance, unless otherwise specified, Internal Timing Mode

Operation (see “Principles of Operation” on page 6). (Continued)

PARAMETER DESCRIPTION CONDITION

MIN

(Note 6) TYP

MAX

(Note 6) UNIT

100

300 400 500 600 700 800 900 1k

WAVELENGTH (nm)

NORMALIZED RESPONSE (%)

ISL76683 D1

ISL76683 D 2

RADIATION PATTERN

LUMINOSITY

ANGLE

RELATIVE SENSITIVITY

90º

80º

70º

60º

50º

40º 30º 20º 10º 0º

90º

80º

70º

60º

50º

40º

30º

20º

10º

0.2 0.4 0.6 0.8 1.0

2.0 2.3 2.6 2.9 3.2 3.5 3.8

320

306

292

278

264

250

SUPPLY CURRENT (µA)

SUPPLY VOLT AGE (V)

TA = +27°C

COMMAND = 00H

5000 lux

200 lux

2.0 2.3 2.6 2.9 3.2 3.5 3.8

OUTPUT CODE (COUNTS)

SUPPLY VOLTAGE (V)

TA = +27°C

COMMAND = 00H

0 lux

RANGE 2

ISL76683

5FN7697.3

September 5, 2012

FIGURE 6. OUTPUT CODE vs SUPPLY VOLTAGE FIGURE 7. OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE

FIGURE 8. SUPPLY CURRENT vs TEMPERATURE FIGURE 9. OUTPUT CODE FOR 0 LUX vs TEMPERATURE

FIGURE 10. OUTPUT CODE vs TEMPERATURE FIGURE 11. OSCILLATOR FREQUENCY vs TEMPERATURE

Typical Performance Curves (REXT = 100kΩ) (Continued)

2.0 2.3 2.6 2.9 3.2 3.5 3.8

1.015

1.010

1.005

1.000

0.995

0.990

OUTPUT CODE RATIO

(% FROM 3V)

SUPPLY VOLT AGE (V)

5000 lux

200 lux

TA = +27° C

COMMAND = 00H

2.0 2.3 2.6 2.9 3.2 3.5 3.8

320.0

319.5

319.0

318.5

318.0

OSCILLATOR FREQUENCY (k Hz)

SUPPLY VOLT AGE (V)

TA = +27°C

260

270

280

290

300

310

320

330

-60 -40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

VDD = 3V

-60 -40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

OUTPUT CODE (COUNTS)

RANGE2

VDD - 3V

COMMAND = 00H

0 LUX

OUTPUT CODE RATIO

(% FROM +25°C)

TEMPERATURE (°C)

0.92

0.94

0.96

0.98

1.00

1.02

1.04

1.06

1.08

1.10

-60 -40 -20 0 20 40 60 80 100 120

RANGE 3

5000 LUX

VDD = 3V

COMMAND = 00H

RANGE 1

200 LUX

330

329

328

327

326

325

OSCILLATOR F REQUE NC Y ( kHz )

TEMPERATURE (°C)

VDD = 3V

-60 -40 -20 0 20 40 60 80 100 120

ISL76683

6FN7697.3

September 5, 2012

Principles of Operation

Photodiodes

The ISL76683 contains two photodiodes. Diode1 is sensitive to

both visible and infrared light, while Diode2 is mostly sensitive to

infrared light. The spectral response of the two diodes are

independent from one another. See Figure 2 “Spectral Response” in

the “Typical Performance Curves” section. The photodiodes

convert light to current then the diodes’ current outputs are

converted to digital by a single built-in integrating type 16-bit

Analog-to-Digital Converter (ADC). An I2C command mode

determines which photodiode will be converted to a digital signal.

Mode1 is Diode1 only. Mode2 is Diode2 only. Mode3 is a

sequential Mode1 and Mode2 with an internal subtract function

(Diode1 - Diode2).

Analog-to-Digital Converter (ADC)

The converter is a charge-balancing integrating type 16-bit ADC.

The chosen method for conversion is best for converting small

current signals in the presence of AC periodic noise. A 100ms

integration time, for instance, highly rejects 50Hz and 60Hz

power line noise simultaneously. See “Integration Time or

Conversion Time” on page 11 and “Noise Rejection” on page 12.

The built-in ADC offers the user flexibility in integration time or

conversion time. Two timing modes are available; Internal Timing

Mode and External Timing Mode. In Internal Timing Mode,

integration time is determined by an internal dual speed oscillator

(fOSC), and the n-bit (n = 4, 8, 12, 16) counter inside the ADC. In

External Timing Mode, integration time is determined by the time

between two consecutive I2C External Timing Mode commands. See

“External Timing Mode” on page 10. A good balancing act of

integration time and resolution depending on the application is

required for optimal results.

The ADC has four I2C programmable range selects to

dynamically accommodate various lighting conditions. For very

dim conditions, the ADC can be configured at its lowest range.

For very bright conditions, the ADC can be configured at its

highest range.

Interrupt Function

The active low interrupt pin is an open drain pull-down

configuration. The interrupt pin serves as an alarm or monitoring

function to determine whether the ambient light exceeds the

upper threshold or goes below the lower threshold. The user can

also configure the persistency of the interrupt pin. This

eliminates any false triggers, such as noise or sudden spikes in

ambient light conditions. An unexpected camera flash, for

example, can be ignored by setting the persistency to 8

integration cycles.

I2C Interface

There are eight (8) 8-bit registers available inside the ISL76683. The

command and control registers define the operation of the device.

The command and control registers do not change until the registers

are overwritten. There are two 8-bit registers that set the high and

low interrupt thresholds. There are four 8-bit data Read Only

registers; two bytes for the sensor reading and another two bytes for

the timer counts. The data registers contain the ADC's latest digital

output, and the number of clock cycles in the previous integration

period.

The ISL76683’s I2C interface slave address is hardwired

internally as 1000100. When 1000100x with x as R or W is sent

after the Start condition, this device compares the first seven bits

of this byte to its address and matches.

Figure 12 shows a sample one-byte read. Figure 13 shows a sample

one-byte write. Figure 14 shows a sync_iic timing diagram sample

for externally controlled integration time. The I2C bus master always

drives the SCL (clock) line, while either the master or the slave can

drive the SDA (data) line. Figure 13 shows a sample write. Every I2C

transaction begins with the master asserting a start condition (SDA

falling while SCL remains high). The following byte is driven by the

master and includes the slave address and read/write bit. The

receiving device is responsible for pulling SDA low during the

acknowledgement period.

Every I2C transaction ends with the master asserting a stop

condition (SDA rising while SCL remains high).

For more information about the I2C standard, please consult the

Philips® I2C specification documents.

ISL76683

7FN7697.3

September 5, 2012

FIGURE 12. I2C READ TIMING DIAGRAM SAMPLE

Start WAA AA

A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A A6 A5 A4 A3 A2 A1 A0 W A

A A A D7D6D5D4D3D2D1D0 A

123456789123456789 123456789123456789

STOP

STOP START

SDA DRIVEN BY MAST E R

DEVICE ADDRESS

SDA DRIVE N BY IS L29003

DATA BYTE0

NAK

I2C SDA

Out

DEVICE ADDRESS

I2C DATA

SDA DRIVEN BY MAST E R

I2C CLK

I2C SDA

SDA DRIVEN BY MASTER

ISL76683

FIGURE 13. I2C WRITE TIMING DIAGRAM SAMPLE

Start

AAA

A6 A5 A4 A3 A2 A1 A0

A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0 A

AAA

123456789123456789123456789

STOP

I2C SDA In

I2C CLK In

SDA DRIVEN BY MASTER

FUNCTIONSREGISTER ADDRESS

I2C SDA Out

DE VICE ADDRE SS

I2C DATA

SDA DRI VEN BY MASTER SDA DRIVEN BY MASTER

FIGURE 14. I2C sync_iic TIMING DIAGRAM SAMPLE

Start

AAStop

A6 A5 A4 A3 A2 A1 A0

A R7R6R5R4R3R2R1R0 A

123456789123456789

SDA DRIVEN BY MASTER

I2C SDA O ut

DE V ICE A DDRE S S

I2C DATA

I2C SDA In

I2C CLK In

SDA DRIVEN BY MASTER

ISL76683

8FN7697.3

September 5, 2012

There are eight registers that are available in the ISL76683. Table 1 summarizes the available registers and their functions.

TABLE 1. REGISTER SET

ADDR

(HEX)

NAME BIT(S) FUNCTION NAME FUNCTIONS/DESCRIPTION

00 Command 7 Enable 0: disable ADC-core

1: enable ADC-core

6 ADCPD 0: Normal operation

1: Power-down Mode

5 Timing_Mode 0: Integration is internally timed

1: Integration is externally sync/controlled by I2C host

4 Reserved

3:2 Mode<1:0> Selects ADC work mode

0: Diode1’s current to unsigned 16-bit data

1: Diode2’s current to unsigned 16-bit data

2: Difference between diodes (I1 - I2) to signed 15-bit data

3: reserved

1:0 Width<1:0> Number of clock cycles; n-bit resolution

0: 216 cycles

1: 212 cycles

2: 28 cycles

3: 24 cycles

01 Control 7 Ext_Mode Always set to logic 0. Factory use only.

6 Test_Mode Always set to logic 0

5 Int_Flag 0: Interrupt is cleared or not yet triggered

1: Interrupt is triggered

4 Reserved Always set to logic 0. Factory use only.

3:2 Gain<1:0> Selects the gain so range is

0: 0 to 1000 lux

1: 0 to 4000 lux

2: 0 to 16000 lux

3: 0 to 64000 lux

1:0 Int_Persist

<1:0>

Interrupt is triggered after

0: 1 integration cycle

1: 4 integration cycles

2: 8 integration cycles

3: 16 integration cycles

02 Interrupt Threshold

7:0 Interrupt Threshold

High byte of HI interrupt threshold. Default is 0xFF

03 Interrupt Threshold

7:0 Interrupt Threshold

High byte of the LO interrupt threshold. Default is 0x00

04 LSB_Sensor 7:0 LSB_Sensor Read-Only data register that contains the least significant byte of the latest

sensor reading.

05 MSB_Sensor 7:0 MSB_Sensor Read-Only data register that contains the most significant byte of the latest

sensor reading.

06 LSB_Timer 7:0 LSB_Timer Read-Only data register that contains the least significant byte of the timer

counter value corresponding to the latest sensor reading.

07 MSB_Timer 7:0 MSB_Timer Read-Only data register that contains the most significant byte of the timer

counter value corresponding to the latest sensor reading.

ISL76683

9FN7697.3

September 5, 2012

Command Register 00(hex)

The Read/Write command register has five functions:

1. Enable; Bit 7. This function either resets the ADC or enables

the ADC in normal operation. A logic 0 disables ADC to reset-

mode. A logic 1 enables ADC to normal operation.

2. ADCPD; Bit 6. This function puts the device in a power-down

mode. A logic 0 puts the device in normal operation. A logic 1

powers down the device.

For proper shut down operation, it is recommended to disable

ADC first then disable the chip. Specifically, the user should first

send I2C command with Bit 7 = 0 and then send I2C command

with Bit 6 = 1.

3. Timing Mode; Bit 5. This function determines whether the

integration time is done internally or externally. In Internal

Timing Mode, integration time is determined by an internal dual

speed oscillator (fOSC), and the n-bit (n = 4, 8, 12,16) counter

inside the ADC. In External Timing Mode, integration time is

determined by the time between two consecutive external-sync

sync_iic pulse commands.

4. Photodiode Select Mode; Bits 3 and 2. This function controls

the mux attached to the two photodiodes. At Mode1, the mux

directs the current of Diode1 to the ADC. At Mode2, the mux

directs the current of Diode2 only to the ADC. Mode3 is a

sequential Mode1 and Mode2 with an internal subtract

function (Diode1 - Diode2).

*n = 4, 8, 12,16 depending on the number of clock cycles

function.

5. Width; Bits 1 and 0. This function determines the number of

clock cycles per conversion. Changing the number of clock

cycles does more than just change the resolution of the

device; it also changes the integration time, which is the

period the device’s analog-to-digital (A/D) converter samples

the photodiode current signal for a lux measurement.

Control Register 01(hex)

The Read/Write control register has three functions:

1. Interrupt flag; Bit 5. This is the status bit of the interrupt. The

bit is set to logic high when the interrupt thresholds have been

triggered, and logic low when not yet triggered.

TABLE 2. WRITE ONLY REGISTERS

ADDRESS

NAME

FUNCTIONS/

DESCRIPTION

b1xxx_xxxx sync_iic Writing a logic 1 to this address bit ends

the current ADC-integration and starts

another. Used only with External Timing

Mode.

bx1xx_xxxx clar_int Writing a logic 1 to this address bit clears

the interrupt.

TABLE 3. ENABLE

BIT 7 OPERATION

0 Disable ADC-Core to Reset-Mode (default)

1 Enable ADC-Core to Normal Operation

TABLE 4. ADCPD

BIT 6 OPERATION

0 Normal Operation (default)

1Power-Down

TABLE 5. TIMING MODE

BIT 5 OPERATION

0 Internal Timing Mode. Integration time is internally

timed determined by fOSC, REXT, and number of clock

cycles.

1 External Timing Mode. Integration time is externally

timed by the I2C host.

TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3

BITS 3:2 MODE

0:0 MODE1. ADC integrates or converts Diode1 only. Current

is converted to an n-bit unsigned data.*

0:1 MODE2. ADC integrates or coverts Diode2 only. Current is

converted to an n-bit unsigned data.*

1:0 MODE3. A sequential MODE1 then MODE2 operation.

The difference current is an (n-1) signed data.*

1:1 No Operation.

TABLE 7. WIDTH

BITS 1:0 NUMBER OF CLOCK CYCLES

0:0 216 = 65,536

0:1 212 = 4,096

1:0 28 = 256

1:1 24 = 16

TABLE 8. INTERRUPT FLAG

BIT 5 OPERATION

0 Interrupt is cleared or not triggered yet

1 Interrupt is triggered

ISL76683

10 FN7697.3

September 5, 2012

2. Range/Gain; Bits 3 and 2. The Full Scale Range can be

adjusted by an external resistor REXT and/or it can be

adjusted via I2C using the Gain/Range function. Gain/Range

has four possible values, Range(k) where k is 1 through 4.

Table 9 lists the possible values of Range(k) and the resulting

FSR for some typical value REXT resistors.

3. Interrupt persist; Bits 1 and 0. The interrupt pin and the

interrupt flag is triggered/set when the data sensor reading is

out of the interrupt threshold window after m consecutive

number of integration cycles. The interrupt persist bits

determine m.

Interrupt Threshold HI Register 02(hex)

This register sets the HI threshold for the interrupt pin and the

interrupt flag. By default, the Interrupt threshold HI is FF(hex).

The 8-bit data written to the register represents the upper MSB of

a 16-bit value. The LSB is always 00(hex).

Interrupt Threshold LO Register 03(hex)

This register sets the LO threshold for the interrupt pin and the

interrupt flag. By default, the Interrupt threshold LO is 00(hex).

The 8-bit data written to the register represents the upper MSB of

a 16-bit value. The LSB is always 00(hex).

Sensor Data Register 04(hex) and 05(hex)

When the device is configured to output a 16-bit data, the least

significant byte is accessed at 04(hex), and the most significant

byte can be accessed at 05(hex). The sensor data register is

refreshed after every integration cycle.

Timer Data Register 06(hex) and 07(hex)

Note that the timer counter value is only available when using the

External Timing Mode. The 06(hex) and 07(hex) are the LSB and

MSB respectively of a 16-bit timer counter value corresponding to

the most recent sensor reading. Each clock cycle increments the

counter. At the end of each integration period, the value of this

counter is made available over the I2C. This value can be used to

eliminate noise introduced by slight timing errors caused by

imprecise external timing. Microcontrollers, for example, often

cannot provide high-accuracy command-to-command timing,

and the timer counter value can be used to eliminate the

resulting noise.

Calculating Lux

The ISL76683’s output codes, DATA, are directly proportional to lux.

The proportionality constant α is determined by the Full Scale

Range, FSR, and the n-bit ADC, which is user defined in the

command register. The proportionality constant can also be

viewed as the resolution; The smallest lux measurement the

device can measure is α.

Full Scale Range, FSR, is determined by the software

programmable Range/Gain, Range(k), in the command register

and an external scaling resistor REXT which is referenced to

100kΩ.

The transfer function effectively for each timing mode becomes:

INTERNAL TIMING MODE

EXTERNAL TIMING MODE

n = 4, 8, 12, or 16. This is the number of clock cycles

programmed in the command register.

Range(k) is the user defined range in the Gain/Range bit in the

command register.

REXT is an external scaling resistor hardwired to the REXT pin.

DATA is the output sensor reading in number of counts available

at the data register.

2n represents the maximum number of counts possible in

Internal Timing Mode. For the External Timing Mode, the

maximum number of counts is stored in the data register named

COUNTER.

COUNTER is the number increments accrued for between

integration time for External Timing Mode.

TABLE 9. RANGE/GAIN TYPICAL FSR LUX RANGES

BITS

3:2 k

RANGE

(k)

FSR LUX

RANGE@

REXT = 100k

FSR LUX

RANGE@

REXT =50k

FSR LUX

RANGE@

REXT =500k

0:0 1 973 973 1946 195

0:1 2 3892 3892 7784 778

1:0 3 15,568 15,568 31,136 3114

1:1 4 62,272 62,272 124,544 12,454

TABLE 10. INTERRUPT PERSIST

BITS 1:0 NUMBER OF INTEGRATION CYCLES

0:0 1

0:1 4

1:0 8

1:1 16

TABLE 11. DATA REGISTERS

ADDRESS

(hex) CONTENTS

04 Least-significant byte of most recent sensor reading.

05 Most-significant byte of most recent sensor reading.

06 Least-significant byte of timer counter value corresponding to

most recent sensor reading.

07 Most-significant byte of timer counter value corresponding to

most recent sensor reading.

EαDATA×=(EQ. 1)

αFSR

-----------

=(EQ. 2)

(EQ. 3)

FSR Range k() 100kΩ

REXT

-------------------

×=

(EQ. 4)

Range k() 100kΩ

REXT

-------------------

---------------------------------------------------- DATA×=

(EQ. 5)

Range k() 100kΩ

REXT

-------------------

COUNTER

---------------------------------------------------- DATA×=

ISL76683

11 FN7697.3

September 5, 2012

Gain/Range, Range (k)

The Gain/Range can be programmed in the control register to

give Range (k) determining the FSR. Note that Range(k) is not

the FSR (see Equation 3). Range(k) provides four constants

depending on programmed k that will be scaled by REXT (see

Table 9). Unlike REXT, Range(k) dynamically adjusts the FSR. This

function is especially useful when light conditions are varying

drastically while maintaining excellent resolution.

Number of Clock Cycles, n-bit ADC

The number of clock cycles determines “n” in the n-bit ADC; 2n clock

cycles is a n-bit ADC. n is programmable in the command register in

the width function. Depending on the application, a good balance of

speed and resolution has to be considered when deciding for n. For

fast and quick measurement, choose the smallest n = 4. For

maximum resolution without regard of time, choose n = 16.

Table 12 compares the trade-off between integration time and

resolution. See Equations 10 and 11 for the relation between

integration time and n. See Equation 3 for the relation of n and

resolution.

External Scaling Resistor REXT and fosc

The ISL76683 uses an external resistor REXT to fix its internal

oscillator frequency, fOSC. Consequently, REXT determines the

fOSC, integration time and the FSR of the device. fOSC, a dual

speed mode oscillator, is inversely proportional to REXT. For user

simplicity, the proportionality constant is referenced to fixed

constants 100kΩ and 655kHz:

fOSC1 is oscillator frequency when Range1 or Range2 are set.

This is nominally 327kHz when REXT is 100kΩ.

fOSC2 is the oscillator frequency when Range3 or Range4 are

set. This is nominally 655kHz when REXT is 100kΩ.

When the Range/Gain bits are set to Range1 or Range2, fOSC

runs at half speed compared to when Range/Gain bits are set to

Range3 and Range4.

The automatic fOSC adjustment feature allows significant

improvement of signal-to-noise ratio when detecting very low lux

signals.

Integration Time or Conversion Time

Integration time is the period during which the device’s analog-

to-digital ADC converter samples the photodiode current signal

for a lux measurement. Integration time, in other words, is the

time to complete the conversion of analog photodiode current

into a digital signal (number of counts).

Integration time affects the measurement resolution. For better

resolution, use a longer integration time. For short and fast

conversions use a shorter integration time.

The ISL76683 offers user flexibility in the integration time to

balance resolution, speed and noise rejection. Integration time can

be set internally or externally and can be programmed in the

command register 00(hex) bit 5.

INTEGRATION TIME IN INTERNAL TIMING MODE

This timing mode is programmed in the command register

00(hex) bit 5. Most applications will be using this timing mode.

When using the Internal Timing Mode, fOSC and n-bits resolution

determine the integration time. tint is a function of the number of

clock cycles and fOSC.

n = 4, 8, 12, and 16. n is the number of bits of resolution.

Therefore, 2n is the number of clock cycles. n can be programmed

at the command register 00(hex) bits 1 and 0.

Since fOSC is dual speed depending on the Gain/Range bit, tint is

dual time. The integration time as a function of REXT and n is:

tint1 is the integration time when the device is configured for

Internal Timing Mode and Gain/Range is set to Range1 or

Range2.

tint2 is the integration time when the device is configured for

Internal Timing Mode and Gain/Range is set to Range3 or

Range4.

TABLE 12. RESOLUTION AND INTEGRATION TIME SELECTION

RANGE1

fOSC = 327kHz

RANGE4

fOSC = 655kHz

tINT (ms)

RESOLUTION

LUX/COUNT tINT (ms)

RESOLUTION

(LUX/COUNT)

16 200 0.01 100 1

12 12.8 0.24 6.4 16

8 0.8 3.90 0.4 250

4 0.05 62.5 0.025 4000

REXT = 100kΩ

(EQ. 6)

fosc1 1

--- 100kΩ

REXT

-------------------655×kHz×=

(EQ. 7)

fosc2 100kΩ

REXT

-------------------655×kHz=

(EQ. 8)

fOSC11

--- fOSC2()=

TABLE 13. INTEGRATION TIMES FOR TYPICAL REXT VALUES

REXT

(kΩ)

RANGE1

RANGE2

RANGE3

RANGE4

n = 16-BIT n = 12-BIT n = 12-BIT n = 4

50 100 6.4 3.2 0.013

100** 200 13 6.5 0.025

200 400 26 13 0.050

500 1000 64 32 0.125

*Integration time in milliseconds

**Recommended REXT resistor value

tint 2n1

fosc

----------

×=(EQ. 9)

for Internal Timing Mode only

tint12

nREXT

327kHz 100kΩ×

-----------------------------------------------

×=(EQ. 10)

tint22

nREXT

655kHz 100kΩ×

-----------------------------------------------

×=(EQ. 11)

ISL76683

12 FN7697.3

September 5, 2012

INTEGRATION TIME IN EXTERNAL TIMING MODE

This timing mode is programmed in the command register

00(hex) bit 5. External Timing Mode is recommended when

integration time can be synchronized to an external signal (such

as a PWM) to eliminate noise.

For Mode1 or Mode2 operation, the integration starts when the

sync_iic command is sent over the I2C lines. The device needs

two sync_iic commands to complete a photodiode conversion.

The integration then stops when another sync_iic command is

received. Writing a logic 1 to the sync_iic bit ends the current

ADC integration and starts another one.

For Mode3, the operation is a sequential Mode1 and Mode2. The

device needs three sync_iic commands to complete two

photodiode measurements. The 1st sync_iic command starts the

conversion of the Diode1. The 2nd sync_iic completes the

conversion of Diode1 and starts the conversion of Diode2. The 3rd

sync_iic pulse ends the conversion of Diode2 and starts over again

to commence conversion of Diode1.

The integration time, tint, is determined by Equation 12:

iI2C is the number of I2C clock cycles to obtain the tint.

fI2C is the I2C operating frequency.

The internal oscillator, fOSC, operates identically in both the

internal and external timing modes, with the same dependence

on REXT. However, in External Timing Mode, the number of clock

cycles per integration is no longer fixed at 2n. The number of

clock cycles varies with the chosen integration time, and is

limited to 216 = 65,536. In order to avoid erroneous lux readings,

the integration time must be short enough not to allow an

overflow in the counter register.

fOSC = 327kHz*100kΩ/REXT. When Range/Gain is set to

Range1 or Range2.

fOSC = 655kHz*100kΩ/REXT. When Range/Gain is set to

Range3 or Range4.

Noise Rejection

In general, integrating type ADC’s have excellent noise-rejection

characteristics for periodic noise sources whose frequency is an

integer multiple of the integration time. For instance, a 60Hz AC

unwanted signal’s sum from 0ms to k*16.66ms (k = 1,2...ki) is

zero. Similarly, setting the device’s integration time to be an

integer multiple of the periodic noise signal greatly improves the

light sensor output signal in the presence of noise.

DESIGN EXAMPLE 1

The ISL76683 will be designed in a portable system. The

ambient light conditions that the device will be exposed to is at

most 500 lux, which is a good office lighting. The light source has

a 50/60Hz power line noise, which is not visible by the human

eye. The I2C clock is 10kHz.

Solution 1

Using Internal Timing Mode

In order to achieve both 60Hz and 50Hz AC noise rejection, the

integration time needs to be adjusted to coincide with an integer

multiple of the AC noise cycle times.

The first instance of integer values at which tint rejects both 60Hz

and 50Hz is when i = 6, and j = 5.

Next, the Gain/Range needs to be determined. Based on the

application condition given, lux(max) = 500 lux, a range of 1000

lux is desirable. This corresponds to a Gain/Range Range1

mode. Also impose a resolution of n = 16-bit. Hence, we choose

Equation 10 to determine REXT.

The Full Scale Range, FSR, needs to be determined from

Equation 3:

The effective transfer function becomes:

Solution 2

Using External Timing Mode

From Solution 1, the desired integration time is 100ms. Note

that the REXT resistor only determines the inter oscillator

frequency when using external timing mode. Instead, the

integration time is the time between two sync_iic commands

sent through the I2C. The programmer determines how many I2C

clock cycles to wait between two external timing commands.

iI2C = fI2C*tint = number of I2C clock cycles

tint

iI2C

fI2C

----------

=(EQ. 12)

tint

65,535

fOSC

-------------------

<(EQ. 13)

TABLE 14. SOLUTION1 SUMMARY TO EXAMPLE DESIGN PROBLEM

DESIGN PARAMETER VALUE

tint 100ms

REXT 50kΩ

Gain/Range Mode Range1 = 1000 lux

FSR 2000 lux

# of clock cycles 216

Transfer Function

tint i1 60Hz⁄()j1 50Hz⁄()== (EQ. 14)

tint 61 60Hz⁄()51 50Hz⁄()== (EQ. 15)

tint 100ms=

for Internal Timing Mode and Gain/Range is set to Range3 or Range4 only

REXT

tint 327kHz 100×× kΩ

--------------------------------------------------------------

REXT 50kΩ=

(EQ. 16)

FSR 1000 lux100kΩ

50kΩ

-------------------

FSR 2000 lux=

(EQ. 17)

Edata

216

-------------2000 lux×=(EQ. 18)

EDATA

216

---------------2000 lux×=

ISL76683

13 FN7697.3

September 5, 2012

iI2C = 10kHz *100ms

iI2C = 1,000 I2C clock cycles. An external sync_iic command sent

1,000 cycles after another sync_iic command rejects both 60Hz

and 50Hz AC noise signals.

Next, is to pick an arbitrary REXT = 100kΩ and to choose the

Gain/Range Mode. For a maximum 500 lux, Range1 is

adequate. From Equation 3:

The effective transfer function becomes:

DATA is the sensor reading data located in data registers 04(hex)

and 05(hex)

COUNTER is the timer counter value data located in data registers

06(hex) and 07(hex). In this sample problem, COUNTER = 1000.

IR Rejection

Any filament type light source has a high presence of infrared

component invisible to the human eye. A white fluorescent lamp,

on the other hand has a low IR content. As a result, output

sensitivity may vary depending on the light source. Maximum

attenuation of IR can be achieved by properly scaling the readings

of Diode1 and Diode2. The user obtains data reading from sensor

Diode1 (D1), which is sensitive to visible and IR, then reading from

sensor Diode2 (D2), which is mostly sensitive from IR. The graph in

Figure 2 shows the effective spectral response after applying

Equation 19 of the ISL76683 from 400nm to 1000nm.

Equation 19 describes the method of cancelling IR in internal

timing mode.

Where:

data = lux amount in number of counts less IR presence

D1 = data reading of Diode1

D2 = data reading of Diode2

n = 1.85. This is a fudge factor to scale back the sensitivity up to

ensure Equation 4 is valid.

k = 7.5. This is a scaling factor for the IR sensitive Diode2.

Flat Window Lens Design

A window lens will surely limit the viewing angle of the ISL76683.

The window lens should be placed directly on top of the device.

The thickness of the lens should be kept at minimum to

minimize loss of power due to reflection and also to minimize

loss of loss due to absorption of energy in the plastic material. A

thickness of t = 1mm is recommended for a window lens design.

The bigger the diameter of the window lens, the wider the

viewing angle is of the ISL76683. Table 16 shows the

recommended dimensions of the optical window to ensure both

35° and 45° viewing angle. These dimensions are based on a

window lens thickness of 1.0mm and a refractive index of 1.59.

Window with Light Guide Design

If a smaller window is desired while maintaining a wide effective

viewing angle of the ISL76683, a cylindrical piece of transparent

plastic is needed to trap the light and then focus and guide the

light on to the device. Hence, the name light guide or also known

as light pipe. The pipe should be placed directly on top of the

device with a distance of D1 = 0.5mm to achieve peak

performance. The light pipe should have minimum of 1.5mm in

diameter to ensure that whole area of the sensor will be exposed.

See Figure 16.

TABLE 15. SOLUTION 2 SUMMARY TO EXAMPLE DESIGN PROBLEM

DESIGN PARAMETER VALUE

tint 100ms

REXT 100kΩ

Gain/Range Mode Range1 = 1000 lux

FSR 1000 lux

# of clock cycles COUNTER = 1000

Transfer Function

FSR 1000 lux100kΩ

100kΩ

-------------------

FSR 1000 lux=

EDATA

COUNTER

--------------------------- 1000 lux×=

EDATA

COUNTER

--------------------------- 1000 lux×=

D3 n D1 kD2–()=(EQ. 19)

TABLE 16. RECOMMENDED DIMENSIONS FOR A FLAT WINDOW

DESIGN

DTOTAL D1

DLENS @ 35° VIEWING

ANGLE

DLENS @ 45° VIEWING

ANGLE

1.5 0.50 2.25 3.75

2.0 1.00 3.00 4.75

2.5 1.50 3.75 5.75

3.0 2.00 4.30 6.75

3.5 2.50 5.00 7.75

t = 1 Thickness of lens

D1 Distance between ISL76683 and inner edge of lens

DLENS Diameter of lens

DTOTAL Distance constraint between the ISL76683 and lens

outer edge

*All dimensions are in mm.

DLENS

∅

D1 DTOTAL

∅ = VIEWING ANGLE

WINDOW LENS

ISL76683

FIGURE 15. FLAT WINDOW LENS

ISL76683

14 FN7697.3

September 5, 2012

Suggested PCB Footprint

Footprint pads should be a nominal 1-to-1 correspondence with

package pads. Since ambient light sensor devices do not

dissipate high power, heat dissipation through the exposed pad is

not important; instead, similar to DFN or QFN, the exposed pad

provides robustness in board mount process. Intersil

recommends mounting the exposed pad to the PCB, but this is

not mandatory.

Layout Considerations

The ISL76683 is relatively insensitive to layout. Like other I2C

devices, it is intended to provide excellent performance even in

significantly noisy environments. There are only a few

considerations that will ensure best performance.

Route the supply and I2C traces as far as possible from all

sources of noise. Use two power-supply decoupling capacitors,

4.7µF and 0.1µF, placed close to the device.

Typical Circuit

A typical application for the ISL76683 is shown in Figure 18. The

ISL76683’s I2C address is internally hardwired as 1000100. The

device can be tied onto a system’s I2C bus together with other

I2C compliant devices.

Soldering Considerations

Convection heating is recommended for reflow soldering; direct

infrared heating is not recommended. The plastic ODFN package

does not require a custom reflow soldering profile, and is

qualified to +260°C. A standard reflow soldering profile with a

+260°C maximum is recommended.

DLENS

LIGHT PIPE

ISL76683

D2 >1.5mm

FIGURE 16. WINDOW WITH LIGHT GUIDE/PIPE

0.56mm

0.46mm

2.00mm

SENSOR OFFSET

0.29mm

2.10mm

FIGURE 17. SENSOR LOCATION DRAWING

ISL76683

15 FN7697.3

September 5, 2012

FIGURE 18. ISL76683 TYPICAL CIRCUIT

VDD

GND

REXT

3INT 4

SCL 5

SDA 6

ISL76683

10k R2

10k R3

RES1

REXT

100k

0.1µF

4.7µF

2.5V TO 3.3V

1.8V TO 5.5V

MICROCONTROLLER

SDA

SCL

I2C SLAVE_0 I2C SLAVE_1 I2C SLAVE_n

I2C MASTER

SCL

SDA

SCL

SDA

ISL76683

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7697.3

September 5, 2012

For additional products, see www.intersil.com/product_tree

Products

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Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page

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Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest revision.

DATE REVISION CHANGE

July 9, 2012 FN7697.3 Page 9, Control Register 01(hex), interrupt flag, removed sentence: “writing a logic low clears/resets the status

bit.”

3/8/11 FN7697.2 Changed TechBrief reference in ordering information for MSL info from TB363 to TB477.

1/24/11 FN7697.1 Initial Release to web.

ISL76683

17 FN7697.3

September 5, 2012

Package Outline Drawing

L6.2x2.1

6 LEAD OPTICAL DUAL FLAT NO-LEAD PLASTIC PACKAGE (ODFN)

Rev 2, 6/10

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to ASME Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

(4X) 0.10

INDEX AREA

PIN 1

ABPIN #1

B0.10 MAC

SEATING PLANE

BASE PLANE

0.08

0.10

SEE DETAIL "X"

0 . 00 MIN.

0 . 05 MAX.

0 . 2 REF

2.10

2.00

2.10

2.50

(1.35)

(6x0.30)

0.65

(6x0.55)

(6x0.20)

(4x0.65)

1.30 REF1.35

0.65

6x0.35 ± 0.05

PACKAGE

6X 0.30±0.05

INDEX AREA

OUTLINE