 
  
FEATURES APPLICATIONS
DESCRIPTION
CDAC
Output
Latches
and
3-State
Drivers
BYTE
16-/8-Bit
ParallelData
OutputBus
SAR
Conversion
and
ControlLogic
Comparator
Clock
+IN
−IN
REFIN CONVST
BUSY
CS
RD
4.096-V
InternalReference
REFOUT
RESET/PD1
PD2
COMMOUT ½
TempSensor
TEMPOUT
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWERSAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE,REFERENCE
•DWDM•Fully Differential Input with Pseudo-BipolarInput Range -4 V to +4 V
•Instrumentation
•High-Speed, High-Resolution, Zero Latency•16-Bit NMC at 4 MSPS
Data Acquisition Systems•1 LSB INL Typ
•Transducer Interface•92dB SNR, -102dB THD Typ with 100-kHz
•Medical InstrumentsInput
•Spectrum Analysis•Internal 4.096-V Reference and Reference
•ATEBuffer
•REFIN/2 Available for Setting Analog InputCommon-Mode Voltage
The ADS8422 is a 16-bit, 4-MHz A/D converter with•Zero Latency
an internal 4.096-V reference. The device includes a•High-Speed Parallel Interface
16-bit capacitor-based multi-bit SAR A/D converter•Single Supply Operation Capability
with inherent sample and hold. This converterincludes a full 16-bit interface and an 8-bit option•Low Power: 155 mW at 4 MHz Typ, Flexible
where data is read using two 8-bit read cycles ifPower-Down Scheme
necessary.•Pin-Out Similar to ADS8412/8402
The ADS8422 has a fully differential, pseudo-bipolar•48-Pin 9 ×9 TQFP Package
input. It is available in a 48-lead TQFP package andis characterized over the industrial -40 °C to +85 °Ctemperature range.
HIGH-SPEED SAR CONVERTER FAMILY
(1)
TYPE/SPEED 500 kHz ~600 kHz 750 kHz 1 MHz 1.25 MHz 2 MHz 3 MHz 4MHz
ADS8383 ADS8381 ADS848118-Bit Pseudo-Diff
ADS8380 (s)
18-Bit Pseudo-Bipolar, Fully Diff ADS8382 (s) ADS8482
ADS8370 (s) ADS8371 ADS8471 ADS8401 ADS841116-Bit Pseudo-Diff
ADS8327/28 (s) ADS8372 (s) ADS8329/30 (s) ADS8405 ADS8410 (s)
ADS8472 ADS8402 ADS8412 ADS842216-Bit Pseudo-Bipolar, Fully Diff
ADS8406 ADS8413 (s)
14-Bit Pseudo-Diff ADS7890 (s) ADS7891
12-Bit Pseudo-Diff ADS7886 ADS7883 ADS7881
(1) S: Serial
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
MAXIMUM
MAXIMUMINTEGRAL NO MISSING CODES PACKAGE PACKAGE TEMPERATURE ORDERING TRANSPORTMODEL DIFFERENTIALLINEARITY RESOLUTION (BIT) TYPE DESIGNATOR RANGE INFORMATION MEDIA QTY.LINEARITY (LSB)(LSB)
Small tape andADS8422IPFBT
reel 2509×9 48-PinADS8422I ±6±2 15 PFB –40 °C to 85 °CTQFP
Tape and reelADS8422IPFBR
1000
Small tape andADS8422IBPFBT
reel 2509×9 48-PinADS8422IB ±2 +1.5/-1 16 PFB –40 °C to 85 °CTQFP
Tape and reelADS8422IBPFBR
1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
+IN to AGND –0.4 to +VA + 0.1 V–IN to AGND –0.4 to +VA + 0.1 VVoltage
+VA to AGND –0.3 to 7 V+VBD to BDGND –0.3 to 7 VDigital input voltage to BDGND –0.3 to +VBD + 0.3 VDigital output voltage to BDGND –0.3 to +VBD + 0.3 VT
A
Operating free-air temperature range –40 to 85 °CT
stg
Storage temperature range –65 to 150 °CJunction temperature (T
J
max) 150 °CPower dissipation (T
J
Max – T
A
)/ θ
JATQFP 48-pin package
θ
JA
thermal impedance 86 °C/WVapor phase (60 sec) 215 °CLead temperature, soldering
Infrared (15 sec) 220 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SPECIFICATIONS
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
T
A
= –40 °C to 85 °C, +VA = 5 V, +VAREG = 5 V to 3 V, +VBD = 5 V to 2.7 V, f
SAMPLE
= 4 MSPS, V
ref
= 4.096 V (measuredwith internal reference buffer) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage
(1)
+IN – (–IN) –V
ref
V
ref
V
+IN –0.2 V
ref
+ 0.2Absolute input voltage V–IN –0.2 V
ref
+ 0.2
Common-mode input range (V
ref
)/2 – 0.2 (V
ref
)/2 (V
ref
)/2 + 0.2 V
Input capacitance 30 pF
Input leakage current 1 nA
SYSTEM PERFORMANCE
Resolution 16 Bits
ADS8422I 15No missing codes BitsADS8422IB 16
ADS8422I –6 ±2 6
LSBIntegral linearity
(2) (3)
(16 bit)
(2)ADS8422IB –2 ±1 2
ADS8422I –2 ±0.7 2
LSBDifferential linearity
(16 bit)ADS8422IB –1 ±0.7 1.5
Offset error –0.5 ±0.25 0.5 mV
Offset error drift ±0.2 ppm/ °C
Gain error
(4) (5)
V
ref
= 4.096 V –0.1 ±0.05 0.1 %FS
Gain error drift V
ref
= 4.096 V ±2 ppm/ °C
At dc 81Common-mode rejection ratio dBAt code 0000h with [+IN + (–IN)]/2 =
78512 mV
pp
at 500 kHz,
Noise At 0000h output code 40 µV RMS
Power supply rejection ratio At 8000h output code 78 dB
SAMPLING DYNAMICS
Conversion time 0.180 µs
Acquisition time 0.070 µs
Throughput rate 4 MHz
Aperture delay 3 ns
Aperture jitter 7 ps RMS
Step response 70 ns
Overvoltage recovery 140 ns
(1) Ideal input span, does not include gain or offset error.(2) LSB means least significant bit and is equal to 2V
REF
/65536.(3) This is endpoint INL, not best fit.(4) Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V.(5) This specification does not include the internal reference voltage error and drift.
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SPECIFICATIONS (Continued)
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
T
A
= –40 °C to 85 °C, +VA = 5 V, +VAREG = 5.25 V to 3 V, +VBD = 5 V to 2.7 V, f
SAMPLE
= 4 MSPS, V
ref
= 4.096 V (measuredwith internal reference buffer) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC CHARACTERISTICS
10 kHz –114
Total harmonic distortion (THD)
(1)
V
IN
= 8 V
pp
100 kHz –102 dB
500 kHz –100
10 kHz 93
Signal to noise ratio (SNR) V
IN
= 8 V
pp
100 kHz 92 dB
500 kHz 90
10 kHz 92.5
Signal to noise + distortion (SINAD) V
IN
= 8 V
pp
100 kHz 91.5 dB
500 kHz 89.5
10 kHz 116
Spurious free dynamic range (SFDR) V
IN
= 8 V
pp
100 kHz 109 dB
500 kHz 106
–3dB Small signal bandwidth 30 MHz
Maximum input frequency, f
i(max)
(2)
V
IN
= 8 V
pp
2 MHz
VOLTAGE REFERENCE INPUT
Reference voltage at REFIN, V
ref
3.9 4.096 4.15 V
Reference resistance 1000 M Ω
INTERNAL REFERENCE OUTPUT
Internal reference start-up time From 95% (+VA), with 1- µF capacitor on REFOUT 25 ms
Reference voltage range, V
ref
I
O
= 0, T
A
= 25 °C 4.088 4.096 4.104 V
Source current Static load 10 µA
Line regulation +VA = 4.75 V to 5.25 V ±1 mV
Drift I
O
= 0 ±6 PPM/ °C
ANALOG COMMON-MODE, PIN 3
Output voltage range I
O
= 0 V
REF
/2 - 0.016 V
REF
/2 V
REF
/2 + 0.016 V
Source current Static load 200 µA
(1) Calculated on the first nine harmonics of the input frequency.(2) ADC Sampling circuit is optimized to accept inputs until Nyquist frequency. Dynamic performance may degrade rapidly above f
i(max)
.
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SPECIFICATIONS (Continued)
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
T
A
= –40 °C to 85 °C, +VA = 5 V, +VAREG = 5 V to 3 V, +VBD = 5 V to 2.7 V, f
SAMPLE
= 4 MSPS, V
ref
= 4.096 V (measuredwith internal reference buffer) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
Logic family – CMOS
V
IH
I
IH
= 5 µA 0.75 ×(+VBD) +VBD + 0.3
V
IL
I
IL
= 5 µA –0.3 0.8Logic level VV
OH
I
OH
= 2 TTL loads +VBD – 0.6
V
OL
I
OL
= 2 TTL loads 0.4
Data format – Twos complement
POWER SUPPLY REQUIREMENTS
+VA 4.75 5 5.25
Power supply voltage +VAREG 2.85 3.0 5.25 V
+VBD 2.7 3.0 5.25
+VA +VA = 5 V, PD1 = 1, PD2 = 1 24 27 mA
+VAREG = 5 V, PD1 = 1, PD2 = 1 12 14+VAREG mASupply current +VAREG = 3 V, PD1 = 1, PD2 = 1 12 14
+VBD = 3 V, 10 pF/pin 0.55+VBD
(1)
mA+VBD = 5 V, 20 pF/pin 1.8
POWER DOWN
(2)
+VA 2.5 3.4 mASupply current PD1 = 0, PD2 = 1, +VA = 5 V+VAREG 5 µA
Power 17 mW
Power-up time ( PD1, PD2) : (0,1) →(1,1) 5 µs
+VA 5Supply current PD1 = 0, PD2 = 0 µA+VAREG 5
Power 40 µW
( PD1, PD2) : (0,0) →(1,1) , 1- µF Storage 25Power-up time mscapacitor from REFOUT to AGND
TEMPERATURE RANGE
Operating free-air –40 85 °C
(1) This includes the current required for charging the external load capacitance on the digital outputs and is measured with four digitaloutputs toggling at the same time.(2) ( PD
1
, PD
2
) = (1,0) is reserved. Do not use this power-down pins combination.
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TIMING CHARACTERISTICS FROM DIGITAL INPUTS
TIMING CHARACTERISTICS OF DIGITAL OUTPUTS
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
All specifications typical at –40 °C to 85 °C, +VBD = 2.7 V to 5.25 V
(1) (2)
PARAMETER MIN TYP MAX UNIT
CONVERSION AND ACQUISITION
t
(ACQ)
Acquisition time, internal to device, not externally visible 70 nst
w1
Pulse duration, CONVST low 20 nst
w2
Pulse duration, CONVST high 100 nst
p1
Period, CONVST 250 nst
q1
Quiet time, last toggle of interface input signals during acquisition before CONVST falling
(3)
30 nst
q2
Quiet time, CONVST falling to first toggle of interface input signals
(3)
10 ns
POWER DOWN
PD1 low for only ADC reset (no powerdown) 20 500t
w3
Pulse duration PD1 low for ADC reset and also ADC powerdown 1500 nsPD2 low pulse duration for REFOUT and COMMOUT buffers powerdown 1500Pulse duration, all others unspecified 10 ns
(1) All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
DD
) and timed from after 90% of transition.(2) All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching90% of transition.(3) Quiet time zones are for meeting performance and not functionality.
All specifications typical at –40 °C to 85 °C, +VBD = 2.7 V to 5.25 V
(1) (2)
PARAMETER MIN TYP MAX UNIT
CONVERSION AND ACQUISITION
t
(CONV)
Conversion time, internal to device, not externally visible 180 nst
d1
Delay time, CONVST fall to conversion start (aperture delay) 3 ns
DATA READ OPERATION
t
d2
Delay time, CONVST low to data valid if CS = RD = 0 225 nst
d3
Delay time, data valid to BUSY low if CS = RD = 0 5 nst
d4
Delay time, RD (or CS) low to data valid 17 nst
d5
Delay time, BYTE toggle to data valid 20 nst
d6
Delay time, data three-state after RD (or CS) high 12 ns
POWER DOWN
t
d7
Delay time, PD1 low to BUSY rising 20 nsDelay time, PD1 high to device operational (with PD2 held high) 5 µst
d8
Delay time, PD2 high to REFOUT/COMMOUT valid 25 msDelay time, power up (after AV
DD
= 4.75 V) 25 mst
d9
Delay time, data three-state after PD1 low 1.5 µs
(1) All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
DD
) and timed from after 90% of transition.(2) All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching90% of transition.
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PIN ASSIGNMENTS
23
BUSY
BDGND
+VBD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
BDGND
13 14
1
2
3
4
5
6
7
8
9
10
11
12
REFIN
REFOUT
COMMOUT
+VA
AGND
+IN
−IN
AGND
CAP1
+VAREG
NC
AGND 15 16 17 18
RD
CONVST
BYTE
RESET/PD1
47 46 45 44 4348 42
REFM
REFM
+VA
AGND
AGND
+VA
CS
DB11
DB10
DB9
CAP2
AGND
AGND
DB15
DB14
DB13
DB12
40 39 3841
19 20 21 22
DB8
36
35
34
33
32
31
30
29
28
27
26
25
+VBD
24
PD2
37
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
PFB Package
(Top View)
A. NC - No connectionB. Pins 9 and 13 are internally regulated 3-V outputs and are externally to be connected to decoupling capacitors only.C. +VAREG can be connected to a 3-V to 5-V supply.D. Pin 3 outputs REFIN/2E. Pin 38 can be used for ADC powerdown and pin 37 for analog output powerdown.
TERMINAL FUNCTIONSNAME NO I/O DESCRIPTION
5, 8, 12, 14,AGND – Analog ground15, 44, 45
BDGND 25, 35 – Digital ground for bus interface digital supply
BUSY 36 O Status output. High when a conversion is in progress.
Byte select input. Used for 8-bit bus reading.BYTE 39 I 0: No fold back1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8].
This pin outputs REFIN/2 and can be used to set the common-mode voltage of the differential analog input, (+IN +COMMOUT 3 O
–IN)/2.
CONVST 40 I Convert start. This input is low true and can act independent of the CS input.
CS 42 I Chip select.
CAP1, CAP2 9, 13 O Decoupling of internally generated 3-V supply. Add 1- µF capacitor from these pins to AGND.
8-BIT BUS 16-BIT BUSData Bus
BYTE = 0 BYTE = 1 BYTE = 0
DB15 16 O D15 (MSB) D7 D15 (MSB)
DB14 17 O D14 D6 D14
DB13 18 O D13 D5 D13
DB12 19 O D12 D4 D12
DB11 20 O D11 D3 D11
DB10 21 O D10 D2 D10
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TYPICAL CHARACTERISTICS
68 14024 13025 93
234937
0
50000
100000
150000
200000
250000
FFFD FFFE FFFF 0000 0001
Code-Hex
COUNTS
+VA =5V,
+VAREG=3V,
+VBD=3V,
IntREFIN=4.096V,
262144Points,
Sigma=0.325,
78 13793
235679
12575 19
0
50000
100000
150000
200000
250000
FFFD FFFE FFFF 0000 0001
Code-Hex
COUNTS
+VA =5V,
+VAREG=3V,
+VBD=3V,
ExtREFIN=4.096V,
262144Points,
Sigma=0.319,
4.094
4.095
4.096
4.097
4.098
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature- C
Aº
REFOUT-InternalReferenceVoltage-V
D1
D3
D2
+VA =5V,
+VAREG=3V,
+VBD=3V
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
TERMINAL FUNCTIONS (continued)NAME NO I/O DESCRIPTION
DB9 22 O D9 D1 D9
DB8 23 O D8 D0 (LSB) D8
DB7 26 O D7 All ones D7
DB6 27 O D6 All ones D6
DB5 28 O D5 All ones D5
DB4 29 O D4 All ones D4
DB3 30 O D3 All ones D3
DB2 31 O D2 All ones D2
DB1 32 O D1 All ones D1
DB0 33 O D0 (LSB) All ones D0 (LSB)
–IN 7 I Inverting input channel
+IN 6 I Noninverting input channel
NC 11 – No connection
Low true signal. A logic low longer than 1.5 µs applied to this pin powers down only the analog outputs that includePD2 37 I
REFOUT and COMMOUT. (NOTE: The combination PD1 = 1, PD2 = 0 is reserved. Do not use this combination.)
REFIN 1 I Reference input. Add 0.1- µF decoupling capacitor between REFIN and REFM.
REFOUT 2 O Reference output. Add 1- µF capacitor between the REFOUT pin and REFM pin when internal reference is used.
REFM 47, 48 I Reference ground
Low true signal. A low pulse applied to this pin resets the ADC; the ongoing conversion is aborted. A low pulse shorterRESET/ PD1 38 I than 0.5 µs only resets, and one longer than 1.5 µs resets and also powers down the ADC. Note that analog outputsREFOUT and COMMOUT can be powered down by PD2, if necessary.
RD 41 I Synchronization pulse for the parallel output.
+VA 4, 46 – Analog power supplies, 4.75 V to 5.25 VDC
+VAREG 10 – Regulator supply, 2.85 V to 5.25 VDC
+VBD 24, 34 – Digital power supply for bus
INTERNAL REFERENCE VOLTAGEHISTOGRAM OF 262144 HISTOGRAM OF 262144 vsCONVERSIONS OF DC INPUT AT CONVERSIONS OF DC INPUT AT FREE-AIR TEMPERATURECENTER CODE (Internal Reference) CENTER CODE (External Reference) (Three Devices Shown)
Figure 1. Figure 2. Figure 3.
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0
0.010
0.020
0.030
0.040
-40 -25 -10 5 20 35 50 65 80
GainError-%FS
T -Free-AirTemperature- C
Aº
+VA =5V,
+VAREG=3V,
+VBD=3V,
REFIN=4.096V
0
0.050
0.100
0.150
0.200
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature- C
Aº
OffsetVoltage-mV
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V
84
86
88
90
92
94
1 10 100 1000
f -InputFrequency-kHz
i
SNR-Signal-to-NoiseRatio-dB
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V
84
86
88
90
92
94
1 10 100 1000
f -InputFrequency-kHz
i
SINAD-Signal-to-Noise+Distortion-dB
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V
1 10 100 1000
13.5
14
14.5
15
15.5
16
EffectiveNumberofBits-ENOB
f -InputFrequency-kHz
i
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V
1 10 100 1000
f -InputFrequency-kHz
i
85
90
95
100
105
110
115
120
125
SFDR-SpuriousFreeDynamicRange-dB
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V
-125
-120
-115
-110
-105
-100
-95
-90
-85
110 100 1000
f -InputFrequency-kHz
i
THD-TotalHarmonicDistortion-dB
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V
-120
-115
-110
-105
-100
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature- C
Aº
THD-TotalHarmonicDistortion-dB
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V,
f =18kHz
i
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
OFFSET VOLTAGE GAIN ERROR SIGNAL-TO-NOISE RATIOvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE INPUT FREQUENCY
Figure 4. Figure 5. Figure 6.
SIGNAL-TO-NOISE + DISTORTION EFFECTIVE NUMBER OF BITS SIGNAL-TO-NOISE RATIOvs vs vsINPUT FREQUENCY INPUT FREQUENCY FREE-AIR TEMPERATURE
Figure 7. Figure 8. Figure 9.
TOTAL HARMONIC DISTORTION SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTIONvs vs vsINPUT FREQUENCY INPUT FREQUENCY FREE-AIR TEMPERATURE
Figure 10. Figure 11. Figure 12.
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40003000200010000
Throughput-KSPS
9
9.5
10
10.5
11
11.5
12
+VAREGCurrent-mA
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V,
Devicenotpowereddownbetween
conversions
120
130
140
150
160
170
180
01000 2000 3000 4000
Throughput-KSPS
P-PowerDissipation-mW
D
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V,
Devicenotpowereddown
betweenconversions
21
21.5
22
22.5
23
23.5
24
24.5
25
40003000200010000
Throughput-KSPS
+VA Current-mA
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V,
Devicenotpowereddownbetween
conversions
-2
-1
0
1
2
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature- C
Aº
INL -LSBs
Max
Min
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V
50
55
60
65
70
75
80
85
1 10 100 1000 10000
f-Frequency-kHz
CMRR-Common-ModeRejectionRatio-dB
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V
-1
-0.50
0
0.50
1
1.50
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature- C
Aº
DNL -LSBs
Min
Max
+VA =5V,+VAREG=3V,
+VBD=3V,REFIN=4.096V
-1
-0.5
0
0.5
1
1.5
0 16384 32768 49152 65536
Code
DNL -LSBs
+VA =5V,+VAREG=3V,+VBD=3V,REFIN=4.096V
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
POWER DISSIPATION +VAREG CURRENT +VA CURRENTvs vs vsTHROUGHPUT THROUGHPUT THROUGHPUT
Figure 13. Figure 14. Figure 15.
DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY COMMON-MODE REJECTION RATIOvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREQUENCY
Figure 16. Figure 17. Figure 18.
DNL
Figure 19.
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-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
016384 32768 49152 65536
Code
INL -LSBs
+VA =5V,+VAREG=3V,+VBD=3V,REFIN=4.096V
-200
-160
-120
-80
-40
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
f-Frequency-kHz
Amplitude-dBofFull-Scale
+VA =5V,+VAREG=3V,+VBD=3V,REFIN=4.096V,
f =10kHz,SNR=93dB,THD=114dB
i
-200
-160
-120
-80
-40
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
f-Frequency-kHz
Amplitude-dBofFull-Scale
+VA =5V,+VAREG=3V,+VBD=3V,REFIN=4.096V,
f =100kHz,SNR=92dB,THD=102dB
i
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
INL
Figure 20.
FFT (10 kHz)
Figure 21.
FFT (100 kHz)
Figure 22.
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-200
-160
-120
-80
-40
0
0 200 400 600 800 1000 1200 1400 1600 20001800
f-Frequency-kHz
Amplitude-dBofFull-Scale
+VA =5V,+VAREG=3V,+VBD=3V,REFIN=4.096V,
f =500kHz,SNR=90dB,THD=100dB
i
TIMING DIAGRAMS
CONVST
DB(Internal)
ACQUISITION
BUSY
Sample(N+1)
Conversion(N)
tq1
tw1
tq2
tp1
tw2
t(acq)
td1
Sample(N)
t(CONV)
CONVERT
DB(N-1)
td2
td3
DB(N)
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)FFT (500 kHz)
Figure 23.
Note: The DB shown here is internal to the device and output on the pins only if and when CS and RD are both low(after t
d4
ns). This is shown in Figure 25 .
Figure 24. Conversion Control Timing
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BYTE
RD
DB
Hi-Z Valid
Data
Valid
Data
Valid
Data
CS
td6
Hi-Z
td4 td4
td5
td6
Hi-Z
BUSY
PD1
DB Hi-Z Undefined
Data DB(1)
ICC
CONVST
DB(2)
Conversion(1)
td8
tw2
td7
td2
td9
Conversion(2)
t >1500ns
w3
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
Note: Data is output on the pins only if CS and RD are both low, t
d4
ns after this condition is satisfied.
Figure 25. Data Read Timing
Note: Data is valid from the first conversion initiated 5 µs after PD1 is pulled high.
Figure 26. ADC Power-Down Timing
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COMMOUT
PD2
REFOUT
Valid
Analog
Outputs
t >1500ns
w3
td8
PD1 =0
RESET TIMING
BUSY
PD1
DB Undefined
Data DB(1)
CONVST
DB(2)
Conversion(1)
tw2
t <500ns
w3
td7
td2
Conversion(2)
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
Note: Analog outputs are valid 25 ms after PD2 is pulled high.
Figure 27. Analog Output Power-Down Timing
Note: Data valid from first conversion initiated 100 ns after PD1 is pulled high.
Figure 28. ADC Reset
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PRINCIPLES OF OPERATION
REFERENCE
ANALOG INPUT
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
The ADS8422 is a member of a family of high-speed multi-bit successive approximation register (SAR)analog-to-digital converters (ADC). The architecture is based on charge redistribution, which inherently includesa sample/hold function. See Figure 34 for the application circuit for the ADS8422.
The conversion clock is generated internally. The conversion time is a maximum of 180 ns that is capable ofsustaining a 4-MHz throughput.
The analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the differential inputon these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs aredisconnected from any internal function.
The ADS8422 has a built-in 4.096-V reference but can operate with an external 4.096-V reference. Wheninternal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with a 0.1- µF decouplingcapacitor and a 1- µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM). The internalreference of the converter is double buffered. If an external reference is used, the second buffer providesisolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitorsof the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if an external reference isused.
The ADS8422 has a pseudo-bipolar, fully differential input. When the input is differential, the amplitude of theinput equals the difference between +IN and –IN. The peak-to-peak amplitude of each input is V
REF
. Howeversince the two inputs are 180 °out of phase, the peak-to-peak amplitude of the difference voltage [+IN – (–IN)] isequal to 2V
REF
. The common-mode input range is from V
REF
/2 – 0.2 V to V
REF
/2 + 0.2 V.
In order to avoid additional external circuitry on the board, the ADS8422 outputs reference input on REFINdivided by 2 on pin 3 (COMMOUT). This voltage can be used to set the common-mode of the output from theinput driver.
Figure 29 ,Figure 30 ,Figure 31 ,Figure 32 , and Figure 33 show the recommended circuits to interface an analoginput signal to the ADS8422.
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+VIN
-VIN 4Vpp
4Vpp
time
Vincm
THS4131
-VCC
0.1 Fm
+VCC
220pFVocm
COMMOUT
+VIN=
ADS8422
+IN
-IN
-VIN=
1
2
85
4
6
3
3
7
6
C0G
Vincm + 4Vpp
Vincm + 4Vpp
390 W
390 W
12 W
12 W
390 W
390 W
0.1 Fm
1 mF
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
PRINCIPLES OF OPERATION (continued)
A. Input common-mode voltage (Vincm) range is restricted by the amplifier. Refer to the amplifier data sheet for moreinformation. Output common mode of the THS4131 is set by the voltage at pin 2. The COMMOUT pin of theADS8422 is designed to source pin 2 of the THS4131. However to use this feature both the positive supply andnegative supply rails must equal (|-VCC| = |+VCC|), absolutely.
Figure 29. Fully Differential Input Driver Circuit for Unipolar or Bipolar Signals
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+Vin=Vincm
-Vin=Vincm
+8Vpp
THS4131
-VCC
0.1 Fm
+VCC
220pFVocm
1
2
85
4
6
3
C0G
COMMOUT
ADS8422
+IN
-IN
3
7
6
time
8Vpp
Vincm
+VIN
-VIN
390 W
390 W
12 W
12 W
0.1 Fm
1 Fm
390 W
390 W
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
PRINCIPLES OF OPERATION (continued)
A. Input common-mode voltage (Vincm) range is restricted by the amplifier. Refer to the amplifier data sheet for moreinformation. Output common mode of the THS4131 is set by the voltage at pin 2. The COMMOUT pin of theADS8422 is designed to source pin 2 of the THS4131. However to use this feature both the positive supply andnegative supply rails must equal (|-VCC| = |+VCC|), absolutely.
Figure 30. Single-Ended Input Driving Circuit for When Input is Unipolar or Bipolar
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COMMOUT
ADS8422
+IN
-IN
3
7
6
+VCC
-VCC
0.1 Fm
+VCC
THS4031
220pF
Vin = 0 to +4V
with
C0G
3
2
7
4
6
-VCC
THS4031
3
2
7
4
6
Vincm=2.048V
time
4Vpp
2.048
VIN
50 W
12 W
12 W
0.1 Fm
50 W
1000 W
1000 W
0.1 Fm
0.1 Fm
1 Fm
-VCC
0.1 Fm
+VCC
THS4032
220pF
+Vin
0Vto +4V
3
2
7
4
6
-VCC
+VCC
C0G
THS4032
3
2
7
4
6
- Vin
0Vto +4V
OpAmp A
ADS8422
+IN
-IN
7
6
with
Vcm=2.048V
with
Vcm=2.048V
OpAmpB
+VIN
-VIN 4Vpp
4 Vpp
time
2.048V
50 W
50 W
50 W
50 W
12 W
12 W
0.1 Fm
0.1 Fm
0.1 Fm
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
PRINCIPLES OF OPERATION (continued)
Figure 31. Single-Ended Driving Circuit for When Input is Single-Ended Unipolar and has Common-Modeof 2.048 V
A. This circuit is used to specify ADS8422 performance parameters listed in the data sheet.
Figure 32. Driver Circuit for When Input is Fully Differential Riding on Common-Mode of 2.048 V
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-VCC
0.1 Fm
+VCC
THS4031
220pF
3
2
7
4
6
-VCC
+VCC
C0G
THS4031
3
2
7
4
6
+4.096V
+4.096V
+VIN =
with
Vincm=0V
8Vpp
-VIN =
with
Vincm=0V
8Vpp
ADS8422
+IN
-IN
7
6
+VIN
-VIN
8Vpp
8Vpp
time
0V
+4 V
-4V
49.9 W
12 W
12 W
1000 W
1000 W
1000 W
1000 W
0.1 Fm
0.1 Fm
0.1 Fm
49.9 W
DIGITAL INTERFACE
Timing and Control
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
PRINCIPLES OF OPERATION (continued)
Figure 33. Driver Circuit for Bipolar Fully Differential Input Signals with 0-V Common-Mode
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, andsource impedance. Essentially, the current into the ADS8422 charges the internal capacitor array during thesample period. After this capacitance has been fully charged, there is no further input current. The source of theanalog input voltage must be able to charge the input capacitance (30 pF) to a 16-bit settling level within the 70ns acquisition time of the device. When the converter goes into hold mode, the input impedance is greater than1 G Ω.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both-IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter linearity may notmeet specifications. To minimize noise, low bandwidth input signals with low pass filters should be used.
Care should be taken to ensure that the output impedances of the sources driving the +IN and –IN inputs arematched. If this is not observed, the two inputs could have different settling times. This may result in offset error,gain error, and linearity error which change with temperature and input voltage.
When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on theinternal capacitor array.
See the timing diagrams for detailed information on timing signals and their requirements.
The ADS8422 uses an internal oscillator generated clock which controls the conversion rate and in turn thethroughput of the converter. No external clock input is required.
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Reading Data
RESET
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
PRINCIPLES OF OPERATION (continued)Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimumrequirement has been met, the CONVST pin can be brought high). The converter switches from sample to holdmode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is importantto the performance of the converter. The BUSY pin is brought high immediately following CONVST going low.BUSY stays high through the conversion process and returns low when the conversion has ended and data isavailable on the DB pins. Once the conversion is started, it cannot be stopped except with an asynchronousRESET (or a logical PD1).
If CONVST is detected high at the end of conversion, the device immediately enters sampling mode and theanalog input is connected to the CDAC. Otherwise, the CDAC is connected to the analog input only whenCONVST goes high. The high duration of CONVST should be at least 100 ns. There is no maximum high pulseduration specification for CONVST.
The ADS8422 outputs full parallel data in 2’s complement format as shown in Table 1 . The parallel output isactive when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge ofCONVST. This is 30 ns prior to the falling edge of CONVST and 10 ns after the falling edge. No data readshould be attempted within this zone. Any other combination of CS and RD three-states the parallel output.BYTE is used for multi-word read operation. BYTE is used whenever lower bits on the bus are output on thehigher byte of the bus. Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION ANALOG VALUE
DIGITAL OUTPUT 2'S COMPLIMENTFull scale range 2V
ref
Least significant bit (LSB) 2V
ref
)/65536 BINARY CODE HEX CODE
+Full scale (+V
ref
) – 0111 1111 1111 1111 7FFFMidscale 0 V 0000 0000 0000 0000 0000Midscale – 1 LSB 0 V – 1111 1111 1111 1111 FFFF-Full scale –V
ref
+ 1000 0000 0000 0000 8000
The output data can be read as a full 16-bit word on pins DB15 – DB0 (MSB-LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In thiscase two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits onpins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7-D0) appear on pins DB15-DB8.
These multi-word read operations can be performed with a multiple active (toggling) RD signal or with the RDsignal tied low for simplicity.
Table 2. Conversion Data Read Out
DATA READ OUTBYTE
PINS PINSDB15–DB8 DB7–DB0
High D7 - D0 All One'sLow D15 - D8 D7 - D0
RESET/ PD1 is an asynchronous active low input signal. Maximum RESET/ PD1 low time is 0.5 µs to avoid ADCpowerdown. Current conversion is aborted no later than 20 ns after the converter is in reset mode. Theconverter returns to normal operation mode no later than 20 ns after the RESET/ PD1 input is brought high (seeFigure 28 ).
The converter provides two power saving options: ADC powerdown (using pin 38, PD1) and analog outputpowerdown ( PD2).
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LAYOUT
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
ADC powerdown is activated by asserting PD1 to 0 for longer than 1.5 µs. If the signal PD1 is asserted 0 forless than 0.5 µs, the ADC is only reset and any ongoing conversion aborted. See Figure 26 . ADC operation canbe resumed from ADC powerdown by de-asserting the PD1 pin. In ADC power-down mode, the analog outputsfrom the ADC(COMMOUT, REFOUT) are not powered down thereby reducing the power-on time.
Full chip power-down is activated by turning off the power supply or by asserting both, PD1 = 0 and PD2 = 0 forlonger than 1.5 µs (see Figure 27 ). In this mode, even the analog outputs of the ADC (COMMOUT, REFOUT)are powered down thereby giving maximum power saving. Device operation can be resumed from full chippower-down by turning on the power supply or by deasserting both, PD1 = 1 and PD2 = 1.
Table 3. Effects of RESET, PD1, and PD2
COMMAND APPLICATION TIME POWER WHEN APPLIED RESUME TIME
RESET/ PD1 = 0 20 ns No change 20 nsPD1 = 0, PD2 = 1 1.5 µs 17mW 5 µsPD1 = PD2 = 0 1.5 µs 40 µW 25 msPD1 = 1, PD2 = 0 Reserved – Do not use this combination
For optimum performance, care should be taken with the physical layout of the ADS8422 circuitry.
As the ADS8422 offers single-supply operation, it is often used in close proximity with digital logic,microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design andthe higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, groundconnections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, drivingany single conversion for an n-clock SAR converter, there are n windows in which large external transientvoltages can affect the conversion result. Such glitches might originate from switching power supplies, nearbydigital logic, or high power devices. The 50 ns period before BUSY falls should be kept free of supply glitches.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of theexternal event.
On average, the ADS8422 draws very little current from an external reference as the reference voltage isinternally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drivethe bypass capacitor or capacitors without oscillation. A 0.1- µF bypass capacitor is recommended from pin 1directly to REFM (pin 48). REFM and AGND should be shorted on the same ground plane underneath thedevice.
The AGND, BDGND, and AGND pins should be connected to a clean ground point. In all cases, this should bethe analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digitalsignal processor. If required, run a ground trace directly from the converter to the power supply entry point. Theideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA and +VAREG should be connected to their respective power supply planesor traces that are separate from the connection for digital logic, until they are connected at the power entry point.Power to the ADS8422 should be clean and well bypassed. A 0.1- µF ceramic bypass capacitor should be placedas close to the device as possible. See Table 4 for capacitor placement. In addition, a 1- µF to 10- µF capacitor isrecommended. In some situations, additional bypassing may be required, such as a 100- µF electrolytic capacitoror even a Pi filter made up of inductors and capacitors — all designed to essentially low-pass filter the +5-Vsupply, thus removing the high frequency noise.
Table 4. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTERCONVERTER ANALOG SIDE
DIGITAL SIDESUPPLY PINS
Pin pairs that require shortest path to decoupling capacitors (4,5), (9,8), (10,12), (13,15), (43,44), (46,45) (24,25), (34,35)
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APPLICATION INFORMATION
ADS8422 TO A HIGH PERFORMANCE DSP INTERFACE
CS
RD
CONVST
BDGND
+VBD
DB[15:0]
TMS320C6713
DSP
+VA =5V
I/OSupply
+VBD+2.7V
ExtRef
Analog
+VA
REFM
AGND
+IN
−IN
ADS8422
REFIN
I/ODigitalGround
BDGND
AGND
EA[16:14]
ED[15:0]
ARE
Input
Input
Address
Decoder
TOUT1
EXT_INTG BUSY
PD2
PD1/RESET
+VAREG
0.1 m
F
10 m
F
AGND
0W
SeeNote A
+VAREG=3V
0.1 Fm
10 Fm
1 Fm
0.1 Fm
BYTE
CE2
+VA
REFOUT
REFIN
REFM
AGND
+VA =5V
ADS8422
AGND
AGND
+VAREG
0.1 m
F
10 m
F
AGND
10 Fm
0.1 Fm
1 Fm
0.1 Fm
0W
SeeNote A
+VAREG=3V
ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
Figure 34 shows a parallel interface between the ADS8422 and a Texas instruments high performance DSPsuch as the TMS320C6713 using the full 16-bit bus. The ADS8422 is mapped onto the CE2 memory space ofthe TMS320C6713 DSP. The read and reset signals are generated by using a 3-to-8 decoder. A read operationfrom the address 0xA000C000 generates a pulse on the RD pin of the data converter, wheras a read operationform word address 0xA0014000 generates a pulse on the RESET/ PD1 pin. The CE2 signal of the DSP acts asCS (chip select) for the converter. As the TMS320C6713 features a 32-bit external memory interface, the BYTEinput of the converter can be tied permanently low, disabling the foldback of the data bus. The BUSY signal ofthe ADS8422 is appiled to the EXT_INT6 interrupt input of the DSP, enabling the EDMA controller to react onthe falling edge of this signal and to collect the conversion result. The TOUT1 (timer out 1) pin of theTMS320C6713 is used to source the CONVST signal of the converter.
A. This resistor (0 Ω) can be installed to use the same 5-V supply.
Figure 34. ADS8422 Application Circuitry
A. This resistor (0 Ω) can be installed to use the same 5-V supply.
Figure 35. ADS8422 Using Internal Reference
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS8422IBPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8422IBPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8422IBPFBT ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8422IBPFBTG4 ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8422IPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8422IPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8422IPFBT ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8422IPFBTG4 ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS8422IBPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
ADS8422IBPFBT TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
ADS8422IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
ADS8422IPFBT TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS8422IBPFBR TQFP PFB 48 1000 367.0 367.0 38.0
ADS8422IBPFBT TQFP PFB 48 250 367.0 367.0 38.0
ADS8422IPFBR TQFP PFB 48 1000 367.0 367.0 38.0
ADS8422IPFBT TQFP PFB 48 250 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
4073176/B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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